JPH0830242A - Liquid crystal driving device - Google Patents

Abstract

PURPOSE:To uniformize luminance characteristics in left/right positions on a liquid crystal display picture and to provide excellent picture quality. CONSTITUTION:A pixel is constituted so that a TFT element 5 as a switching element and liquid crystal capacity CLC connected to it are arranged in matrix on each intersected point between a drain line DL and a gate line GL. A bi- directional shift register 6 in a drain line drive circuit 3 inputs a right shift clock CKR, an inversion right shift clock CKR, a left shift clock CKL, an inversion left shift clock CKL and opens/closes respective gates, and alternately inputs a sampling clock from a right shifting sampling clock RIN or a left shifting sampling clock LIN, and inverts an sampling order of a video signal in an odd gate line and an even gate line, and applies a uniform bias in the left/right positions of the picture, and uniformizes the luminance characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal driving device.

[0002]

2. Description of the Related Art A liquid crystal driving device for driving an active matrix type liquid crystal display device (LCD: Liquid Crystal Display) is generally provided with a gate line (scanning electrode) in a row direction and a drain line in a column direction for one pixel. (Signal electrode) is provided. Then, a data signal is input to this drain line, and a gate voltage is selectively applied to the gate line sequentially in response to horizontal scanning.

A thin film transistor (TFT) as a switching element is connected to each pixel corresponding to each intersection of the gate line and the drain line, and the TFT is switched to switch a predetermined voltage to the liquid crystal of each pixel. Is applied to control the display.

Conventionally, for example, in a drive circuit integrated LCD in which a drive circuit is formed on the same substrate as an active matrix type liquid crystal display panel in which a switching element is provided for each pixel, the so-called dot sequential scanning is called. The driving method described above is used.

That is, the gate lines (scanning lines) of the active matrix array formed on the liquid crystal display panel.
As shown in FIG. 5A, a voltage is sequentially applied to the scanning line from the gate line driving circuit to each scanning line by, for example, 1 line (G1), 2 lines (G2), 3 lines (G3) ,. The TFT connected to is turned on to bring it into a selected state.

In addition, the drain line (signal line) is sequentially sampled from the drain line drive circuit at each sampling timing of D1, D2, D3, ... As shown in FIG. It

The video signal at each sampled pixel position is once a parasitic capacitance CD of the drain line itself.
After that, the driving voltage is written to the liquid crystal capacitance through the above TFT, and while another gate line is selected, the unselected TFT is turned off and each pixel is charged by the charge written in the liquid crystal. Each liquid crystal is driven.

[0008]

However, in such a liquid crystal driving device, as shown in FIG. 5A, during the period A in which a voltage is applied to the gate line G1 to select a TFT. A for the drain lines D1 to Dn
The video signal is sequentially sampled from the left side to the right side at a timing of 1 to an, and a predetermined video signal is written for each pixel.

When scanning the next gate line G2, b1 is applied to the drain lines D1 to Dn in the period B in which a voltage is applied to the gate line G2 to bring it into a selected state.
Video signals sampled from the left side to the right side are sequentially written at the timings from to bn.

As described above, in the conventional liquid crystal driving device, the video signal is always sampled in the same direction (here, from left to right) with respect to the sequentially selected gate lines, and the drain lines are connected to the respective pixel electrodes. The video signal is written to.

Therefore, as shown in FIG. 5C, even if the pixels are driven by the same gate line, VP1 and D
As indicated by the thick line 1 in FIG. 1, a new video signal is written from the pixel on the left side at the timing of a1 in the same figure (b). The data will be written longer. In this way, for example, if the video signals that are always sampled from the left to the right are sequentially written to each pixel electrode, the right pixel and the left pixel on the same gate line are not uniformly biased, There is a problem that the brightness characteristics are not the same on the left and right sides of the liquid crystal display screen.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a liquid crystal drive device in which the brightness characteristics at the left and right positions of the liquid crystal display screen are uniform and good image quality is obtained. I am trying.

[0013]

According to another aspect of the present invention, there is provided a liquid crystal driving device, wherein pixel electrodes arranged in a matrix on a liquid crystal display panel and a predetermined voltage provided for each pixel electrode. Is applied to the pixel electrode at a predetermined timing, a scanning line driving means for applying a control voltage to a predetermined scanning line to bring the switching element connected to the scanning line into a selected state, and a scanning line driving unit in the selected state. In a liquid crystal driving device having a signal line driving means for writing video signals corresponding to respective pixel positions of a plurality of switching elements to respective pixel electrodes through a signal line in a predetermined order, the signal line driving means is inputted. The video signal is sampled at the pixel position of each signal line in accordance with the scanning timing of the scanning line driving means, and the sampling direction is reversed for every predetermined scanning line. By having the image signal sampling unit that performs, to achieve the above object.

The liquid crystal driving device of the present invention is, for example,
According to a second aspect of the present invention, the video signal sampling section sets a sampling direction in accordance with a scanning timing of the scanning line driving means for each predetermined scanning line at the time of sampling for extracting a video signal corresponding to each pixel position. A sampling pulse generator that generates a sampling pulse in the opposite direction, and a sampling processor that samples the video signal based on the sampling pulse from the sampling pulse generator and extracts a video signal corresponding to each pixel position. It may be provided.

The liquid crystal driving device of the present invention is, for example,
As described in claim 3, the video signal sampling section may sample the video signal for each scanning line by alternately changing the sampling direction from left to right or from right to left.

[0016]

In the liquid crystal drive device according to the first aspect, the pixel electrodes are arranged in a matrix on the liquid crystal display panel, the switching element is provided for each pixel electrode, and the control voltage is applied to a predetermined scanning line by the scanning line driving means. The switching element is applied to bring the switching element into a selected state. Then, the signal line driving means for supplying the video signal corresponding to each pixel position to the switching element in the selected state is provided with a video signal sampling section, and the video signal of each signal line is supplied in accordance with the scanning timing of the scanning line driving means. The video signal at the pixel position is sampled, and the sampling direction is reversed in every predetermined scanning line.

Therefore, the sampling order of the video signals written via the switching elements in the selected state is
Since it is performed in the reverse direction for each predetermined scan line, the influence of the video signal before one scan is not biased to the right or left side of the screen, and the brightness characteristics of the entire liquid crystal display screen are made uniform and good image quality is obtained. To be

In the liquid crystal drive device according to the second aspect, the video signal sampling section reverses the sampling order of the video signals for each predetermined scanning line in accordance with the scanning timing of the scanning line driving means in the sampling pulse generating section. A sampling pulse is generated, and the sampling processing unit samples the video signal based on the sampling pulse, and the video signal corresponding to each pixel position is extracted.

Therefore, since the video signal is written in order from the right direction or the left direction for each predetermined scanning line, the influence of the video signal of one scanning before is not biased to the left or right, and the luminance characteristics of the screen are made uniform. , Good image quality can be obtained.

In the liquid crystal driving device according to the third aspect, the video signal sampling section samples the video signal for each scanning line by alternately changing the sampling direction from left to right or from right to left.

Therefore, the region where the influence of the video signal before one scan remains is alternately changed for each scanning line between the right side and the left side, so that the pixels are pseudo-biased uniformly in the entire display region. Therefore, the unevenness of brightness is made uniform.

[0022]

EXAMPLES The present invention will be described below based on examples.
1 to 4 are views for explaining an embodiment of the liquid crystal driving device of the present invention. First, the configuration will be described. FIG. 1 is a circuit block diagram showing the configuration of the liquid crystal drive device 1 of the present embodiment. Here, an active matrix type liquid crystal display panel in which a thin film transistor (TFT) is provided as a switching element for each pixel is used. The present invention is applied to a liquid crystal display device integrated with a drive circuit in which a drive circuit is integrally formed on the same substrate as the liquid crystal display panel.

In FIG. 1, a liquid crystal drive device 1 includes a liquid crystal display panel 2, a drain line drive circuit 3, a gate line drive circuit 4, a TFT element 5, a bidirectional shift register 6,
It is composed of a transfer gate circuit 7, a shift register 8, a buffer 9, and the like.

The liquid crystal display panel 2 has n on a glass substrate.
Drain lines (signal lines) D1 to Dn and gate lines (scanning lines) G1 to Gm are arranged in row m column. At each intersection of the drain line DL and the gate line GL, a TFT element 5 as a switching element and a liquid crystal capacitance CLC connected to the TFT element 5 are arranged in a matrix to form a pixel.

The gate electrode G of the TFT element 5 is connected to the gate line GL common to the TFT elements 5 forming the same row, and the drain D is the drain line DL common to the TFT elements 25 forming the same column. The source S is connected to a pixel electrode (not shown) for each pixel. A liquid crystal capacitance CLC is formed between the pixel electrode and a common electrode which is arranged to face the pixel electrode.
An interline capacitance CD is formed in each of the drain lines DL, and the video signal for each pixel supplied from the transfer gate 7 is temporarily held therein, and the TFT 5
Is written in the liquid crystal capacitance CLC via.

The drain line drive circuit 3 is composed of a bidirectional shift register 6 and a transfer gate circuit 7. The bidirectional shift register 6 is configured by combining a gate and an inverter for each drain line, and has a right shift clock CKR, an inverted right shift clock ￣ CKR (hereinafter, ￣ means inversion), The left shift clock CKL and the inverted left shift clock ￣ CKL are respectively input to open and close each gate, and the sampling clock is input from the right shift sampling clock RIN or the left shift sampling clock LIN in a predetermined order. Create the output sampling clock.

The transfer gate circuit 7 is, for example, a P (thin film transistor) TFT.
MOS (P-channel Metal Oxide Semiconductor) and N
The video signal is sampled based on the sampling clock output from the bidirectional shift register 6 and is composed of MOS (N-channel Metal Oxide Semiconductor) tying-type transfer gates, and each pixel position is the sampling result. The video signal is written for each pixel through the drain lines D1 to Dn. Further, the gate line drive circuit 4 includes a shift register 8 and a buffer 9
It consists of and.

A shift clock CK and a scan side drive signal φv are input to the shift register 8, and the gate lines G1 to Gm are sequentially predetermined through the buffer 9 according to the shift clock CK and the scan side drive signal φv. Supply the scanning signal of.

FIG. 2 shows the drain line drive circuit 3 of FIG.
It is a figure which shows one circuit example. As shown in FIG. 2, the drain line driving circuit 3 includes a bidirectional shift register 6 and a transfer gate circuit 7.

In the bidirectional shift register 6, shift registers SR1, SR2, ... SRn provided for respective stages of drain lines D1, D2, ... Dn are continuously connected. The shift register SR in each stage latches the right shift sampling clock RIN or the left shift sampling clock LIN at a predetermined timing and outputs the latched clock to the transfer gate 7 in the next stage.

The shift register SR of each stage includes four gates RS1, RS2, RS3, RS4 for right shift, two inverters RI1, RI2 for right shift, and four gates LS1 for left shift. It is provided with LS2, LS3, LS4 and two left shift inverters LI1, LI2. Also,
The transfer gate circuit 7 has a drain line D1,
For each stage of D2, ... Dn, two inverters I1 and I2 connected in series and a transfer gate TG (T
G1, TG2, ... TGn) are provided.

The gate R of the first-stage shift register SR1
S1 has a right shift sampling clock input terminal RI
N is connected and the sampling clock for right shift is input.

From the gate RS1, a left shift inverter LI1, gates LS1 and LS3, an inverter LI2, gates LS4 and LS2 are serially connected in this order,
It serves as the output terminal of the first-stage shift register SR1. The gate LS2 serving as the output terminal is the inverter I1 of the first transfer gate TG1 of the transfer gate circuit 7.
And to the right shift gate RS1 of the next-stage shift register SR2.

From the gates LS4 and LS2, a right shift inverter RI1 and a gate RS are serially connected.
2, RS4, inverter RI2, and gate RS3 are connected in this order, and are connected between the gate RS1 and the inverter LI1. The gate LS1 and the gate LS3 are connected to each other, the inverter RI2 and the gate RS4 are connected to each other, and the gate LS3 and the inverter LI2 are connected.
And the gate RS4 and the gate RS2 are connected to each other.

The shift registers SR1, SR2, ... SRn of the respective stages thus constructed are continuously connected to each other, and the gate L of the last shift register SRn is connected.
S2 is connected to the inverter I1 of the transfer gate TGn and also to the sampling clock input terminal LIN for left shift.

The gates RS1 and RS2 in the shift register SR for each stage are used for the right shift clock CK.
Driven by R, gates RS3 and RS4
Are driven by an inverted clock for right shift ￣CKR. The gates LS1 and LS2 are driven by the left shift clock CKL and the gate L
S3 and LS4 are driven by the left shift inversion clock _CKL.

FIG. 3 is a timing chart of the drive voltage applied to the gate line and the drain line of the liquid crystal drive device 1 of this embodiment, and FIG. 4 is input to the bidirectional shift register 6 of FIG. It is a figure which shows the input signal at the time of right shift and left shift.

The liquid crystal drive device of this embodiment is constructed as described above, and its operation will be described below. First, FIG.
As shown in FIG. 3, the shift register 8 of the gate line driving circuit 4 receives each gate line G1 via the buffer 9 according to the input shift clock CK and the scanning side driving signal φv.
.About.Gm are sequentially supplied with predetermined scanning signals to bring the TFTs connected to the respective scanning lines into a selected state. Then, in each pixel connected to the gate line in the selected state, the video signal supplied from the drain lines D1 to Dn is written in each liquid crystal capacitor CLC to drive the liquid crystal.

In the liquid crystal drive device of the present embodiment, when a predetermined gate line is selected, the order of writing the sampling video signal at each pixel position supplied from the drain line is the reverse direction for each predetermined gate line. It is designed to be Then, when the odd gate lines are selected, the right shift is performed by sequentially scanning from the left side to the right direction, and when the even gate lines are selected, the left shift is performed by sequentially scanning from the right side to the left direction. This is performed alternately in the left and right directions, and the effects of the video signal of one scan before are mutually compensated between two adjacent pixels, so that a uniform bias is always applied to the entire screen to uniformize the brightness characteristics. To do.

Specifically, the clock input terminals CKR, CKRR, CK of the bidirectional shift register 6 shown in FIG.
As shown in FIG. 4, various signals are input from L and CKL depending on right shift and left shift. Further, the sampling clock for right shifting is input from the sampling clock terminal RIN for right shifting of the bidirectional register 6 shown in FIG. 2, and the sampling clock for left shifting is input from the sampling clock terminal LIN for left shifting. It

Therefore, at the time of right shift, as shown in FIG. 4, by inputting "H" to the clock input terminal CKR, the gates RS1 and RS2 are opened, and at the same time, inputting "L" to the clock input terminal _CKR. RS3, RS4
Close. Then, the sampling clock for the right shift input from the sampling clock terminal RIN for the right shift is inverted by the inverter LI1. Then, a predetermined clock pulse is input to the clock input terminal CKL to open / close the gates LS1 and LS2 at the same time, and an inverted clock having an opposite phase is input to the clock input terminal _CKL, so that the gates LS3 and LS4 are connected to the gate LS1. L
Open and close at the same time as S2. As a result, the sampling clock whose phase is inverted by the inverter LI1 is further inverted by the inverter LI2, and the sampling clock is output to the transfer gate circuit 7 in accordance with the timing at which the gates LS4 and LS2 are opened.

The inverter I1 of the transfer gate TG1 of the transfer gate circuit 7 inverts the input sampling clock and applies it to the p-channel gate. Further, since the sampling clock inverted by the inverter I1 is further inverted by the inverter I2 and applied to the n-channel type gate, the transfer gate TG1 is simultaneously turned on at a predetermined timing, and the input video signal of After sampling, it is output to the drain line D1.

In this way, the right shift sampling clock input from the right shift sampling clock terminal RIN is sequentially output from the left side to the right direction to the transfer gate circuit 7 at a predetermined sampling timing, and each video signal is output. Sampling is performed at a timing corresponding to the pixel position of the stage, and the sampling data is output to the drain lines D1 to Dn, respectively.

When this is seen in the timing chart of FIG. 3, the gate line G1 in FIG. 3 (a) is kept in the selected state during the period indicated by X, and the drain line is shown from the left side in FIG. 3 (b) during the X period. So that each drain line D1, D2,
With respect to D3, ... Dn, sampling clocks with timings of X1, X2, X3, ... Xn are created, video signals are sequentially sampled, and written in the liquid crystal capacitance CLC of each pixel via the TFT.

Next, when the even gate lines are shifted to the left, the sampling clock terminal L for the left shift shown in FIG.
The sampling clock at the time of left shift input from IN is the transfer gate T of the transfer gate circuit 7.
The video signal input to the Gn inverters I1 and I2 and having the inverted video data arrangement is sampled at the position of the drain line Dn, and the sampling data is output to the drain line Dn.

Then, as shown in FIG. 4, by inputting "H" to the clock input terminal CKL, the gates LS1 and LS2 of the shift register SRn of FIG. 2 are opened, and "L" is input to the clock input terminal _CKR. By inputting, the gates LS3 and LS4 are closed. In this state, when the sampling clock for left shift is input from the left shift sampling clock terminal LIN, it is inverted by the inverter RI1. Then, a predetermined clock pulse is input to the clock input terminal CKR to open / close the gates RS1 and RS2 at the same time, and an inverted clock having an opposite phase is input to the clock input terminal _CKL, so that the gate RS
3 and RS4 are simultaneously opened and closed at the timing opposite to that of the gates RS1 and RS2. As a result, the sampling clock inverted by the inverter RI1 is sequentially inverted again by the inverter RI2, and the sampling clock is input to the inverters I1 and I2 of the transfer gate TGn according to the timing of opening the gates RS4 and RS2.
The sampling clock is input to the gate RS1 of the shift register SRn-1 at the next stage.

As described above, when scanning an odd number gate line,
The right shift sampling clock input from the right shift sampling clock terminal RIN is sequentially output from the left side to the right direction to the transfer gate circuit 7 at a predetermined sampling timing, and the video signal is output according to the pixel position of each stage. Sampling is performed at the timing, and the sampling data is output to the drain lines D1 to Dn, respectively.

Further, during even-numbered gate line scanning, the left shift sampling clock input from the left shift sampling clock terminal LIN is sequentially output from the right side to the left direction at a predetermined sampling timing to the transfer gate circuit 7. , The video signal whose data position is inverted from that in the right shift is sampled at a timing corresponding to the pixel position of each stage, and the sampling data is output to the drain lines D1 to Dn, respectively.

Looking at this in the timing chart of FIG. 3, the odd gate line G1 in FIG. 3A is in the selected state during the period indicated by X, and during the X period, from the left side of the drain line from FIG. 3B. As shown in each drain line D
1, D2, D3, ... Dn to the right, X1, X2,
A sampling clock is created at the timing of X3, ..., Xn to sequentially sample the video signal, and the video signal for each pixel is written in the liquid crystal capacitor CLC via the TFT.

Further, the even-numbered gate G2 of FIG. 3 (a) is in a selected state during the period indicated by Y, and during the Y period, as shown in FIG. 3 (b) from the right side of the drain line, each drain line D1, D2, D3, ... Y1 to the left with respect to Dn,
A sampling clock is created at the timing of Y2, Y3, ... Yn, and the video signals are sequentially sampled.
A video signal for each pixel is written in the liquid crystal capacitor CLC via the TFT.

In this embodiment, since the sampling directions are opposite when scanning the odd number gate lines and the even number gate lines, it is necessary to change the data arrangement of the video signal for sampling according to the scanning direction. The rearrangement of the video signals can be easily performed using, for example, a DSP (Digital Signal Processor) as an existing technique.

As described above, in this embodiment, the odd-numbered gate lines G of the liquid crystal display panel 2 of the liquid crystal driving device 1 shown in FIG. 1 are used.
1, G3, G5, ... Are sequentially scanned from the left side of the screen to the right direction, and even gate lines G2, G4, G6 ,. Therefore, for example, when focusing on the upper and lower two pixels connected to the adjacent gate lines G1 and G2, the two pixels compensate each other and a uniform bias is applied to the entire screen. That is, since the averaged bias is applied in two scans, it is possible to obtain uniform luminance characteristics on the entire screen.

In the above embodiment, the sampling order of the odd number gate lines and the even number gate lines when scanning is set to the left and right directions. However, the present invention is not limited to this example, and two lines, three lines or more may be used. The sampling direction may be changed for each line so that the biases are mutually compensated.

[0054]

According to the liquid crystal drive device of the first aspect,
The video signal is sampled at the pixel position of each signal line in accordance with the scanning timing of the scanning line driving means, and the sampling direction is set to the opposite direction for each predetermined scanning line. The influence of the signal is not biased to the right side or the left side of the screen, the brightness characteristics of the entire liquid crystal display screen are made uniform, and good image quality can be obtained.

According to the liquid crystal driving device of the second aspect, the video signal sampling section sets the sampling direction in the sampling pulse generating section to the opposite direction for every predetermined scanning line in accordance with the scanning timing of the scanning line driving means. A sampling pulse is generated, and a video signal is sampled based on the sampling pulse in the sampling processing unit so that a video signal corresponding to each pixel position is taken out. It is possible to write from the left direction, the brightness characteristics of the screen are made uniform, and good image quality can be obtained.

According to the liquid crystal driving device of the third aspect, in the video signal sampling section, the video signal is sampled for each scanning line by alternately changing the sampling direction from left to right or from right to left. Therefore, the region where the influence of the video signal before one scan remains is alternately changed between the right side and the left side for each scanning line, so that the pixels are pseudo-biased uniformly in the entire display region. Therefore, the unevenness in brightness is made uniform.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a liquid crystal drive device according to an embodiment.

FIG. 2 is a diagram showing an example of a circuit of the drain line driving circuit of FIG.

FIG. 3 is a timing chart of drive voltages applied to a gate line and a drain line of the liquid crystal drive device of the present embodiment.

4 is a diagram showing an input signal input to the bidirectional shift register of FIG. 2 during a right shift and a left shift.

FIG. 5 is a timing chart of drive voltages applied to a gate line and a drain line of a liquid crystal drive device in a conventional example.

[Explanation of symbols]

 1 liquid crystal drive device 2 liquid crystal display panel 3 drain line drive circuit 4 gate line drive circuit 5 TFT element 6 bidirectional shift register 7 transfer gate circuit 8 shift register 9 buffer

Claims (3)

[Claims] 1. A pixel electrode arranged in a matrix on a liquid crystal display panel, a switching element provided for each pixel electrode to apply a predetermined voltage to the pixel electrode at a predetermined timing, and a control voltage to a predetermined scanning line. Scanning line driving means for applying a switching element connected to the scanning line to a selected state, and a video signal corresponding to each pixel position of the plurality of switching elements in the selected state through a signal line in a predetermined order. In the liquid crystal driving device having a signal line driving unit for writing in each pixel electrode, the signal line driving unit is configured to image the input video signal at the pixel position of each signal line according to the scanning timing of the scanning line driving unit. A liquid crystal driving device comprising a video signal sampling section for sampling a signal and performing the sampling direction in a reverse direction for each predetermined scanning line. 2. A sampling method in which the video signal sampling section sets sampling directions in accordance with the scanning timing of the scanning line driving means to opposite directions for every predetermined scanning line at the time of sampling for extracting a video signal corresponding to each pixel position. A sampling pulse generator that generates a pulse; and a sampling processor that samples the video signal based on the sampling pulse from the sampling pulse generator to extract a video signal corresponding to each pixel position. The liquid crystal drive device according to claim 1. 3. The video signal sampling section samples the video signal by alternately changing the sampling direction from left to right or from right to left for each scanning line. LCD drive device.