JP2001356739A - Display device and drive method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device controlling occurrence of odd-even stripes caused by variation in a pixel potential at down-up scanning in a dot line inversion drive mode and to provide a drive method therefor. SOLUTION: This display device is provided with a pixel part 15 wherein pixels 11 are arranged in a matrix form, and pixel columns each are wired with signal lines 12-1-12-4, respectively, and gate lines 13-1-13-5, for example, are meanderingly connected between upper and lower two lines, respectively, a vertical drive circuit 16 for sequentially generating double scanning pulses Vg1-Vg5 consisting of the pulses at the timing of writing original video signals in each pixel of the pixel part 15 and those at the timing earlier than the former ones by 2H, and a horizontal drive circuit 17 for sequentially supplying video signals video 1, vide 2 of the inverted polarity through the signal lines 12-1-12-4 to adjoining pixels of the rows to which the double scanning signals Vg1-Vg5 are given from the vertical drive circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of driving the same, and more particularly, to a so-called dot line inversion driving type active matrix type display device and a method of driving the same.

[0002]

2. Description of the Related Art A display device in which pixels are arranged in a matrix, for example, an active matrix type liquid crystal display device (LC)
D; liquid crystal display), as a driving method, a dot-sequential driving method in which each pixel is sequentially driven in units of one line (one line) is known. As the dot sequential driving method, there are a 1H inversion driving method and a dot inversion driving method.

In the 1H inversion driving method, when a video signal is written, a predetermined DC voltage is applied to each pixel by a common voltage Vcom.
(Hereinafter referred to as Cs line), there is a resistance between the left and right pixels, and there is a parasitic capacitance between the Cs line and the signal line. Since the video signal jumps into the gate line and the potential of the Cs line fluctuates in the direction of the same polarity as the video signal, crosstalk in the horizontal direction becomes remarkable, or shading failure occurs, and the image quality is greatly impaired.

Further, while the pixel holds the pixel information for one field period, the potential of the signal line fluctuates every 1H (H is a horizontal scanning period). Here, in the case of the 1H inversion driving method, since the polarities of the video signals written to the adjacent left and right pixels are the same, the fluctuation of the potential of the signal line becomes large. Since the pixel jumps into the pixel due to the drain coupling, crosstalk in the vertical direction becomes remarkable, which causes a poor image quality.

On the other hand, in the dot inversion driving method, since the video signal is simultaneously written to the adjacent left and right pixels with the opposite polarity, the fluctuation in the potential of the Cs line and the gate line signal line is canceled between the adjacent pixels. Therefore, 1H
The problem of poor image quality in the inversion driving method can be solved. However, on the other hand, since the polarities of the video signals written to the adjacent left and right pixels are different, they are affected by the electric field of the adjacent pixels, so that a domain (light leakage area) is generated at the corner of the opening of the pixel. As a result, the aperture ratio of the pixel is reduced, and the transmittance is reduced, so that the contrast is reduced.

[0006]

On the other hand, in the pixel array after the video signal has been written, the polarities of the pixels are set so that adjacent right and left pixels have the same polarity and upper and lower pixels have the opposite polarity. , An odd number of rows 2 apart between adjacent pixel columns
A driving method has been proposed in which video signals of opposite polarities are simultaneously written to pixels in a row, for example, upper and lower two rows. Hereinafter, this driving method is referred to as a dot line inversion driving method.

In this dot line inversion driving method, similarly to the case of the dot inversion driving method, adjacent signal lines are supplied with video signals of opposite polarities, and the pixel arrangement in the pixel array after the video signal is written. As in the case of the 1H inversion driving method, the left and right pixels have the same polarity, so that it is possible to improve image quality defects such as horizontal crosstalk and shading without reducing the aperture ratio of the pixels. Become.

In the so-called down scan in which the screen is scanned from the top to the bottom in the dot line inversion driving method, as shown in FIG. 7, the pixels 1-1 and 1-2 share the gate line 101-1 at a certain 1H. −2, 1-3, 2-4
(Where H represents a video signal having a potential higher than the reference potential, and L represents a video signal having a potential lower than the reference potential), and in the next 1H LHLH is written to the pixels 2-1, 3-2, 2-3, 3-4.

At this time, for example, the pixel potentials of the pixels 2-1 and 2-3 change from H, which is the previous pixel potential held for one field period, to L. The change in the pixel potential causes the transparent conductive film ITO (Indium Tin Oxid
Coupling enters the pixels 2-2 and 2-4 via e). This coupling is a minus coupling, and the potential of the pixels 2-2 and 2-4 holding L is lowered by the minus coupling. As a result, the potential difference from the common voltage Vcom commonly applied to the pixels increases, so that the pixels 2-2 and 2-4 become black (high density).

Similarly, the next 1H includes the pixels 3-1 and 3-3.
Changes from L, which is the previous pixel potential held for one field period, to H, so that the adjacent pixel 3-
A positive coupling enters 2,3-4. As a result, the pixel potentials of the pixels 3-2 and 3-4 holding H increase, and the potential difference from the common voltage Vcom increases, so that the pixels 3-2 and 3-4 become black.

That is, at the time of down scan in the dot line inversion driving method, the color density of the pixels in the odd (odd) columns and the pixels in the even (even) columns changes, and as a result, this density difference is displayed on the display screen. It will be seen as a vertical streak (hereinafter referred to as an odd-even streak) above.

Similarly, in the so-called up scan in which the screen is scanned from the bottom to the top, as shown in FIG. 8, contrary to the down scan, coupling is performed from the pixels in the even column to the pixels in the odd column. , The pixel in the odd column is e
It becomes black compared to the pixels in the ven column. As described above, in the dot line inversion driving method, the odd-even during scanning is used.
n streaks occur and, depending on the scan direction, od
The color density is inverted between the d-th row and the even-row.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an odd-line streak caused by a change in pixel potential during down / up scan in a dot line inversion drive system. It is an object of the present invention to provide a display device in which generation is suppressed and a driving method thereof.

[0014]

According to the display device of the present invention, pixels are arranged in a matrix, signal lines are wired for each pixel column, and two rows separated by an odd number of rows between adjacent pixel columns. A pixel portion in which a gate line is wired as a unit, and a pulse at a timing at which an original video signal is written to each pixel of the pixel portion and a pulse at a timing earlier by an even multiple of the horizontal scanning period than that. With 2
A first driving means for sequentially generating a series of scanning pulses and applying the same to a gate line; and a signal line connected to a gate line to which two series of scanning pulses are applied from the first driving means for adjacent pixels. And second driving means for sequentially supplying video signals of opposite polarities through the second driving means.

In the display device having the above-described configuration, at the time of vertical scanning, two scanning pulses are sequentially output from the first driving means and sequentially applied to the gate lines of the pixel portion, so that one pixel on a certain line is supplied to one pixel. First, at the timing of the first pulse, a video signal having the same polarity as the video signal to be originally written to this pixel is written from the second driving means through a signal line. Thereafter, an original video signal is written from the second drive unit through the signal line at the timing of two pulses. At this time, since a video signal of the same polarity is written in the pixel in advance, a change in the pixel potential in the pixel is suppressed.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration example of an active matrix type liquid crystal display device of a dot line inversion drive system according to the present invention. Here, for simplification of the drawing, a case of a pixel array of 6 rows and 4 columns is shown as an example. In the first and sixth rows, pixels are arranged every other column, and no video signal is written.
For example, it is a dummy pixel array for writing a black signal.

In FIG. 1, pixels 11 of 6 rows × 4 columns are arranged in a matrix. However, only pixels in odd columns are arranged as dummy pixels in the first row, and pixels in even columns are arranged as dummy pixels in the sixth row. Pixel 11
Are thin film transistors T, which are pixel transistors.
FT, a liquid crystal cell LC in which a pixel electrode is connected to a drain electrode of the thin film transistor TFT, and a storage capacitor Cs in which one electrode is connected to a drain electrode of the thin film transistor TFT.

For each of these pixels 11, signal lines 12-1 to 12-4 are wired for each column along the pixel arrangement direction. On the other hand, the gate lines 13-1 to 13-5
Is not two lines apart from each other in the pixel arrangement direction, but two lines separated by an odd number of lines, for example, upper and lower two lines (upper and lower two lines)
Are wired in a meandering manner between the pixels in the two rows.

Specifically, the gate line 13-1 is wired to each pixel in the first row, first column, second row, second column, first row, third column, and second row, fourth column. The gate line 13-2 is wired to each pixel in the second row and first column, the third row and second column, the second row and third column, and the third row and fourth column. Gate lines 13-3, 13-
Similarly, wirings 4 and 13-5 are wired in a meandering manner between the upper and lower two pixels.

In each of the pixels 11, the source electrode (or drain electrode) of the thin film transistor TFT is connected to the corresponding signal line 12-1 to 12-4, respectively. Further, the counter electrode of the liquid crystal cell LC and the storage capacitor Cs
The other electrode is commonly connected to the Cs line 14 between the pixels. A predetermined DC voltage is applied to the Cs line 14 as a common voltage Vcom.

The connection relation to the gate lines 13-1 to 13-5 is as follows. That is, for odd columns (first and third columns), each row (first to fifth rows)
The gate electrode of the thin film transistor TFT of each pixel is connected to the gate line 13-1 to 13-5 of the row corresponding to each,
For even columns (second and fourth columns), each row (second row to
6th line), the gate lines 13-1 to 13 in the line above one line
-5 is connected to the gate electrode of the thin film transistor TFT of each pixel.

As described above, the pixels 11 are arranged in a matrix, and the signal lines 12-1 to 12-4 are
Are wired for each column and gate lines 13-1 to 13-5
Are two rows separated by an odd number between adjacent pixel columns, for example,
A pixel unit 15 is formed in which the two rows of pixels are wired in a meandering manner in units of rows. In the pixel section 15, one end of each of the gate lines 13-1 to 13-5 is connected to the output end of each row of the vertical drive circuit 16 disposed on the left side of the pixel section 15, for example.

The vertical drive circuit 16 scans in the vertical direction (row direction) every one field period to scan the gate line 13-1.
13-5 are sequentially selected from the pixels 11 alternately connected between the upper and lower two rows. That is, the vertical drive circuit 16
When the scanning pulse Vg1 is applied to the gate line 13-1, the pixels in the first row, first column, second row, second column, first row, third column, and second row, fourth column are selected.

The scanning pulse V is applied to the gate line 13-2.
When g2 is given, the second row, the first column, the third row, the second column,
Each pixel in the third row and the third row and the fourth column is selected. Similarly, when the scanning pulses Vg3, Vg4, and Vg5 are sequentially applied to the gate lines 13-3, 13-4, and 13-5, the pixels are alternately arranged in the horizontal direction (column direction) between the upper and lower rows. Is selected. The specific configuration of the vertical drive circuit 16 will be described later in detail.

A horizontal drive circuit 17 is arranged, for example, above the pixel section 15. The horizontal drive circuit 17 converts video signals video1 and video2,
A sampling process is sequentially performed for each H, and a writing process is performed on each pixel 11 selected by the vertical driving circuit 16.
As the two video signals video1 and video2, the polarity is inverted every 1H and a certain reference potential (common voltage Vco) is used.
m), video signals of opposite polarities are input. Here, the case where the potential of the video signal is higher than the common voltage Vcom is defined as positive polarity (H), and the case where the potential is lower than the common voltage Vcom is defined as negative polarity (L).

The video line 18-1 for inputting the video signal video1 and the signal line 1 of, for example, an odd column of the pixel portion 15
Sampling switches SW1 and SW3 are respectively connected between each of 2-1 and 12-3. Sampling switches SW2 and SW4 are connected between the video line 18-2 for inputting the video signal video2 and the signal lines 12-2 and 12-4 in the even columns of the pixel section 15, respectively.

The sampling switches SW1 to SW
W4 is a pair of two (SW1 and SW2, SW3 and SW
4). By sequentially performing the ON operation in response to the sampling pulses Vh1 and Vh2 sequentially output from the horizontal drive circuit 17, the two series of video signals video1 and video2 having opposite polarities are arranged in two columns ( Writing is performed in units of two pixels) through the signal lines 12-1 to 12-4.

Next, the basic operation of the active matrix type liquid crystal display device of the dot line inversion driving system having the above configuration will be described with reference to the timing chart of FIG. In the pixel array of 6 rows × 4 columns, addresses of each pixel are assigned as shown in FIG. Here, d represents a dummy pixel.

First, in the first line, when the scanning pulse Vg1 is output from the vertical drive circuit 16, the scanning pulse Vg1 is supplied to the pixel d- through the gate line 13-1.
1, 1-2, d-3, 1-4 thin film transistors TF
Since these are applied to the gate electrode of T, these pixels d−1,
1-2, d-3 and 1-4 are turned on.

Here, video signals video of opposite polarities are shown.
O1 and o2 are input through the video lines 18-1 and 18-2, while the sampling pulses Vh1 and Vh2 are sequentially output from the horizontal drive circuit 17, so that the sampling switches SW1 and SW2 and SW3 and SW4 are sequentially paired. It turns on.

Then, video signals video of opposite polarities are displayed.
o1, are sampling switches SW1, SW
2 to the signal lines 12-1 and 12-2. Thereby, the pixel d-1 has a negative polarity (denoted as L in FIG. 3).
, And a video signal video2 of positive polarity (denoted by H in FIG. 3) is written to the pixel 1-2. However, the video signal v at this time
As a video signal, a black signal is input, and a dummy pixel d-1 is input.
Is written with a black signal.

Subsequently, the sampling switches SW3, S
The video signal vi is applied to the signal lines 12-3 and 12-4 through W4.
deo1 and deo2 are given. Thus, the negative video signal video1 is written to the pixel d-3, and the positive video signal video2 is written to the pixel 1-4. Also at this time, the black signal is input to the dummy pixel d-3 by inputting the black signal as the video signal video1.

Next, when the scanning pulse Vg2 is output from the vertical drive circuit 16 on the second line, the scanning pulse Vg2 is applied to the pixels 1-1 and 1-1 through the gate line 13-2.
2-2, 1-3, and 2-4 are applied to the gate electrodes of the thin film transistors TFT, and these pixels 1-1, 2-2, and 1 are applied.
-3 and 2-4 are turned on. In the second line, the polarities of the video signals video1 and video2 with respect to the reference potential are inverted.

That is, in the first line, the video signal vid
Although eo1 has a negative polarity and the video signal video2 has a positive polarity, in the second line, the video signal video1 has a positive polarity and the video signal video2 has a negative polarity. Then, the sampling pulse Vh is again sequentially output from the horizontal drive circuit 17.
By outputting 1, Vh2, the sampling switches SW1 and SW2, and the sampling switches SW3 and SW4 are sequentially turned on in pairs.

Then, video signals video of opposite polarities are displayed.
o1, are sampling switches SW1, SW
2 to the signal lines 12-1 and 12-2. Accordingly, the video signal video of the positive polarity is applied to the pixel 1-1.
1 is written in the pixel 2-2 with the negative video signal video2. Subsequently, the signal lines 12-3,
Video signals video1 and video2 are given to 12-4. Accordingly, the video signal video1 of the positive polarity is applied to the pixel 1-3.
However, the negative video signal video2 is written to the pixel 2-4.

Thereafter, video signals video of opposite polarities are displayed.
While 1 and 2 are input with the polarity of the reference potential inverted every 1H, the above-described operation is repeated, so that the vertical driving circuit 16 scans in the row direction (vertical direction) and the horizontal driving circuit 17 scans in the column direction. (Horizontal direction) scanning is performed. In the case of scanning the gate line 13-5, a black signal is input as the video signal video2, and the black signal is written to the dummy pixels d-2 and d-4.

As described above, for example, two systems of video signals video 1 and 2 are input with a polarity opposite to a certain reference potential, and the video signals video 1 and 2 of the opposite polarity are
At the same time, writing is performed simultaneously on pixels in two rows (in this example, upper and lower two rows) separated by an odd number of rows between adjacent pixel columns, and the polarity of the pixels in the pixel array after writing is changed to the right and left adjacent pixels as shown in FIG. By performing dot line inversion driving in which pixels have the same polarity and upper and lower pixels have the opposite polarity, the following operational effects can be obtained.

That is, as is clear from the timing chart of FIG. 2, the sampling pulses Vh1 and Vh2 are sequentially output, and the sampling switches SW1 and SW2,
When SW3 and SW4 are sequentially turned on in pairs, video signals video1 and video2 having opposite polarities with respect to a certain reference potential are applied to signal lines 12-1 and 12-2 and 12-3 and 12-4. Therefore, image quality defects such as horizontal crosstalk and shading, and vertical crosstalk can be improved.

That is, due to the presence of a resistance component between pixels on the Cs line 14, the video signals video1, video2,
2 jumps into the Cs line 14 via the parasitic capacitance existing between the signal lines 12-1 to 12-4 and the Cs line 14, the storage capacitance Cs of the pixel 11, and the like. By applying the video signals video1 and video2, the potential of the Cs line 14 does not fluctuate, so that the occurrence of crosstalk in the horizontal direction can be suppressed and the shading defect can be eliminated.

The source / source of the thin film transistor TFT
Due to the parasitic capacitance between the drain electrode and each of the signal lines 12-1 to 12-4, the signal lines 12-1 to 12-1
Since the fluctuation of the potential every 1H in 2-4 jumping into the pixel due to the source / drain coupling of the thin film transistor TFT can be canceled by applying video signals video1 and video2 having opposite polarities to adjacent signal lines, Crosstalk can be suppressed. Thus, the video signals video1 and video2 can be written at a sufficient level, so that the contrast can be improved.

Further, video signals video of opposite polarities are provided.
Writing to pixels o1 and o2 is not performed in one horizontal line as in the case of the dot inversion driving method, but is performed in two different pixels.
By performing every other pixel (every other column) between lines (in this example, the upper and lower two lines), the polarity of each pixel in the pixel array after the writing of the video signal is adjacent to each other, as is clear from FIG. Since the left and right pixels that match have the same polarity,
No problematic domain occurs in the case of the dot inversion driving method. As a result, the aperture ratio of the pixel does not need to be reduced, and the contrast does not decrease.

Here, it is assumed that two systems of video signals video1 and video2 are input as the video signals. However, the number of input video signals is not limited to two and may be 2m (m).
Is an integer) system. Further, the video signals video1 and video2 having the opposite polarities are simultaneously written to the pixels in the upper and lower two rows. However, the video signals need not always be in the upper and lower two rows. Any configuration may be used as long as writing can be performed simultaneously on pixels on different horizontal lines so that the left and right pixels have the same polarity and the upper and lower pixels have the opposite polarity.

In the above-described example, the case where the analog video signal is input, and sampled and applied to a liquid crystal display device equipped with an analog interface driving circuit for driving each pixel in a dot-sequential manner has been described. The same applies to a liquid crystal display device equipped with a digital interface drive circuit that receives a digital video signal, latches it, converts it to an analog video signal, samples this analog video signal, and drives each pixel in a dot-sequential manner. Applicable to

In the active matrix type liquid crystal display device of the dot line inversion drive system described above, the present invention is characterized by a specific configuration of the vertical drive circuit 16 and its driving method.

FIG. 4 is a block diagram showing an example of a specific configuration of the vertical drive circuit 16. As shown in FIG. 4, the vertical drive circuit 16 according to the present example has a configuration including a shift register 21, a frequency divider 22, and a logic gate circuit 23. The vertical drive circuit 16 includes a vertical start pulse VST shown in FIG.
CKX and enable pulse ENB are supplied from a pulse generation circuit (not shown).

The vertical start pulse VST is a signal for instructing the start of scanning in the vertical direction, and its frequency is divided by, for example, で by the frequency divider 22, and the period is doubled as shown in FIG. Is input to the shift register 21 as the vertical start pulse 2VST. Vertical clock VCK, VCK
X is a first clock pulse serving as a reference for vertical scanning, the frequency of which is divided by, for example, で by the frequency divider 22 and, as shown in FIG. , 2VCKX to the shift register 21.

Here, the 1/2 frequency divider 22 is used as the clock generating means for generating the vertical scanning clocks 2VCK and 2VCKX as the second clock pulse.
This is only an example and the present invention is not limited to this.

When the vertical start pulse 2VST is applied, the shift register 21
VST is applied to the vertical scanning clocks 2VCK and 2V of opposite phases.
Shifts (transfers) sequentially in synchronization with CKX, and sequentially outputs as shift pulses SP1, SP2,... From each shift stage (S / R). These shift pulses SP1, SP2,
.. Are supplied to the logic gate circuit 23.

The logic gate circuit 23 includes two NAND gates 231-1 and 231-2 and two inverters 232-1 and 232-2 arranged in the input stage, and the pixel unit 15 (see FIG. 1).
NAND gates 233-1, 233-2, 23 provided corresponding to the gate lines (13-1 to 13-5 in this example)
3-3,... And inverters 234-1, 234-2, 23
4-3,....

In this logic gate circuit 23, NAN
The D gate 231-1 has two inputs of a shift pulse SP1 and an enable pulse ENB output from the first shift stage of the shift register 21. The output of the NAND gate 231-1 is inverted by the inverter 232-1 and becomes one input of each of the NAND gates 233-1 and 233-2.

The NAND gate 231-2 has two inputs of the shift pulse SP1 and the enable pulse ENB output from the first shift stage of the shift register 21. The output of the NAND gate 231-2 is inverted by the inverter 232-2 to form the NAND gates 233-3 and 233.
-4 is one of the inputs.

Then, the vertical clock VCK is input to the NAND gate 233-1 as the other input of the NAND gate 233-1.
3-2, the vertical clock VCKX is the other input,
The vertical clock V is used as the other input of the ND gate 233-3.
CK is supplied with the vertical clock VCKX as the other input of the NAND gate 233-4. The output pulses of the NAND gates 233-1, 233-2, 233-3,... Correspond to the inverters 234-1, 234-2, 234-3,.
And the scanning pulses Vg1, Vg2, Vg3,...
And the gate lines 13-1, 13-2, 1 of the pixel section 15
3-3,...

In the vertical drive circuit 16 having the above configuration,
The shift pulses SP1, SP2,... Are sequentially generated based on the vertical scanning clocks 2VCK, 2VCKX having, for example, twice the period of the vertical clocks VCK, VCKX, and the shift pulses SP1, SP2,.
By taking a logical product with VCKX, the scanning pulse Vg is obtained.
, Vg2, Vg3,...
As is clear from the timing chart of FIG. 5, two consecutive pulses are obtained as the scanning pulses Vg1, Vg2, Vg3,.

The logic gate circuit 23 according to the present embodiment has a circuit configuration in which the shift pulse SP1, SP2,... Is NANDed with the enable signal ENB.
It is not limited to this circuit configuration. For example, shift pulses SP1, SP2,... And vertical scanning pulses VCK,
NAND with VCKX, then enable signal E
A circuit configuration that takes NAND with NB may be used.

However, considering the load on the line transmitting the enable signal ENB, the shift pulses SP1 and SP
NAN of 2,... And vertical scanning pulses VCK, VCKX
In the circuit configuration that takes NAND and then NANDs with the enable signal ENB, each input section of the four NAND gates, whereas in the circuit configuration of this example, two NAND gates are used.
Each input part of the gates 231-1 and 231-2 has an advantage that the load can be reduced by half.

In the above-described vertical scanning, two scanning pulses Vg are output from the logic gate circuit 23 of the vertical driving circuit 16.
, Vg2, Vg3,...
Are applied to each of the gate lines 13-1, 13-2, 13-3,..., The potential of the pixel 11 changes as shown in FIG. FIG. 6 shows a change in the pixel potential of a certain pixel in the n-th stage.

By applying a double scanning pulse Vgn to a certain pixel in the n-th stage, the first scanning pulse Vgn is applied.
When the thin film transistor TFT of the pixel is turned on at the generation timing t1 of gnA, a video signal to be written to the pixel of the second previous stage (n−2) is written in the pixel in advance. The polarity of the video signal at this time is, for example, positive polarity H.

Thereafter, at the generation timing t2 of the second scanning pulse VgnB, the thin film transistor TFT of the pixel is turned on. Then, by the time the sampling switch SW of the pixel row is turned on, the video signal to be written to the previous (n-1) th pixel is written. At this time, the polarity of the video signal becomes negative L. Then, when the sampling switch SW is turned on at the same writing timing t3 as in the case of the conventional single-shot scanning pulse, the current stage (the n-th stage)
Is written.

Thus, as is apparent from FIG. 6 showing the change in the pixel potential, the pixel potential of the pixel at the n-th stage changes from H →
Although it changes from L to H, between the video signal level written in advance and the video signal level written this time,
Assuming that the time difference between the two video signals is equivalent to only 2H and that there is no level change (level difference) in the short period, the pixel potential change from H → L and the pixel potential change from L → H Are canceled with each other. Therefore, coupling to adjacent left and right pixels via the transparent conductive film ITO due to a change in pixel potential does not occur.

As described above, in the active matrix type liquid crystal display device of the dot line inversion drive system, writing is performed before another line, for example, two lines (2H) prior to writing an original video signal during vertical scanning. By writing a video signal of the same polarity in advance and then writing the original video signal, the level difference when writing the original video signal is small, so it is possible to suppress the change in pixel potential. it can.

As a result, it is possible to eliminate the coupling between the adjacent pixels due to the change in the pixel potential, and the color between the pixels in the odd-numbered columns and the pixels in the even-numbered columns due to the coupling. The occurrence of odd-even streaks appearing on the display screen can be substantially suppressed by this density difference.

In the above embodiment, the video signal 2H before is written before the original video signal is written. However, the present invention is not limited to the video signal 2H before, and the video signal of the same polarity is used. Any video signal before a certain even line may be used. However, in order to reduce the change in pixel potential when writing the original video signal, and to make the change to the pixel potential as small as possible, it is necessary to write the video signal immediately before the change in the video signal level is small, preferably the video signal 2H before the shortest. And the video signal 2H before is also effective in suppressing the occurrence of ghost.

Further, as the circuit example of the vertical drive circuit 16, since the circuit example shown in FIG. 4 is only an example configured on the assumption that the video signal of 2H is written, it is limited to this circuit example. However, various modifications are possible. In the case of the circuit example on the premise that the video signal before 2H is written, as is clear from FIG. 4, since the scanning pulse Vg for two lines can be generated based on one shift pulse SP, Since the number of shift stages (S / R) of the shift register 21 can be reduced by half as compared with the conventional circuit in which one line of the scanning pulse Vg is generated by one shift pulse SP, the circuit size of the vertical drive circuit 16 can be significantly reduced. There are advantages.

Further, in the above embodiment, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as a display element of a pixel has been described as an example. However, the present invention is not limited to the application to a liquid crystal display device. The present invention is applicable to all display devices adopting the line inversion driving method.

[0066]

As described above, according to the present invention,
In a display device of a dot line inversion drive system, a video signal having the same polarity as a video signal to be originally written to this pixel is written in advance to one pixel during vertical scanning,
Then, by writing the original video signal, a change in the pixel potential at the time of writing the original video signal can be suppressed, so that the occurrence of odd-even streaks can be substantially suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of an active matrix type liquid crystal display device of a dot line inversion drive system according to the present invention.

FIG. 2 is a timing chart illustrating a basic operation of dot line inversion driving.

FIG. 3 is a diagram showing the address of each pixel and the polarity of a video signal written to each pixel in the case of dot line inversion driving.

FIG. 4 is a block diagram illustrating an example of a specific configuration of a vertical drive circuit according to the present invention.

FIG. 5 is a timing chart for explaining a circuit operation of the vertical drive circuit according to the present invention.

FIG. 6 is a waveform diagram showing a change in pixel potential when a video signal is written.

FIG. 7 is a diagram illustrating a conventional problem at the time of down scan.

FIG. 8 is a diagram illustrating a conventional problem at the time of an up scan.

[Explanation of symbols]

11 pixels, 12-1 to 12-4 signal lines, 13-1 to 1
3-5 gate line, 15 pixel unit, 16 vertical drive circuit, 17 horizontal drive circuit, 21 shift register, 22
... 1/2 frequency divider, 23 ... Logic gate circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623W 680 680H (72) Inventor Takeyasu Kashima 6-chome Kitashinagawa, Shinagawa-ku, Tokyo No.7-35 Sony Corporation F-term (reference) 2H093 NA16 NA32 NA34 NA43 NC10 NC12 NC34 NC35 ND04 ND10 ND15 5C006 AA11 AC11 AC24 AC27 AF42 AF43 BB16 BC11 BC23 FA36 5C080 AA10 BB06 DD10 EE29 FF11 JJ02 JJ09 A03 A03 5 BA03 BA43 CA19 CA20 DA13 DB01 DB04 EA04 EA07 EB02 FA01 GA10 JA20

Claims (8)

[Claims] 1. A pixel section in which pixels are arranged in a matrix, a signal line is wired for each pixel column, and a gate line is wired in units of two rows separated by an odd number between adjacent pixel columns. And successively generating a double scan pulse of a pulse at the timing of writing the original video signal and a pulse at a timing earlier by an even multiple of the horizontal scanning period than that at each pixel of the pixel portion. A first driving means for applying the two scanning pulses from the first driving scanning means to the gate line, and an opposite pixel connected to the gate line through the signal line. A second driving unit for sequentially supplying the video signals. 2. The display device according to claim 1, wherein a pulse interval between the two scanning pulses is substantially twice as long as a horizontal scanning period. 3. The method according to claim 1, wherein the first driving unit has a second clock pulse having a period twice as long as a first clock pulse serving as a reference for vertical scanning.
Clock generating means for generating a clock pulse, a shift register for performing a shift operation in synchronization with the second clock pulse generated by the clock generating means, and a shift sequentially output from each shift stage of the shift register. 3. The display device according to claim 2, further comprising logic gate means for sequentially outputting said gate pulse based on a pulse and said first clock pulse. 4. The display device according to claim 1, wherein the display element of the pixel is a liquid crystal cell. 5. A pixel array after writing a video signal, wherein odd-numbered rows are separated between adjacent pixel columns such that adjacent pixels have the same polarity on adjacent left and right pixels and opposite polarities on upper and lower pixels. A method of driving a display device in which video signals of opposite polarities are written to two rows of pixels, wherein a video signal having the same polarity as a video signal to be originally written to this pixel is previously written to one pixel during vertical scanning. A method for driving a display device, comprising writing and then writing an original video signal. 6. The method according to claim 5, wherein the video signal to be written in advance is a video signal before an even-numbered line of the video signal to be originally written. 7. The method according to claim 6, wherein the even lines are two lines. 8. The method according to claim 5, wherein the display element of the pixel is a liquid crystal cell.