JPS61116393A - Liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a liquid crystal display device using a liquid crystal matrix panel.

(b) Conventional technology In recent years, portable type LCD televisions using liquid crystal matrix panels have been actively developed.

551J (issued September 10, 1982) 3211
The details are introduced on pages 240 to 240.

An example of an electrode circuit diagram of an active matrix panel using TF'I' (thin film transistor) in the above liquid crystal television is shown in Figure 6. In the same figure (11(1)...
is a segment electrode formed on the first substrate.

+21 (21... is each of these segment electrodes (1) (
1) T formed on the ff11 substrate corresponding to...
F' T (thin film transistor), and this T P
The sources of T+21 (21...) are connected to the corresponding segment electrodes (11 (11...).

(3H31... is the segment in the column direction) Electricity% (1
1 (T P T [2H2+... corresponding to 11...
・Drain line connected to its drain for each column,
f4)(4)... is the segment electrode (1) in the row direction.
TPT(21(2)) corresponding to 1(11...) is a gate line connected to the gate of each row.

On the other hand, (5) is each segment electrode (1) (1)...
・, TFT (21(2+..., drain line (3
1 (31..., gate lines (4), (41...) are formed on a second substrate opposite to the first substrate on which gate lines (4) (41...) are formed, and a liquid crystal is formed between the M1. Filled.

In addition, the number of one line, that is, the gate line (41 (41・
The number of .

Therefore, during driving, all 240 lines are used in each of the odd and even fields, and the same element is driven again after 1760 seconds.

Video signals are applied to the drain lines (3H31...) of the active matrix panel.1 Normally, when driving a liquid crystal, AC drive is used, in consideration of its durability, that is, the signal is applied at a predetermined period. It is preferable to invert the polarity, and the video signal becomes as shown in FIG. 7, for example.

That is, if the nth odd field is Qn and the nth even field is En, then the odd field (01)
(02) has a positive polarity, and the even field (it) (Rz) has a negative polarity, so that the polarity is reversed for each field.

Therefore, the period in which the same element is driven with the same polarity is 115
The period is 0 seconds, that is, 1 frame. Therefore, flicker on the screen due to polarity reversal is hardly noticeable.

However, in the conventional example mentioned above, the number of lines is 240, which is 9
This had the disadvantage that the number of pixels was small and the degree of deterioration was relatively low.

For this reason, a method has been proposed in which the number of lines is increased to 480 and the number of pixels is increased to improve the image quality.

Figure '@8 shows an electrode circuit diagram of an active matrix panel in the second conventional example, and the same parts as in Figure '@6 are given the same figure numbers and their explanations will be omitted.

At the same entrance, the gate line (4υ (42...1d480
In a book, each row is drawn out to the left and right, and the gate lines (4υ... are applied with gate signals during odd fields, and the gate lines (42... are applied with gate signals during even fields). applied.

As shown in FIG. 9, the polarity of the video signal applied to the drain line (31(3)) of the active matrix panel is reversed every two fields.

The period in which the same element is driven with the same polarity is 1/15 second, that is, a period of 2 frames.

Therefore, the flicker on the screen due to polarity reversal has a low frequency and is very noticeable.

In addition, in the color matrix panels in the two conventional examples mentioned above, the R (red) is placed between the liquid crystal and faces the segment commutative electrode.
, G (green), and B (blue) color filters are repeatedly arranged in a row in the horizontal line direction, and are arranged in a so-called mosaic pattern in which the order of arrangement is different for each line. .

Each B constitutes a color unit display element.

As a signal to be applied to each of the color unit display elements, one of the RlG and B primary color signals is selected at a certain timing, sampled and applied, and this is sequentially repeated.

(c) Problems that the invention attempts to solve The present invention has been made in view of the above points.

The purpose is to make flicker on the screen less noticeable due to AC drive of the liquid crystal even when the number of lines of a color matrix display device is increased from, for example, 240 to 480 to increase the number of pixels and improve resolution. .

B) Means for Solving the Problems The liquid crystal display device of the present invention sequentially displays RlG, B! at the same timing. After selecting two primary color signals f out of l primary color signals, each of the two color signals t is selected within one horizontal scanning period.
The polarities of the two color signals are inverted every vertical scanning period while being applied to each row of color unit display elements in units marked with -2.

(E) Operation Even if the number of lines is increased by the above-described means, the period in which the same display element is driven with the same polarity becomes a relatively short period of one frame.

(f) Example An embodiment of the present invention will be described below with reference to the drawings.

The liquid crystal matrix panel used in this example has 480 pixels.
This is a dual active matrix color LOD panel using X480's a-8i TFT (Ammo/lz7As silicon thin film transistor), and as shown in the v11 diagram, all segment voltages tJj (11
Each T F T(21(21...) corresponding to (1)...
One gate line 1431 that applies a common timing signal to the gates of the two rows is connected, and the drain of each TPT corresponding to the segment electrode of one row of this two-row unit corresponds to the segment electrode of the other row) tlJj Drain lines C311Ga, . . . to which different signals are supplied are connected to the drains of the respective TPTs.

That is, one gate line (43 (4:
1 has a so-called 2N matrix structure, which has the same number of rows as the conventional IJ matrix.

The video signals applied to the drain lines CIl+...corresponding to odd-numbered rows and the drain lines C33... corresponding to even-numbered rows among the two-row units are odd-numbered fields (01) as shown in FIG. The polarity is reversed every field so that (02) has positive polarity and even field (El) (12) has Q polarity.

Here, the video signal applied to the drain line is actually changed from RGB to RGB by a single color signal switching circuit as described later. Two of the primary color signals are selected at the same timing, and these two selected color signals are sampled at the same timing, and these are connected to the drain line (31
1... and l37J... in sequence. Therefore, one gate line G! When a timing signal is applied to J (one horizontal scanning period), two rows of color unit display elements are driven simultaneously.

Therefore, the period in which the same element is driven with the same polarity is 115
0 seconds, and the 7 hits on the screen due to AC drive are virtually inconspicuous.

Next, according to FIGS. 3 to 5, the color LCD in this embodiment
The panel drive circuit will be explained.

The drive circuit in this embodiment can be roughly divided into two types: color LCD
Panel 161. '1pJ1 and 'iJ&2 row drive section (7
1(8).

Row driving section (9) is composed of a one-color signal processing circuit (IG and synchronization control circuit α1).

The LCD panel (6) is a matrix panel shown in FIG. 1 with mosaic color filters facing each other,
Color unit display elements are sequentially arranged horizontally from the upper left as shown in (), RlB, . . . .

141, ml! 2-column drive unit (7) (81 is the first drive unit to which the !!1 clock pulse (op+) and $1 start pulse (EITI) are respectively generated from the synchronous control circuit σB.
and a second shift register (71) (st), and the output pulse of each digit of this shift register is given as a sampling pulse, and the color signal from the color signal processing circuit fi (l) is sampled, and the horizontal synchronization pulse (Hp) The first sample hold circuit (72) and the second sample hold circuit (82) hold the sample for one horizontal scanning period.
The drain of each TPT is driven by the @2 number hold circuit output.

The row driving section (9) uses the second start pulse (Sr1) generated by the synchronization control circuit aD as data input.

It consists of a lift register that takes the horizontal synchronizing pulse (HP) t-clock input, and each digit output is one for each TFTz row.
Driving the book gate line.

The color signal processing circuit CIG sequentially selects two of the three primary color signals R, C) and B at the same timing, and obtains two primary color signal sequences ((z)(02)) with different switching orders. The signal switching circuit (101) and these two signal trains (01) (0
2) and a polarity inverting circuit (1o2) that inverts the polarity of each field based on the vertical synchronizing pulse (Vp), and this polarity inverting circuit outputs (01') (02')
are respectively connected to the first and second sample and hold circuits (71
) (81).

Built-in synchronous control circuit (111FiPLL circuit)
``The first start pulse (8T1) synchronized with the horizontal synchronization pulse (HP), the second start pulse (Sr1) synchronized with the vertical synchronization pulse (vp), and the V in the PLL circuit.
Create a $1 clock pulse (op+) which is the branch output of O2.

Next, the specific configuration of the color signal switching circuit will be explained with reference to FIG.

- (t01&) is controlled by the first clock pulse (aP+) and has the outputs (01&) (Q21L) (Q5&), (10111) is controlled by the horizontal synchronization pulse (MP) output (Ql b) (Q2
'b) (Qs'b) The three outputs of each kakunta are configured so that the high output state sequentially moves from the right side in the figure.

(Sl) to (85) are turned on when the first ternary kakunta outputs (Qla), (Qza), and (Qxa) are high. Katsuka line! '#J41 to the fifth analog switch, (a4) to (S6) derived in 1), are the outputs (Q
Turns on when ta) (Qta) (qsa) is high,
Select the R, B, and () signals, respectively, and send them to the second output line 1.
2) 4th to 6th analog switches, (87)
~(89) are the outputs (01 &) (Q2!L) respectively.
) (Q!!L) turns on when it is high, and B respectively.

These are seventh to ninth analog switches that select G and R signals and output them to the third output line (15).

Therefore, the first output line (l!1) contains G, RlB,
G, R, B,...,'#II2 outgoing carp life line)
are outputted in the order of R, B, G, R, B, G, . . . , and B, G, RlB, (), R, .

Further, (slo) to (812) are respectively the second 3
It turns on when the decimal counter output (Ql'b) (qzb) (Q51)) is high, and (11) (I!2) (I
! 3) selects the output to obtain 0 in the first primary color signal train; 10th to 1812th analog switches;

(+313) to (815) are the outputs (Q
11') (Q2b) (qx)) is turned on when it is high, selects the output of (I!5) (l!1) (l!2), respectively, and obtains the second primary color signal sequence (02). '13th ~ lA15
It is an analog switch.

Therefore, the first primary color signal train (OL) is outputted in the order of (1) 12) (1!3)... every horizontal scanning period, and at the same time, the second primary color signal train (02) is output. Ha (I!
! 5) Obtain output in the order of 11) (I!2)...

Next, the operation of the drive circuit shown in FIG. 3 will be explained with reference to FIG. 4.

'first start pulse (STl) from the synchronous control circuit aυ
) is applied to the first and second shift registers (71) (81), a pulse synchronized with the rising edge of the first clock pulse (OPl) is output for each digit (Ql) (Q2) (Q5).
..., and by the fall of each digit output, the polarity inverting circuit (102) 8 output (01') (a
z') are sequentially sampled and held, and the outputs thereof are sequentially applied to the drain fins of the upper and lower rows of the two-row single rotation color unit display element, respectively. Thereafter, this operation is repeated in horizontal cycles.

On the other hand, the row driving section (9) is connected to the synchronization control circuit 1111.
By applying the second start pulse (ST2) from the first. Similar to the operation of the second shift register.

A pulse synchronized with the rising edge of the horizontal synchronization pulse (Hp), which is a clock input, is sequentially shifted to each digit output, and each digit output is marked on one gate line in units of two rows, turning on each corresponding TPT. shall be.

Thereafter, this operation is repeated in vertical cycles.

(G) Effects of the Invention As described above, according to the present invention, even when the number of lines of the color LOD panel is set to, for example, 480 lines to improve the resolution,
When driving an LCD panel with AC, the cycle in which the same pixels are driven with the same polarity is, for example, 1750 seconds, which is the same as in the case of 240 pixels.
In other words, since the cycle is relatively short, one frame per frame, flicker on the screen becomes less noticeable, and image quality can be greatly improved.

[Brief explanation of the drawing]

FIG. 81 is an electrode circuit diagram of an active matrix panel according to an embodiment of the present invention, FIG. 2 is a video signal waveform diagram applied to the panel of FIG. 1, 'i! Figure 113 is a block diagram of the drive circuit in this embodiment, Figure 4 is the time chart of Figure 3, Figure SS is a circuit diagram of the color signal switching circuit, and Figure 6 is the electrode circuit of a conventional 240-row active matrix panel. Figure 7 is a video signal waveform diagram applied to the panel in Figure 6,
FIG. 8 is an electrode circuit diagram of a conventional 480-row active matrix panel, and FIG. 9 is a video signal waveform diagram applied to the panel of FIG. (6)...Color LCD panel, (71(81...)
・Man 1. @2 column drive unit, (9)...row drive unit, OI・
...Color signal processing circuit, σD...Synchronization control circuit.

Claims (1)

[Claims] (1) A plurality of color unit display elements are arranged in a matrix, and a scanning line is commonly connected to two rows of the color unit display elements, and a scanning line is connected to the color unit display element belonging to one of the two rows. and a second signal line connected to the color unit display element belonging to the other of the two rows, and connected to the first and second signal lines. The first to be
, a second column drive unit, a row drive unit connected to the scanning line, and sequentially select two primary color signals at the same timing among the R, G, and B three primary color signals to form two sets of primary color signal sequences. It consists of a signal switching circuit and a polarity inverting circuit that inverts the polarity of each of the two sets of primary color signal strings for each field, and inverts the two sets of primary color signal strings whose polarity has been inverted by the polarity inverting circuit to the first and second primary color signal strings, respectively. A liquid crystal display device characterized in that the liquid crystal display is supplied to a second column driving section.