JP3032721B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device, and more particularly to a display device which performs active matrix driving by adding a switching element to each display picture element arranged in a matrix. Open.

The present invention relates to a matrix-type liquid crystal display device, and more particularly to a structure of a driving circuit portion of a matrix-type liquid crystal display device in which a switching transistor for address is added to each picture element in a matrix-type display pattern.

[0003]

2. Description of the Related Art A liquid crystal display device is widely used as a small and lightweight display device. In particular, an active matrix liquid crystal display device in which display picture elements are arranged in a matrix and, for example, a switching transistor is added to each display picture element. Is to sequentially select display picture elements by using a switching effect of a switching transistor and apply a display voltage corresponding to display data to obtain a display. Such an active matrix type liquid crystal display device is widely used as a display device having a high contrast and capable of multi-level gradation display, such as a television receiver or a monitor device of a video tape recorder.

FIG. 10 shows a block diagram of such a conventional liquid crystal display device 1. As shown in FIG. The liquid crystal display device 1 has a display picture element 2
Are arranged in a matrix, and one terminal of a switching transistor 4 is connected to each display picture element 2. The other terminal of each switching transistor 4 is connected to a column electrode 5, and the gate of the switching transistor 4 is connected to a row electrode 6-1, 6-2, respectively.
.., 6-n (collectively denoted by reference numeral 6 if necessary). Each row electrode 6 is connected to a scanning circuit 7, respectively.
The column electrode 5 is connected to a data signal circuit 8, and the operation of these circuits 7, 8 is controlled by a control circuit 9.

The scanning circuit 7 sequentially sets the row electrodes 6 to, for example, a high level to make the respective switching transistors 4 connected to the row electrodes 6 conductive. At this time, a display voltage corresponding to a desired display is applied to each column electrode 5. Thereby, each display picture element 2 performs a corresponding display. Such display is repeated for each row electrode 6, and the display for one screen is completed. Such processing is repeated, for example, every 1/60 second or 1/30 second, and display is performed.

When such a liquid crystal display device 1 is used as a so-called liquid crystal television receiver, a video signal of, for example, the NTSC system is used as the display signal. In such a case, the video signal is received by the antenna 10, and the desired video signal is separated by a receiving circuit 11 including, for example, a detection circuit and an amplification circuit, and the analog / digital conversion circuit (hereinafter, referred to as an A / D conversion circuit). After conversion into a digital signal at 12, various signal processes are performed at a signal processing circuit 13, and a digital / analog conversion circuit (hereinafter, D / A)
A signal is converted into an analog signal at 14 and supplied to the data signal circuit 8 while the reference signal S
y is input to the circuits 8 and 9 to perform a predetermined scanning operation.

In the matrix type liquid crystal display device 1 as described above, when display is to be performed based on a television image signal, the number of the row electrodes 6 is set to the number of effective scanning lines of the television signal (in the case of the NTSC system). When the number is close to (about 480 lines), or when the number is close to a half thereof, a driving method for supplying the television signal to the liquid crystal display device 1 in a line-sequential manner for each horizontal scanning period is used. At this time, when the number of the row electrodes 6 is close to the number of effective scanning lines, display for one screen of the display device 3 is performed every frame period. The display of each screen of the display unit 3 is performed for each field period.

On the other hand, when the number of the row electrodes 6 is relatively smaller than the number of effective scanning lines or half thereof, when the above-described display is performed, for example, a video signal If horizontal scanning lines within one vertical scanning period are allocated to the row electrodes 6 from the upper side in the vertical scanning direction, the row electrodes 6 are allocated before video signals for all the scanning lines are input, and display is completed. In this case, a display in which the lower part of the proper screen is missing is displayed on the unit 3. Further, when the missing video signal is excluded from the beginning of one vertical scanning period and the remaining video signal is displayed on the display unit 3, a display in which an upper portion of a proper video signal is lost is performed.

For this reason, when the number of row electrodes 6 is relatively smaller than the number of effective scanning lines or a half thereof, in order to display an apparently proper full screen, the video signal in one vertical scanning period is displayed. Among them, a method of thinning out a video signal corresponding to a specific scanning line is used. In this method, for example, a video signal of a PAL system (625 scanning lines) is converted into an NTSC system (52 scanning lines).
The same can be applied to the case of conversion into five (5) signals. The currently performed signal processing for thinning out the video signal corresponding to one or more scanning lines is performed by a digital circuit such as the signal processing circuit 13 shown in FIG. 10 in terms of processing accuracy and the like. Therefore, the A /
The D conversion circuit 12, the signal processing circuit 13, the D / A conversion circuit 14, and the like are essential, and there is a problem that the circuit configuration becomes extremely complicated.

An object of the present invention is to solve the above-mentioned technical problems and to provide a display device capable of changing the number of scanning lines on a display with a simple configuration and without deteriorating the display quality. It is.

[0011]

According to the present invention, there are provided a plurality of display picture elements arranged in a matrix, switching elements connected to the display picture elements, and a plurality of display picture elements in a row direction along a horizontal scanning direction. In a display device provided with a plurality of row electrodes for sequentially selecting pixels and a plurality of column electrodes for applying signals to a plurality of display picture elements along a column direction, a column electrode drive for outputting display data to each column electrode Means and a clock signal generating circuit for generating a plurality of clock signals which are set in one horizontal scanning period and are generated in one vertical period, and have a pause period W1 in which a display picture element of the display device is not selected by a row electrode. the period of rest period W1 of the clock signal, stops the sequential shift operation for the row electrodes, provided with a row electrode driving means for outputting a signal to said switching element and a non-selected state to the row electrode Ri, the clock signal generating circuit, the time
The thinning process is performed from the earliest field, and
Field decimation position is the other field decimation
The pause period W so that it is located on the upstream side in the vertical scanning direction from the position.
1 is provided, and furthermore, a thinning-out position is set for each field.
Scanning that is switched and thinned out when viewed in one frame
A display device is driven so that lines are not adjacent to each other.

[0012]

According to the present invention, when displaying a plurality of display picture elements on the display means arranged in a matrix, the number of row electrodes provided on the display means is equal to the number of row electrodes in one vertical scanning period of the video signal. If the number is smaller than the number of scanning lines, the stop signal generating means outputs a stop signal to the row electrode selecting means for stopping the selecting operation of the row electrode selecting means for a predetermined stopping period at every predetermined number of horizontal scanning lines. I do. The row electrode selecting means sequentially designates a plurality of row electrodes for selecting a display pixel column in a row direction along the horizontal scanning direction.

Therefore, in the above-described stop period, the selection operation of the row electrodes is stopped while the video signal is input to the display device, and the video signal over the stop period is thinned out. Accordingly, even when the number of row electrodes of the display device is smaller than the number of scanning lines of the video signal, it is possible to display an image within the entire range of the vertical scanning period.

The stop signal is generated such that at least one horizontal scanning period is provided in the vertical scanning direction at an output timing within one frame period of the video signal. Thus, when the thinning process is performed for each field period of the video signal, the situation where the thinned scanning lines for each field period are adjacent in the vertical scanning direction within one frame period is prevented, and the display quality is reduced. The drop can be prevented.

[0015]

FIG. 1 is a block diagram showing the structure of a liquid crystal display device 21 which is a display device according to an embodiment of the present invention.
FIG. 1 is a system diagram showing a configuration of a display unit 22 which is a display unit of the liquid crystal display device 21. The liquid crystal display device 21 will be described with reference to these drawings. As shown in FIG. 2, the liquid crystal display device 21 includes the display unit 22 in which display picture elements 23 configured as display electrodes and the like are arranged in a matrix. In each display picture element 23, a switching transistor 24 realized as, for example, a TFT (thin film transistor) element is arranged.

The output terminal of the switching transistor 24 is connected to the display picture element 23, and the input terminal is connected to a column electrode 25 provided for each display picture element row in the column direction (vertical direction in FIG. 2) along the vertical scanning direction. You. The gate of the switching transistor 24 is connected to a row electrode 26 formed for each display pixel column in the row direction along the horizontal scanning direction. Each column electrode 25 has a column electrode driving circuit 27 serving as a column electrode driving means.
, And the row electrode 26 is connected to a row electrode driving circuit 28 which is a row electrode selecting means. Each drive circuit 27, 28
For example, the operation state is controlled by a control circuit 29 which is a stop signal generating means including a microprocessor or the like. The control circuit 29 receives a reference signal Sy such as a vertical synchronizing signal and a horizontal synchronizing signal separated from the video signal supplied to the liquid crystal display device 21.

The row electrode drive circuit 28 includes a control circuit 29
And a shift register 30 having the same number of bits as the number of the row electrodes 26. The output of each bit of the shift register 30 is applied to each row electrode 26 via the corresponding AND circuit 31. A signal obtained by inverting the clock signal CL by an inverting circuit 32 is provided to the other input of the AND circuit 31. These ANDs 31 constitute a pause circuit 33 that realizes a function described later.

FIG. 3 is a time chart for explaining the basic display operation of the display section 22 of the liquid crystal display device 21. Third
The display operation of the display unit 22 will be described with reference to the drawings. In this description, the column electrode 2 is used for simplification of the description.
A description will be given of a case where there are five and five row electrodes 26, and the row electrodes 26 are individually denoted by reference numerals G1, G2,.
G5 is attached. In the vertical scanning direction (first
3 (1) to 3 (1) to 3 (1)
The scanning signals G1 to G5 as shown in (5) are sequentially applied. 3 (6) is a signal waveform applied to a certain column electrode 25, and v1 to v5 are five row electrodes G.
It is an example of the display voltage applied to each display picture element 23 through the switching transistor 24 connected to each of 1 to G5.

Here, focusing on the display picture element 23 connected to the first row electrode G1 in the vertical scanning direction, the switching transistor 2 is switched during the period T1 by the scanning signal G1.
4 becomes conductive, during which the display voltage v1 is applied to the display picture element 23. Such an operation of applying the display voltage is performed on each column electrode 25 over the drive period T1. The remaining periods T2 to T other than the driving period T1
In 5, the switching transistor 24 is turned off, and the applied voltage v1 is held in the liquid crystal capacitance of a liquid crystal material (not shown) corresponding to the display picture element 23.

After the above operation is performed in the driving periods T2 to T5 of the remaining row electrodes 26, the vertical scanning period TV1 ends, and the driving period T of the next vertical scanning period TV2 ends.
At 1 ', the switching transistor 24 of the first row electrode G1 becomes conductive again. At this time, as shown in FIG. 3 (6), if the applied voltage is -v1, the charge corresponding to the liquid crystal capacitance of the display picture element 23 is held. The drive signal V1i, which is an AC rectangular wave having an amplitude v1 shown in 7), is applied. The same applies to the remaining display picture elements 23.

Such a switching transistor 24
In the liquid crystal display device 21 using the display device, the display voltage is always applied to the liquid crystal corresponding to the display picture element 23 while the switching transistor 24 is in the conductive state, and this charge is held while the switching transistor 24 is in the cutoff state. Therefore, high-contrast display without crosstalk can be realized.

In the present embodiment, in the liquid crystal display device 21 of such a display system, the number of the row electrodes 26 is smaller than the number of the scanning lines of the television image signal to be displayed or a half thereof. Even so, it is intended to realize a display including the entire range of the vertical scanning period. This is the case, for example, when a display is performed on the liquid crystal display device 21 having the number of row electrodes of the NTSC system using the above-described television video signal of the PAL system.

For this purpose, in the present embodiment, the row electrode drive circuit 28 is provided with a pause circuit 33 composed of an AND circuit 31 for pausing the generation of the scanning pulse to the row electrode 26 for a specific period. During the period corresponding to the scanning line to be thinned out of the signals, the generation of the scanning signal is stopped,
During this period, the television image signal being received is not supplied to the display pixel electrode. Thus, the thinning operation is performed, and a large effective display range can be obtained in the display unit 22 having a small number of row electrodes.

The configuration for this purpose is a pause circuit 33 in the present embodiment, which comprises a plurality of AND circuits 31 to which the output of each bit of the shift register 30 is inputted. It has a feature that cannot be realized by a technology with a very easy and simple configuration, which is not included in the above-described conventional technology.

FIG. 4 is a time chart for explaining the operation of this embodiment. This embodiment will be described with reference to FIG. 1 and FIG. In the following description, the number of the row electrodes 26 is a matter of design, and individual reference numerals G1, G2,.
Add n. Clock signal C output from control circuit 29
L is a signal synchronized with the horizontal synchronization signal of the television video signal, and the scanning start signal SP is a signal synchronized with the vertical synchronization signal. As shown in FIG. 4 (1), the control circuit 29 outputs a signal for maintaining the high level state for the idle period W1, for example, every seven clocks for the clock signal CL. In the shift register 30, the scan start signal SP of FIG. 4B is sequentially shifted by the clock signal CL as shown in FIGS. Output to G1 to Gn. At this time, a pause period W1 is provided in the clock signal CL. During this period, the shift operation in the shift register 30 is stopped, the respective AND circuits 31 are cut off, and the scanning signals G1, G2, ... will not be output. Therefore, as shown in FIG. 4 (3), the idle period W1 of the clock signal CL is set to the idle period, and the scanning line of the video signal corresponding to this idle period is thinned out.

At present, television systems adopted in various countries are mainly systems having 525 scanning lines (about 485 effective scanning lines) and 625 (about 576 scanning lines). Here, the video signal of the system with 625 scanning lines is
Considering the case of displaying on the system liquid crystal display device 21 having about 525 scanning lines, the ratio of the effective scanning lines is 48
5: 576 = 1: 1.19, and an integer ratio close to this ratio is 6: 7 = 1.17 or 5: 6 = 1: 1.20.
It is effective to thin out the scanning lines at a rate of one out of six or seven. For example, when a display device having 240 row electrodes is driven to thin out one of seven electrodes, 2
A display range equivalent to 40 + 6 × 7 = 280 lines is obtained.

FIG. 5 is a diagram showing another example of such a thinning operation, and FIG. 6 is a time chart for realizing this example. In this operation example, the scanning lines H1, H2,
.. Are as shown in FIG. 6 (1), that is, the case where the scanning lines H1, H2,. When such a video signal is displayed on the liquid crystal display device 21 having 18 row electrodes as shown in FIG. 5 (2), the clock signal CL described with reference to FIGS. As shown in FIG. 6A, the idle period W1 is set, for example, every seven clocks.

According to this, for example, the scanning lines H4 and H1
1, H18 are thinned out, and the row electrodes G1, G2,.
, H3, H5,..., H10, H1
, H17, H19,..., H21 are respectively assigned. Thus, an image including the range of the entire vertical scanning period can be displayed.

In the present embodiment, the above-described thinning operation is performed by using the structure shown in FIG. 1, whereby the structure for performing the thinning processing as described above can be simplified. . On the other hand, in the configuration shown in FIG. 1 only, as will be described later, adjacent scanning lines are thinned out in one frame period, or the positions of the scanning lines thinned out in even-numbered fields which are slower in time are thinned out in odd-numbered fields. It can be assumed that it is located on the upstream side in the vertical scanning direction from the position of the scanning line to be cut, and the display quality is degraded.

That is, when the number of the row electrodes 26 is close to and smaller than the number of effective scanning lines, display is performed on the display unit 22 every frame period. Therefore, the above-described thinning process needs to be performed for each of the odd field and the even field by the same number of scanning lines. On the other hand, for example, when the position in the vertical scanning direction of the scanning line thinned out in the odd field and the position of the scanning line thinned out in the even field are viewed as one frame obtained by combining them, the vertical scanning direction When adjacent to each other along the line, signals of two continuous scanning lines are not displayed, and there is a problem that image quality is deteriorated, for example, a missing signal is visually recognized.

FIG. 7 is a diagram for explaining the problem assumed. Hereinafter, a case where the number of the row electrodes 26 is equal to or less than half the number of the scanning lines will be described. In such a case, the video signal of the odd field and the video signal of the even field described above are alternately applied to the same row electrode 26. This state is shown in FIG. 7 (1). In FIG. 7, a solid line indicates an odd-numbered field, a broken line indicates an even-numbered field, symbols 1o, 2o,... Indicate scanning lines in an odd-numbered field, and symbols 1e, 2e,. Show.

When the number of scanning lines matches the number of row electrodes 26, as shown in FIG. 7 (1), odd fields are applied to the row electrodes G1, G2,. , 6o are allocated, and in the next field period, the scanning lines 1e, 2e,.
e are respectively assigned. Therefore, each row electrode G1
G6 is supplied with signals of adjacent scanning lines in the vertical scanning direction in the frame period, and no display trouble occurs.

On the other hand, in the case where the thinning processing is performed from a field earlier in time, that is, an odd field, and the thinning position of the odd field is upstream of the thinning position of the even field in the vertical scanning direction. Is shown in FIG. 7 (2). In this example, the third scanning line 3o of the odd field and the fifth scanning line 5e of the even field are used.
And have been culled. Also in this example, adjacent scanning lines in one frame are allocated to each row electrode 6, and no display trouble occurs.

On the other hand, as shown in FIG. 7 (3), the scanning line 3e of the even field and the scanning line 6 of the odd field
When o is thinned out, the scan line of the even field that is slower in time is upstream with respect to the vertical scanning direction. In such a case, as shown in the figure, non-adjacent scanning lines 3o, 4e; 4o, 5e; 5o, 6e are assigned to the same row electrodes G3, G4, G5 as shown in FIG. It is assumed that the situation will occur. Therefore, even in the case of performing the signal processing for thinning out the scanning lines as described above, it is desired to perform the processing in consideration of the above-described situation.

FIG. 8 is a block diagram for explaining the structure of another embodiment of the present invention. This embodiment is similar to the previous embodiment, and corresponding parts are denoted by the same reference numerals. In this specific circuit example, the control circuit 29 and the row electrode driving circuit 28
, Specifically, as shown in FIG.
4. A thinning position setting circuit 35 and a flip-flop circuit 36 for outputting a switching signal F for switching the thinning position set by the thinning position setting circuit 35 for each field are provided.

The control circuit 29 outputs a scanning start signal SP synchronized with the vertical synchronizing signal of the video signal, a clock signal CL synchronized with the horizontal synchronizing signal, a vertical synchronizing signal VS and a mode switching signal SW. Mode switching signal SW
Indicates that the operation of the liquid crystal display device 21 is performed in such a manner that the operation of performing the thinning process and the scanning line of the input video signal are one-to-one on
In this embodiment, a display operation including a thinning operation is performed when the level of the mode switching signal SW is at a high level.
The 7-bit counter 34 includes a 3-bit counter 37 to which a clock signal CL is input.
The output of Q0 is input in parallel to the thinning-out position setting circuit 35 and also to the NAND circuit 38,
The output of the circuit 38 is input to a latch circuit 41 composed of a pair of NAND circuits 39 and 40. Latch circuit 41
When the output of the NAND circuit 38 is input to the reset terminal R of the counter 37 as a reset signal, the output signal is shaped into a waveform synchronized with the clock signal CL.

The output of the latch circuit 41 is a NAND circuit 42
, And a signal obtained by inverting the vertical synchronizing signal VS of the video signal by the inverting circuit 43 and the mode switching signal SW are input to the NAND circuit 42.

The vertical synchronizing signal VS is input to a clock terminal of a flip-flop circuit 36 for switching a thinning position in a thinning position setting circuit 35 described later for each field. The inverted output Q of the flip-flop circuit 36 is connected to the data input terminal D, and the output terminal Q is input to an exclusive OR circuit (hereinafter abbreviated as EX circuit) 44 of the thinning-out position setting circuit 35. The EX circuit 44 of the thinning position setting circuit 35 has the most significant bit Q2
And its output is input to the NAND circuit 45. The NAND circuit 45 includes a bit Q1 of the counter 37.
, And the least significant bit Q0 is input.

The output of the NAND circuit 45 is the NAN to which the inverted signal of the rotter signal CL by the inverting circuit 47 is input.
D circuit 48, the output of which is applied to clock signal CL1
The clock input terminal CK of the shift register 30
To the AND circuit 31 of the pause circuit 33 via the inverting circuit 32.

FIG. 9 is a time chart for explaining the operation of the configuration shown in FIG. The operation of this embodiment will be described with reference to FIGS. 8 and 9. The scanning start signal SP, the clock signal CL and the vertical synchronization signal VS are supplied as shown in FIGS. 9 (1) to 9 (3), and the ternary counter 34 uses the vertical synchronization signal VS to output the NAND circuit 4
2 becomes high level, and the counter 37 is reset. Thereafter, the counter 37 counts up for each clock signal CL as shown in FIG. 9 (2). The counter 37 has 3 bits and therefore counts the count values 0 to 7, but the output (Q2, Q1, Q0) = (1,
At the time of (1, 1), the output of the NAND circuit 38 is switched from the high level to the low level in the remaining count values 000 to 110.
The output of the circuit 42 is inverted from the low level to the high level, and the counter 37 is reset. In this manner, the seven-digit counter 34 shown in FIG. 7 can realize a seven-digit count between 0 and 6 using the 3-bit counter 37.

(1) When the switching signal F is at the high level When the switching signal F is at the high level, the pause signal ST output from the NAND circuit 45 becomes the low level,
The state where the clock signal CL1 is not supplied from the NAND circuit 48 is when all the inputs of the NAND circuit 45 are at the high level, which is (Q2, Q1, Q0).
= (0,0,1). Therefore, as shown in FIG. 9 (4), when the count value of the counter 37 is 0, the pause signal ST output from the NAND circuit 45 is at the high level, and the clock signal CL is output via the NAND circuit 48. Is done. Thereby, the scanning start signal SP
Are shifted by one clock in the shift register 30, and each NAND circuit 31 is also turned on, so that the row electrodes G1
As shown in FIGS. 9 (6) to (8), the scanning signal G1 is derived from Gn only to the row electrode G1.

When the count value of the counter 37 becomes 1,
The pause signal ST goes low, and the NAND circuit 4
8 is shut off, and the clock signal CL1 is fixed at a high level. As a result, the shift operation of the shift register 30 is stopped, and the respective AND circuits 31 are also cut off. As a result, the signal corresponding to the scanning line of the video signal input to the liquid crystal display device 21 is not displayed on the display unit 22 during the pause period W1 between times t1 and t2. Thereafter, as the counter value of the counter 37 increases, the remaining row electrodes G2, G3,... Are sequentially selected, and the above operation is repeatedly performed in the cycle of the seven-digit counter 34 using the counter 37.

(2) When the switching signal F is at low level At this time, the condition that the pause signal ST becomes low level is (Q2, Q1, Q0) = (1, 0, 1). Therefore, as shown in FIGS. 9 (9) to (13), when the counter value of the counter 37 is 5, the pause signal ST falls from the high level to the low level. None of the electrodes G1 to Gn will be selected. In the case of the remaining count value, the row electrodes G1 to Gn are sequentially selected in the same manner as described above.

In the above description, the case where the mode switching signal SW is at the high level has been described. If this signal is at the low level, the output of the NAND circuit 42 is fixed at the high level, and the counter 37 is fixed at the reset state. Is done. As a result, the pause signal ST, which is the output of the NAND circuit 45, is fixed at a high level, and the NAND circuit 48 is maintained in a conductive state. Therefore, the clock signal CL is supplied to the clock input terminal CK of the shift register 30 by the inverting circuit 47, N
It is input via an AND circuit 48. At this time, the clock signal CL1 is the same as the clock signal CL as shown in FIG. 9 (15).

As described above, according to the present embodiment, the seven-digit counter 34 is used to determine the scanning line of the input video signal.
By performing a process of thinning out one of the books, the display unit 22 can realize an image range over the entire vertical scanning period of the image signal. Further, according to the configuration shown in FIG. 8, the positions to be thinned out are switched for each field, and the positions of the scanning lines to be thinned out when viewed in one frame are not adjacent. As a result, it is possible to prevent a situation in which the thinned scanning lines are adjacent in one frame and the display quality is degraded.

In the above-described embodiment, the positions of the scanning lines to be decimated are switched for each field. However, as another embodiment of the present invention, the flip-flop circuit 36 in FIG. In the case of an odd field, the positions of the scanning lines to be decimated in the vertical scanning period are located upstream of the positions of the scanning lines to be decimated in the even field in the vertical scanning direction. Can be According to the example of FIG. 8, the switching signal F may be set to the high level in the odd field, and the switching signal F may be set to the low level in the even field. According to such a configuration, it is possible to prevent a situation in which a video signal corresponding to a scanning line that is not adjacent in the vertical scanning direction is assigned to the same row electrode 26 described with reference to FIG. It is also possible to prevent the display quality from deteriorating. The mode switching signal S
Since W is set, it is possible to cope with a system having a different number of scanning lines, and convenience is remarkably improved.

In each of the above-described embodiments, one out of seven scanning lines is used.
Although the operation of thinning out the books has been described, it is a matter of course that one may be thinned out from the other number of scanning lines.

In each embodiment, the liquid crystal display device 21 has been described. However, the present invention can be widely applied to a matrix type display device.

[0049]

As described above, according to the present invention, when displaying a plurality of display picture elements arranged in a matrix, the number of row electrodes to be displayed is smaller than the number of scanning lines of a display signal. In this configuration, the row electrode driving means outputs a signal for setting the switching element to the non-selection state to the row electrode at intervals of a predetermined display signal over a stop period. Thus, even when the number of row lines to be displayed is smaller than the number of lines of the display signal, it is possible to display an image within the entire range of the display signal using a simple configuration.

According to the present invention, since a signal for deselecting the switching element is output to the row electrode during the idle period W1, the selection period of the switching element becomes the same as that of the switching elements other than the row, and the signal for the picture element is output. Voltage application time can be made uniform, and variation in display luminance can be suppressed.

Further, since the present invention includes the clock signal having the idle period W1, the idle period W of the clock signal is provided.
The thinning position of the display signal can be changed only by changing the timing of No. 1.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 21 according to one embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing an electric configuration of a display unit 22.

FIG. 3 is a time chart showing the operation of the configuration example of FIG. 2;

FIG. 4 is a time chart for explaining a basic operation of the liquid crystal display device 21 of FIG.

FIG. 5 is a view for explaining another operation example of the embodiment.

FIG. 6 is a time chart for explaining the operation of FIG. 5;

FIG. 7 is a view for explaining the operation of the embodiment.

FIG. 8 is a block diagram showing a configuration of a part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 9 is a time chart showing the operation of the configuration of FIG. 8;

FIG. 10 is a block diagram showing a configuration of a typical conventional liquid crystal display device 1.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 22 Display part 23 Display picture element 25 Column electrode 26 Row electrode 28 Column electrode drive circuit 29 Control circuit 30 Shift register 33 Pause circuit 34 Hexadecimal counter 35 Thinning-out position setting circuit 36 Flip-flop circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/36 G02F 1/133 G09G 3/20 H04N 5/66

Claims (1)

(57) [Claims] 1. A plurality of display picture elements arranged in a matrix,
A switching element connected to the display picture element; a plurality of row electrodes for sequentially selecting a plurality of display picture elements in a row direction along a horizontal scanning direction; and a plurality of signals for applying a signal to the plurality of display picture elements in a column direction. A column electrode driving means for outputting display data to each column electrode, a plurality of column electrodes being set in one horizontal scanning period and being generated in one vertical period,
A clock signal generating circuit for generating a clock signal having a pause period W1 during which a display picture element of the display device is not selected by a row electrode; and stopping a sequential shift operation on the row electrode during the pause period W1 of the clock signal. And a row electrode driving means for outputting to the row electrode a signal for setting the switching element to a non-selection state , wherein the clock signal generation circuit has
From the field and thinning out the field
Vertical scanning than the decimation position of the other field
A pause period W1 is provided so as to be on the upstream side in the direction, and further, the thinning position is switched for each field, and
The positions of the scanning lines to be thinned out in one frame are not adjacent.
A display device characterized by being driven as follows .