JP3269082B2 - Liquid crystal drive - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device for driving a liquid crystal used in, for example, a liquid crystal television receiver.

[Prior Art] It is known that, when driving a liquid crystal, increasing the frame frequency of driving improves the contrast.

FIG. 4 shows a liquid crystal driving device in which the driving frame frequency is increased in order to improve the display contrast in the conventional liquid crystal driving, and FIG. 5 is a timing chart showing the operation state of the liquid crystal driving device in FIG. It is a chart.

First, the receiving circuit 1 extracts a video signal Sv, a horizontal synchronizing signal φH, and a vertical synchronizing signal φV from the received television signal. The video signal Sv is supplied to the A / D converter 3 by the horizontal synchronizing signal φH.
And the vertical synchronizing signal φV are sent to the control circuit 2.
The control circuit 2 receives a start signal ST, a clock signal φs, a latch signal φn, an inversion signal φF, a switching signal SEL, address designation signals AD1, AD2, a read / write signal R / W from the input horizontal synchronization signal φH and vertical synchronization signal φV. Generate various timing signals such as shift registers 5, 8, 9 and drive circuit
6, 10 and 11, a switching circuit 4, outputs to the memories A and B, etc., and generates a plurality of types of liquid phase driving voltages VLC to generate driving circuits 6, 10, and 11.
Output to

On the other hand, the A / D converter 3 converts the input video signal Sv into k-bit digital video data E and outputs the k-bit digital video data to the memories A and B. Signal AD1, AD2 and read / write signal R / W
, The even fields (n, n + 2, n + 4,...) Of the video data E
..) Are stored in the odd field (n + 1, n + 3,...).
..) Is read by the memory B.

Next, the video data of n fields read into the memory A is n + 1 fields, and the speed at the time of writing is 2
Twice, that is, twice as fast as normal video data, and is read out twice as an output signal EA.
Similarly, the video data of the (n + 1) th field read into the memory B is the (n + 2) fields, and is read twice at twice the writing speed, that is, twice as fast as the normal video data. , As an output signal EB to the switching circuit 4. The output signals EA and EB input to the switching circuit 4 are switched every field time by a switching signal SEL from the control circuit 2, become data DAB, output to the shift register 5, and synchronized with the clock signal φs of the control circuit 2. And stored in the shift register 5. The data DAB stored in the shift register 5 is latched every 1 / 2H (horizontal scanning period) by the latch signal φn from the control circuit 2 in the segment drive circuit 6, and is driven by the inversion signal φF to perform AC driving. The level is shifted to the liquid crystal drive voltage VLC whose polarity is inverted, and the segment electrodes of the liquid crystal display panel 7 are driven.

Further, the common side of the liquid crystal display panel 7 is
1H (horizontal scanning period) from the start signal ST is input to the shift registers 8 and 9 and the clock signal φn outputs 1 / 2H
Since the shift register is sequentially shifted every (horizontal scanning period), the output signals X'1 to X 'from the shift registers 8 and 9 are shifted.
120 and X'121 to X'240 are added to the corresponding common electrode drive circuits 10 and 11 to drive two common electrodes respectively. The common electrode driving circuits 10 and 11 are connected to each of the output signals X'1 to
A liquid crystal driving voltage VLC that inverts the polarity so that AC driving is performed by an inversion signal φF corresponding to X'120, X'121 to X'240.
Is applied to the common electrode of the liquid crystal display panel 7, and the common electrodes are driven two by two.

[Problems to be Solved by the Invention] As described above, the selection time of the common electrode of the liquid crystal display panel at one time is 1/2 and the selection frequency is doubled, so that the contrast is improved. However, in this conventional liquid crystal driving device, the transfer speed of the shift register must be doubled, and the memory capacity needs to be two fields, which causes a rise in cost.

Therefore, the present invention has been made in view of the above circumstances, and it is possible to use as little memory as possible and to increase the frame frequency of liquid crystal driving without increasing the data transfer speed to the segment electrode driving circuit. It is an object to provide a liquid crystal driving device.

[Means and Actions for Solving the Problems] A storage unit having a capacity of 1/2 field × 1 bit in which video data of the most significant bit of a series of video data is stored;
The video data read from the most significant bit for the 1/2 field stored in the storage means after 1/2 field and the video data excluding the most significant bit which is not passed through the storage means are halved. Switching means for alternately outputting every scanning period, and a liquid crystal driving voltage based on video data excluding the most significant bit which does not pass through the storage means during the first half horizontal scanning period of one horizontal scanning period. A segment electrode driving unit that outputs a liquid crystal driving voltage based on at least the most significant bit data of the storage unit in a / 2 horizontal scanning period, and corresponds to video data that does not pass through the storage unit in the first half horizontal scanning period. Drive the scanning electrode
In the 1/2 horizontal scanning period, the common scanning device further comprises common electrode driving means for scanning and driving another scanning electrode corresponding to the video data from the storage means. In order to alternately output the most significant bit data of the video data stored in the memory of the capacity and the raw video data not passing through the memory every 1/2 horizontal scanning period, and drive the segment electrodes, The common electrode corresponding to the video data is driven.

Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a liquid crystal driving device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing an operation state and data contents of the liquid crystal driving device of FIG.

First, the receiving circuit 1 extracts a video signal Sv, a horizontal synchronizing signal φH, and a vertical synchronizing signal φV from the received television signal. The video signal Sv is supplied to the A / D converter 3 by the horizontal synchronizing signal φH.
And the vertical synchronizing signal φV are sent to the control circuit 2.
The control circuit 2 receives a start signal ST ₀ , a clock signal φs, a latch signal φn, an inversion signal φF, an output inhibition signal INH1,2, a switching signal SEL ₀ , an address designation signal AD from the input horizontal synchronization signal φH and vertical synchronization signal φV. In addition to generating various timing signals such as read / write signal R / W, and outputting the signals to shift registers 15, 18, 19, drive circuits 16, 20, 21, switching circuit 14, memory M, output control circuits 22, 23, etc. A plurality of types of liquid crystal drive voltages VLC are generated and output to drive circuits 16, 20, and 21.

On the other hand, the A / D converter 3 converts the video signal Sv input to the image data E of k bits, for example 3 bits (D ₁ to D _3), and outputs to the memory M, the memory M, the control circuit 12
Addressing signal AD and read / write signal from
The data of the most significant bit (E.MSB) of the video data E is read according to R / W.

Next, the data of 1/2 field read into the memory M is read after 1/2 field according to the address designation signal AD and the read / write signal R / W from the control circuit 12, and is read by one bit (D ₄ ) The data is output to the shift register 15 as the data Ec. The 3-bit (D _{1 to} D ₃ ) video data E from the A / D converter 3 and the 1-bit (D ₄ ) data Ec from the memory M input to the shift register 15 are as follows:
The data is stored in a 4-bit shift register 15 in synchronization with the clock signal φs of the control circuit 12. The data E and E _C stored in the shift register 15 are output to the switching circuit 14 in the next horizontal scanning period H, and the data E and E _C input to the switching circuit 14 are controlled by the switching circuit 14. According to the switching signal SEL ₀ from the circuit 12, the first half is data E and the second half is data
E _C is output alternately every 1/2 H (horizontal scanning period) and input to the segment drive circuit 16. And this data E and E _C
Is driven by the latch signal φn from the control circuit 12 in the segment drive circuit 16 every 1/2 H (horizontal scanning period), and the level of the liquid crystal drive voltage VLC is inverted by the inversion signal φF so that the polarity is inverted. The shift is performed, and the segment electrodes of the liquid crystal display panel 7 are driven.

Further, the common side of the liquid crystal display panel 7 is
The start signal ST ₀ of 1H (horizontal scanning period) from the input to the shift register 18, 19 IH by a clock signal φn
The data is sequentially shifted in the shift register every (horizontal scanning period). Therefore, the output signals from the shift registers 18 and 19 are always output to the output control circuits 22 and 23 so that the common electrode drive circuits 20 and 21 alternately drive the common electrodes, respectively. 23 is an output inhibit signal that is inverted every 1H (horizontal scanning period) in synchronization with the horizontal synchronizing signal φH
The output signals X'1 to X'120, X'121 to X'120 from the shift registers 18 and 19 are alternately changed every 1H (horizontal scanning period) according to INH1 and INH2.
X'240 is added to the corresponding common electrode drive circuits 20 and 21, respectively. The common electrode drive circuits 20, 21 are connected to the output signals X'1 to
A liquid crystal driving voltage VLC that inverts the polarity so that AC driving is performed by an inversion signal φF corresponding to X'120, X'121 to X'240.
Is applied to the common electrode of the liquid crystal display panel 7 to drive the common electrode.

As described above, in the first half of the field, the liquid crystal display panel 7
1H, 121H (MSB), 2H, 122H (MSB)
When the data of ……… is input, X ₁ , X ₁₂₁ ,
X ₂ , X ₁₂₂ ... Are selected, and in the latter half of the field, 121H, 1H (MSB), 122H, 2H (MSB),.
When the data of… is entered, X ₁₂₁ , X ₁ , X ₁₂₂ , X
₂ , ……… is selected and correct driving is performed.

FIG. 3 shows an example of the switching circuit 14, and an AND circuit 31.
36, an OR circuit 37 to 39, and an inverter 40. That is, among the video data E and the memory data E _C stored in the 4-bit shift register 15 of D _{1 to} D ₄ , D _{1 to} D ₃ are respectively added to one input terminals of the AND circuits 31 to 33. , D ₄ is applied to the input terminal of the aND circuit 34 to 36. A switching signal is applied to the other one input terminal of the AND circuits 34 to 36.
SEL ₀ is added, the AND circuit other in the input switching signal SEL ₀ of 31 to 33 is applied through an inverter 40.
The outputs of the AND circuits 31, 34 are connected to the input terminal of an OR circuit 37,
The outputs of the AND circuits 32 and 35 are connected to the input terminal of an OR circuit 38,
Outputs of the AND circuits 33 and 36 are applied to input terminals of an OR circuit 39, respectively. As a result, D _{1 to} D ₃ are output to the output terminals of the OR circuits 37 to 39 and are applied to the segment drive circuit 16.

As described above, the video data of the most significant bit read from the memory having a capacity of 1/2 field × 1 bit and 1/2 field after the video data of the most significant bit of the series of video data, Video data that does not pass through
By driving the liquid crystal display panel by alternately outputting every 1/2 horizontal scanning period, the memory capacity can be reduced to 1/2 field ×
One bit is sufficient, the memory capacity can be reduced as compared with the conventional memory capacity of 2 fields × the number of data bits, and the driving frequency is doubled without increasing the data transfer speed of the segment electrode driving circuit. be able to.

[Effects of the Invention] As described above, according to the present invention, video data stored in a memory having a capacity of 1/2 field × 1 bit and raw video data not passing through the memory are 1/2 horizontal The segment electrodes are driven alternately every scanning period to drive the segment electrodes and the common electrodes corresponding to the video data. It is possible to provide a liquid crystal driving device in which the driving frequency is doubled without increasing the data transfer speed of the electrode driving circuit.

[Brief description of the drawings]

1 to 3 show one embodiment of the present invention.
FIG. 2 is a block diagram showing a circuit configuration of the liquid crystal driving device. FIG. 2 is an explanatory diagram showing waveforms and data contents of respective parts in FIG.
FIG. 3 is an explanatory diagram showing an example of the switching circuit of FIG. 1, and FIG.
FIG. 1 is a configuration explanatory view showing an example of a conventional liquid crystal driving device, and FIG.
FIG. 4 is an explanatory diagram showing waveforms and data contents of respective parts in FIG. M: memory, 1: receiving circuit, 3: A / D converter, 7
… Liquid crystal display panel, 12… Control circuit, 14… Switching circuit, 15, 18, 19… Shift register, 16… Segment drive circuit, 20, 21… Common electrode drive circuit, 22, 23… Output control circuit.

Claims (1)

(57) [Claims] 1. A storage means having a capacity of 1/2 field.times.1 bit for storing video data of the most significant bit of a series of video data, and a most significant bit of 1/2 field stored in said storage means. Switching means for alternately outputting the video data read out after 1/2 field after the video data and the video data excluding the most significant bit without passing through the storage means every 1/2 horizontal scanning period; In the first half horizontal scanning period, a liquid crystal drive voltage based on video data excluding the most significant bit not passing through the storage means is output, and in the latter half horizontal scanning period, at least the most significant bit data of the storage means is output. A segment electrode driving unit that outputs a liquid crystal driving voltage according to the first half of the horizontal scanning period, and drives a scanning electrode corresponding to video data that does not pass through the storage unit during the first half of the horizontal scanning period.
A liquid crystal driving device comprising: a common electrode driving unit that scans and drives another scanning electrode corresponding to video data from the storage unit during a horizontal scanning period.