JPH09307787A - Vertical synchronization circuit and timing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the vertical synchronization circuit and the timing controller by which how to overlap an odd number field and an even number field of an interlace signal to be displayed on a dot matrix display device is changed. SOLUTION: A setting value used to overlap an even numbered field onto an odd numbered field and a setting value used to overlap an odd numbered field onto an even numbered field are set in advance in a decoder 22 of the vertical synchronization circuit 9. The decoder 22 receives a selection signal SEL1. The decoder 22 selects either of the setting values based on the selection signal SEL1 and provides an output of signals S1, S2 based on the selected setting value and a control signal STV is generated to start vertical scanning of the odd numbered field and the even numbered field based on the signals S1, S2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing circuit and a timing controller, and more particularly, to an LCD (Liquor
The present invention relates to a vertical synchronization circuit and a timing controller of an image display device for displaying an image of interlaced scanning on a dot matrix display such as an id crystal display).

[0002]

2. Description of the Related Art In recent years, a display for displaying a video signal of a TV or the like has been replaced with an LRT instead of a CRT (Cathode-RayTube).
A display device such as a CD (Liquid Crystal Display) has been used. The display such as LCD is a CRT
It is called a flat display because it can be thinner than. Further, a display device such as an LCD has an advantage that it consumes less power than a CRT.

As a display for displaying an image, since a dot matrix type display in which electric signals are converted into optical information, that is, display elements are arranged in a matrix is used, a display such as an LCD is used. May be called a dot matrix display.

By the way, in the case of a video signal of the NTSC system, an image is composed of about 480 scanning lines out of 525 scanning lines. Therefore, the number of scanning lines is 480
By using such a display device, one scan of the video signal can be displayed on each scan line to obtain an output video for one screen.

[0005]

However, when an output image is to be obtained using a display device in which the number of scanning lines is smaller than the number of scanning lines of the video signal, for example, the number of scanning lines is about 240 lines, 1 A method of obtaining one screen of output video by displaying two scans of a video signal on a scanning line of a book is used. In the case of an interlaced scanning video signal, as shown in FIG. 8, an image 51 for one screen is an image 52 of an odd field and an image 53 of an even field.
Therefore, the image 52 of the odd field and the image 53 of the even field are overwritten on each scanning line L of the display 54 to display the entire image 51 for one screen. .

By the way, the image 5 of the odd / even field
The appearance of the projected image differs depending on how the 2, 53 are overlapped. For example, as shown in FIG. 9A, in the arbitrary plurality of scanning lines L1 to L10 of the original image, focusing on the column C1 in the vertical direction, the column C1 of each scanning line L1 to L10.
The pixels G1 forming the
"Black, black, white, white, white, white" shall be displayed.

As shown in FIG. 9B, when the image 53 of the even field is superimposed on the image 52 of the odd field, the images of the scanning lines L1 and L2 are displayed on one scanning line. The image displayed on this one scanning line is represented as “L1 + L2”. In this case, “white” and “white” are displayed in the pixels G1 of the scanning lines L1 and L2 that form the column C1. Therefore, the image displayed on the display element G2 forming the column C1 of “L1 + L2” is
It becomes "white".

Similarly, the images of the scanning lines L3 to L10 are
"L3 + L4", "L5 + L6", "L7 + L8"
“L9 + L10” is displayed, and “white”, “black”, “white”, and “white” are displayed on the display elements G2 that form the column C1.

On the other hand, as shown in FIG. 9C, when the image 52 of the odd field is superimposed on the image 53 of the even field, the images of the scanning lines L2 and L3 are displayed on one scanning line. It In this case, the display elements 1 of the scanning lines L2 and L3 that form the column C1 are respectively “white”.
Since "white" is displayed, the column C1 of "L2 + L3"
"White" is displayed on the display element G2 that configures the.

However, when displaying the images of the scanning lines L4 and L5 on one scanning line, the pixel G1 of the scanning line L4 is "white" and the pixel of the scanning line L5 is "black". "Gray" which is an intermediate color between "white" and "black" is displayed on the display element G2 which constitutes the column C1 of "L4 + L5". Similarly, when displaying the image of the scanning line L6 and the scanning line L7 on one scanning line, the pixel G1 of the scanning line L6 is “grey” and the pixel of the scanning line L7 is “white”.
In the display element G2 forming the column C1 of “L6 + L7”,
"Gray" which is an intermediate color between "black" and "white" is displayed.

That is, the "black" pixel of two scanning lines is 1 when the even field is superimposed on the odd field.
It is displayed as "black" on one scan line, and displayed as "grey" on two scan lines when an odd field is overlaid on an even field. As a result, depending on how the odd-numbered field image 52 and the even-numbered field image 53 are overlapped with each other, relatively fine characters and thin horizontal line edges of the image displayed on the display 54 may be difficult to see and difficult to read. was there.

Further, the manner of overlapping the odd field and the even field is set at the design stage of the image display device so as to correspond to only one of them, and therefore cannot be easily changed. Therefore, there is a problem in that it is necessary to prepare an image display device in which the odd field is overlapped with the even field and an image display device in which the odd field is overlapped with the even field.

The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to change the overlapping manner of odd fields and even fields of interlaced signals displayed on a dot matrix display. It is to provide a synchronization circuit and a timing controller.

[0014]

According to a first aspect of the present invention, a video signal composed of an odd field and an even field is applied to a dot matrix display having scan lines less than the scan lines of the video signal. In order to display the field and the even field overlaid,
A vertical synchronizing circuit for generating a control signal for controlling the start of vertical scanning of both fields, wherein a set value for superposing an even field on an odd field and a set value for superposing an odd field on an even field. The gist is that one of the preset setting values is selected and the control signal is generated based on the selected setting value.

According to a second aspect of the invention, a counter that counts the clock signals generated based on the horizontal synchronizing signal, outputs the count value, and clears the count value based on the vertical synchronizing signal, A decoder for outputting a signal in accordance with a preset period based on the count value of the counter, and scanning a video signal composed of an odd field and an even field with less than the number of scanning lines of the video signal. In a vertical synchronizing circuit for generating a control signal for controlling the start of vertical scanning of both fields in order to display an odd field and an even field on a dot matrix display having lines, the decoder is provided with an odd field. Set values for overlapping even fields and odd fields on even fields Set sleeping a set value for in advance, selects one of them set value, and summarized in that which is adapted to generate the control signal based on a setting value selection.

According to a third aspect of the present invention, in the vertical synchronizing circuit according to the second aspect, a selection signal is input to the decoder, and one of preset values set based on the selection signal. The point is to select.

According to a fourth aspect of the present invention, a horizontal synchronizing circuit for generating and outputting a control signal for starting horizontal scanning of an output image and a clock signal corresponding to a horizontal scanning interval based on the horizontal synchronizing signal. And a vertical synchronizing circuit according to any one of claims 1 to 3.

Therefore, according to the first aspect of the present invention,
A set value for superposing the even field on the odd field and a set value for superposing the odd field on the even field are set in advance, and one of the set values is selected, and based on the selected set value. A control signal for starting vertical scanning of the odd field and the even field is generated.

According to the second aspect of the present invention, the decoder is preset with a set value for superposing the even field on the odd field and a set value for superposing the odd field on the even field. The decoder selects one of the set values and, based on the selected set value, generates a control signal for starting vertical scanning of the odd field and the even field.

According to the third aspect of the invention, the selection signal is input to the decoder, and one of the preset values set in advance is selected based on the selection signal. Claim 4
According to the invention described in claim 1, a control signal for starting horizontal scanning of the output image based on the horizontal synchronization signal, and a horizontal synchronization circuit for generating and outputting a clock signal corresponding to a horizontal scanning interval, The vertical synchronizing circuit according to any one of 1 to 3 is provided.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block circuit diagram of the image display device 1. The image display device 1 is
It is composed of a drive circuit unit 2 and a liquid crystal display module 3.

The drive circuit section 2 includes a sync separation circuit 4, a timing controller 5, a voltage controlled oscillator circuit (VCO) 6,
And a video signal processing circuit 7. A video signal is input to the sync separation circuit 4 from the outside.
The sync separation circuit 4 converts the video signal from the horizontal sync signal HSYNC.
The vertical sync signal VSYNC is separated, and the separated horizontal sync signal HSYNC and vertical sync signal VSYNC are output to the timing controller 5.

The timing controller 5 is provided with a horizontal synchronizing circuit 8 and a vertical synchronizing circuit 9. A horizontal synchronizing signal HSYNC is input to the horizontal synchronizing circuit 8. The horizontal synchronizing circuit 8 generates various pulse signals such as a control signal STH for controlling the start of horizontal scanning based on the horizontal synchronizing signal HSYNC and outputs the pulse signals to the liquid crystal display module 3. Further, the horizontal synchronizing circuit 8 and the VCO 6 form a PLL (Phase Locked L
oop), generates a clock signal CLK having a predetermined frequency based on the horizontal synchronizing signal HSYNC, and outputs it to the vertical synchronizing circuit 9. The vertical synchronizing circuit 9 receives the vertical synchronizing signal VSYNC and
Based on the clock signal CLK input from the horizontal synchronizing circuit 8, various pulse signals such as a control signal STV for controlling the start of vertical scanning are generated and output to the liquid crystal display module 3.

The video signal processing circuit 7 amplifies the video signal. Further, although not shown in the figure, the polarity inversion signal FRP is input to the video signal processing circuit 7. The video signal processing circuit 7 operates in synchronization with the polarity inversion signal FRP, converts the amplified video signal into a waveform necessary for driving the liquid crystal display module 3, and outputs it as an image signal Vd to the liquid crystal display module 3.

The liquid crystal display module 3 includes the liquid crystal panel 1
0, a horizontal drive circuit (data driver) 11, and a vertical drive circuit (scan driver) 12.
Various pulse signals such as the control signal STH generated by the horizontal synchronizing circuit 8 are input to the horizontal drive circuit 11, and the image signal Vd processed by the video signal processing circuit 7 is input. Various pulse signals such as the control signal STH generated by the vertical synchronizing circuit 9 are input to the vertical drive circuit 12. Horizontal drive circuit 11 and vertical drive circuit 12
Starts horizontal scanning and vertical scanning based on various pulse signals such as control signals STH and STV, respectively.
By the vertical scanning, the image signal is displayed on the liquid crystal panel 10 as a complete output image.

As shown in FIG. 2, the vertical synchronizing circuit 9 includes:
A counter 21, a decoder 22 and a pulse signal generator 23 are provided. A clock signal is supplied to the counter 21.
CLK is input. The counter 21 has a clock signal CLK.
Are counted and the count value is output to the decoder 22. Based on the count value input from the counter 21, the decoder 22 outputs a signal to the pulse signal generation unit 23 as a signal generation unit when the count value matches a preset set value.

The pulse signal generator 23 generates various pulse signals such as the control signal STV based on the signal input from the decoder 22 and outputs them to the liquid crystal display module 3.
That is, the decoder 22 is preset with a period for generating various pulse signals as a set value, and outputs a signal according to the period to the pulse signal generator 23.

When various pulse signals such as the control signal STV are inputted, the liquid crystal display module 3 receives those control signals STV.
Scanning is started based on various pulse signals such as V, and an image is displayed.

The decoder 22 has a switch SW.
1 and SW2 are respectively connected. Switch SW
1 and SW2 are mechanical switches and the like provided in the drive circuit unit 2. The switch SW1 is provided to select the odd field / even field stacking method. The switch SW2 is provided to select the NTSC system or the PAL system.

That is, the decoder 22 inputs the selection signal SEL1 of H level or L level according to the ON or OFF state of the switch SW1. Then, the decoder 22
A set value for outputting a signal to the pulse signal generation unit 23 is selected based on the input selection signal SEL1. The set value is preset with a value when the odd field is superposed on the even field and a value when the even field is superposed on the odd field.

For example, when the H-level selection signal SEL1 is input, the decoder 22 selects a set value for superimposing an odd field on an even field. When the L level selection signal SEL1 is input, the decoder 22
Selects a set value for superimposing an even field on an odd field. Then, the decoder 22 outputs a signal to the pulse signal generation unit 23 when the selected set value and the count value of the counter 21 match.

The pulse signal generator 23 generates various pulse signals for controlling the start of vertical scanning based on the signal input from the decoder 22. Therefore, the vertical synchronizing circuit 9 generates and outputs various pulse signals based on the selection signal SEL1 at the timing of superposing the odd field on the even field or the timing of superposing the even field on the odd field.

Since the liquid crystal display module 3 starts vertical scanning based on various pulse signals output from the vertical synchronizing circuit 9, the image displayed on the liquid crystal panel 10 is an even field image and an odd field image. The image is a superposed image, or an even field image is superposed on an odd field image.

Further, the decoder 22 inputs the selection signal SEL2 of H level or L level according to the ON or OFF state of the switch SW2. Then, the decoder 22
Based on the input selection signal SEL2, the set value for outputting a signal to the pulse signal generation unit 23 is selected. As the set value, for example, a value corresponding to the NTSC system and a value corresponding to the PAL system are preset.

For example, when the L level selection signal SEL2 is input, the decoder 22 selects a set value corresponding to the NTSC system. In addition, an H level selection signal SEL2
When inputting, the decoder 22 selects a setting value corresponding to the PAL system. Then, the decoder 22 outputs a signal to the pulse signal generation unit 23 when the selected set value and the count value of the counter 21 match.

The pulse signal generator 23 generates various pulse signals for controlling the start of vertical scanning based on the signal input from the decoder 22. Therefore, the vertical synchronizing circuit 9 generates and outputs various pulse signals based on the selection signal SEL2 at a timing corresponding to the NTSC system or the PAL system.

Since the liquid crystal display module 3 starts vertical scanning based on various pulse signals output from the vertical synchronizing circuit 9, the image display device 1 produces a video signal corresponding to the NTSC system or the PAL system, respectively. The image can be displayed based on.

Next, the structure of the decoder 22 will be described in detail with reference to FIG. FIG. 3 is a partial circuit diagram of the decoder 22 and the pulse signal generator 23. The decoder 22 includes input circuit units 31 to 33, AND circuits 34 to 37, and AND circuits 38 to 38.
41 and OR circuits 42 and 43.

A plurality of bits (10 bits in the present embodiment) of count signals IN0 to IN9 are input from the counter 21 to the input circuit section 31 as count values. FIG.
As shown in FIG.
It is composed of a pair of inverter circuits and buffer circuits corresponding to each of 0 to IN9. Then, the input circuit unit 31 generates a complementary bit signal and an inverted bit signal corresponding to the count value from each of the count signals IN0 to IN9.

For example, the input circuit section 31 includes the bit signal B1 and the inverted bit B1N from the lowest count signal IN0.
From the next bit count signal IN1 to the bit signal B
2 and the inverted bit signal B2N are generated. The input circuit section 31 is adapted to generate the bit signal B512 and the inverted bit signal B512N from the highest count signal IN9.

Bit signals B2 to B512 and inverted bit signals B2N to B512N generated by the input circuit section 31.
Are input to the AND circuits 34 to 37 in accordance with the timing of generating the signals S1 and S2. For example,
As shown in FIG. 5, the AND circuit 34 includes a bit signal B
2, B8, B16 and inverted bit signals B4N, B32N-
B512N is input. Then, the AND circuit 34
The signal S3a is generated when each input signal is "1". Therefore, the AND circuit 34 is adapted to generate the signal S3a when the bit signals B2, B8, B16 are "1", that is, when the count value of the counter 21 is "26".

Similarly, although not shown in the figure, bit signals B2 to B8 and B32 are input to the AND circuit 35,
The signal S3b is generated when the count value is "46". The bit signals B4 to B16 are input to the AND circuit 36,
The signal S4a is generated when the count value is "28". The bit signals B16 and B32 are input to the AND circuit 37, and the signal S4b is generated when the count value is "48".

The signal X generated by the input circuit section 32 is input to each of the AND circuits 34 to 37. The selection signal SEL1 is input to the input circuit unit 32. Also,
The bit signal B1 and the inverted bit signal B1N generated by the input circuit unit 31 are input to the input circuit unit 32. As shown in FIG. 4, the input circuit section 32 includes a pair of inverter circuits and a buffer circuit, and the selection signal SE
Complementary signals EO and OE are generated based on L1.
For example, when the selection signal SEL1 is at the L level, the H level signal EO and the L level signal OE are generated, and when the selection signal SEL1 is at the H level, the L level signal EO and the H level signal OE are generated. It is like this.

The signal EO is input to one input terminal of the AND circuit 44, and the inverted bit signal B1N is input to the other input terminal of the AND circuit 44. The signal OE is input to one input terminal of the AND circuit 45, and the bit signal B1 is input to the other input terminal of the AND circuit 45. The output terminals of the AND circuits 44 and 45 are respectively connected to the input terminals of the NOR circuit 46 having two input elements, and the output terminals of the NOR circuit 46 are connected to the input terminals of the inverter circuit 47. The inverter circuit 47 outputs the signal X.

The signal X becomes H level when the signal EO is at H level and the inverted bit signal B1N is at H level, or when the signal OE is at H level and the bit signal B1 is at H level. Further, the signal X becomes L level when the signal EO is H level and the inverted bit signal B1N is L level, or when the signal OE is H level and the bit signal B1 is L level. The signal EO becomes H level when the selection signal SEL1 is L level, and the signal OE becomes H level when the selection signal SEL1 is H level.
Level. Further, the inverted bit signal B1N becomes H level when the count signal IN0 is L level, and the bit signal B1 becomes H level when the count signal IN0 is H level.

Therefore, the input circuit 32 receives the signal OE at H level.
The bit signal B1 is output as the signal X when the level, that is, the selection signal SEL1 is at the H level, and the inverted bit signal B1N is output as the signal X when the signal EO is at the H level, that is, the selection signal SEL1 is at the L level. Has become.

The signal X is input to the AND circuits 34 to 37. Then, the AND circuits 34 to 37 have the bit signals B2 to B512 and the inverted bit signals B2N to B51.
When the count value is obtained by adding the signal X to the count value based on 2N, the signals S3a to S4b are output. Therefore, in each of the AND circuits 34 to 37, the selection signal SEL1 is H level.
When the level is the level, the signals S3a to S4b are output when the count value is "1" added to the count value, and when the selection signal SEL1 is the L level, the signals S3a to S4b are output when the count value is the level above. .

That is, when the selection signal SEL1 is at the H level, the AND circuits 34-37 output the signals S3a- when the count values are "27""47""29""49", respectively.
Outputs S4b. On the other hand, when the selection signal SEL1 is at the L level, each of the AND circuits 34 to 37 outputs the signal S3 when the count value is "26""46""28""48".
a to S4b are output.

As shown in FIG. 3, AND circuits 34 to 3 are provided.
The signals S3a to S4b outputted from the No. 7 are inputted to one input terminals of the AND circuits 38 to 41, respectively. The AND circuits 38 to 41 are two-input elements and are connected to the input circuit section 33, respectively, and the signal SNTSC is input to the other input terminals of the AND circuits 38 and 40.
The signal SPAL is input to the other input terminal of 1.

As shown in FIG. 4, the input circuit section 33 is composed of a pair of inverter circuits and a buffer circuit, and the complementary signals SNTSC and SPAL based on the selection signal SEL2.
Generate For example, when the selection signal SEL2 is at the H level, the input circuit section 33 generates the H level signal SNTSC and the L level signal SPAL. On the other hand, when the selection signal SEL2 is at L level, the input circuit section 33 causes the L level signal S
Generates NTSC and H level signal SPAL.

Therefore, as shown in FIG. 3, when the signal SNTSC is at H level, that is, when the selection signal SEL2 is at H level,
The AND circuits 38 and 40 receive the input signals S3a and S4a.
Is output, and the AND circuits 39 and 41 do not output a signal.
On the other hand, the signal SPAL is at H level, that is, the selection signal SEL2
Is at the L level, the AND circuits 38 and 40 do not output the signal, and the AND circuits 39 and 41 input the signal S3b,
Outputs S4b.

The output terminals of the AND circuits 38 and 39 are connected to the input terminals of the OR circuit 42, respectively.
The output terminals of 0 and 41 are connected to the input terminals of the OR circuit 43, respectively. The OR circuit 42 outputs the signal S1 and the OR circuit 43 outputs the signal S2.

Therefore, the decoder 22 outputs the count signal I
Based on N0 to IN9 and the selection signals SEL1 and SEL2, how to overlap odd fields / even fields and NT
Switching between the SC / PAL systems is selected, and signals S1 and S2 corresponding to the selection results are output.

For example, NT based on the selection signal SEL2
When switched to the SC system, the selection signal SEL2 is L
Level. When the odd field and the even field are selected so as to overlap with each other, the selection signal SEL1 becomes H level. Then, the decoder 22 outputs the signal S when the count value output from the AND circuit 34 is "26".
3a and the signal S4a when the count value output from the AND circuit 36 is "28", respectively.
Output as

On the other hand, when the odd field is selected to overlap the even field, the selection signal SEL1 becomes L level. Then, the decoder 22 operates the AND circuit 34.
Signal S3a when the count value output from is 27.
And the count value output from the AND circuit 36 is "2.
The signal S4a for "9" is output as signals S1 and S2, respectively.

Similarly, when switching to the PAL system,
The selection signal SEL2 becomes H level. When the odd field and the even field are selected so as to overlap with each other, the selection signal SEL1 becomes H level. Then, the decoder 22 outputs the signal S3b when the count value output from the AND circuit 35 is "46" and the signal S4b when the count value output from the AND circuit 37 is "48" to the signal S1, respectively. Output as S2.

On the other hand, when the odd field is selected to overlap the even field, the selection signal SEL1 becomes L level. Then, the decoder 22 operates the AND circuit 35.
Signal S3b when the count value output from is 47.
And the count value output from the AND circuit 37 is "4.
The signal S4b for "9" is output as signals S1 and S2, respectively.

The signals S1 and S2 are the JK flip-flops (hereinafter, referred to as JKFF) which constitute the pulse signal generator 23.
Input) 23a. Further, the clock signal CLK is input to the JKFF 23a. The JKFF 23a operates in synchronization with the clock signal CLK, and outputs the control signal STV, which becomes a pulse signal based on the signals S1 and S2, from the output terminal Q. Based on the control signal STV, the liquid crystal display module 3 starts vertical scanning of odd fields and even fields.

The control signal STV is generated based on the signals S1 and S2. For example, in the case of switching to the NTSC system, the signals S1 and S2 are generated based on the selection signal SEL1 and the count value based on "26" and "28" when the selection signal SEL1 is at the H level. On the other hand, when the selection signal SEL1 is at L level, the control signal STV
Is generated based on the count values of "27" and "29".

That is, the decoder 22 selects the selection signal SEL1.
, When the selection signal SEL1 is at L level,
As compared with the case where the selection signal SEL1 is at the H level, the count value is delayed by "1" and the control signal STV is generated. The liquid crystal display module 3 starts vertical scanning based on this control signal STV. Therefore, the liquid crystal display module 3 selects the selection signal SEL1 so that when the selection signal SEL1 is at the L level, that is, the odd field is superimposed on the even field, the selection signal SEL1 is at the H level, that is, the odd field is superimposed on the even field. Compared with the case where the scanning is performed, the count value of the counter 21 is delayed by "1" and the vertical scanning is started.

Then, as shown in FIGS. 6 and 7, the displayed images are overlapped differently. For example, when the H-level selection signal SEL1 is input and the odd field is selected to overlap the even field, the count value "26"
When the vertical scanning is started based on the control signal STV generated based on the signals S1 and S2 of "28", the image of the even field is superimposed and displayed on the image of the odd field. For example, as shown in FIG. 6, when the arbitrary lines L1, L3, L5 of the odd field and the arbitrary lines L2, L4, L6 of the even field are overlapped, the line L2 of the even field is overlapped with the line L1 of the odd field. Then, the image is displayed on one scanning line of the liquid crystal panel 10.
Similarly, the line L4 and the line L4 are displayed so as to be superimposed on the line L3 and the line L5.

As shown in FIG. 6, the odd field and the even field are sent to the liquid crystal display module 3 with the count value of the counter 21 shifted by "1" (= 0.5H). ing.

On the other hand, the L-level selection signal SEL1 is input and selected so that the odd field is superimposed on the even field, and the signals S1 and S having the count values "27" and "29" are selected.
When the vertical scanning is started based on the control signal STV generated on the basis of 2, the image of the even field is superimposed and displayed on the image of the odd field. For example, as shown in FIG. 7, arbitrary lines L1, L3 of an odd field are
L5, L7 and arbitrary lines L2, L of even fields
Suppose 4, L6 are stacked. At this time, since the control signal STV is delayed by the count value "1", the liquid crystal display module 3 starts the vertical scanning with the count value delayed by "1". Then, the line L2 of the even field and the line L3 of the odd field are overlapped and displayed on one scanning line of the liquid crystal panel 10. Similarly, the line L4 and the line L5 are overlapped and the line L6 and the line L7 are overlapped and displayed.

That is, by scanning the switch SW1 and setting the selection signal SEL1 to the H level or the L level, it is possible to switch the superimposing method in which the even field is overlapped with the odd field and the odd field is overlapped with the even field.

When the NTSC system is switched to the PAL system, similarly, when the selection signal SEL1 is at the H level, the decoder 22 outputs the signal S3b when the count value is "46" output from the AND circuit 35. , AND circuit 3
The signal S4b when the count value is "48" output from 7
The control signal STV is generated based on On the other hand, the selection signal S
When EL1 is at L level, the decoder 22 outputs the signal S3 output from the AND circuit 35 when the count value is "47".
b and the count value “4 output from the AND circuit 37.
The control signal STV is generated based on the signal S4b at the time of "9". Since the liquid crystal display module 3 starts vertical scanning based on the control signal STV, when the odd field is overlapped with the odd field, the liquid crystal display module 3 is compared with the case where the even field is overlapped with the odd field. And the count value is delayed by "1". As a result, it is possible to switch over the odd field and the even field.

As described above, the present embodiment has the following effects. (1) The decoder 22 of the vertical synchronizing circuit 9 is preset with a set value for superposing an even field on an odd field and a set value for superposing an odd field on an even field. The selection signal SEL1 is input to the decoder 22. The decoder 22 selects one of the set values based on the selection signal SEL1 and outputs the signals S1 and S2 based on the selected set value. And
Based on the signals S1 and S2, the control signal STV for starting the vertical scanning of the odd field and the even field is generated. As a result, it is possible to change the manner in which the odd field and the even field are overlapped by simply changing the selection signal SEL1.

(2) The decoder 22 uses the selection signal SEL2
Is entered. The decoder 22 selects one of the setting value corresponding to the NTSC system and the setting value corresponding to the PAL system based on the selection signal SEL2, and generates the control signal STV at the selected timing. Signal S
1 and S2 are generated. As a result, it is possible to support a plurality of video signals of different timing systems.

The present invention is not limited to the above-mentioned embodiment, but may be carried out as follows. (1) In the above embodiment, the selection signals SEL1 and SEL are made by the switches SW1 and SW2 provided in the drive circuit unit 2.
Although the level of 2 is set and the odd field / even field is superposed and the NTSC / PAL system is switched respectively, the switch SW1 and SW2 are replaced by E.
You may implement by providing a register, such as EPROM. This register may be provided on the chip forming the vertical synchronizing circuit 9. Even with this configuration, by changing the data stored in the register, the odd field /
It is possible to respectively switch the even field superposition method and the NTSC / PAL method.

Further, instead of the switches SW1 and SW2, a fuse or the like is provided on the chip forming the vertical synchronizing circuit 9,
The fuse may be cut at the time of shipment of the chip, if desired, or may be cut by the user. According to this configuration, although switching cannot be easily performed, the chip on which the vertical synchronizing circuit 9 is formed can be shared.

Further, the selection signal SEL1,
A terminal for inputting SEL2 may be provided, and both signals SEL1 and SEL2 may be input from the outside of the drive circuit unit 2 to switch between odd field / even field stacking and NTSC / PAL system.

(2) In the above embodiment, the video signals of the NTSC system and the PAL system are respectively supported, but it is also possible to support only one of the NTSC system and the PAL system.

(3) In the above embodiment, the signal S
The count value when generating 1 and S2 may be changed as appropriate. For example, in the above embodiment, the signals S1 and S2 are generated when the count values are “27” and “29” (“47” and “49” in the PAL system) when the odd field is superimposed on the even field. However, the count values of the signals S1 and S2 are "25" and "27", respectively.
It may be generated at the time of (for example, “45” and “47” in the PAL system).

(4) In the above embodiment, the image display device 1 using the liquid crystal display module 3 as a display is embodied, but instead of the liquid crystal display module 3, a PDP (plasma) is used.
display panel: Plasma display panel), FE
D (field emission display), EL (electrolumines
cence) panel, organic EL panel, ECD panel, EP
It may be embodied in an image display device using another display such as an ID panel or a fluorescent display tube.

Although the respective embodiments of the present invention have been described above, technical ideas other than the claims which can be understood from the respective embodiments will be described below together with their effects. (A) In the vertical synchronizing circuit according to any one of claims 1 to 3, a second selection signal is input to the decoder, and the decoder is based on the second selection signal.
A vertical synchronizing circuit configured to select one of a plurality of preset timings and generate a signal for generating the control signal at the selected timing. With this configuration, it becomes easy to support a plurality of video signals of different timing systems.

[0075]

As described above in detail, according to the present invention, there is provided a vertical synchronizing circuit and a timing controller capable of changing the overlapping manner of the odd field and the even field of the interlaced signal displayed on the dot matrix display. be able to.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a liquid crystal display device according to an embodiment.

FIG. 2 is a block circuit diagram of a vertical synchronizing circuit according to an embodiment.

FIG. 3 is a block circuit diagram of a decoder unit according to an embodiment.

FIG. 4 is a partial circuit diagram of a decoder unit according to an embodiment.

FIG. 5 is a partial circuit diagram of a decoder unit according to an embodiment.

FIG. 6 is a timing chart showing the operation of the vertical synchronizing circuit.

FIG. 7 is a timing chart showing the operation of the vertical synchronizing circuit.

FIG. 8 is an explanatory diagram showing superposition of image data.

9A to 9C are explanatory views showing superposition of pixels.

[Explanation of symbols]

 9 Vertical synchronization circuit SEL1 selection signal STV control signal

Claims (4)

[Claims] 1. In order to display a video signal composed of an odd field and an even field on a dot matrix display having scan lines smaller than the scan lines of the video signal, the odd field and the even field are overlapped. A vertical synchronizing circuit for generating a control signal for controlling the start of vertical scanning of a field, wherein a set value for superposing an even field on an odd field and a set value for superposing an odd field on an even field are previously set. A vertical synchronizing circuit that is set, selects one of the set values, and generates the control signal based on the selected set value. 2. A counter that counts clock signals generated based on a horizontal synchronizing signal, outputs the count value, and clears the count value based on the vertical synchronizing signal; and a counter based on the count value of the counter. And a decoder that outputs a signal according to a preset period, and a video signal composed of an odd field and an even field is displayed on a dot matrix display having scan lines less than the scan lines of the video signal. In a vertical synchronization circuit that generates a control signal for controlling the start of vertical scanning of both odd and even fields so that they are displayed in an overlapping manner, the decoder is configured to set the odd and even fields to overlap. The value and the setting value for overlapping the odd field on the even field A vertical synchronizing circuit which is preset and which selects one of the set values and generates the control signal based on the selected set value. 3. The vertical synchronization circuit according to claim 2, wherein a selection signal is input to the decoder, and one of preset values set based on the selection signal is selected. Synchronous circuit. 4. A horizontal synchronizing circuit for generating and outputting a control signal for starting horizontal scanning of an output image and a clock signal corresponding to a horizontal scanning interval based on the horizontal synchronizing signal. And a vertical synchronization circuit according to any one of the above.