JPH07146666A - Scanning electrode driving circuit and image display device using the same - Google Patents

Abstract

PURPOSE:To provide a scanning electrode driving circuit and an image display device for performing a magnified display without providing peripheral devices such as a memory, A/D and D/A converters in the image display device. CONSTITUTION:A mode selection circuit 20 selecting scanning electrodes so that a single scanning electrode is driven or plural scanning electrodes are driven simultaneously in one scanning period of time in when image data for the amount of one line are outputted is provided between the shift register 10 of a scanning electrode driving circuit 40 and a buffer circuit part 30. Moreover, an image display device 60 is provided with a display panel 61, a signal electrode driving circuit 62 outputting inputted image data DT on the display panel 61, a drive electrode driving circuit 63 having a magnifying function. a timming signal generating circuit 66 generating various tinging signals, a changeover switch SW specifying display modes and a display mode setting circuit 67 outputting a mode signal (m) setting display modes by the changeover of the changeover switch SW.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device,
The present invention relates to a scan electrode driving circuit that enables enlarged display in a vertical direction in an image display device having a display panel that performs matrix driving, such as a liquid crystal display device and a plasma display panel, and an image display device using the same.

When displaying an image of a personal computer or the like using a liquid crystal display device, which is a type of image display device, there is a demand to enlarge a part of the display screen depending on the application. For example, in a presentation using a projector, it is an effective means to enlarge a finely displayed portion on the screen for explanation. In such a case, there is no problem if the signal source side such as a personal computer has the enlargement function, but if the signal source side does not have the enlargement function, it is controlled by the drive circuit of the liquid crystal display device. There is a need.

[0003]

2. Description of the Related Art Conventionally, when a liquid crystal display device is controlled to realize enlarged display in a vertical direction, a method of storing data of an area to be enlarged and displayed in a memory and writing the same data to a plurality of lines of the display device is known. It was taken. 12 and 13 are diagrams for explaining a driving method of the liquid crystal display device,
Here, a basic driving method of a dot matrix type liquid crystal display device using a thin film transistor (hereinafter referred to as a TFT) as a switching element will be described.

FIG. 12 is a diagram for explaining the structure of a liquid crystal display device. In the figure, 71 is a liquid crystal panel, 72 is a display pixel, 72a is a TFT serving as a switching element, and 72b.
Is a liquid crystal serving as a pixel capacitance, 73 is a data driver, 74 is a data bus line connected to the output terminal Y of the data driver 73, 75 is a gate driver, and 76 is a gate bus line connected to the output terminal X of the gate driver 75. And 70 indicates a liquid crystal display device composed of these.

As shown in FIG. 1, the liquid crystal panel 71 has an M
Data bus lines 74 and N gate bus lines 7
6 form a matrix electrode, and the intersection (Y _i ,
X _j ) is the display pixel 72, and constitutes a display panel of M × N pixels. The display pixel 72 has a TF connected to the data bus line 74 and the gate bus line 76.
T72a is formed as a switching element, and the data bus line 74 and the gate bus line 76 are connected to the data driver 73 and the gate driver 75, respectively, and apply a drive voltage to the liquid crystal 72b.

The data driver 73 is a shift register,
It is composed of a latch or the like, and the image data is latched by a timing signal for data latch created based on a synchronization signal obtained in synchronization with the image data. Image data is output to the data bus line 74 all at once.

Further, the gate driver 75 is composed of a shift register or the like, and shifts the gate output by a timing signal synchronized with the horizontal synchronizing signal to generate a signal for turning on the TFT 72a for each line in the liquid crystal panel 71. The data is output to the gate bus line 76. In this manner, normally, one gate bus line 76 of the liquid crystal panel is sequentially scanned every horizontal period to display the entire area of the panel 71. This operation will be described with reference to FIG.

FIG. 13 is a diagram for explaining a conventional gate driver, FIG. 13 (a) is a basic configuration diagram of the gate driver,
FIG. 6B is a time chart showing the operation of the gate driver shown in FIG. In the figure, 10e is a shift register, 15 _-1 , 15 _-2 , ..., 15 _-n are n D-flip-flops in the shift register 10e, and 30e.
, 35 _-1 , 35 _-2 , ..., 35 _-n are n output buffers in the buffer circuit section 30e, 40e
Is a gate driver composed of them, CK is a shift clock synchronized with the horizontal synchronizing signal, Q ₁ , Q ₂ ,.
.., Q _n are respectively D-flip-flops 15 _-1 to 1
Outputs of 5- _n , X ₁ , X ₂ , ..., X _n are output terminals of output buffers 35 _{-1 to} 35 _-n , DT ₁ , DT ₂ ,.
DT ₃ ... Shows one line of image data output from the data driver in one horizontal period, and the subscripts represent line numbers on the display screen in normal display.

As shown in FIG. 1A, the gate driver 40e generally comprises a shift register 10e and a buffer circuit section 30e. In addition, the shift register 10
e is composed of n D-flip-flops 15 _-1 to 15 _-n , and has a start pulse SP and a shift clock CK.
Is input, the output Q of the D-flip-flop 15, that is, the start pulse SP is shifted every time the shift clock CK is input, and the outputs Q _{1 to} Q _n are sequentially output at a constant cycle. Then, the output buffers 35 _{-1 to} 35 _-n
The drive voltage of the gate is output from the output terminals X _{1 to} X _n , and the gate of the TFT 72 a on the gate bus line 76 of FIG. 12 connected to the output terminal X _j is turned on or off at the same time.

That is, as shown in FIG.
The shift clock CK with the same synchronization as the synchronization signal is the gate
When input to the driver, output terminal X
The gate output pulse appearing in₁, X₂, ..., X
_nAnd the output terminal X₁Gate connected to
Image data D is stored in the TFT 72a on the bus line 76.
T ₁, Output terminal X₂Gate bus line 76 connected to
Image data DT is displayed on the upper TFT 72a.₂And so on
The output from the data driver is via the data bus line 74.
Then, it is applied as a signal voltage to each TFT 72a.

FIG. 14 is a block diagram of a control circuit of the analog type liquid crystal driver. In the figure, 81 is an amplification / inversion circuit, 82 is a timing generation circuit, 83 is a data driver, and 84 is a gate driver. As shown in the figure,
When the video signal is an analog signal and an analog input data driver is used, the video signal composed of analog RGB signals is input to the amplification / inversion circuit 81, converted into a liquid crystal drive voltage, and then sent to the data driver 83, and the timing is set. The data driver 83 and the gate driver 84 are driven by the timing signal from the generation circuit 82 to display an image.

15 to 17 are views for explaining the conventional vertical enlargement function. FIG. 15 is a block diagram of a conventional control circuit of a liquid crystal driver having a vertical enlargement display function. In the figure, 85 is a timing generation circuit, 85 'is a memory control unit in the timing generation circuit 85, and 86 is an A / D.
A converter, 87 is a memory, and 88 is a D / A converter, and those having the same functions as those in FIG. 14 are denoted by the same reference numerals.

As shown in the figure, when a video signal is an analog signal and a data driver of an analog input is used to enlarge and display a part of the screen in the vertical direction, first, an analog R signal is displayed.
A video signal composed of a GB signal is converted from an analog signal to a digital signal by the A / D converter 86, and the data is held in the memory 87. Conventionally, the memory controller 85 'in the timing generation circuit 85 reads the same data a plurality of times, and the read data is read by D
After the digital signal was converted into the analog signal by the / A converter 88, it was input to the amplification / inversion circuit 81 to be the liquid crystal drive voltage and supplied to the data driver 83.

FIGS. 16A and 16B are time charts for explaining the conventional vertical enlarged display described above. FIG. 16A is a time chart for a 2 × enlargement, and FIG. 16B is a time chart for a 4 × enlargement. is there. As shown in the figure, conventionally, even during the vertical enlarged display, the control of the liquid crystal driver including the data driver 83 and the gate driver 84 shown in FIG. 15 is the same as the normal display, but The difference is that the same image data D is stored in the data driver 83.
That is, T is repeatedly read from the memory 87 by the memory control unit 85 'a plurality of times, and the same image data DT is displayed over a plurality of lines on the display screen.

That is, the gate output pulse is sequentially shifted by the timing signal synchronized with the horizontal synchronizing signal, and the output of the data driver 83 is output to each line. Here, the same image data DT is output from the memory 87 a plurality of times.
Is read out and the same image data DT is sent to the data driver 83 over a plurality of horizontal periods, thereby making the display data of a plurality of lines the same and performing an enlarged display in the vertical direction.

That is, as shown in FIG. 7A, when the image is enlarged twice in the vertical direction, the same image data D is read from the memory 87.
By reading T twice and sending out the same image data DT to the data driver 83 twice, the same image data DT is displayed on two lines of the display screen as shown in FIG. Was going on. Similarly, the memory 87 is controlled by the memory control unit 85 'so that the same image data DT is displayed on four lines at the time of 4 times magnification in the vertical direction, and the image data DT on the same line is read four times. The data DT was sent to the data driver 83 four times to display the image in the vertical direction at a magnification of 4 times.

[0017]

However, in the conventional method, as shown in FIG. 15, an A / D converter, a D / A converter, and a memory are provided in order to have a vertically enlarged display function. Also, since a device such as a memory control unit is required, the display device becomes large and complicated, and further, the cost is increased.

In view of the above, the present invention provides a scan electrode drive circuit that enables enlarged display in the vertical direction without using many complicated peripheral devices as described above, and an image display device including the same. To aim.

[0019]

The above problems can be solved by the following scan electrode driving circuit and image display device according to the present invention. That is, in the scan electrode drive circuit according to the first aspect of the present invention, a shift register that generates a plurality of shift pulses by inputting a start pulse and a shift clock, and a shift register that is connected to the shift register and that corresponds to the shift pulse and the display mode. Mode signal is input, and data for one line is output according to the mode signal. A single scan electrode or a plurality of continuous scan electrodes are selected to be driven simultaneously within one horizontal period in which data is output, and the signal is selected. The mode selection circuit section for outputting and the output of the mode selection circuit section connected to the mode selection circuit section, and the voltage for controlling ON / OFF of the switching element connected to the scan electrode is output to the scan electrode connected to the subsequent stage. And a buffer circuit section that operates.

Further, the mode selection circuit section described above receives a plurality of shift pulses and a mode signal from the shift register, selects one of the plurality of shift pulses according to the mode signal, and outputs the selected one to the buffer circuit section. It is characterized by comprising a multiplexer circuit. As yet another aspect, the above-described mode selection circuit unit receives a plurality of shift pulses from the shift register, creates an intermediate signal having a pulse width that is an integral multiple of the pulse width of the shift pulse, and outputs the intermediate signal creation circuit. And a multiplexer circuit that receives the intermediate signal, the shift pulse, and the mode signal, selects one of the intermediate signal and the shift pulse according to the mode signal, and outputs the selected one to the buffer circuit unit. To do.

In the image display device according to the second aspect of the present invention, a changeover switch for changing over and designating the display mode and a display mode setting circuit for setting the display mode according to the changeover of the changeover switch and outputting the mode signal. And a display panel in which the signal electrodes and the scanning electrodes are arranged in a matrix and display pixels are arranged at the intersections of the signal electrodes and the scanning electrodes, and image data sent from the outside is input.
A signal electrode driving circuit for converting the image data into a signal voltage level necessary for driving a display panel and outputting the signal voltage to a signal electrode through a data bus line, and a scanning electrode driven through a gate bus line according to the present invention. The scan electrode driving circuit according to the first aspect of the present invention and a synchronizing signal sent from the outside are input, and a data clock and a latch pulse are output to the signal electrode driving circuit based on the synchronizing signal, and the synchronizing signal and the display mode are displayed. And a timing generation circuit for outputting a start pulse and a shift clock corresponding to the display mode to the scan electrode drive circuit based on the mode signal from the setting circuit.

[0022]

In the scan electrode driving circuit configured as described above, the display mode is set by inputting the mode signal to the mode selection circuit portion provided between the shift register and the output buffer, and the display mode is set to one line. One or more scan electrodes are driven according to the display mode within one horizontal period in which image data is output. Therefore, if one scan electrode is driven in one horizontal period, normal display is performed, and if a plurality of scan electrodes are simultaneously driven in one horizontal period, the same image data for one line is displayed on the display screen. It will be displayed in multiple lines and enlarged in the vertical direction.

Further, in the image display device constructed as described above, the display mode is switched by the changeover switch, and in accordance with this switching, a mode signal corresponding to the display mode is generated from the display mode setting circuit and the scan electrode drive circuit and timing is generated. It is output to the circuit. With this mode signal, the timing generation circuit outputs a shift clock and a start pulse according to the display mode to the scan electrode drive circuit, and the scan electrode drive circuit outputs the mode signal from the display mode setting circuit and the shift clock from the timing generation circuit. Also, by the start pulse, the normal display or the vertically enlarged display is performed by the operation according to the display mode.

[0024]

1 and 2 are views for explaining a gate driver according to a first embodiment of the present invention, which is a gate driver capable of a normal display and a double-magnification display in the vertical direction. Here, FIG. 1 is a block diagram of the gate driver, and FIG. 2 is a time chart showing the operation of the gate driver shown in FIG. Further, in FIG. 2, FIG. 2A shows the normal mode, and FIG. 2B shows the vertically enlarged image in the enlargement mode.

Note that the present invention is intended for enlarged display in the vertical direction, and hereinafter, the expression "enlargement" means "enlargement in the vertical direction" unless otherwise specified. In the figure, 10a is a shift register having n output stages, and 11 is n D-numbers constituting the shift register 10a.
Flip-flop (hereinafter, D-FF), 20a is a mode selection circuit section, 21a is n / 2 gate selection circuits constituting the mode selection circuit section 20a, and 22 is a gate selection circuit 2
2 input OR circuit in 1a, 23 is gate selection circuit 21
a multiplexer circuit in a, a buffer circuit section 30a,
Reference numeral 31 denotes n output buffers forming the buffer circuit unit 30a, X denotes output terminals of the output buffer 31, and the number of output terminals is n. A gate driver 40a is composed of these components.

Further, SP is a start pulse synchronized with the vertical synchronizing signal, CKa and CKa 'are shift clocks, CKa' is a shift clock for enlarged display, M is a mode switching signal, and is generated from the mode switching signal M. and a mode signal m _0, a mode signal m ₀ and a mode signal m ₁ inverted by the inverter is always input to the mode selection circuit section 20a, the logical switching of the mode signal m _0, m _1, normal mode Alternatively, the enlargement mode is set.

Q is the output of the D-FF 11 and A is 2
Output of input OR circuit 22, B is multiplexer circuit 23
, And DT represents image data for one line output from the data driver in one horizontal period. First, as shown in FIG. 1, the gate driver 40a according to the first embodiment of the present invention has a mode between the shift register 10a and the buffer circuit section 30a as compared with the structure of the conventional gate driver shown in FIG. The difference is that the selection circuit section 20a is provided.

The mode selection circuit section 20a includes a plurality of gate selection circuits 21a (n / 2 in the case of this embodiment).
And each gate selection circuit 21a.
Is composed of an OR circuit 22 and a multiplexer circuit 23. The OR circuit 22 has two consecutive D-FF1s.
It is connected to the output terminal of 1 and its two outputs Q are input, and the logical sum whose pulse width is an integral multiple of the output Q is set as the output A.

The multiplexer circuit 23 has one D
One is provided for each -FF11. The output Q of the D-FF11 and the output A of the OR circuit 22 are input to each multiplexer circuit 23, and the corresponding output buffer 31 is connected to the output end. Further, the mode signals m ₀ and m ₁ generated from the mode switching signal M are input to the multiplexer circuit 23, whereby the normal mode or the expansion mode is set, and one of the two inputs is selected. Is used as the output B of the multiplexer circuit 23.

As described above, the gate selection circuit in the mode selection circuit section is provided with a logic circuit such as an OR circuit which outputs a pulse having a pulse width which is an integral multiple of the plurality of input pulses as a logical sum, and a plurality of inputs. A multiplexer circuit for selecting one of the above is provided, and by inputting a mode signal from the outside to this multiplexer circuit, the operation of the shift register and the output of the output buffer are displayed in one-to-one correspondence. It is possible to select a normal mode and an expansion mode in which the same output is provided to two adjacent output terminals of the output buffer.

Next, the operation of the gate driver of this embodiment will be described with reference to FIG. First, the start pulse SP is input from the input terminal, and each time the shift clock CKa is input, the start pulse SP is shifted and D-
The shift pulses Q _{1 to} Q _{n that} are the outputs of the FF 11 are created. Here, it is assumed that the number of outputs of the shift register 10a is n. A mode selection circuit unit 20a is provided at the output stage of the shift register 10a, and the output Q of the D-FF 11 is input to it.

Further, the mode selection circuit section 20a has a structure in which a plurality of gate selection circuits 21a are further arranged in parallel. In the gate selection circuit 21a, a two-input OR circuit 22 is provided, and two OR circuits 22 in the shift register 10a are provided. D-FF11
One is provided for the output of
The logical sum A of the output Q of the shift register 10a is created therein, and the output Q of the shift register 10a and the output A of the OR circuit 22 are input to the multiplexer circuit 23.

That is, D- in the shift register 10a
Flip-flop 11_-2k-1Output Q_2k-1And D-free
Up flop 11_-2kOutput Q_2kIs the mode selection circuit section 2
0a to enter the gate selection circuit in the mode selection circuit section 20a.
Road 21a_-kOR circuit 22 in _-kAnd input it to
Output A whose pulse width is twice the output Q_kCreated by
In addition, the output Q_2k-1And output A_kHas multiplexer times
Road 23_-2k-1Output Q _2kAnd output A_kIs a multiplexer
Circuit 23_-2kAre input respectively.

A mode signal m generated from the mode switching signal M is input to the multiplexer circuit 23, and the display mode is set by this mode signal m.
In the normal mode, the multiplexer circuit 23 selects the output Q of the D-flip-flop 11 as its output B, and in the expansion mode, the multiplexer circuit 23 outputs the output A _k of the OR circuit 22 as its output B. select.
These outputs are converted into a gate drive voltage via the output buffer 31 and output from the output terminal X to the gate bus line.

That is, the mode signals m ₀ and m ₁ generated from the mode switching signal M are the multiplexer circuits 23.
_-2k-1 and _23-2k are always input, and the display mode is set by the logical switching. Mode signal m _0, if it is set to the normal mode by switching the m _1, the multiplexer circuit 23 _-2k-1 as its output B _2k-1, the output Q _2k-1 of _{D-FF11 -2k-1} The multiplexer circuit 23 _-2k selects and outputs the output Q _-2k of the D-FF 11 _-2k as its output B _2k .

On the other hand, when the enlargement mode is set by switching the mode signals m ₀ , m ₁ , both the multiplexer circuits 23 _-2k-1 , 23 _-2k output B _2k-1 ,
The output A _k of the OR circuit 22 _-k is selected and output as B _2k . These outputs are output buffers 31 _-2k-1 , 31 _-2k
Is converted into a gate drive voltage via the output terminal X _2k-1 ,
It is output to the gate bus line from X _2k .

FIG. 2 is a diagram showing a time chart in the gate driver 40a of the first embodiment shown in FIG. 1. FIG. 2 (a) is a time chart in the normal mode, and FIG.
The figure is a time chart in the double display in the enlargement mode.
As shown in FIG. 7A, in the normal mode, as described above, the mode selection circuit unit 20a operates so as to output the shift pulse Q of the corresponding D-FF 11 to the output buffer 31 and the output terminal X. The gate output waveform that appears at is D-
In order to show the waveform synchronized with the shift pulse Q of FF11,
Normal display is performed in which the output of the data driver is sequentially displayed on each line.

On the other hand, as shown in FIG. 7B, the shift clock CKa 'for double display in the enlarged mode has a frequency twice that of the shift clock CKa in the normal mode and one horizontal period corresponds to two cycles. The clock is input. Further, the pulse width of the start pulse SP becomes a pulse synchronized with the shift clock CKa 'when the pulse width is 1/2 of one horizontal period. Therefore, the waveform of the shift pulse is Q ₁ , Q ₂ ,
Continuous pulses such as Q ₃ , ... Are output. For example, when observing the first horizontal period of the first line where the output of the data driver becomes the image data DT ₁ , Q ₁ , Q ₂ within this one horizontal period. 2 consecutive pulses are output. The shift pulses Q ₁ and Q ₂ are input to the OR circuit 22 _-1 ,
A pulse A ₁ having a pulse width twice that of the shift pulse Q is created.

Here, the display mode is the enlargement mode.
Then, the multiplexer circuit 23_-1, 23_-2Is the OR circuit 22
_-1The output from is selected and the multiplexer circuit 23_-1,
23 _-2Output B₁, B₂OR circuit 22_-1Output A₁
Is output. Therefore, the output of the data driver is
Image data DT₁Output in the horizontal period of the 1st line
Terminal X₁, X₂The gate output waveforms appearing in are both output A₁
And the same image data on two adjacent lines.
Data DT₁Is displayed. In this way, the display screen
The image is enlarged and displayed twice.

FIGS. 3 and 4 are views for explaining a gate driver which is a second embodiment of the present invention, and like the first embodiment, a gate which enables a normal display and a double enlarged display. Is a driver. 3 is a block diagram of the gate driver, and FIG. 4 is a time chart showing the operation of the gate driver shown in FIG. Further, in FIG. 4, FIG. 4A shows the normal mode, and FIG. 4B shows the enlarged mode at the time of double magnification display.

In the figure, 10b is a shift register having n output stages, 12 is n D-FFs forming the shift register 10b, 20b is a mode selection circuit section, and 24 is a mode selection circuit section 20b. / 2 MUX, 30b
Is a buffer circuit section, 32 is n output buffers that constitute the buffer circuit section 30b, and 40b is a gate driver configured by these.

Further, SP is a start pulse synchronized with the vertical synchronizing signal, CKb and CKb 'are shift clocks, CKb' is a shift clock for enlarged display, M is a mode switching signal, and is generated from the mode switching signal M. and a mode signal m _0, a mode signal m ₀ and a mode signal m ₁ inverted by the inverter is always input to the mode selection circuit 20b, a logical switching of the mode signal m _0, m _1, normal mode Alternatively, the enlargement mode is set.

Q represents the output of the D-FF 12, C represents the output of the multiplexer circuit 24, and DT represents the image data for one line output from the data driver in one horizontal period. First, as shown in FIG. 3, the gate driver 40b according to the second embodiment of the present invention is different from the gate driver 40a according to the first embodiment shown in FIG. 1 in the configuration of the mode selection circuit section 20b. The mode selection circuit section 20b is composed of only a plurality of multiplexer circuits 24 (n / 2 in this embodiment), and each multiplexer circuit 24 corresponds to the gate selection circuit shown in the first embodiment. There is.

In the case of this embodiment, one multiplexer circuit 24 is provided for two consecutive D-FFs 12, and the input terminal of each multiplexer circuit 24 is the output of two consecutive D-FFs 12. Two outputs Q are connected to the input end and two outputs Q are input, and the output end is connected to the output buffer 32 corresponding to the D-FF 12 in the subsequent stage of the two D-FFs 12 connected to the input end.

Further, the mode signals m ₀ and m ₁ generated from the mode switching signal M are input to the multiplexer circuit 24, whereby the normal mode or the expansion mode is set, and one of the two inputs is set. Is selected as the output C of the multiplexer circuit 24. in this way,
The mode selection circuit section is configured by only a plurality of multiplexer circuits that select one from a plurality of inputs, and the mode signal from the outside is input to this multiplexer circuit, thereby operating the shift register and outputting the output buffer. It is possible to select a normal mode in which the display is in a one-to-one correspondence and an enlargement mode in which the same output is made to two adjacent output terminals of the output buffer.

Next, the operation of the gate driver of this embodiment will be described with reference to FIG. First, the start pulse SP is input from the input terminal, and each time the shift clock CKb is input, the start pulse SP is shifted and D-
The shift pulses Q _{1 to} Q _{n that} are the outputs of the FF 12 are created. Here, it is assumed that the number of outputs of the shift register is n. A mode selection circuit section 20b in which a multiplexer circuit 24 is arranged in parallel is provided at the output stage of the shift register 10b, and the output Q of the D- _FFs 12 _{-2 k-1} and 12 _-2k .
_2k-1 and _Q2k are input to the multiplexer circuit 24- _k in the mode selection circuit unit 20b.

Furthermore, the output Q of the D- _{FF12 -2k-1
In} addition to being input to the multiplexer circuit 24- _k as described above, _2k-1 is directly sent to the output buffer _32-2k-1 without passing through the multiplexer circuit, and the output buffer _32-2k-1.
Output terminal X after being converted to gate drive voltage at _-2k-1
Output from _2k-1 to gate bus line. Further, the mode signals m ₀ and m ₁ generated from the mode switching signal M are always input to the multiplexer circuit 24- _k , and the display mode is set by the logical switching. When the normal mode is set by switching the mode signals m ₀ and m ₁ , the multiplexer circuit 24 _-k outputs the output C
selects the output Q _2k of D-FF12 _-2k output as _k.

On the other hand, the mode signal m₀, m₁For switching
When set to more magnified mode, multiple
Comb circuit 24_-kIs its output C_kAs D-FF12
_-2k-1Output Q_2k-1To output. These outputs
Is the output buffer 32_-2k-1, 32 _-2kDrive through the gate
Converted to dynamic voltage and output terminal X_2k-1, X_2kMore gate bar
It is output to the spline.

FIG. 4 is a diagram showing a time chart in the gate driver 40b of the second embodiment shown in FIG. 3, where FIG. 4 (a) is a time chart in the normal mode, and FIG. 4 (b).
The figure is a time chart in the double display in the enlargement mode.
As shown in FIG. 6A, in the normal mode, as described above, the mode selection circuit unit 20b operates so as to output the shift pulse Q of the corresponding D-FF 12 to the output buffer 32, and the output terminal X. The gate output waveform that appears at is D-
In order to show the waveform synchronized with the shift pulse Q of FF12,
Normal display is performed in which the output of the data driver is sequentially displayed on each line.

On the other hand, as shown in FIG. 7B, the shift clock CKb 'in the double display in the enlarged mode has a frequency twice that of the shift clock CKb in the normal mode and one horizontal period corresponds to two cycles. The clock is input. The shift pulse Q is a pulse whose pulse width is synchronized with the shift clock CKb 'in one horizontal period like the start pulse SP. Therefore, the waveform of the shift pulse Q is the shift clock CK like Q ₁ , Q ₂ , Q ₃ , ....
Pulses that are overlapped with each other by being shifted by one cycle of b ′ are output. For example, when looking at the one horizontal period of the first line where the output of the data driver becomes the image data DT ₁ , the shift pulse Q ₁ , Q ₂ overlaps and is output.

Here, the display mode is the enlargement mode.
Then, the multiplexer circuit 24_-1Is D-FF12_-1from
Selects output and multiplexer circuit 24_-1Output C₁To
Is D-FF12_-1Output Q₁Is output. According to
Then, the output of the data driver is the image data DT₁Becomes 1
Output terminal X in the first horizontal period of the line₁, X₂Appear in
Both gate output waveforms are shift pulse Q ₁The same waveform as
The same image data DT on two adjacent lines.₁Is the table
Shown. In this way, the display screen is doubled
Is displayed.

FIG. 5 to FIG. 7 are views for explaining a gate driver which is a third embodiment of the present invention, and a normal display and 2
It is a gate driver that enables enlarged display of 2 times and 4 times. 5 is a block diagram of the gate driver, FIG. 6 is a diagram for explaining the operation of the multiplexer circuit in FIG.
FIG. 7 is a time chart showing the operation of the gate driver shown in FIG. Further, in FIG. 7, (a) shows the normal mode, and (b) shows the 2 × enlarged display in the enlarged mode.
The figure (c) shows the case of a 4 × magnified display in the magnification mode.

In the figure, 10c is a shift register having n output stages, 13 is n D-FFs constituting the shift register 10c, 20c is a mode selection circuit section, and 21 is a n mode selection circuit section 20c. / 4 gate selection circuits, 25 and 26 are 2-input OR circuits in the gate selection circuit 21, 27 is a multiplexer circuit in the gate selection circuit 21, 30c is a buffer circuit section, and 33 is a buffer circuit section 30c. N output buffers, X is an output terminal of the output buffer 33, and the number of output terminals is n. Reference numeral 40c is a gate driver composed of these components, and 50 is a decoding circuit.

Further, SP is a star that synchronizes with the vertical synchronizing signal.
Pulse, CKc, CKc ', CKc "are shift black
And CKc 'and CKc "are each doubled.
And shift clock at 4 times magnification, M₀, M₁Is the mode
A switching signal is indicated, and the decoding circuit 50 selects a mode selection signal.
Three types of mode signals m input to the road portion 20c₀,
m ₁, m₂Is created and this mode signal m₀, m₁, m
₂Normal mode or expansion by logical switching of
The mode shall be set.

Then, Q is the output of the D-FF 13 and D is 2
The output of the input OR circuit 25, E is the output of the 2-input OR circuit 26, F is the output of the multiplexer circuit 27, and DT is the image data for one line output from the data driver in one horizontal period. First, as shown in FIG. 5, a gate driver 40c according to a third embodiment of the present invention.
The configuration of the mode selection circuit unit 20c is different from that of the first and second embodiments, and the mode selection circuit unit 20c is
Is a plurality of gate selection circuits 21c (n in the case of the present embodiment).
/ 4) are arranged in parallel.

Each gate selection circuit 21c has 2
Types of OR circuits 25 and 26 and multiplexer circuit 2
7, a plurality of first OR circuits 25 are provided in each gate selection circuit 21, and two consecutive D circuits are provided.
-Connected to the output terminal of FF13, the two outputs Q are input and the logical sum whose pulse width is an integral multiple of output Q is output D
I am trying. One second OR circuit 26 is provided for each of the two first OR circuits 25, and two first OR circuits 2 are provided.
The output D of 5 is used as an input, and the logical sum of which the pulse width is an integer multiple of the output D, that is, the output Q is an output E.

Further, the multiplexer circuit 27 has one D
One is provided for each -FF 13, and the output Q of the D-FF 13, the output D of the first OR circuit, and the output E of the second OR circuit are input to each multiplexer circuit 27, and the corresponding output terminals are provided. The output buffer 33 is connected.
Further, the multiplexer circuit 27 has a mode switching signal M
_The mode signals m ₀ , m ₁ , m _{2 obtained} by converting ₀ , M ₁ by the decoding circuit 50 are input, whereby the normal mode or the expansion mode is set, and one of the three inputs is selected. Output from the multiplexer circuit 27
I am trying.

As described above, the gate selection circuit in the mode selection circuit section is output to the gate selection circuit as shown in the first embodiment, and the OR circuit which outputs the pulse width is an integral multiple of the input pulse. A normal mode in which the operation of the shift register and the output of the output buffer are displayed in a one-to-one correspondence by inputting a mode signal from the outside to the multiplexer circuit in a two-stage configuration with a logic circuit such as It is now possible to select a 2x magnification mode in which the same output is output to two adjacent output terminals of the output buffer and a 4x magnification mode in which the same output is output to four consecutive output terminals of the output buffer. There is.

Next, the operation of the gate driver of this embodiment will be described with reference to FIG. First, the start pulse SP is input from the input terminal, and each time the shift clock CKc is input, the start pulse SP is shifted and D-
The shift pulses Q _{1 to} Q _{n that} are the outputs of the FF 13 are created. Here, it is assumed that the number of outputs of the shift register is n. A mode selection circuit section 20c is provided at the output stage of the shift register 10c, and the D-FFs _{13-4K-3 to 13-13} are provided.
Output Q _4k-3 ~Q _4k of _-4K is input to the gate selection circuit 21c _-k in the mode selection circuit section 20c.

Then, in the gate selection circuit 21c- _k , D
-FF13 -4K _-3 (not shown) output Q _4k-3 and D-FF
The output Q _{4k -2} of 13 _-4K-2 is input to the _first OR circuit 25 _-2k-1 , and the output D _2k-1 which is the logical sum thereof is created, while the output Q _4k-2 of D-FF 13 _-4K-1 is generated. Output Q _4k-1 and D-FF13
Input to the output Q _4k Hamou one of the first OR circuit 25 _-2k of _-4K, output D _2k as pulse width is twice the output Q is generated as a logical OR.

Further, the first OR circuit 25_-2k-1And 25
_-2kSecond OR circuit 26 provided at the output end of the_-kHas
First OR circuit 25_-2k-1, 25_-2kOutput D_2k-1Out
Force D _2kIs input and the pulse width is the logical sum of the output D
Output E that is twice, that is, four times output Q_kIs created
It Then, the gate selection circuit 21c_-kMultiplex in
Service circuit 27_-4K-3Output Q to_4k-3, Output D_2k-1And out
Power E_kBut the multiplexer circuit 27_-4K-2Output Q to
_4k-2, Output D_2k-1And output E_kBut multiplexer times
Road 27_-4K-1Output Q to_4k-1, Output D_2kAnd output E_k
But the multiplexer circuit 27_-4KOutput Q to_4k, Output D
_2kAnd output E_kAre input respectively.

Further, the mode switching signals M ₀ , M ₁ are decoded into the mode signals m ₀ , m ₁ , m ₂ by the decoding circuit 50, and the mode signals m ₀ , m ₁ , m ₂ are multiplexed by the multiplexer circuit 27 _-4K-3. It is always input to each of _~ 27 _-4K , and the display mode is set by the logical switching. When the normal mode is set by switching the mode signals m ₀ , m ₁ and m ₂ , the multiplexer circuits 27 _{-4K-3 to} 27 _{-4 K} are output as their outputs F _{4k-3 to} F _4k , respectively. Input D- _{FF13 -4K- 3} ~ 1
Output of 3 _-4K Select and output Q _{4k -3 to} Q _4k .

On the other hand, when the mode signals m ₀ , m ₁ and m ₂ are switched to set the double display of the enlarged mode, the multiplexer circuits 27 _{-4K-3 to} 27 _-4K output the output F _4k-. O input to each as _{3 to} F _4k
Output of R circuit 25 _-2k-1 D _{2k -1} or OR circuit 25 _-2k
Output D _2k is selected and output. Furthermore, the mode signal m
_{When the} quadruple display of the enlargement mode is set by switching ₀ , m ₁ and m ₂ , the multiplexer circuit 27
_{-4K-3 to} 27 _-4K selects and outputs the output E _k of the OR circuit 26 _-k , which is input to each of them, as their outputs F _{4k-3 to} F _4k . These outputs are output buffer 33 _-4K-3
Is converted to a gate drive voltage via .about.33 _-4K and output to the gate bus line from the output terminals X _{4k-3 to} X _4k .

By the operation of the multiplexer circuit described above,
The relationship between the display mode and the output F of the multiplexer circuit 27 is shown in the table of FIG. 7A and 7B are diagrams showing a time chart in the gate driver 40c of the third embodiment shown in FIG. 5, where FIG. 7A is the time chart in the normal mode, and FIG. 7B is the double display in the enlarged mode. The time chart of (4) and (c) are time charts at the time of quadruple display in the enlargement mode.

As shown in FIG. 9A, in the normal mode, as described above, the mode selection circuit section 20c shifts the shift pulse Q of the D-FF 13 individually corresponding to the output buffer 33.
, And the gate output waveform appearing at the output terminal X shows a waveform synchronized with the shift pulse Q of the D-FF 13, a normal display in which the output of the data driver is sequentially displayed on each line is performed.

On the other hand, as shown in FIG. 9B, when the double display is performed in the enlarged mode, the shift clock CKc 'has a frequency twice the shift clock CKc in the normal mode and one horizontal period corresponds to two cycles. The clock is input. Further, since the pulse width of the start pulse SP is ½ of one horizontal period, the shift pulse Q also becomes a pulse synchronized with the shift clock CKc ′ in ½ of the horizontal period. Therefore, the waveform of the shift pulse Q is Q ₁ , Q
_-2 , Q _-3 , ... Continuous pulses are output,
For example, looking at the two first horizontal periods of the first line where the output of the data driver becomes the image data DT ₁ and the second line where the output of the data driver becomes the image data DT ₂ , the Q ₁ and Q ₂ two pulses consecutive is, within one horizontal period of the second line two pulses consecutive of Q _3, Q ₄ are output.

This shift pulse Q₁, Q₂And Q₃,
Q_FourIs the first OR circuit 25_-1And 25_-2To each
Input, the pulse width is twice the shift pulse Q
Space D ₁And D₂Is created. Furthermore, pulse D₁Oh
And pulse D₂Is the second OR circuit 26_-1Enter the
The pulse width is twice the pulse D, that is, 4 times the shift pulse Q.
Doubled pulse E₁Is created. Where the display mode
Is a double display of the enlarged mode,
Road 27_-1~ 27_-FourIs the first OR circuit 25_-1And 25_-2
The output from the multiplexer circuit 27_-1, 27
_-2Output F₁, F₂The first OR circuit 25_-1Output D
₁But the multiplexer circuit 27_-3, 27 _-FourOutput F₃,
F_FourThe first OR circuit 25_-2Output D₂Is output
It

Therefore, in the one horizontal period of the first line in which the output of the data driver becomes the image data DT ₁ , the gate output waveforms appearing at the output terminals X ₁ and X ₂ are both output D _1.
And the same image data DT ₁ is displayed on two adjacent lines. Similarly, in the one horizontal period of the second line in which the output of the data driver becomes the image data DT ₂ , the gate output waveforms appearing at the output terminals X ₃ and X ₄ both have the same waveform as the output D ₂ , so that the two adjacent output waveforms are the same. The same image data DT ₂ will be displayed on the line. In this way, the display screen is enlarged and displayed twice.

On the other hand, as shown in FIG. 7C, the shift clock CKc ″ in the 4 × display in the enlarged mode has a frequency of 4 × the shift clock CKc in the normal mode and one horizontal period corresponds to 4 cycles. Further, since the pulse width of the start pulse SP is ¼ of one horizontal period, the shift pulse Q is also synchronized with the shift clock CKc ″ at a pulse width of ¼ of one horizontal period. It becomes a pulse. Therefore, the waveform of the shift clock Q is Q ₁ ,
Continuous pulses such as Q ₂ , Q ₃ , ... Are output. For example, when looking at one horizontal period of the first line where the output of the data driver becomes the image data DT ₁ , the shift pulse Q
Is ₄ consecutive Q _{1 to} Q ₄ within one horizontal period of the 1st line.
Two pulses are output.

This shift pulse Q ₁ , Q ₂ and Q ₃ ,
Q ₄ is input to the first OR circuits 25 _-1 and 25 _-2 , respectively, to generate pulses D ₁ and D ₂ . further,
The pulse D ₁ and the pulse D ₂ are input to the second OR circuit 26 _-1 to generate the pulse E ₁ . Here, since the display mode is quadruple display of the enlargement mode, the multiplexer circuits 27 _{-1 to} 27 _-4 select the output from the second OR circuit 26 _-1 , and the multiplexer circuits 27 _{-1 to} 27 _-4. Output of F ₁
The output E ₁ of the second OR circuit 26 _-1 is output to -F ₄ .

Therefore, in the one horizontal period of the first line when the output of the data driver becomes the image data DT ₁ , the gate output waveforms appearing at the output terminals X _{1 to} X ₄ are both output E _1.
And the same image data DT ₁ is displayed on four adjacent lines. In this way, the display screen is enlarged four times and displayed. 8 to 10 are diagrams for explaining a gate driver according to a fourth embodiment of the present invention, and like the third embodiment, a gate that enables normal display and double and quadruple enlarged display. Is a driver. Here, FIG. 8 is a block diagram of the gate driver, FIG. 9 is a diagram for explaining the operation of the multiplexer circuit in FIG. 8, and FIG. 10 is a time chart showing the operation of the gate driver shown in FIG. Further, in FIG. 10, (a) shows the normal mode, (b) shows the 2 × magnified display in the enlarged mode, and (c) shows the 4 × magnified display in the enlarged mode.

In the figure, 10d is a shift register having n output stages, 14 is n D-FFs forming the shift register 10d, 20d is a mode selection circuit section, and 21d is a n mode selection circuit section 20d. / 4 gate selection circuits, 28 is a multiplexer circuit in the gate selection circuit 21d, 30d is a buffer circuit section, and 34 is a buffer circuit section 3
The number n of output buffers forming 0d, X is the output terminal of the output buffer 34, and the number of output terminals is n. 40d is a gate driver composed of these components, and 50 is a decoding circuit.

Further, SP is a star that synchronizes with the vertical synchronizing signal.
Pulse, CKd, CKd ', CKd "are shift black
And CKd 'and CKd "are each doubled.
And shift clock at 4 times magnification, M₀, M₁Is the mode
A switching signal is indicated, and the decoding circuit 50 selects a mode selection signal.
Three types of mode signals m input to the road portion 20d₀,
m ₁, m₂Is created and this mode signal m₀, m₁, m
₂Normal mode or expansion by logical switching of
The mode shall be set.

Q represents the output of the D-FF 14, G represents the output of the multiplexer circuit 28, and DT represents the image data of one line output from the data driver in one horizontal period. First, as shown in FIG. 8, in the gate driver 40d according to the fourth embodiment of the present invention, the configuration of the mode selection circuit section 20d is different from that of the first to third embodiments. The section 20d has a configuration in which a plurality of gate selection circuits 21d (n / 4 in the present embodiment) are arranged in parallel.

Each gate selection circuit 21d includes a plurality of multiplexer circuits 28 (three in the present embodiment).
It is composed of. Further, in the case of this embodiment, three multiplexer circuits 28 are provided for four consecutive D-FFs, and the remaining D-Fs except the leading D-FF 14 are provided.
The output Q of the D-FF 14 is input to each of the output terminals of the F14, and the output buffer 34 is connected to the output terminal.

Further, the mode signals m ₀ , m ₁ , m _{2 obtained} by converting the mode switching signals M ₀ , M ₁ by the decoding circuit 50 are input to the multiplexer circuit 28, whereby the normal mode or the expansion mode is set. Is set,
One of two or three inputs is selected and used as the output G of the multiplexer circuit 28. As described above, the gate selection circuit in the mode selection circuit unit is configured to include a plurality of multiplexer circuits that select one from the outputs of the plurality of D-FFs, and a mode signal from the outside is input to the multiplexer circuit. The normal mode in which the operation of the shift register and the output of the output buffer correspond to each other on a one-to-one basis, the double expansion mode in which the same output is made to two adjacent output terminals of the output buffer, and the continuous output buffer It is possible to select a 4x enlargement mode in which the same output is provided to the four output terminals.

Next, the gate dry of this embodiment will be described with reference to FIG.
The operation of B will be described. First, start pulse from the input terminal
Input the shift clock CKd.
The start pulse SP is shifted each time the force is applied, and D-
Shift pulse Q which is the output of FF14₁~ Q_nCreated by
Be done. Here, it is assumed that the number of outputs of the shift register is n.
It A mode selection circuit is provided at the output stage of the shift register 10d.
The portion 20d is provided, and the D-FF 14 is provided._-4K-3~ D-
FF14_-4KOutput Q_4k-3~ Q _4kIs the mode selection circuit unit 2
Gate selection circuit 21d in 0d_-kTo enter.

Then, the gate selection circuit 21d_-kWithin
D-FF14_-4K-2And the corresponding output buffer 34
_-4K-2Between the multiplexer circuit 28_-4K-2But DF
F14_-4K-1And the corresponding output buffer 34_-4K-1
Between the multiplexer circuit 28_-4K-1But D-FF14
_-4KAnd the corresponding output buffer 34_-4KBetween
Chipplexer circuit 28_-4KAre provided respectively.
Chipplexer circuit 28 _-4K-2D-FF14_-4K-3of
Output Q_4k-3And D-FF14_-4K-2Output Q_4k-2Two of
Output is input, multiplexer circuit 28_-4K-1For D
-FF14_{-4K- 3}Output Q_4k-3And D-FF14_-4K-1of
Output Q_4k-1The two outputs of
Road 28_-4KD-FF14_-4K-3Output Q_4k-3And D-
FF14 _-4K-1Output Q_4k-1And D-FF14_-4Kof
Output Q_4k3 outputs are input.

Further, the output Q _{4k-3 of the} D-FF 14 _{-4K -3}
Is the multiplexer circuit 28 _{-4K-2 to} 28 as described above.
In addition to being input to _-4K, sent directly to the output buffer 34 _-4K-3 without going through the multiplexer circuit, the output terminal X _4k-3 after being converted to the gate drive voltage in the output buffer 34 _-4K-3 It is output to the gate bus line. Also,
The mode switching signals M ₀ , M ₁ are decoded by the decoding circuit 50 into the mode signals m ₀ , m ₁ , m ₂ , and the mode signals m ₀ , m ₁ , m ₂ are multiplexer circuits 28 _-4K-2 to _2-4.
It is always input to each of 8 _-4K , and the display mode is set by the logical switching. Mode signal m
_{When the} normal mode is set by switching ₀ , m ₁ and m ₂ , the multiplexer circuit 28 _-4K-2 outputs the output Q _4k-2 of the D-FF _-4K-2 as its output G _4k-2. , The multiplexer circuit 28 _-4K-1 outputs D- as its output G _4k-1.
The output Q _{4k -1} of the FF _-4K-1 is _supplied to the multiplexer circuit 28.
_-4K selects and outputs the output Q _4k of D-FF _-4K as its output G _4k .

On the other hand, the mode signal m₀, m₁, m₂Slice of
If it is set to double display in enlargement mode by changing
The multiplexer circuit 28_-4K-2Is its output G_4k-2
As D-FF_-4K-3Output Q_4k-3The multiplexer
Circuit 28_-4K-1Is its output G _4k-1As D-FF_-4K-1
Output Q_4k-1To the multiplexer circuit 28_-4KIs out
Force G_4kAs D-FF_-4K-1Output Q_4k-1Each selected
Select and output.

Further, when the mode signals m ₀ , m ₁ and m ₂ are switched to set the quadruple display in the enlargement mode, the multiplexer circuits 28 _{-4K-2 to} 28 _-4K all output their output G _4k. Output Q of D-FF _-4K-3 as _{-2 to} G _4k
Select _4k-3 and output. These outputs are converted to a gate drive voltage through the output buffer 34 _-4K-2 ~34 _-4K, is output to the gate bus line from the output terminal X _4k-2 ~X _4k.

By the operation of the multiplexer circuit described above,
The relationship between the display mode and the output G of the multiplexer circuit is shown in the table of FIG. FIG. 10 is a diagram showing a time chart in the gate driver 40d of the fourth embodiment shown in FIG. 8, and FIG. 10 (a) is a time chart in the normal mode,
(B) The figure shows the time chart for the double display in the enlarged mode,
FIG. 7C is a time chart at the time of 4 × display in the enlargement mode.

As shown in FIG. 8A, in the normal mode, as described above, the mode selection circuit section 20d shifts the shift pulse Q of the D-FF 14 individually corresponding to the output buffer 34.
, And the gate output waveform appearing at the output terminal X shows a waveform synchronized with the shift pulse Q of the D-FF 14, so that the normal display in which the output of the data driver is sequentially displayed on each line is performed.

On the other hand, as shown in FIG. 7B, the shift clock CKd 'in the double display in the enlarged mode has a frequency twice the shift clock CKd in the normal mode and one horizontal period corresponds to two cycles. The clock is input. The shift pulse Q is a pulse which has the same pulse width as that of the start pulse SP in one horizontal period and is synchronized with the shift clock CKd '. Therefore, the waveform of the shift pulse Q is the shift clock CK like Q ₁ , Q ₂ , Q ₃ , ....
When overlapping pulses are output with a shift of one cycle of d ′, for example, when two horizontal periods of the first line where the output of the data driver is the image data DT ₁ and the second line where the output is the image data DT ₂ are seen. In the one horizontal period of the first line, the shift pulses Q ₁ and Q ₂ are overlapped and output, and 2
In the first horizontal period of the line, the shift pulses Q ₃ and Q ₄ are overlapped and output.

Here, the display mode is a double table of the expansion mode.
As shown, the multiplexer circuit 28_-2Is the output Q
₁To the multiplexer circuit 28_-3And 28_-FourIs the output Q
₃And the multiplexer circuit 28_-2Output G₂In
D-FF14_-1Output Q₁But the multiplexer circuit 28
_-3, 28_-FourOutput G₃, G_FourD-FF14_-3Output
Q ₃Is output.

Therefore, the output of the data driver is an image.
Data DT₁In the one horizontal period of the first line,
Terminal X₁, X₂The gate output waveform appearing in
Ruth Q₁It has the same waveform as and is the same on two adjacent lines.
Image data DT₁Is displayed. Data dry as well
Output is image data DT₂2nd line 1 horizontal
In the period, output terminal X₃, X_FourOutput waveform appearing in
Together with shift pulse Q ₃Since it has the same waveform as, it is next to
The same image data DT on two lines₂Is displayed
Becomes In this way, the display screen is doubled
Is displayed.

On the other hand, as shown in FIG. 7C, the shift clock CKd ″ in the 4 × display in the enlarged mode has a frequency of 4 times the shift clock CKd in the normal mode and one horizontal period corresponds to 4 cycles. Further, since the pulse width of the start pulse SP is ½ of one horizontal period, the shift pulse Q also has a pulse width of ½ of one horizontal period and is synchronized with the shift clock CKd ″. It becomes a pulse. Therefore, the waveform of the shift clock Q is Q ₁ ,
When pulses such as Q ₂ , Q ₃ , ... Which are shifted and overlapped by one cycle of the shift clock CKd ″ are output, for example, when the output of the data driver sees one horizontal period of the first line of the image data DT ₁ , And the shift pulses Q _{1 to} Q ₄ are overlapped and output.

Since the display mode is the quadruple display of the enlargement mode, the multiplexer circuits 28 _{-2 to} 28 _-4 select the output Q ₁ , and the multiplexer circuits 28 _{-2 to} 28 _-4 output G ₂ to. The output Q ₁ of the D-FF 14 _-1 is output to G ₄ . Therefore, in the one horizontal period of the first line where the output of the data driver becomes the image data DT ₁ , the output terminal X
_The gate output waveforms appearing in _{1 to} X ₄ are both shift pulse Q.
_The waveform is the same as that of _1, and the same image data DT ₁ is displayed on four adjacent lines. In this way, the display screen is enlarged four times and displayed.

In the above example, the double expansion and the four expansion are performed.
I showed a gate driver with a double-magnification display function,
The present invention is not limited to the above-described embodiment, and the mode selection circuit unit is configured to combine a plurality of multiplexer circuits and OR circuits as in the first and third embodiments, so that an enlarged display of an arbitrary integral multiple is possible. A possible gate driver can be configured.

Further, even if the mode selection circuit section is composed of only the multiplexer circuit as in the second and fourth embodiments, a gate driver capable of enlarging display by an arbitrary integral multiple is constructed depending on the construction method. can do. Further, in the above embodiment, the pulse signals are converted into the gate drive voltage by the output buffers 31 to 34 in the buffer circuit section 30 and output, but the present invention is not limited to such a configuration. The pulse signal may be converted into the gate drive voltage before being input to the shift register 10, and the voltage may be output to the gate bus line through the output buffer as it is.

The scan electrode driving circuit according to the present invention can be generally used for matrix-driving display panels such as liquid crystal display panels or plasma display panels, and its use range is limited as long as it is a matrix-driving display panel. Not done. FIG. 11 is a diagram showing an embodiment of the image display device according to the present invention, and shows a liquid crystal display device using a matrix type liquid crystal panel for the display panel.

In the figure, 61 is a liquid crystal display panel, 62 is a data driver, 63 is a gate driver, 64 is a data bus line, 65 is a gate bus line, 66 is a timing generation circuit, and 67 is a display mode setting circuit. Is a liquid crystal display device composed of these. An external image signal generator 68 serves as an image signal source. Also,
SP is a start pulse, CK is a shift clock, DC is a data clock, LA is a latch pulse, DT is image data, TM is a synchronization signal, SW is a changeover switch, and m is a mode signal.

As shown in the figure, a liquid crystal display device 60 according to the present invention is connected by a liquid crystal display panel 61, a data driver 62 connected to the liquid crystal display panel 61 by a data bus line 64, and a gate bus line 65. The selected gate driver 63, the timing generation circuit 66 for outputting various timing signals to the data driver 62 and the gate driver 63, the changeover switch SW for switching between the normal mode and the enlargement mode, and the display for setting the display mode by the changeover switch SW. It has a mode setting circuit 67.

The liquid crystal display panel 61 has a structure in which a plurality of data electrodes and a plurality of gate electrodes are arranged in a matrix, and display pixels using TFTs as switching elements are arranged at the intersections thereof. The data driver 62 is composed of a shift register that performs serial input and parallel output, a latch circuit, and a buffer circuit. Then, the horizontal synchronizing signal and the data clock DC are input from the timing generating circuit 66 to the shift register, the image data DT which is the serial signal from the image signal generating device 68 is converted into a parallel signal, and the image converted into the parallel signal is obtained. The data DT is input to the latch circuit and held for one horizontal period. Further, the held data DT is converted into a display signal voltage corresponding to the image data via the buffer circuit by the latch pulse LA from the timing generation circuit 66, and is output to the data electrode of the liquid crystal display panel 61 via the data bus line 64. To do.

The gate driver 63 is a gate driver according to the first aspect of the present invention and comprises a shift register, a mode selection circuit and a buffer circuit. A start pulse SP and a shift clock CK are input from the timing generation circuit 66 to the gate driver 63, and a logical signal m for setting the display mode is set from the display mode setting circuit 67.
Is entered. The mode signal m is always input to the mode selection circuit in the gate driver 63 to set the display mode, and the operation according to the normal mode or the enlargement mode is performed.

Here, the display mode setting circuit 67 outputs the mode signal m according to the display mode by switching the changeover switch SW, and the gate driver 63 and the timing generation circuit 66 input this mode signal m. Further, the timing generation circuit 66 includes an external image signal generator 68.
To sync signal T including horizontal sync signal, vertical sync signal, etc.
M is input, and the data clock D is output from this synchronization signal TM.
C, a latch pulse LA is generated and output to the data driver 62, and a start pulse SP and a shift clock CK corresponding to the display mode are output to the gate driver 63 by the mode signal m from the display mode setting circuit 67.

As described above, in the liquid crystal display device 60 of this embodiment, the peripheral circuit includes a memory, a memory control circuit,
Alternatively, the enlarged display of the image signal can be performed without providing the A / D conversion circuit and the D / A conversion circuit.
Further, in the liquid crystal display device 60 configured as in this embodiment, any signal source such as a personal computer, a television receiver, a video camera device or a communication circuit device can be connected as an image signal generating device, and a digital signal or an analog signal can be connected. Any of these can be displayed.

Further, these signal sources may not have a magnifying function in the signal source device itself, and, of course, even in the case of image data magnified and displayed from a device having a magnifying function, the display in the normal mode is possible. The enlarged display can be performed by using, and further enlargement can be performed by using the enlargement function of the display device. In addition, since it is possible to connect to a device that generates various image signals, not only for enlarging, but also when the number of scanning lines of an image to be displayed and the number of scanning lines of the display panel are different, It is also possible to display according to the number of scanning lines.

Further, the display panel constituting the image display device of the present invention is not limited to the liquid crystal display panel shown in the above-mentioned embodiment, and any display panel for matrix driving such as plasma display panel can be used. Is possible.

[0100]

According to the scan electrode driving circuit of the present invention, by providing the means for driving a plurality of scan electrodes in one horizontal period in the scan electrode driving circuit, the signal source side does not have a magnifying function. Even if there is, it is possible to perform enlarged display. Further, according to the image display device of the present invention including this drive circuit, since a plurality of scan electrodes are driven when displaying one image data, it is not necessary to convert an analog signal into a digital signal. Therefore, it is not necessary to provide a memory for controlling the memory, a circuit for controlling the memory, a circuit for mutually converting an analog signal and a digital signal, and the size, weight, and cost of the display device can be reduced.

Further, when the signal source is an analog signal, since A / D conversion processing or D / A conversion processing is not performed, signal deterioration does not occur and high quality display quality can be maintained. It is possible. Further, in addition to simply enlarging the display, when the number of scanning lines of the display image and the number of scanning lines of the display panel are different, it is possible to display the image according to the number of scanning lines of the display panel, The image display device has high versatility and can cope with various image signals such as image data having different numbers of scanning lines and signals of different types.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a gate driver that is a first embodiment of the present invention.

2A and 2B are time charts showing the operation of the gate driver according to the first embodiment of the present invention, FIG. 2A is a time chart in a normal mode, and FIG. 2B is a time chart in an enlarged mode. .

FIG. 3 is a configuration diagram of a gate driver that is a second embodiment of the present invention.

4A and 4B are time charts showing the operation of the gate driver according to the second embodiment of the present invention, FIG. 4A is a time chart in a normal mode, and FIG. 4B is a time chart in an enlarged mode. .

FIG. 5 is a configuration diagram of a gate driver which is a third embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between a display mode and an output according to an operation of a multiplexer circuit according to a third embodiment of the present invention.

7A and 7B are time charts showing the operation of the gate driver according to the third embodiment of the present invention, in which FIG. 7A is a time chart in the normal mode, and FIG. 7B is a double time display in the enlarged mode. The time chart, (c) is a time chart at the time of quadruple display in the enlargement mode.

FIG. 8 is a configuration diagram of a gate driver which is a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a relationship between a display mode and an output according to the operation of the multiplexer circuit in the fourth exemplary embodiment of the present invention.

10A and 10B are time charts showing the operation of the gate driver according to the fourth embodiment of the present invention, in which FIG. 10A is a time chart in the normal mode, and FIG. 10B is a double display in the enlarged mode. The time chart, (c) is a time chart at the time of quadruple display in the enlargement mode.

FIG. 11 is a diagram showing an embodiment of an image display device according to the present invention.

FIG. 12 is a diagram illustrating a configuration of a liquid crystal display device.

FIG. 13 is a diagram illustrating a conventional gate driver,
FIG. 7A is a basic configuration diagram of the gate driver, and FIG. 8B is a time chart showing the operation of the gate driver shown in FIG.

FIG. 14 is a block diagram of a control circuit of an analog liquid crystal driver.

FIG. 15 is a block diagram of a control circuit of a conventional liquid crystal driver having a vertical enlargement display function.

16A and 16B are time charts for explaining conventional vertical enlarged display, in which FIG. 16A is a time chart at the time of 2 × enlargement, and FIG. 16B is a time chart at the time of 4 × enlargement.

FIG. 17 is a diagram illustrating display screens of normal display and enlarged display.

[Explanation of symbols]

 10 ... Shift register 11, 12, 13, 14, ... D-flip-flop 20 ... Mode selection circuit section 21 ... Gate selection circuit 22, 25, 26 ... OR circuit 23, 24, 27, 28 ... Multiplexer circuit 30 ... Buffer circuit Parts 31, 32, 33, 34 ... Output buffer 40 ... Gate driver 50 ... Decode circuit 60 ... Image display device 61 ... Liquid crystal display panel 62 ... Data driver 63 ... Gate driver 64 ... Data bus line 65 ... Gate bus line 66 ... Timing Generation circuit 67 ... Display mode setting circuit SW ... Switch m ... Mode signal

Claims (4)

[Claims] 1. A shift register (10) for generating a plurality of shift pulses (Q) by inputting a start pulse (SP) and a shift clock (CK), and the shift pulse connected to the shift register (10). (Q) and a mode signal (m) corresponding to the display mode are input, and a single scan electrode is supplied within one horizontal period during which image data for one line is output according to the mode signal (m). Alternatively, a mode selection circuit unit (20) for selecting a scan electrode and outputting a signal so as to simultaneously drive a plurality of continuous scan electrodes, and a mode selection circuit unit (20) connected to the mode selection circuit unit (20). The buffer circuit section (3) which receives the output of 20) and outputs a voltage for controlling on / off of the switching element connected to the scan electrode to the scan electrode connected to the subsequent stage.
0) and a scan electrode drive circuit. 2. The mode selection circuit section (20) receives a plurality of the shift pulses (Q) and the mode signal (m) from the shift register (10) and receives the mode signal (m) according to the mode signal (m). Multiple shift pulses (Q)
2. The scan electrode drive circuit according to claim 1, wherein the scan electrode drive circuit is configured by a multiplexer circuit that selects one of the above and outputs it to the buffer circuit section (30). 3. The mode selection circuit section (20) receives a plurality of the shift pulses (Q) from the shift register (10) and outputs a pulse width that is an integral multiple of the pulse width of the shift pulse (Q). An intermediate signal creating circuit for creating and outputting an intermediate signal having the intermediate signal, the intermediate signal, the shift pulse (Q), and the mode signal (m), and the intermediate signal and the shift according to the mode signal (m). The scan electrode drive circuit according to claim 1, wherein the scan electrode drive circuit comprises a multiplexer circuit that selects one of the pulses (Q) and outputs the selected pulse to the buffer circuit section (30). 4. A changeover switch (SW) for switching and designating a display mode, and a display mode setting circuit (67) for setting the display mode according to the changeover of the changeover switch (SW) and outputting a mode signal (m). , A display panel (61) in which signal electrodes and scanning electrodes are arranged in a matrix, and display pixels are arranged at intersections of the signal electrodes and scanning electrodes, and image data (DT) sent from the outside are input.
A signal electrode drive circuit (62) for converting the image data (DT) into a signal voltage level necessary for driving the display panel (61) and outputting the signal voltage level to the signal electrode via a data bus line (64); The scan electrode drive circuit (63) according to claim 1, wherein the scan electrode is driven via a gate bus line (65).
And a sync signal (TM) sent from the outside is input, and a data clock (DC) is generated based on the sync signal (TM).
And a latch pulse (LA) are output to the signal electrode drive circuit (62), and a display mode is determined based on the synchronization signal (TM) and the mode signal (m) from the display mode setting circuit (67). A start pulse (SP) and a shift clock (CK) are supplied to the scan electrode driving circuit (6).
An image display device comprising: a timing generation circuit (66) for outputting to 3).