JP2001147674A - Dot matrix display device and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a dot matrix display device and a control method thereof capable of degreasing the number of interface signals without decreasing functions of display modes. SOLUTION: D-FF1 of (n)-pieces are cascaded and an input terminal D of each D-FF is provided with a data selector 2 to control a transfer direction of an output of each D-FF. When a synchronous signal SYNC is inputted to a clock input terminal C of D-FF3 during a blanking period of a clock signal CLK, a change-over control signal DIR is outputted from an output terminal Q, and is given to a select input terminal S of each data selector 2. Then, when a start signal ST is inputted scanning pulses are sequentially outputted to the (n)-pieces of D-FF1 starting with the 1st stage D-FF1 over the last stage D-FF1 according to the number of inputs of the clock signals CLK. The scanning direction is decided according to the polarity of the clock signal CLK in the blanking period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a dot matrix display device for displaying an output image of a computer, a video image of a television broadcast, and the like, and a control method therefor.

[0002]

2. Description of the Related Art A dot matrix display device represented by a liquid crystal display device (LCD) has attracted attention because of its features such as thinness and power saving, and there is an increasing demand for lower cost and higher performance. In particular, a polysilicon TFT-LCD in which a drive circuit is integrally formed is expected as a high display rate and low cost dot matrix display panel.

FIG. 11 is a configuration diagram of a scanning circuit used in a conventional dot matrix display device. Such a scanning circuit includes a D flip-flop (D-F
F) There is generally provided a data selector 2 which can select a data input for bidirectional scanning and a circuit having these circuits connected in a plurality of columns.

[0004] The operation of the scanning circuit thus configured will be described. 12 and 13 are time charts showing the operation of the scanning circuit shown in FIG. First, the output Q1 of the _first stage D-FF1 is converted to the output Q1 of the last stage D-FF1.
_In the case of shifting to _n , the data selector 2 selects the signal at the input terminal A, as shown in FIG.
A switching control signal DIR that changes to L level at ₁ is applied to the input terminal S of each data selector 2. The Figure 12 (a), a gives the clock signal CLK to the level change of H / L from time t ₃ at a predetermined period to the clock input C of the D-FF1. Then, the start signal ST is changed to the state shown in FIG.
At time t ₂ ~t ₃ shown in (b) is changed from L level to H level, the time t ₄ ~t ₅ in changing to the L level, the input terminal A of the first stage of the data selector 2, the last stage data selector 2 to the input terminal B.

[0005] As described above, the clock signal CLK is changed to the state shown in FIG.
By inputting at the timing shown in (a), the outputs Q ₁ , Q ₂ , Q _{3 are} output at the rising edge of the clock signal CLK.
· · · Q _n-1, Q _n becomes between H level for one clock cycle, the H level sequentially pulsed over the output Q _n from the output Q ₁ is shifted. Each D-FF 1 captures input data at the rising edge of the clock signal. In the present invention, a register that captures input data at the rising or falling edge of the CLK input is called a D flip-flop, and a register that captures input data at the high or low level of the CLK input is called a D latch.

[0006] Conversely, when the shift pulse to the output Q ₁ from the output Q _n, as shown in FIG. 13 (c), the time t ₁
Is supplied to the input terminal S of each data selector 2 so that the data selector 2
Set to select the signal of. In this case, FIG.
The start signal ST shown in (b) is applied to the data selector 2 at the same timing as in FIG. Also, the clock signal CLK is applied to each D-phase at the timing shown in FIG.
Give to FF1. In this way, as shown in FIG. 13 (d), it is sequentially pulse output Q ₁ from the output Q _n is shifted. As described above, in the conventional scanning circuit, it is necessary to externally supply the switching control signal DIR of the data selector 2 via the input terminal for bidirectional scanning.

[0007]

However, in the conventional configuration, when a scanning circuit is used in a dot matrix display device, two sets of scanning circuits are used to scan a large number of display pixels in the horizontal and vertical directions. I need. Then, it is necessary to independently switch the scanning direction, and the number of interface signals for generating the switching control signal DIR increases. For this reason, there has been a problem that the number of input terminals increases and the cost of the dot matrix display device increases.

The present invention has been made in view of such conventional problems, and in particular, by reducing the number of interface signals, the number of external input terminals can be reduced.
An object is to realize a dot matrix display device having a simple structure and to embody a control method thereof.

[0009]

According to the first aspect of the present invention, each display pixel is scanned in a horizontal direction or a vertical direction using a scanning circuit on a display panel in which the display pixels are formed in a dot matrix. A method of controlling a dot matrix display device in which a scanning direction is controlled by a display mode signal, wherein the display mode signal is supplied to the scanning circuit during a blanking period of horizontal scanning or vertical scanning of the display panel. It is characterized in that a direction is set.

According to a second aspect of the present invention, a display mode signal is provided for a display panel in which display pixels are formed in a dot matrix by using a scanning circuit to scan each display pixel in a horizontal direction or a vertical direction. A control method of a dot matrix display device that controls a scanning direction by applying a display mode signal to the scanning circuit during a blanking period of a clock signal used for horizontal scanning or vertical scanning of the display panel, and changing a scanning direction. It is characterized by setting.

According to a third aspect of the present invention, a display mode signal is provided when a display circuit scans each display pixel in a horizontal direction or a vertical direction using a scanning circuit on a display panel in which the display pixels are formed in a dot matrix. A dot matrix display device that controls a scanning direction by extracting a display mode signal from a combination of a plurality of signals given during a blanking period of a horizontal scan or a vertical scan of the display panel, and extracting the display mode signal to the scanning circuit. And a display mode signal extracting means for providing the display mode signal.

According to a fourth aspect of the present invention, there is provided a display mode signal for scanning a display panel in which a display pixel is formed in a dot matrix in a horizontal direction or a vertical direction using a scanning circuit. A dot matrix display device that controls the scanning direction by extracting the display mode signal from a combination of a plurality of signals given during a blanking period of a clock signal used for horizontal scanning or vertical scanning of the display panel. And a display mode signal extracting means provided to the scanning circuit.

The invention of claim 5 of the present application is the invention of claim 3 or 4
In the dot matrix display device, the display mode signal extracting means may change an output level of a clock signal supplied during a blanking period of the horizontal scanning or the vertical scanning,
The image processing apparatus further includes a register that captures a horizontal or vertical synchronization signal of the display panel and generates the display mode signal as a signal for instructing a display image on the display panel to be horizontally inverted or vertically inverted.

The invention of claim 6 of the present application is directed to claim 3 or 4
In the dot matrix display device, the display mode signal extracting means may change an output level of a clock signal supplied during a blanking period of the horizontal scanning or the vertical scanning,
The image processing apparatus further includes a register that captures a display start signal of the display panel and generates the display mode signal as a signal for instructing the display image of the display panel to be horizontally inverted or vertically inverted.

According to a seventh aspect of the present invention, a display panel in which display pixels are formed in a dot matrix scans each display pixel in a horizontal direction using a horizontal scanning circuit, and vertically scans using a vertical scanning circuit. When scanning in the direction
A dot matrix display device for controlling a scanning direction by a display mode signal, wherein the horizontal scanning circuit and the vertical scanning circuit are formed on the same substrate as the display panel by the same process.

[0016]

(Embodiment 1) Hereinafter, a dot matrix display device and a control method thereof according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a scanning circuit used in the dot matrix display device according to the present embodiment. This scanning circuit includes n D-FFs 1, n data selectors 2, and one D-FF 3 that generates a switching control signal DIR.

Each D-FF1 has a data input terminal D,
It has an input terminal C for a clock signal CLK and an output terminal Q for data, and is connected in cascade through n data selectors 2. Each data selector 2 has input terminals A and B for data, an input terminal S for a switching control signal DIR, and an output terminal Y for data. The data output terminals Y of the first to n-th data selectors 2 are connected to the data input terminals D of the first to n-th D-FFs 1, respectively.

The signal at the output terminal Q of the first stage D-FF1 is Q ₁
Then, the signal Q ₁ is supplied to the input terminal A of the data selector 2 in the second stage. Similarly the signal Q _i of the output terminal Q of the i-th stage of D-FF1 is (i + 1) th stage of the data selector 2
Is input to the input terminal A. And the D- in the (n-1) th stage
Signal Q _n-1 of the output terminal Q of FF1 is applied to the input terminal A of the data selector 2 for the n-th stage is the last stage. On the other hand, the output signal Q _n of the n-th stage of D-FF1 which is the final stage, (n-
1) given to the input terminal B of the data selector 2 at the stage
Output signal Q _i th stage of D-FF1 is, (i-1) applied to the input terminal B of the stage of the data selector 2, the second-stage D-
The output signal Q ₂ of the FF1 is adapted to be applied to the input terminal B of the first stage of the data selector 2.

There are three interface signals for the scanning circuit: a synchronization signal SYNC, a clock signal CLK, and a start signal ST. The synchronization signal SYNC is D-
It is provided to a clock input terminal C of the FF3. The clock signal CLK is supplied to the data input terminal D of the D-FF3 and the clock input terminal C of the D-FF1 of the first to n-th stages. The start signal ST is supplied to the data input terminal A of the first-stage data selector 2 and the data input terminal B of the n-th data selector 2. In the first to third embodiments, the D-FF 3 extracts the display mode signal from the combination of the interface signals given in the blanking period of the horizontal scanning or the vertical scanning of the display panel, and extracts the display mode signal to be given to the scanning circuit. It has the function of means.

A control method in the scanning circuit having such a configuration will be described with reference to FIGS. Figure 2 is a time chart showing the waveform of each part in the case of operating in (scanned sequentially from Q ₁ toward Q _n) right shifted scanning circuit shown in FIG. 3 is a time chart showing the waveform of each part in the case of operating the scanning circuit in left shift (Q sequential scanning of _n towards the Q _1).

First, a case where the scanning circuit is operated by right shift will be described. In the initial state, as shown at time t ₀ in FIG. 2, clock signal CLK, a start signal ST, the synchronization signal SYNC of (c) in (b) of (a) is L level.
The level of the synchronizing signal SYNC to H at time t ₁ as shown in Figure 2 (c). At this time, since the clock signal CLK is at the L level, the input terminal D of the D-FF 3 is held at the L level, and at the rising of the synchronization signal SYNC, the D-FF 3
Output terminal Q becomes L level. Thus switching control signal DIR as shown in FIG. 2 (d) is locked from time t ₁ to L level. The value is the input terminal S of each data selector 2.
Is set so that the signal of the input terminal A is selected by each data selector 2. Such a switching control signal D
IR controls the scanning direction of a dot matrix display panel, and is also called a display mode signal.

Next, as shown in FIG. 2A, it is assumed that a clock signal CLK is inputted at a constant period from time t ₃ ,
Time t ₃ the first clock signal CLK becomes H level -
For t _4, the start signal ST to the H level.
The start signal ST is supplied to the input terminal A of the first-stage data selector 2 and the input terminal B of the n-th stage data selector 2. The H-level start signal ST is input to the input terminal D of the first-stage D-FF 1 via the first-stage data selector 2. Thus, at time t ₃ the clock signal C
When LK goes to H level, H-level start signal ST
It is taken into D-FF1 in the first stage, the output signal Q ₁ as shown in FIG. 2 (e) has an H level.

[0023] 2 times indicated by the time t ₅ of the clock signal CL
When K is input, the start signal ST has changed to L level, and the output terminal Q of the first stage D-FF1 is at L level. Output signal to Q ₁ H-level at time t ₃ ~t ₅ is supplied to the input terminal A of the data selector 2 in the second stage, the second clock signal C inputted from the time t ₅
From the LK, it is taken into the second stage D-FF1.

When the above operation is repeated, FIG.
Output signal to Q ₁ value as shown in (e) (H level),
Each time the clock signal CLK is input, the second stage D-FF1,
The data is sequentially transferred to the third D-FF1, the fourth D-FF1,..., The n-th D-FF1.

To set the scanning circuit to the left shift, the level of the clock signal CLK is set to H during the blanking period from time t _{1 to} t ₃ in FIG.
The synchronizing signal at time t ₂ as shown in FIG. 3 (c) SY
The NC level is set to H. At this time, the clock signal CLK
Since is H level, the input terminal D is H level D-FF3, at the rising edge of the synchronization signal SYNC time t _2, the output terminal Q of the D-FF3 rises to the H level. Thus, the switching control signal DIR is locked at the H level as shown in FIG. The value is provided to the input terminal S of each data selector 2, and each data selector 2 is set so that the signal of the input terminal B is selected. In such a state, D
-The data transfer direction of FF1 is switched from the nth stage to the first stage. The output signals Q ₁ , Q ₂ ,.
_n is output at a timing as shown in FIG.

[0026] Thus, in D-FF3, the period represented by the time t ₀ ~t ₅ in FIG. 3, i.e. the clock signal CL
During the blanking period of K, an interface signal is taken in, and a switching control signal DIR in the shift direction is generated as a display mode signal of the display panel. The output level of this switching control signal DIR (H /
L) allows the scanning circuit shown in FIG. 1 to perform bidirectional scanning.

As described above, according to the present embodiment, the switching control signal DIR in the scanning direction can be generated from the combination of the synchronization signal SYNC and the clock signal CLK.
It is not necessary to input the switching control signal DIR via the external input terminal.

(Embodiment 2) A dot matrix display device and a control method thereof according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a configuration diagram of a scanning circuit used in the dot matrix display device according to the present embodiment. This scanning circuit corresponds to the first embodiment.
In the same manner as described above, it is configured to include n D-FFs 1, n data selectors 2, and one D-FF 3 for generating the switching control signal DIR. Each D-FF1 and each data selector 2
Is the same as in the first embodiment, and a description thereof will be omitted.

The clock signal CLK and the start signal ST are two interface signals to the scanning circuit.
There is one. The clock signal CLK is supplied to the data input terminal D of the D-FF3 and the clock input terminal C of the D-FF1 of the first to n-th stages.
And given to. The start signal ST is provided to the clock input terminal C of the D-FF 3, the data input terminal A of the first-stage data selector 2, and the data input terminal B of the n-th data selector 2. The output terminal Q of the D-FF 3 is connected to the input terminal S of each of the first to n-th data selectors 2.

A control method in the scanning circuit having such a configuration will be described with reference to FIGS. Figure 5 is a time chart showing the waveform of each part in the case of operating in (scanned sequentially from Q ₁ toward Q _n) right shifted scanning circuit shown in FIG. 6 is a time chart showing the waveform of each part in the case of operating the scanning circuit shown in FIG. 4 at the left-shift (sequential scanning towards for Q ₁ from Q _n).

First, when the scanning circuit is operated by right shift.
Will be described. In the initial state, time t in FIG.₀ As shown
5A shows the clock signal CLK and FIG.
The signal ST is at the L level. As shown in FIG.
Time t₁ To set the level of the start signal ST to H. this
Since clock signal CLK is at L level, DF
The input terminal D of F3 is held at the L level, and the start signal S
At the rise of T, the output terminal Q of the D-FF3 becomes L level.
Become. In this way, as shown in FIG. ₁ Switch with
Control signal DIR is locked at the L level. Its value is
The signal supplied to the input terminal S of the data selector 2
The signal is set to be selected.

[0032] Then the clock signal CLK at a predetermined period from the time t ₂ as shown in FIG. 5 (a) is input. The time t ₂ ~t ₃ the first clock signal CLK becomes H level, the start signal ST is held at H level. The start signal ST is supplied to the data selector 2 of the first stage.
And the input terminal B of the data selector 2 at the n-th stage. The H-level start signal ST is input to the input terminal D of the first-stage D-FF 1 via the first-stage data selector 2. Therefore, when the clock signal CLK goes _high at time t ₂ , the start signal S at high level
T is taken into D-FF1 in the first stage, the output signal Q ₁ as shown in FIG. 5 (d) has an H level at time t _2.

The second clock signal CL shown at time t ₄
When K is input, the start signal ST has changed to L level, and the output terminal Q of the first stage D-FF1 is at L level. Time t ₂ ~t output signal to Q ₁ H-level at ₄ is supplied to the input terminal A of the second stage of the data selector 2, a second input from the time t ₄ the clock signal C
From the LK, it is taken into the second stage D-FF1.

When the above operation is repeated, FIG.
The value of the output signal Q ₁ as shown in (d) (H level),
Each time the clock signal CLK is input, the second stage D-FF1,
The data is sequentially transferred to the third D-FF1, the fourth D-FF1,..., The n-th D-FF1.

To set the scanning circuit to the left shift,
Time t in FIG. 6A which is a part of the blanking period₁ ~
t_Three , The clock signal CLK is set to the H level.
You. Then, as shown in FIG._Two Star from
The level of the trigger signal ST is set to H. At this time, time t_Two Then
Since the clock signal CLK is at the H level, the D-FF3
Becomes high level at time t._Two Start signal
At the rise of ST, the output terminal Q of the D-FF 3 is set at time t._Two 
To H level. Thus, as shown in FIG.
In addition, the switching control signal DIR, which is a display mode signal, is H level.
Locked by the The value is the input of each data selector 2.
Terminal S and set so that the signal at input terminal B is selected.
Is In such a state, the data transfer of the D-FF1 is performed.
The sending direction switches from the nth stage to the D-FF direction of the first stage
Wrong. Output signal Q in this case₁ , Q _Two , ... Q_n Is
It is output at a timing as shown in FIG.

As described above, the D-FF 3 originally captures the interface signal during the blanking period of the clock signal CLK, and generates the switching control signal DIR at the rising edge of the start signal ST. Thus, the scanning circuit can be scanned in both directions.

According to the above embodiment, the switching control signal DIR in the scanning direction can be generated from the combination of the start signal ST and the clock signal CLK. Synchronous signal SY
Even when there is no NC, there is no need to externally input the switching control signal DIR via the external input terminal.

(Embodiment 3) A dot matrix display device and a control method thereof according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a configuration diagram of a scanning circuit used in the dot matrix display device according to the present embodiment. As in the first embodiment, this scanning circuit includes n D-latches 4, n data selectors 2, and one D-FF 3 for generating a switching control signal DIR. Each D latch 4 and each data selector 2
Is the same as in the first embodiment, and a description thereof will be omitted.

There are three interface signals to the scanning circuit: a clock signal CLK, an inverted clock signal / CLK obtained by inverting the polarity of the clock signal CLK, and a start signal ST. The clock signal CLK is D-FF3
, And a clock input terminal G of an odd-numbered D-latch 4 as in the first and third stages.
The inverted clock signal / CLK is supplied to the clock input terminal G of the even-numbered D-latch 4 as in the second and fourth stages. The start signal ST is supplied to the clock input terminal C of the D-FF 3 and the data input terminal A of the first-stage data selector 2.
And the data input terminal B of the data selector 2 at the n-th stage. The output terminal Q of the D-FF 3 is connected to the input terminal S of the data selector 2 of the first to n-th stages.

A control method in the scanning circuit having such a configuration will be described with reference to FIGS. Figure 8 is a time chart showing the waveform of each part in the case of operating in (scanned sequentially from Q ₁ toward Q _n) right shifted scanning circuit shown in FIG. 9 is a time chart showing the waveform of each part in the case of operating the scanning circuit shown in FIG. 7 by a left shift (sequential scanning towards for Q ₁ from Q _n).

First, the case where the scanning circuit is operated in the right shift will be described. In the initial state, as shown at time t ₀ in FIG. 8, the clock signal CLK in (a) is at the L level, the inverted clock signal / CLK in (b) is at the H level, and the start signal ST in (c) is at the L level. . To H level of the start signal ST at time t ₁ as shown in Figure 8 (c). At this time, since the clock signal CLK is at the L level, DF
The input terminal D of F3 is held at the L level, and the start signal S
At the rise of T, the output terminal Q of the D-FF 3 goes to L level. Thus, as shown in FIG.
IR is locked to L level. The value is given to the input terminal S of each data selector 2 and the signal at the input terminal A is set to be selected.

[0042] Next at a fixed period from the time t ₂ as shown in FIG. 8 (a) and the clock signal CLK inverted clock signal / C
LK is input. The time t ₂ ~t ₃ the first clock signal CLK becomes H level, the start signal S
T is held at the H level. This start signal ST
Are supplied to a clock input terminal C of the D-FF 3, an input terminal A of the first-stage data selector 2, and an input terminal B of the n-th stage data selector 2. The H-level start signal ST is input to the input terminal D of the first-stage D latch 4 via the first-stage data selector 2. Therefore, when the clock signal CLK becomes H level at time t _2, the start signal ST at an H level is latched in the D latch 4 in the first stage, the output signal Q ₁ as shown in FIG. 8 (e) is a H-level Become. Since the first inverted clock also signal / CLK is input to the input terminal G to the D latch 4 of the even-numbered stages, the output terminal Q of the D latch 4 of the previous stage is at the L level at time t ₂ ~t ₃ The output of the output terminal Q of the even-numbered D latch 4 remains at the L level.

[0043] In time t ₃ inverted clock signal / CLK is H
When the level changes to the H level, the output signal Q ₁ at the H level is latched by the second stage D latch 4. In On input the second clock signal CLK time t _4, the start signal ST is changed to L level, the output terminal Q of the first stage of D-latch 4 has an L level. The output signal Q ₂ to which is latched in the second stage D-latch 4, during the time t ₃ ~t _5, is held at H level.

When the above operation is repeated, FIG.
Output signal to Q ₁ value as shown in (e) (H level),
Each time the clock signal CLK is input, the second-stage D latch 4
The data is sequentially transferred to the third-stage D-latch 4, the fourth-stage D-latch 4,...

To set the scanning circuit to the left shift, FIG.
As shown at time t ₀ ~t ₂ of (a), to set the level of the clock signal CLK, which is part of the original blanking period H, to set the level of the inverted clock signal / CLK to L. And the level of the start signal ST to H from time t ₁ as shown in FIG. 9 (c). Since this time the time t ₁ the clock signal CLK is at H level, D-FF
The input terminal D of the D-FF 3 goes high, and the output terminal Q of the D-FF 3 goes high at the rise of the start signal ST at time t ₁ . Thus switching control signal DIR as shown in FIG. 9 (d) is locked from time t ₁ to the H level. The value is given to the input terminal S of each data selector 2 and the signal at the input terminal B is set so as to be selected. In such a state, the data transfer direction of the D latch 4 is 1 from the n-th stage.
The direction is switched to the direction of the D latch 4 of the stage. The output signals Q ₁ , Q ₂ ,..., Q _{n in} this case are output at timings as shown in FIG.

Here, the D-FF 3 captures an interface signal during the blanking period of the clock signal CLK or the inverted clock signal / CLK, and generates the switching control signal DIR at the rising edge of the start signal ST. Thus, the scanning circuit can operate bidirectionally.

As described above, according to the present embodiment, even when the register of the scanning circuit is constituted by the D latch, the switching control signal DIR in the scanning direction can be generated from the start signal ST and the clock signal CLK. it can. Then, there is no need to input the switching control signal DIR via the external input terminal. In particular, if the register of the scanning circuit is an even-numbered stage,
By inverting the polarity of the clock signal according to the scanning direction, switching during the blanking period is not required.

(Embodiment 4) Next, a dot matrix display device according to Embodiment 4 of the present invention will be described. FIG. 10 is a configuration diagram of a dot matrix display device according to the present embodiment, in which the scanning circuits described in the first to third embodiments are used for horizontal scanning and vertical scanning.

This dot matrix display device has a pixel array 30 as a dot matrix display,
It is configured to include a scanning line driving circuit 10 and a signal line driving circuit 20 for driving the pixel array 30, and a D-FF 31 and a D-FF 32 for providing a switching control signal to these driving circuits.

The scanning line driving circuit 10 is a circuit for switching and controlling each horizontal scanning line of the pixel array 30 in the vertical direction, and includes a vertical scanning circuit 11 and a vertical driving circuit 12. The signal line drive circuit 20 is a circuit that scans each vertical scan line of the image array 30 in the horizontal direction and supplies a pixel signal to each cell of the image array 30, and includes a horizontal scan circuit 21 and a horizontal drive circuit 22. . Signal line drive circuit 2
The pixel line 30 and the scanning line driving circuit 10 can be formed on the same substrate (glass) and the same process as the pixel array 30 using, for example, a polysilicon thin film.

The D-FF 32 and the horizontal scanning circuit 21 correspond to, for example, the scanning circuit shown in FIG.
CLK and the horizontal start signal HST are provided as interface signals from two input terminals. Also DF
The F31 and the vertical scanning circuit 11 also correspond to, for example, the scanning circuit shown in FIG. 4, and receive a vertical clock signal VCLK and a vertical start signal VST as interface signals from two input terminals.

When the vertical start signal VST is applied to the clock input terminals C of the D-FFs 31 and 32, the switching control in the horizontal direction from the output terminal Q of the D-FF 32 in accordance with the polarity of the horizontal clock signal HCLK during the blanking period. The signal HDIR is output and supplied to the horizontal scanning circuit 21. Similarly, a switching control signal VDIR in the vertical direction is output from the output terminal Q of the D-FF 31 according to the polarity of the vertical clock signal VCLK during the blanking period, and is supplied to the vertical scanning circuit 11. And the horizontal start signal HST
Becomes H level, the horizontal scanning circuit 21 outputs a scanning pulse in synchronization with the horizontal clock signal HCLK, and supplies it to the horizontal driving circuit 22. When the vertical start signal VST is H
When the level becomes the level, the vertical scanning circuit 11 outputs a scanning pulse in synchronization with the vertical clock signal VCLK, and gives it to the vertical driving circuit 12.

With this configuration, the D-FFs 31, 3
In 2, the clock signal VCLK of the vertical scanning circuit 11 and the clock signal HCLK of the horizontal scanning circuit 21 are taken in at the rising edge of the start signal VST. The switching control signal VDIR in the vertical scanning direction and the switching control signal HDIR in the horizontal scanning direction are transmitted to the vertical scanning circuit 10.
And to the horizontal scanning circuit 20, the switching control signal V
External input terminals for DIR and HDIR can be eliminated from the dot matrix display device.

Further, since the number of input terminals of the dot matrix display device can be reduced, the number of input inspection terminals is also reduced, and the scale of a connection jig and the like can be reduced. Therefore, the effect of further reducing the manufacturing cost of the display device can be obtained.

In the first embodiment, the display mode represents the function of inverting the display image vertically or horizontally. However, the display mode can be used for controlling interlaced scanning for enlarging or reducing the display image. . In the above embodiment, the interface signal is inserted during the blanking period of the clock signal CLK.
It is not necessary to limit to LK.

In the third embodiment, during the blanking period, the signal for taking in the display mode is changed to the start signal S.
Although set to T, this is not limited to the start signal ST, and any other signal may be used as long as information can be taken in the blanking period. Further, the register that captures these signals is not limited to the D-FF, and a D-latch or the like may be used depending on the signal form used. In the present embodiment, the number of stages of the D latch 4 is set to an even number, but may be an odd number.

In the fourth embodiment, the switching control signal DIR in the vertical and horizontal scanning directions is generated by the vertical start signal VST.
A configuration using T and HST may be used.

[0058]

As described above, according to the first to sixth aspects of the present invention, the display mode signal is generated by changing the output level in the blanking period with respect to the signal originally used for driving the display panel. I am trying to do it.
Therefore, there is no need to provide a signal for controlling the scanning direction of the display panel by providing an external terminal, and the effect of reducing the number of terminals of the dot matrix display device can be obtained.

According to the seventh aspect of the present invention, the horizontal scanning circuit and the vertical scanning circuit can be formed on the same substrate by the same process, and the peripheral circuit of the display panel can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a scanning circuit used in a dot matrix display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a right shift operation in the scanning circuit according to the first embodiment;

FIG. 3 is a timing chart showing a left shift operation in the scanning circuit according to the first embodiment.

FIG. 4 is a configuration diagram of a scanning circuit used in a dot matrix display device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing a right shift operation in the scanning circuit according to the second embodiment.

FIG. 6 is a timing chart showing a left shift operation in the scanning circuit according to the second embodiment.

FIG. 7 is a configuration diagram of a scanning circuit used in a dot matrix display device in Embodiment 3 of the present invention.

FIG. 8 is a timing chart showing a right shift operation in the scanning circuit according to the third embodiment.

FIG. 9 is a timing chart showing a left shift operation in the scanning circuit according to the third embodiment.

FIG. 10 is a block diagram illustrating a configuration of a dot matrix display device according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram of a scanning circuit used in a conventional dot matrix display device.

FIG. 12 is a timing chart showing a right shift operation in a conventional scanning circuit.

FIG. 13 is a timing chart showing a left shift operation in a conventional scanning circuit.

[Explanation of symbols]

 1, 3, 31, 32 D-FF 2 Data selector 4 D latch 10 Scan line drive circuit 11 Vertical scan circuit 12 Vertical drive circuit 20 Signal line drive circuit 21 Horizontal scan circuit 22 Horizontal drive circuit 30 Pixel array

Claims (7)

[Claims] When a display circuit scans each display pixel in a horizontal direction or a vertical direction using a scanning circuit on a display panel in which the display pixels are formed in a dot matrix, the display mode signal controls the scanning direction. A method of controlling a matrix display device, comprising: providing a display mode signal to the scanning circuit during a blanking period of horizontal scanning or vertical scanning of the display panel to set a scanning direction. Control method. 2. A method of controlling a scanning direction by a display mode signal when a scanning circuit scans each display pixel in a horizontal direction or a vertical direction on a display panel in which the display pixels are formed in a dot matrix. A method for controlling a matrix display device, wherein the display mode signal is supplied to the scanning circuit during a blanking period of a clock signal used for horizontal scanning or vertical scanning of the display panel, and a scanning direction is set. A method for controlling a dot matrix display device. 3. A dot for controlling a scanning direction by a display mode signal when a display circuit scans each display pixel in a horizontal or vertical direction using a scanning circuit on a display panel in which the display pixels are formed in a dot matrix. A matrix display device, comprising: a display mode signal extracting unit that extracts the display mode signal from a combination of a plurality of signals given during a blanking period of horizontal scanning or vertical scanning of the display panel and gives the display mode signal to the scanning circuit. A dot matrix display device comprising: 4. A dot for controlling a scanning direction by a display mode signal when a display circuit scans each display pixel in a horizontal direction or a vertical direction on a display panel formed in a dot matrix using a scanning circuit. A matrix display device, comprising: a display mode for extracting the display mode signal from a combination of a plurality of signals given during a blanking period of a clock signal used for horizontal scanning or vertical scanning of the display panel and giving the display mode signal to the scanning circuit. A dot matrix display device comprising signal extraction means. 5. The display mode signal extracting means captures an output level of a clock signal supplied during a blanking period of the horizontal scanning or vertical scanning by a horizontal or vertical synchronization signal of the display panel, and 5. The dot matrix display device according to claim 3, further comprising a register for generating the display mode signal as a signal for instructing a display image to be horizontally inverted or vertically inverted. 6. The display mode signal extracting means captures an output level of a clock signal supplied during a blanking period of the horizontal scanning or the vertical scanning with a display start signal of the display panel, and displays a display image of the display panel. 5. The dot matrix display device according to claim 3, further comprising: a register for generating the display mode signal as a signal for instructing horizontal inversion or vertical inversion. 7. When a display panel in which display pixels are formed in a dot matrix scans each display pixel in a horizontal direction using a horizontal scanning circuit and scans in a vertical direction using a vertical scanning circuit, 7. A dot matrix display device for controlling a scanning direction by a display mode signal, wherein the horizontal scanning circuit and the vertical scanning circuit are formed on the same substrate as the display panel by the same process. The dot matrix display device according to any one of the above items.