JP2003044013A - Driving circuit, electrode board, and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit, an electrode board, and a liquid crystal display device capable of displaying a high-definition map on a car navigation screen, and displaying a TV image on a TV screen without contraction of a display image. SOLUTION: In the case of displaying a car navigation screen, a scanning signal outputted from each shift register circuit part 201 is outputted to each scanning line sequentially by switching on a NAND circuit 211 of a mode change-over circuit part 202 and switching off an inverter circuit 212 by a display change-over signal. In the case of displaying a TV image, the scanning signal outputted from each shift register circuit part 201 is thinned out every other signal and a single scanning signal is outputted to two scanning lines at the same time by switching off the NAND circuit 211 of the mode change- over circuit part 202 and switching on the inverter circuit 212 by a display mode change-over signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit, an electrode substrate, and a liquid crystal display device, and more particularly, to a scan line drive circuit for outputting a scan signal to a scan line, and the scan line drive circuit on the same substrate as a pixel portion. The present invention relates to a formed array substrate and an active matrix type liquid crystal display device including the array substrate.

[0002]

2. Description of the Related Art A liquid crystal display device is widely used as a display device for a portable information terminal because of its characteristics of low power consumption in addition to being thin and lightweight. Above all, a thin film transistor (TF) is provided for each pixel arranged in a matrix.
The active matrix type liquid crystal display device provided with the switching element composed of T) is used in a field requiring a high-definition display image because it is excellent in color development and has less afterimage. In recent years, a scanning line driving circuit that supplies a scanning signal to a switching element, a signal line driving circuit that supplies a video signal to a pixel electrode via a signal line, and the like are integrally formed on an insulating substrate on which pixels are formed. A liquid crystal display device with a built-in drive circuit has also been developed.

[0003]

By the way, one of the applications of the liquid crystal display device is an in-vehicle monitor. Such a vehicle-mounted monitor is required to have a function of displaying both a car navigation screen and a TV screen. Generally, since the car navigation screen has a higher resolution than the TV screen, when the car navigation screen is displayed on the liquid crystal monitor for the TV screen, the resolution becomes low and there is a problem that a detailed map cannot be displayed. Further, when a TV screen is displayed on a liquid crystal monitor for a car navigation screen having a high resolution, the display screen is reduced in size, making it difficult to see the screen.

It is an object of the present invention to display a high-definition map on a car navigation screen and to display a TV image on the TV screen without reducing the display screen. An object is to provide a liquid crystal display device.

[0005]

In order to achieve the above object, the invention according to claim 1 is a shift register circuit for sequentially transferring a scanning signal by a plurality of stages of transfer circuits and outputting each of the transfer circuits, i ( An odd-numbered stage transfer circuit and a transmission gate type first NAND circuit that receives the outputs of the (i-1) th stage transfer circuit as two inputs, and the output of the i-th stage transfer circuit to the output side of the first NAND circuit. A first circuit provided with a transmission gate type first inverter circuit for inputting; a transmission circuit type second NAND circuit for inputting an output of the (i + 1) th stage transfer circuit and the i stage stage transfer circuit to two inputs; a second transmission gate type inverter circuit for inputting the output of the i-th stage transfer circuit to the output side of the second NAND circuit;
Circuits are alternately arranged, and when the first display mode is selected by a display mode switching signal that controls ON / OFF of the transmission gate, the first and second display circuits are selected.
A NAND circuit is turned on, the first and second inverter circuits are turned off, and the result of NAND operation of the outputs of the i-th stage transfer circuit and the i−1-th stage transfer circuit is the first stage of the i-th stage. The signal is output as a scanning signal from the circuit, and the i +
The NA of the outputs of the first-stage transfer circuit and the i-th stage transfer circuit
The result of the ND operation is output as a scanning signal from the second circuit of the (i + 1) th stage, and the second mode is output by the display mode switching signal.
When the display mode is selected, the NAND circuit is turned off,
Turning on the first and second inverter circuits, inputting the output of the i-th stage transfer circuit to the output sides of the first and second NAND circuits via the first and second inverter circuits, respectively, A drive circuit comprising a mode switching circuit for outputting a scanning signal from the i-th first circuit and the (i + 1) -th second circuit.

In a preferred form, the shift register circuit is composed of a half clock type shift register.

As a preferred form, the first display mode is a display mode for a car navigation screen having a large number of scanning lines, and the second display mode is a display screen for a TV screen having a smaller number of scanning lines than the car navigation screen. Mode.

In a preferred form, the display mode switching signal is a high level or low level DC signal.

[0009] As a preferred form, High or Low
A NAND circuit having two inputs of the level shut signal and the scanning signal output from the mode switching circuit is arranged in the subsequent stage of the mode switching circuit, and the scanning signal is output by inputting the high level shut signal at all times. Tolerate,
The output of the scanning signal is suppressed by inputting a low level shut signal for a predetermined period immediately after the power is turned on.

According to a second aspect of the present invention, in the first aspect, when the first display mode is selected by the display mode switching signal, the pulse waveform of the scanning signal output from the i-th stage first circuit is changed. The pulse waveform of the scanning signal output from the i + 1th stage second circuit is cut by the pulse cut output signal from the i-1th stage second circuit, and the pulse waveform of the scanning signal output from the i + 1th stage pulse is output from the i-th stage first circuit. When the second output mode is selected by the display mode switching signal, the pulse waveform of the scanning signal output from the i-th stage first circuit is changed to the i-th second stage The pulse cut output signal from one circuit is cut, and the pulse waveform of the scanning signal output from the second circuit at the i + 1th stage is cut by the pulse cut output signal from the second circuit at the (i-1) th stage. pulse Characterized by comprising the Tsu bets circuit.

Further, in order to achieve the above-mentioned object, claim 3
In the invention, a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a pixel portion in which a pixel electrode is arranged through a switching element in the vicinity of each intersection of the two lines, A signal line driving circuit for supplying a signal, and a scanning line driving circuit configured by the driving circuit according to claim 1 or 2, wherein the scanning line driving circuit selects the first display mode by the display mode switching signal. When scanning, every scanning line (G
1, G2, ... Gn), and when the second display mode is selected by the display mode switching signal, the two scanning lines are simultaneously (G1 + G2, G3 + G).
4, ... Gn-1 + Gn) is an electrode substrate which outputs a scanning signal.

Further, in order to achieve the above object, claim 4
According to another aspect of the present invention, there is provided a first substrate including the electrode substrate according to claim 3, a second substrate on which a counter electrode facing the pixel electrode is formed, and a liquid crystal layer held between the two substrates. The line driving circuit outputs a scanning signal for each scanning line (G1, G2, ... Gn) when the first display mode is selected by the display mode switching signal output from the external driving circuit, and The liquid crystal display device is characterized in that when the second display mode is selected by the display mode switching signal, the scanning signal is output simultaneously with the two scanning lines (G1 + G2, G3 + G4, ... Gn-1 + Gn).

In a preferred form, a control signal and a display mode switching signal are supplied to the scanning line drive circuit of the first substrate,
Further, an external drive circuit that supplies a control signal and a video signal to the signal line drive circuit is provided. As the control signal, for example, a horizontal start signal XST, a horizontal clock signal XCK, etc. are supplied to the signal line drive circuit. Further, the scanning line driving circuit is supplied with a vertical start signal YST, a vertical clock signal YCK, a shut signal YSHUT, a display mode switching signal ENA, and the like.

In order to achieve the above object, the invention of claim 5 is such that a scan signal sequentially transferred by a plurality of transfer circuits is output from each output stage, a first shift register circuit, and a scan signal from the output stage is input. In the transmission gate type buffer circuit, the scanning signal from the output stage is output as its own output when the first display mode is selected by the display mode switching signal that controls ON / OFF of the transmission gate. Also, a first drive circuit having a first buffer circuit that makes an output in a floating state when the second display mode is selected by the display mode switching signal, and a scan signal obtained by sequentially transferring scan signals by a plurality of transfer circuits. , A second shift register circuit that outputs from each output stage, and a transmission gate type that receives the scanning signal from the output stage In the two buffer circuits, when the first display mode is selected by the display mode switching signal that controls the on / off of the transmission gate, the output is brought into a floating state, and by the display mode switching signal, the second display mode. When is selected, a second drive circuit having a buffer circuit that outputs the scanning signal from the output stage to the output of the self stage and the next stage is provided.

In a preferred form, the first shift register circuit and the second shift register circuit are composed of a half clock type shift register.

According to a sixth aspect of the present invention, in the fifth aspect, a pulse cut circuit is provided for cutting the pulse waveform of the scanning signal output from the output stage with the pulse cut output signal from the preceding output stage. And

In order to achieve the above object, the invention of claim 7 is such that a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a pixel is provided near each intersection of the two lines through a switching element. 7. A pixel portion in which electrodes are arranged, a signal line drive circuit which supplies a video signal to the signal line, and
And a scanning line driving circuit configured by the driving circuit according to claim 1,
When the display mode is selected, every scanning line (G
1, G2, ... Gn), and when the second display mode is selected by the display mode switching signal, the two scanning lines are simultaneously (G1 + G2, G3 + G).
4, ... Gn-1 + Gn) is an electrode substrate which outputs a scanning signal.

In a preferred form, the first drive circuit and the second drive circuit which form the scanning line drive circuit are arranged at both ends of the pixel portion.

Further, in order to achieve the above object, claim 8
According to another aspect of the present invention, there is provided a first substrate including the electrode substrate according to claim 7, a second substrate on which a counter electrode facing the pixel electrode is formed, and a liquid crystal layer held between the two substrates. The line driving circuit outputs a scanning signal for each scanning line (G1, G2, ... Gn) when the first display mode is selected by the display mode switching signal output from the external driving circuit, and The liquid crystal display device is characterized in that when the second display mode is selected by the display mode switching signal, the scanning signal is output simultaneously with the two scanning lines (G1 + G2, G3 + G4, ... Gn-1 + Gn).

In a preferred form, a control signal and a display mode switching signal are supplied to the scanning line drive circuit of the first substrate,
Further, an external drive circuit that supplies a control signal and a video signal to the signal line drive circuit is provided. As the control signal, for example, a horizontal start signal XST, a horizontal clock signal XCK, etc. are supplied to the signal line drive circuit. Further, the first drive circuit that constitutes one of the scanning line drive circuits is supplied with, for example, a vertical start signal YST, a vertical clock signal YCK, a shut signal YSHUT, a display mode switching signal ENA, and the other of the scanning line drive circuits. The vertical drive signal YST, the vertical clock signal YCK, the shut signal YSHUT, the display mode switching signal ENB, and the like are supplied to the second drive circuit constituting the above.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A case where the drive circuit, electrode substrate and liquid crystal display device according to the present invention are applied to an active matrix type liquid crystal display device will be described below.

[First Embodiment] In the first embodiment, an example in which one scanning line drive circuit can switch between two display modes will be described.

FIG. 2 is a block diagram showing a schematic configuration of the liquid crystal display device according to the first embodiment.

The pixel array section 101 includes a plurality of signal lines S.
1, S2, ... Sm (hereinafter, generically S) and a plurality of scanning lines G
1, G2, ... Gn (hereinafter collectively referred to as G) are wired so as to cross each other, and a pixel transistor 106 as a switching element is arranged at each intersection of these two lines. The gate of the pixel transistor 106 is commonly connected to the scanning line G for each horizontal line, and the source is commonly connected to the signal line S for each vertical line. Further, the drain is connected to the pixel electrode 107 (and an auxiliary capacitance not shown). The counter electrode 108 electrically opposed to the pixel electrode 107 is formed on a counter substrate (not shown) arranged to face the array substrate 104, and a liquid crystal layer 109 is held between the two substrates. Note that the pixel array section constitutes the pixel section in this embodiment.

The signal line drive circuit 102 is composed of a shift register, a level shifter, a buffer circuit, etc. (not shown), and sequentially samples the video signal to the corresponding signal line S according to various timing signals supplied from an external drive circuit 105 described later. To do.

The scanning line driving circuit 103 is composed of a shift register circuit section 201, a mode switching circuit section 202, etc., which will be described later, and sequentially outputs scanning signals to the scanning lines G in accordance with various timing signals supplied from the external driving circuit 105. To do. In the scanning line driving circuit 103 of the present embodiment, the scanning line driving circuit 103 receives a display mode switching signal ENA (/ ENA), which will be described later, sent from the external driving circuit 105 for each scanning line (G1,
The first display mode in which a scanning signal is output to G2, ... Gn and two scanning lines simultaneously (G1 + G2, G3 + G4 ,.
Gn-1 + Gn) is configured to be able to switch between two display modes of the second display mode in which a scanning signal is output to (Gn-1 + Gn). In the present embodiment, the first display mode is the display mode of the car navigation screen, and the second display mode is the TV.
Set the screen display mode.

The external drive circuit 105 is the array substrate 104.
The signal line drive circuit 102 is a control circuit arranged outside.
Is a horizontal start signal XST, a horizontal clock signal XCK
A vertical start signal YST, a vertical clock signal YCK, a shut signal YSHUT described later, and a display mode switching signal ENA are supplied to the scanning line drive circuit 103. A video signal supplied from the outside is supplied to the signal line drive circuit 102 via a video bus (not shown) via the external drive circuit 105 (or not).

FIG. 1 is a circuit diagram of the scanning line drive circuit 103. The scanning line drive circuit 103 includes a shift register circuit unit 201, a mode switching circuit unit 202, a shut circuit unit 203, a level shifter circuit unit (L / S) 204, a pulse cut circuit unit 205, and a buffer circuit unit 206. The configuration of each of the above parts will be described below. However, in FIG. 1, a range surrounded by a solid line frame is set as a circuit unit of each of the above-described units, and one of them will be described as a representative.

The shift register circuit section 201 is a circuit for sequentially transferring the vertical start signal YST supplied from the external drive circuit 105 at the timing of the vertical clock signals YCK and / YCK and outputting it as a scanning signal for each stage. ,
Inverter circuit 207 with transmission gate,
It is composed of 208 and inverter circuits 209 and 210. Among them, the inverter circuits with transmission gates 207 and 208 are CMOs as shown in FIG.
It is composed of an S circuit. P-ch and n- shown in FIG.
ch transmission gate uses vertical clock signal Y
ON / OFF is controlled by CK and / (inversion) YCK. Further, the vertical start signal YST is input to IN.

In FIG. 1, p-c of the inverter circuit 207 is shown.
The h and n-ch transmission gates are written as
The p-ch and n-ch transmission gates of the inverter circuit 208 are denoted by. The vertical clock signal YCK is applied to the n-ch transmission gate marked with and the p-ch transmission gate marked with, and to the p-ch transmission gate marked with n and the n-ch transmission gate marked with. / YCK is input respectively.

As shown in the timing chart of FIG.
The vertical start signal YST sequentially transferred at the timing of the vertical clock signals YCK and / YCK is the output stage 2 of FIG.
, 221, ..., 225 are output as scanning signals with a phase difference of half a clock.

The shift register circuit unit 201 is the transfer circuit in this embodiment, and the plurality of shift register circuit units 201 constitute the shift register circuit in this embodiment.

The mode switching circuit section 202 is a circuit for switching the output format of the scanning signal according to the display mode switching signal ENA (/ ENA), and includes a NAND circuit 211 with a transmission gate, an inverter circuit 212 with a transmission gate, and an inverter. And a circuit 213. Of these, the NAND circuit 211 is connected so that the outputs from its own output stage and the preceding output stage are input to two input terminals. In addition, the inverter circuit 212
Is 2 scanning lines (G1 + G2, G3 + G4, ... Gn
−1 + Gn) corresponding to two mode switching circuit units 202
When paired, odd-numbered stages (G1, G3, G5, ...)
The scanning signal output from the output stage of each inverter circuit 2
They are connected via 12 so as to enter the output side of each NAND circuit 211.

The NAND circuit 211 and the inverter circuit 212 in the solid line frame shown in FIG. 1 are the second NAND circuit and the second inverter circuit, respectively, in this embodiment, and the mode switching circuit section 202 including these circuits is It constitutes the first circuit in the present embodiment. Further, the NAND circuit 211 and the inverter circuit 212 located on the left side of the mode switching circuit unit 202 are the first NAND circuit and the first inverter circuit in this embodiment, and the mode switching circuit unit 202 including these circuits is the main circuit. It constitutes the second circuit in the embodiment. Further, the plurality of mode switching units 202 constitutes the mode switching circuit in this embodiment.

According to the above configuration, in the two mode switching circuit sections 202 corresponding to the two scanning lines, the NA is set.
When the ND circuit 211 is turned on and the inverter circuit 212 is turned off, the scanning signals output from the output stage of the self stage and the output stage of the preceding stage are input to each NAND circuit 211 with a phase difference of a half clock. It is output as a scanning signal for each scanning line. Further, when the NAND circuit 211 is turned off and the inverter circuit 212 is turned on, 1 output from the odd-numbered output stages (G1, G3, G5, ...) Is output.
One scanning signal is supplied to the output side line of each NAND circuit 211, and two scanning lines are simultaneously output.

The NAND circuit 211 with a transmission gate is composed of a CMOS circuit as shown in FIG. Then, the p-ch and n-ch transmission gates have the display mode switching signals ENA, / (inversion).
ON / OFF is controlled by ENA. Further, the output from the shift register circuit section of the own stage is input to IN1, and the output from the shift register circuit section of the previous stage is input to IN2. Further, the inverter circuit 212 with a transmission gate is composed of a CMOS circuit as shown in FIG.

In the mode switching circuit section 202 of FIG.
The p-ch and n-ch transmission gates of the NAND circuit 211 are denoted by, and p of the inverter circuit 212 is
-Ch and n-ch transmission gates are marked as. The display mode switching signal ENA is given to the n-ch transmission gate marked with and the p-ch transmission gate marked with, and the p-ch transmission gate marked with and the n-ch transmission gate marked with In / ENA
Are input respectively.

The display mode switching signal ENA supplied from the external drive circuit 105 is a high level or low level DC signal. Therefore, if the display mode switching signal ENA is High level, / ENA becomes Low level, and if the display mode switching signal ENA is Low level, / ENA becomes High level. In the present embodiment, in the car navigation screen display mode, the display mode switching signals ENA = H and / ENA = L are set, and the TV
In the screen display mode, the display mode switching signal ENA =
L and / ENA = H.

The High level is the first potential in this embodiment, and the Low level is the second potential in this embodiment.

The shut circuit unit 203 is a circuit for temporarily stopping the function of the scanning line driving circuit 102, and N
It is configured by an AND circuit 214. The H or L level shut signal YSHUT is input to one input end of the NAND circuit 214, and the scanning signal output from the mode switching circuit unit 202 of its own stage is input to the other input end. Normally, the shut circuit unit 203 is supplied with an H level shut signal YSHUT, and the mode switching circuit unit 202
The scanning signal output from is directly sent to the level shifter circuit section 204 in the subsequent stage. On the other hand, the shut signal YSHUT of L level is given for a predetermined period immediately after the power is turned on,
During this period, the scanning signal is not output so that an unnecessary image is not displayed.

The level shifter circuit section 204 is a circuit for boosting the amplitude of the scanning signal sent through the shut circuit section 203 to a voltage required for driving the pixel transistor.

The pulse cut circuit unit 205 is a circuit for preventing pulse waveforms of scanning signals output to adjacent scanning lines for each line (or for every two lines) from overlapping due to variations in transistors, and NOR Circuit 215,
It is composed of an inverter circuit 216 and inverter circuits 217 and 218 with a transmission gate.
Among these, the inverter circuits with transmission gates 217 and 218 are composed of CMOS circuits as shown in FIG.

In the pulse cut circuit unit 205 of FIG. 1, the p-ch and n-ch transmission gates of the inverter circuit 217 are denoted by, and the inverter circuit 21
The eight p-ch and n-ch transmission gates are marked as. The display mode switching signal ENA is given to the n-ch transmission gate marked with and the p-ch transmission gate marked with, and the p-ch transmission gate marked with and the n-ch transmission gate marked with In /
ENA is input respectively.

A plurality of pulse cut circuit units 205
Constitute a pulse cut circuit in the present embodiment.

The buffer circuit section 206 outputs the scanning signal output from the pulse cut circuit section 205 to each scanning line G1, G1.
2, ... A circuit for outputting to Gn, and an inverter circuit 21
It is composed of nine.

Next, in the scanning line driving circuit 102 configured as described above, there are a case where the car navigation screen is displayed in the first display mode and a case where the TV screen is displayed in the second display mode. Each operation will be described. Note that, here, only the operation of the main circuit unit among the above units will be described.

First, when the car navigation screen is displayed, the display mode switching signals ENA = H and / ENA = L are set as shown in the timing chart of FIG. In each mode switching circuit unit 202, the NAND circuit 21 of each stage is
Since 1 is on and the inverter circuit 212 is off, for example, the scanning signal output from the output stage 221 is input to one input end of the NAND circuit 211, and the scanning signal from the output stage 222 is input to the other end of the NAND circuit 211. It will be input to the input end with a phase difference of half a clock. As a result,
In the mode switching circuit unit 202, the output is valid only while both of the input terminals of the NAND circuit 211 are at the H level, and as shown in FIG. 5, every scanning line (G1, G2, G1).
The scanning signal is output to.

At this time, in the pulse cut circuit section 205, since the display mode switching signals ENA = H and / ENA = L, the inverter circuit 218 is turned on and the inverter circuit 217 is turned off. For this reason, the pulse waveform of the output signal of its own stage is cut by the pulse waveform of the output signal of the preceding stage, and the waveform is output as the scanning signal.

The output signal of its own stage is a scanning signal, and the output signal of the preceding stage is a scanning signal output from the preceding stage, which means the pulse cut output signal in this embodiment.

On the other hand, when the TV screen is displayed, the screen shown in FIG.
As shown in the timing chart of, the display mode switching signals ENA = L and / ENA = H. In each mode switching circuit unit 202, since the NAND circuit 211 of each stage is turned off and the inverter circuit 212 is turned on, for example, the output stage 221
The scanning signal output from the above is not input to the NAND circuit 211 but is input to the inverter circuit 212 of the mode switching circuit 202 corresponding to the scanning lines G1 and G2 at the same time. As a result, the output stage 211 is output from each of the mode switching circuit units 202 corresponding to the scanning lines G1 and G2.
The same output that is input from will be taken out,
Simultaneous two scanning lines (G1 + G2, G3 + G4, ... Gn
The scan signal is output to (-1 + Gn).

At this time, in the pulse cut circuit section 205, since the display mode switching signals ENA = L and / ENA = H, the inverter circuit 218 is turned off and the inverter circuit 217 is turned on. Therefore, the pulse waveform of the output signal of the self stage is cut with the pulse waveform of the output signal of the previous stage, and the waveform is output as the scanning signal.

According to the scanning line driving circuit 103 of the first embodiment, when the car navigation screen is displayed, by setting the display mode switching signals ENA = H and / ENA = L, every scanning line ( Since a scanning signal can be output to G1, G2, ... Gn), high-definition map display can be performed. Also, when displaying the TV screen,
By setting the display mode switching signals ENA = L and / ENA = H, two scanning lines simultaneously (G1 + G2, G3 + G).
4, ... Gn-1 + Gn), a TV signal can be displayed without reducing the display screen.

Further, since the pulse cut circuit section 205 outputs the waveform obtained by cutting the pulse waveform of the output signal of its own stage with the pulse waveform of the output signal of the preceding stage or the preceding stage, as a scanning signal, one line is generated due to variations in transistors. It is possible to prevent the pulse waveforms of the scanning signals output to the scanning lines adjacent to each other (or every two lines) from overlapping. Therefore, display unevenness does not occur, and insufficient writing of the video signal to the selected pixel does not occur, so that good display quality can be obtained.

[Second Embodiment] In the second embodiment, two scanning line driving circuits corresponding to the display mode are arranged, and only the scanning line driving circuit corresponding to the selected display mode is operated so that the two display modes are realized. An example of enabling switching of will be described.

FIG. 7 is a block diagram showing a schematic configuration of the liquid crystal display device according to the second embodiment. 7, the same parts as those in FIG. 2 are indicated by the same reference numerals. Here, the description of the pixel array 101 and the signal line driving circuit 102 is omitted.

The scanning line driving circuits 301 and 303 are composed of a shift register circuit section 401 described later, etc., and sequentially output scanning signals to the scanning lines G in accordance with various timing signals supplied from the external driving circuit 305. The scanning line driving circuits 301 and 303 are arranged at both ends of the scanning line G. The scanning line driving circuit 301 is configured to scan each scanning line (G
1, G2, ... Gn) is a drive circuit that operates in the first display mode to output a scan signal to the scan line drive circuit 303.
Scans two scan lines simultaneously (G1 + G2, G3 + G4, ...
Gn-1 + Gn) is a drive circuit that operates in the second display mode that outputs a scanning signal to (Gn-1 + Gn). The operation of the two scanning line drive circuits is performed by the display mode switching signals ENA (/ ENA) and ENB (/ EN) sent from the external drive circuit 305.
It is switched by B). In the present embodiment, the first display mode is the car navigation screen display mode, and the second display mode is the TV screen display mode.

In FIG. 7, the scanning line drive circuit 30
The positional relationship between 1 and the scanning line driving circuit 303 may be reversed.

The external drive circuit 305 is arranged on the array substrate 104.
The signal line drive circuit 102 is a control circuit arranged outside.
Is a horizontal start signal XST, a horizontal clock signal XCK
The vertical start signal YST, the vertical clock signal YCK, and the shut signal YSH are supplied to the scanning line driving circuit 301.
The UT and the display mode switching signal ENA are supplied. Further, the scanning line drive circuit 303 is supplied with a vertical start signal YST, a vertical clock signal YCK, a shut signal YSHUT, and a display mode switching signal ENB. Further, a video signal supplied from the outside is supplied to the signal line drive circuit 102 via a video bus (not shown) via the external drive circuit 305 (or not).

FIG. 8 is a circuit configuration diagram of the scanning line drive circuit 301. The scanning line drive circuit 301 includes a shift register circuit unit 401, a shut circuit unit 402, a level shifter circuit unit (L / S) 403, a pulse cut circuit unit 404, and a buffer circuit unit 405. Hereinafter, the configuration of each unit will be described. In FIG. 8, a range surrounded by a solid line frame is set as a circuit unit of each unit, and one of the units will be described as a representative. The configurations of the shut circuit unit 402 and the level shifter circuit unit 403 are the same as those of the shut circuit unit 20 of FIG.
3, the description is omitted because it is the same as the level shifter circuit unit 204.

The shift register circuit section 401 is a circuit for sequentially transferring the vertical start signal YST supplied from the external drive circuit 305 at the timings of the vertical clock signals YCK and / YCK. In the present embodiment, one is provided for every two stages. One scanning signal is output. The shift register circuit unit 401 includes transmission gate type inverter circuits 406 and 407 and an inverter circuit 4
And 08. Among these, the transmission gate type inverter circuits 406 and 407 are composed of CMOS circuits as shown in FIG. The p-ch and n-ch transmission gates shown in FIG. 3 are turned on / off by the vertical clock signals YCK, / (inversion) YCK.
Off is controlled. In addition, the vertical start signal YS
T is input.

In FIG. 8, the pc of the inverter circuit 406 is
The h and n-ch transmission gates are written as
The p-ch and n-ch transmission gates of the inverter circuit 407 are denoted by. The vertical clock signal YCK is applied to the n-ch transmission gate marked with and the p-ch transmission gate marked with, and to the p-ch transmission gate marked with n and the n-ch transmission gate marked with. / YCK is input respectively.

The shift register circuit section 401 is the transfer circuit in this embodiment. Then, the plurality of shift register circuit units 401 constitute the first shift register circuit in this embodiment.

The pulse cut circuit section 404 is composed of a NOR circuit 410 and inverter circuits 411 and 412, and cuts the pulse waveform of the output signal of its own stage in the NOR circuit 410 with the pulse waveform of the output signal of the preceding stage. This prevents the scanning signals output to the adjacent scanning lines from overlapping.

The output signal of its own stage is a scanning signal, and the output signal of the preceding stage is a scanning signal output from the preceding stage, which means the pulse cut output signal in this embodiment.

The buffer circuit section 405 is a circuit for outputting the scanning signal output from the pulse cut circuit section 404 to G1, G2, ... Gn for each scanning line, and is composed of a transmission gate type inverter circuit 413. There is. The inverter circuit 413 is a C circuit as shown in FIG.
The display mode switching signal ENA (or / ENA) is input to the n-ch transmission gate and the p-ch transmission gate.

The buffer circuit section 405 is the first buffer circuit in this embodiment. The scanning line drive circuit 301 including the shift register circuit unit 401 and the buffer circuit unit 405 constitutes the first drive circuit in this embodiment.

FIG. 9 is a circuit configuration diagram of the scanning line drive circuit 303. The scanning line drive circuit 303 includes a shift register circuit section 501, a shut circuit section 502, a level shifter circuit section (L / S) 503, a pulse cut circuit section 504, and a buffer circuit section 505. Hereinafter, the configuration of each unit will be described. In FIG. 9, a range surrounded by a solid line frame is a circuit unit of each unit, and one of the units will be described as a representative. The configurations of the shut circuit unit 502 and the level shifter circuit unit 503 are the same as those of the shut circuit unit 20 of FIG.
3, the description thereof is omitted because it is the same as the level shifter circuit section 204, and the description of the pulse cut circuit section 504 is omitted because it is the same as that of the pulse cut circuit section 404 of FIG.

The shift register circuit section 501 is a circuit for sequentially transferring the vertical start signal YST supplied from the external drive circuit 305 at the timings of the vertical clock signals YCK and / YCK. In this embodiment, one is provided for every two stages. One scanning signal is output. The shift register circuit unit 501 includes transmission gate type inverter circuits 506 and 507 and an inverter circuit 5
And 08. Among them, the transmission gate type inverter circuits 506 and 507 are composed of CMOS circuits as shown in FIG. In Figure 9,
The p-ch and n-ch transmission gates of the inverter circuit 506 are denoted by, and the p-ch and n-ch transmission gates of the inverter circuit 507 are denoted by. The vertical clock signal YCK is applied to the n-ch transmission gate marked with and the p-ch transmission gate marked with, and to the p-ch transmission gate marked with n and the n-ch transmission gate marked with. / YCK
Are input respectively. However, the scanning line driving circuit 303
YCK (/ YCK) given to YCK (/ YCK) shown in FIG. 12 is shown in the timing chart of FIG.
It is 1/2 of the frequency of CK).

The shift register circuit section 501 is the transfer circuit in this embodiment. Then, the plurality of shift register circuit units 501 configure the second shift register circuit in this embodiment.

The buffer circuit section 505 is a circuit for outputting the scanning signal output from the pulse cut circuit section 504 to two scanning lines simultaneously (G1 + G2, G3 + G4, ... Gn-1 + Gn), and a transmission gate type inverter circuit 511. , 512. The inverter circuits 511 and 512 are CMOS circuits as shown in FIG.
The display mode switching signal ENB (or / ENB) is input to each of the n-ch transmission gate and the p-ch transmission gate.

The plurality of buffer circuit sections 505 are the second buffer circuits in this embodiment. The scanning line drive circuit 303 including the shift register circuit section 501 and the buffer circuit section 505 constitutes the second drive circuit in this embodiment.

Next, in the scanning line drive circuits 301 and 303 configured as described above, the car navigation screen in the first display mode and the TV screen in the second display mode are displayed. The operation in this case will be described. Note that, here, only the operation of the main circuit unit among the above units will be described.

When the car navigation screen is displayed, as shown in the timing chart of FIG. 12, the display mode switching signal ENA is sent to the scanning line driving circuit 301.
= H, / ENA = L is supplied to the scanning line driving circuit 303, the display mode switching signal ENB = H, / ENB =
L (not shown) is supplied.

At this time, in the buffer circuit section 405 of the scanning line drive circuit 301, the inverter circuit 413 is turned on by the display mode switching signal ENA, so that the scanning signals output from the shift register circuit section 401 every two stages are: Figure 1
As shown in FIG. 2, every scanning line (G1, G2, ... G
n). On the other hand, in the buffer circuit portion 505 of the scanning line driving circuit 303, the inverter circuits 511 and 512 are turned off by the display mode switching signal ENB, so that the output of the buffer circuit portion 505 is in a floating state.

As described above, during the display of the car navigation screen, the scanning line driving circuit 301 outputs a scanning signal for each scanning line, while the scanning line driving circuit 303 is in a stopped state. .

In the case of displaying the TV screen, the display mode switching signal ENA = to the scanning line driving circuit 301.
L, / ENA = H (not shown) is supplied to the scanning line drive circuit 303, as shown in the timing chart of FIG. 13, the display mode switching signals ENB = L, / ENB =
Supply H.

At this time, in the buffer circuit section 505 of the scanning line driving circuit 303, the inverter circuits 511 and 512 are turned on by the display mode switching signal ENB, so that the scanning signal output from the shift register circuit section 501 every two stages. Shows two scanning lines simultaneously (G1 + G
2, G3 + G4, ... Gn-1 + Gn). On the other hand, since the inverter circuit 413 of the scan line driver circuit 301 is turned off, the output of the buffer circuit portion 405 is in a floating state.

As described above, during the period of displaying the TV screen, the scanning line driving circuit 303 outputs the scanning signals for two scanning lines simultaneously, while the scanning line driving circuit 301 is in the stopped state.

The scanning line driving circuit 301 of the second embodiment,
According to 303, when the car navigation screen is displayed, the display mode switching signals ENA = H, / ENA = L,
Further, by setting the display mode switching signals ENB = H and / ENB = L, the scanning line driving circuit 301 outputs a scanning signal for each scanning line (G1, G2, ... Gn), and the scanning line driving circuit 303. Since it can be stopped, high-definition map display can be performed. When displaying the TV screen, the display mode switching signal ENA = L,
/ ENA = H, and display mode switching signal ENB = L, /
By setting ENB = H, the scanning line driving circuit 303 simultaneously scans two scanning lines (G1 + G2, G3 + G4, ... G).
Since the scanning signal can be output to (n-1 + Gn) and the scanning line driving circuit 301 can be stopped, a TV image can be displayed without reducing the display screen.

In particular, the scanning line drive circuit 30 of the second embodiment
1 and 303, the circuit configuration can be simplified and the circuit design can be facilitated as compared with the scanning line driving circuit 103 of the first embodiment.

The pulse cut circuit units 404 and 504 are also provided.
In this case, since the waveform obtained by cutting the pulse waveform of the output signal of its own stage with the pulse waveform of the output signal of the preceding stage is output as the scanning signal, it is output to the scanning line adjacent to each line (or every two lines) due to the variation of the transistor. It is possible to prevent the pulse waveforms of the scanning signals to be overlapped. Therefore, uneven display does not occur, and insufficient writing of the video signal to the selected pixel does not occur,
A good display quality can be obtained.

By the way, as a conventional example related to the liquid crystal display devices of the above-described first and second embodiments, Japanese Patent Laid-Open No. 6-950 is known.
In Japanese Patent Publication No. 71, a technique is proposed in which one liquid crystal display device can perform various kinds of driving such as interlaced driving, simultaneous driving of two lines, and sequential driving.

However, in the liquid crystal display device disclosed in Japanese Unexamined Patent Publication No. 6-95071, the signal waveform of the control signal is changed for each of odd and even fields when two lines are simultaneously driven (same for interlace driving). Must be,
In particular, when performing sequential scan driving, it is necessary to input a control signal having a clock waveform synchronized with the shift pulse, and therefore, there is a problem that an external circuit for supplying this control signal has a heavy load. On the other hand, the first and second embodiments described above
In any of the liquid crystal display devices, the display mode switching signal is a high-level or low-level DC signal in any driving method, and the control signal can be supplied more easily than in the conventional example, so that the load on the external circuit is reduced. can do.

The scanning line drive circuit of each embodiment does not have to be formed integrally with the pixel array section 101 on the array substrate 104. For example, it may be arranged on the external drive circuit together with the signal line drive circuit.

Further, the scanning line drive circuit of each embodiment is
Besides being applied to a liquid crystal display device or its electrode substrate, for example, a flat display device having a structure in which an organic EL is formed on an electrode substrate, or a flat display device having a structure in which an organic EL is held between opposed electrode substrates. Can also be applied to.

[0086]

As described above, according to the present invention,
When displaying a car navigation screen, high-definition map display can be performed by outputting a scanning signal for each scanning line, and when displaying a TV screen, scanning signals are output simultaneously for two scanning lines. By doing so, it becomes possible to display the TV image without reducing the display screen. Therefore, in the vehicle-mounted monitor to which the present invention is applied, a display image suitable for both the car navigation screen and the TV screen can be obtained on one monitor screen.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a scanning line drive circuit according to a first embodiment.

FIG. 2 is a block diagram showing a schematic configuration of the liquid crystal display device according to the first embodiment.

FIG. 3 is a circuit configuration diagram showing a specific example of a transmission gate type inverter circuit.

FIG. 4 is a circuit configuration diagram showing a specific example of a transmission gate type NAND circuit.

FIG. 5 is a timing chart when a car navigation screen is displayed in the first embodiment.

FIG. 6 is a timing chart when a TV screen is displayed in the first embodiment.

FIG. 7 is a block diagram showing a schematic configuration of a liquid crystal display device according to a second embodiment.

FIG. 8 is a circuit configuration diagram of a scanning line drive circuit according to a second embodiment.

FIG. 9 is a circuit configuration diagram of a scanning line drive circuit according to a second embodiment.

FIG. 10 is a circuit configuration diagram showing a specific example of a transmission gate type inverter circuit.

FIG. 11 is a circuit configuration diagram showing a specific example of a transmission gate type inverter circuit.

FIG. 12 is a timing chart when a car navigation screen is displayed in the first embodiment.

FIG. 13 is a timing chart when a TV screen is displayed in the first embodiment.

[Explanation of symbols]

101 ... Pixel array section, 102 ... Signal line drive circuit, 10
3, 301, 303 ... Scan line drive circuit, 104 ... Array substrate, 105, 305 ... External drive circuit, 201, 40
1, 501 ... Shift register circuit section, 202 ... Mode switching circuit section, 203, 402, 502 ... Shut circuit section,
204, 403, 503 ... Level shift circuit section, 20
5, 404, 504 ... Pulse cut circuit section, 206, 4
05,505 ... Buffer circuit unit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 660 G09G 3/20 660C F term (reference) 2H093 NA79 NC09 NC11 NC22 NC34 ND60 5C006 AA01 AA02 AB01 AF45 AF47 BB16 BC03 BF26 BF27 FA04 5C080 AA10 BB05 DD21 EE17 EE21 GG07 GG08 JJ02 JJ03 JJ04 KK20

Claims (8)

[Claims] 1. A shift register circuit for sequentially transferring a scanning signal by a plurality of stages of transfer circuits and outputting each of the transfer circuits, an output of an i (odd) stage transfer circuit, and an output of the (i-1) th stage transfer circuit. First transmission gate type with two inputs
A first circuit including a NAND circuit and a transmission gate type first inverter circuit for inputting an output of the i-th stage transfer circuit to an output side of the first NAND circuit;
A second transmission gate type NA having two inputs, i + 1 stage transfer circuit and the i stage transfer circuit
The output of the ND circuit and the transfer circuit of the i-th stage is connected to the second N
A second circuit having a transmission gate type second inverter circuit input to the output side of the AND circuit and a second circuit are alternately arranged, and a first display is performed by a display mode switching signal for controlling ON / OFF of the transmission gate. When the mode is selected, the first and second NAND circuits are turned on, the first and second inverter circuits are turned off, and the outputs of the i-th stage transfer circuit and the i-1th stage transfer circuit are output. The result of the NAND operation is output from the first circuit of the i-th stage as a scanning signal, and the result of the NAND operation of the outputs of the i + 1-th stage transfer circuit and the i-th stage transfer circuit is the i + 1-th stage of the first circuit. Two circuits output the scanning signals, and when the second display mode is selected by the display mode switching signal, the NAND circuit is turned off, and the first and second inverters are turned off. And the output of the transfer circuit of the i-th stage is input to the output sides of the first and second NAND circuits via the first and second inverter circuits, respectively, and the first circuit of the i-th stage is turned on. And a mode switching circuit for outputting as a scanning signal from the second circuit of the (i + 1) th stage. 2. When the first display mode is selected by the display mode switching signal, the pulse waveform of the scanning signal output from the first circuit in the i-th stage is changed to the second waveform in the (i-1) th stage.
While cutting with the pulse cut output signal from the circuit,
The pulse waveform of the scanning signal output from the i + 1-th stage second circuit is cut by the pulse-cut output signal from the i-th stage first circuit, and the second display mode is selected by the display mode switching signal. In this case, the pulse waveform of the scanning signal output from the i-th stage first circuit is cut by the pulse-cut output signal from the i-2 stage first circuit, and the i + 1-th stage second circuit is also cut. The pulse waveform of the scanning signal output from
The drive circuit according to claim 1, further comprising a pulse cut circuit that cuts with a pulse cut output signal from the second circuit of the first stage. 3. A pixel section in which a plurality of signal lines and a plurality of scanning lines are arranged orthogonal to each other, and a pixel electrode is arranged in the vicinity of each intersection of the two lines via a switching element, and the signal line. A signal line drive circuit for supplying a video signal, and
Or a scanning line driving circuit configured by two driving circuits, wherein the scanning line driving circuit outputs a scanning signal for each scanning line when the first display mode is selected by the display mode switching signal. An electrode substrate, which outputs a scanning signal simultaneously with two scanning lines when the second display mode is selected by the display mode switching signal. 4. A first substrate comprising the electrode substrate according to claim 3, and a second substrate on which a counter electrode facing the pixel electrode is formed.
The scanning line driving circuit includes a substrate and a liquid crystal layer held between the substrates. When the first display mode is selected by a display mode switching signal supplied from the outside, the scanning line driving circuit is arranged for each scanning line. A liquid crystal display device, wherein a scanning signal is output to and a scanning signal is output simultaneously to the two scanning lines when the second display mode is selected by the display mode switching signal. 5. A first shift register circuit which outputs a scanning signal sequentially transferred by a plurality of transfer circuits from each output stage, and a transmission gate type buffer circuit which receives the scanning signal from the output stage as an input. When the first display mode is selected by the display mode switching signal for controlling the on / off of the transmission gate, the scanning signal from the output stage is used as the output of its own stage, and the second display mode is generated by the display mode switching signal. A first drive circuit having a first buffer circuit that makes the output in a floating state when is selected, and a second shift circuit that outputs a scan signal obtained by sequentially transferring scan signals by a plurality of transfer circuits from each output stage. A register circuit, and two transmission gate type buffer circuits which receive the scanning signal from the output stage, The output is set to a floating state when the first display mode is selected by the display mode switching signal that controls the on / off of the transmission gate, and the output is set when the second display mode is selected by the display mode switching signal. A second drive circuit including a buffer circuit that outputs a scanning signal from the stage to the output of the self stage and the next stage. 6. The drive circuit according to claim 5, further comprising a pulse cut circuit that cuts a pulse waveform of the scanning signal output from the output stage with a pulse cut output signal from the preceding output stage. . 7. A pixel portion in which a plurality of signal lines and a plurality of scanning lines are arranged so as to be orthogonal to each other, and a pixel electrode is arranged in the vicinity of each intersection of the two lines through a switching element, and the signal line. A signal line drive circuit for supplying a video signal, and
Or a scanning line driving circuit configured by a driving circuit of 6, wherein the scanning line driving circuit outputs a scanning signal for each scanning line when the first display mode is selected by the display mode switching signal. An electrode substrate, which outputs a scanning signal simultaneously with two scanning lines when the second display mode is selected by the display mode switching signal. 8. A first substrate comprising the electrode substrate according to claim 7, and a second substrate on which a counter electrode facing the pixel electrode is formed.
The scanning line driving circuit includes a substrate and a liquid crystal layer held between the substrates. When the first display mode is selected by a display mode switching signal supplied from the outside, the scanning line driving circuit is arranged for each scanning line. A liquid crystal display device, wherein a scanning signal is output to and a scanning signal is output simultaneously to the two scanning lines when the second display mode is selected by the display mode switching signal.