JP2001343921A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device whose power consumption is reduced and in which a display defect is prevented from being generated by stopping clock pulses which are supplied to drivers in a non-display period when display is not performed. SOLUTION: In this display device, a gate driver 50 supplying a gate signal which is connected to plural gate signal lines 51 and a drain driver 60 supplying a drain signal which is connected to plural drain signal lines are arranged on an insulating substrate 10 and power consumption by oscillation of clock pulses CKH1, CKH2 which are supplied to respective divers is reduced by fixing the clock pulses at prescribed voltages in a horizontal flyback period and stopping the oscillating of the pulses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display device having a shift register of a drain driver or a gate driver driven by a clock pulse.

[0002]

2. Description of the Related Art In recent years, a thin film transistor (hereinafter, referred to as "T
FT ”. ) Is provided, and a display device such as a liquid crystal display device provided with a shift register is being developed for the peripheral drive circuit.

FIG. 5 shows an equivalent circuit diagram of a conventional liquid crystal display device.

[0004] As shown in FIG.
A plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal on the insulating substrate 10;
A plurality of drain signal lines 61 connected to a drain driver 60 for supplying a drain signal are arranged, and the display pixel 20 near the intersection of the two signal lines 51 and 61 is arranged.
In the 0 region, a TFT 70 connected to both of the signal lines 51 and 61 and a display electrode 8 connected to the TFT 70 are provided.
0 is arranged.

A driver scan LSI 91 is provided on an external circuit board 90 separate from the insulating board 10.

The driver scan LSI 91 includes:
As shown in a block diagram of a drive circuit for driving the liquid crystal display device of FIG. 3, a timing controller is provided. A level shifter 93 is provided before the input of the drain driver 60.

Each signal is externally input to the driver scan LSI 91 via a wiring 92, and start signals STV and STV are output from the driver scan LSI 91.
TH is input to the gate driver 50 and the drain driver 60, respectively, and the video signal is transmitted to the data line 62.
Is input to

The sampling pulses SP1, SP2,... Output from the shift register of the drain driver 60
In accordance with the timing of SPn, sampling transistors SPT1, SPT2,.
By sequentially turning on the SPTn, the data signal line 62
Is supplied to each drain signal line 61.

Each of the sampling transistors SPT1 and SPT1 in response to a sampling signal based on a start signal STH.
PT2 turn on, and the video signal of the data line 62 is supplied to the drain signal line 61. Further, a gate signal generated in response to the start pulse STV or the like supplied to the gate driver 50 is input from the gate signal line 51 to the gate electrode 13 of each TFT 70, and
Turns on. Thereby, a video signal is applied to the display electrode 80 via the TFT 70. At the same time, a video signal is also applied to the auxiliary capacitor 85 via the TFT 70 in order to hold the voltage applied to the display electrode 80 for one field period. One electrode 86 of the storage capacitor 85 is a TFT
70 and the other electrode 87
, A common potential is applied to each display pixel 200.

A counter electrode 81 facing the display electrode 200 is connected to a common potential Vcom.

When a video signal is applied to the liquid crystal 21 by opening the gate of the TFT 70, the video signal must be held for one field period. However, the voltage of the signal is gradually reduced with the lapse of time using only the liquid crystal. .
Then, it appears as display unevenness, and good display cannot be obtained. Therefore, an auxiliary capacitor 85 is provided to hold the voltage for one field period.

The voltage applied to the display electrode 80 is
, The liquid crystal 21 is oriented according to the voltage to obtain a display.

FIG. 3 is a block diagram of a driving circuit for driving the liquid crystal display device.

As shown in FIG. 1, a timing controller to which an external video signal is input, and various timing signals from the timing controller, for example, clock pulses CKH1 and CKH2 and a start pulse STH
1, a level shifter for converting the level of STH2, a shift register for driving based on various level-shifted timing signals, and a liquid crystal display for displaying on each display pixel by a video signal sampled by a sampling pulse from the shift register. Consists of panels.

[0015]

Here, the timing of stopping the conventional clock pulses CKH1 and CKH2 will be described.

FIG. 7 shows the relationship between a conventional clock pulse and an LCD panel. In the same figure, the clock pulse is one of the clock pulses CKH1 and CKH2.
Only one is shown.

As shown in FIG. 1, a video signal supplied from the outside comprises a video signal period V1 in a display period and a horizontal retrace period V2 in a non-display period. The case where the clock pulse is stopped in the middle of the video signal period in the scanning period is shown.

The clock pulses CKH1 and CKH2 are output throughout the display period and the non-display period of the video signal, and are supplied to the drain driver 60.

A start pulse is generated based on a clock pulse, and is a pulse for starting sampling of a video signal. When the start pulse is input to the drain driver 60, the start pulse is sequentially transmitted from the first shift register constituting the drain driver 60 to the next. It is conveyed to Dan.

FIG. 3B shows a case where the clock pulse is stopped during the display period in one horizontal scanning period in which the video signal shown in FIG. FIGS. 8C to 8I show start pulses SRSTH1 to SRSTH1 to 7 sequentially sent to the next-stage shift register in the shift resist based on the start pulse STH. That is, a case is shown in which the start pulse SRSTH in the shift register is supplied up to the seventh pulse, not supplied to the eighth pulse, and the display is stopped.

As shown in FIG. 7, the clock pulse CKH
Stops in the middle of one horizontal scanning period, the start pulse SRSTH7 in the shift register remains on. That is, since the sampling switch for supplying the data signal to the seventh shift register (the drain signal line in the seventh column) is turned on, the data signal is continuously supplied to the drain signal, and the signal is supplied to the display electrode. Since the information is supplied, the display is kept displayed during that time.

Then, as shown in FIG. 2J, in the liquid crystal display device having the gate driver 50, the drain driver 60 and the display area 201 on the insulating substrate 10, the drain signal of the seventh pulse of the clock pulse is outputted. The voltage is still applied to each display electrode connected to the line, and the area 202 has a disadvantage that the luminance is different from that of the other display area 201 and a vertical line defect appears. .

Therefore, the present invention has been made in view of the above-mentioned conventional disadvantages, and stops the clock pulse supplied to the driver during the non-display period, thereby reducing power consumption and saving the entire display device. It is an object of the present invention to provide a display device in which power consumption is reduced and a timing at which the clock pulse is stopped is set to a non-display period, thereby preventing a region having a higher or lower luminance than another display region from being generated. Aim.

[0024]

A display device according to the present invention comprises a plurality of gate signal lines and a plurality of drain signal lines arranged crossing each other, and each crossing of the two signal lines connected to the two signal lines. A switching element disposed in the vicinity of the switching element, a display electrode connected to the switching element, a gate driver for supplying a scanning signal to the gate signal line, and sampling a video signal supplied from the outside to the drain signal line. A drain switch comprising a sampling switch to be applied, a horizontal shift register for sequentially turning on the sampling switch, and a precharge circuit for supplying a precharge voltage of the same polarity as a voltage applied to the display electrode to the drain signal line Wherein the signal output from the drain driver to the display electrode is stopped, The voltage from Yaji circuit and supplies to the display electrode.

Further, the above-described display device is a display device in which a signal output from the drain driver to the display electrode is stopped by fixing a clock pulse supplied to the shift register to a predetermined level during a non-display period. is there.

Further, the above-mentioned display device is a display device in which the voltage supplied from the precharge circuit to the drain signal line is an AC driving voltage.

In the above-mentioned display device, the non-display period is a horizontal non-display period.

Still further, the above-mentioned display device is a display device in which the non-display period is a horizontal retrace period or a vertical retrace period.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A display device according to the present invention will be described below.

FIG. 1 shows signals supplied to the driver of the liquid crystal display device, and FIG. 2 shows an equivalent circuit diagram when the display device of the present invention is applied to a liquid crystal display device.

As shown in FIG. 2, the liquid crystal display panel 100
The liquid crystal display panel 100 is driven based on each signal of the external substrate 90 separate from the above.

In the liquid crystal display panel 100, a plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal are arranged in a row direction (horizontal direction) and connected to a drain driver 60 for supplying a drain signal. A plurality of drain signal lines 61 are arranged in the column direction (vertical direction). A TFT 70 is connected to the two signal lines 51 and 61 and near the intersection of the two signal lines. The rise and fall of the liquid crystal 21 are controlled by the voltage applied to the display electrode 80 connected to the TFT 70.

Each driver 5 is provided on an external circuit board 90.
LSI that supplies signals for scanning 0 and 60
91 are provided. Further, the drain driver 60 is provided with a level shifter 93 before inputting.

A block diagram of a driving circuit for driving the liquid crystal display device is the same as that shown in FIG.
A timing controller to which a video signal is input, various timing signals from the timing controller,
For example, a level shifter that converts the levels of the clock pulses CKH1 and CKH2 and the start pulses STH1 and STH2, a horizontal shift register that is driven based on various level-shifted timing signals, and a video signal sampled by a sampling pulse from the shift register And a liquid crystal display panel for displaying on each display pixel.

As shown in FIG. 2, the precharge circuit 300 is provided on the insulating substrate 10 opposite to the side where the drain driver 60 is provided. Then, switches SW1, SW2,.
.. Are connected via SWn.

In the precharge signal supplied from the precharge circuit 300, a precharge voltage having the same polarity as the video signal voltage supplied in the horizontal period is superimposed.
This precharge voltage is applied to all drain signal lines 61 and held.

Subsequently, horizontal start pulses STH1, S
Based on TH2, the output of each stage is supplied from the horizontal shift register to each sampling switch, each sampling switch is turned on, the video signal voltage is sampled, applied to each drain signal line 61, and rewritten in the next field. Held until

Here, the precharge voltage will be described.

First, a precharge voltage is sampled from a video signal during a precharge period, and the precharge voltage is supplied to a drain signal line to charge an auxiliary capacitance. Thereafter, when the horizontal shift register is started and an H (high) level is output from the output stage, the corresponding pixel signal voltage is sampled from the original image signal and the video signal voltage of the drain signal line is changed. . That is, first, a precharge voltage having the same polarity as the pixel signal voltage to be supplied in the horizontal scanning period is applied to each drain signal line, and thereafter, the drain signal line is turned on by the gate signal line corresponding to the scanning signal voltage. It is supplied to each display pixel via the TFT.

Therefore, the voltage applied to each drain signal line can reach a predetermined pixel signal voltage by a slight voltage change from the precharge voltage applied in advance. Therefore, during the sampling period of each column, it is possible to prevent the reverse polarity pixel signal voltage applied in the previous field from being inverted and being received by the pixel signal voltage, and the predetermined voltage can be prevented. The time to reach the value is shorter.

Accordingly, each drain signal line can be charged to a predetermined voltage value in a short sampling time, so that the peripheral drive circuit-integrated p-type with a high resistance of the sampling switch is provided.
In a liquid crystal display device provided with a SiTFT, even if the sampling time assigned to one column during one horizontal scanning period is shortened, the drain signal line is charged, so that high definition or a large screen can be achieved.

Here, when the display (display of a moving image or the like) is not required on the liquid crystal display panel, stopping the horizontal shift register to reduce the power consumption is referred to as a low power consumption mode.

The case where the display mode is switched from the normal display mode to the low power consumption mode will be described below.

In the normal display mode, as described above, the precharge voltage is applied during the horizontal retrace period, and thereafter, the data signal is supplied from the sampling switch to hold the data for one field period, and the moving image is held. Is displayed.

Then, the normal display mode is switched to the low power consumption mode. That is, when the ON signal is supplied to each sampling switch and the sampling switch is turned on, the clock pulses CKH1 and CKH2 are set to a predetermined level (CKH1 is 0 V, C
(KH2 is fixed at 3 V) and the supply is stopped. Then, only the voltage from the precharge circuit is supplied to each drain signal line. That is, only a signal having the same polarity as the data signal is supplied to each drain signal line 61 from the precharge circuit connected to the other end of each drain signal line.

By doing so, the data signal is not supplied to each drain signal line via the sampling switch, so that an image display by a video signal supplied from the outside such as a moving image is not performed, and a white or black monochromatic raster is not displayed. Can be switched to the display. The precharge signal is driven by an alternating current, and the polarity is inverted to ± 2 V every 1 H around the potential Vc of the counter electrode of the liquid crystal display device. The voltage applied to the display electrode in the normal display mode is ± 3.5 V around the potential Vc of the counter electrode.
And a lower voltage. In the case of the low power consumption mode, since a single color raster display is performed without displaying a moving image or the like, a high voltage need not be applied unlike the normal display mode. That is, since the voltage is low, the contrast is lowered because the liquid crystal does not rise sufficiently as in the normal display mode, but there is no hindrance to the display because a normal moving image or the like is not displayed. is there.

As described above, in the block diagram of FIG. 3, since the output of the clock pulse from the timing controller is not performed, the clock pulse is not supplied to the level shifter, the shift register, and the liquid crystal display device. Therefore, since the level shifter and the shift register are not driven, power consumption can be reduced.

As a result, since the power consumption can be greatly reduced, even if the liquid crystal display device is used as a display of a mobile phone or the like having a limited battery, the power consumption can be reduced as compared with the case where the normal display mode is always used.

Here, the clock pulse of the display device of the present invention will be described.

As shown in FIG. 1, the clock pulse CKH
1, CKH2 is a signal having one cycle of 330 nsec (nanosecond) and a frequency of about 3 MHz, and the phases of which are inverted. The video signal is a video signal period V1 of a display period.
And one horizontal scanning period (1H) of the horizontal blanking period V2 in the non-display period.

The video signal shown in FIG. 1A is input from outside. Further, clock pulses CKH1 and CKH2 are oscillated as shown in FIGS. Start pulses STH1 and STH1 at the timing when the video signal is started in response to the clock pulses CKH1 and CKH2.
TH2 ((d) and (e) in the figure) is turned on. As a result, the signal PX shown in FIG.

The polarity of the precharge signal shown in FIG. 7 (f) is switched before the start of the video signal, and as shown in FIG.
CG is high (H) at the timing before the video signal starts
Level, and at that timing, a precharge voltage is supplied to the drain signal line.

Here, the clock pulses CKH1, CKH
The so-called clock pulse stop timing at which 2 is fixed to a constant potential is a non-display period V2 between the period A and the period B as shown in (b) and (c) of FIG. What is necessary is just to stop within this non-display period V2. That is,
The operation may be stopped in a display area of the liquid crystal display device, that is, at a timing except during the display period.

More specifically, the clock pulses CKH1 and CKH2 have a low level of 0V and a high level.
When the level is 3V, for example, one clock pulse CKH1 is fixed to 0V and the other clock pulse CKH2 is fixed to 3V in the non-display period. Then, the non-display period V between the period A and the period B
At 2, the clock pulses CKH1 and CKH2 are stopped.
By doing so, it is possible to prevent clock pulses from being generated during the non-display period and to prevent each driver from supplying clock pulses.

As the timing except during the display period, a clock pulse corresponding to the generation of a sampling pulse for supplying a video signal to a drain signal line connected to a display pixel which is actually displayed on the panel is used. It is sufficient that the clock pulse is stopped in a period other than the supply period.

In this manner, when the clock pulse CKH stops in the middle of one horizontal scanning period as in the conventional clock pulse stop timing shown in FIG. 7, the start pulse SRSTH in the shift register is provided.
7, the on state is maintained, and the sampling switch for supplying the data signal to the seventh shift register (the drain signal line in the seventh column) does not remain in the on state. A voltage remains applied to each display electrode connected to the drain signal line of the seventh pulse, and the luminance of the area 202 is different from that of the other display areas 201, and a vertical line defect appears. No more.

Therefore, by setting the timing for stopping the clock pulse to the display area of the liquid crystal display device, that is, the timing except during the display period, the vertical line defect shown in FIG. 7 does not appear. <Second Embodiment> In the above-described first embodiment, the case where the supply of the clock pulse to each driver is stopped in the horizontal blanking period V2 of the non-display period has been described. In the embodiment, the case where the supply of the clock pulse to each driver is stopped during the vertical flyback period is shown.

FIG. 4 shows clock pulses supplied to the driver of the liquid crystal display device.

FIG. 7A shows a conventional oscillation state of a clock pulse, and FIG. 7B shows a state in which the clock pulse of the present invention is fixed at a constant potential during the vertical retrace period and is not output. .

As shown in the figure, a video signal is composed of a video signal period which is a display period, and a horizontal retrace period and a vertical retrace period which are non-display periods.

The clock pulse signals CKH1, CK
H2 has a frequency of about 3 MHz, as in the first embodiment.
And the phases of the clock pulses CKH1 and CKH2 are opposite to each other.

As shown in FIG. 4B, the clock pulses CKH1 and CKH2 are supplied with a predetermined potential during the vertical retrace period so as not to oscillate the clock pulse during the retrace period of the horizontal retrace period or the vertical retrace period. And stop it. By doing so, it is not necessary to drive the level shifter and the shift register, so that power consumption for the fixed period can be saved. Therefore, by using the display device of the present invention for a display device having a limited power supply (battery) such as a mobile phone, the battery can be used effectively, and long-time use is possible.

As described above, according to the present invention, by fixing the clock pulse to a constant potential in the horizontal or vertical retrace period, the power consumption can be reduced without outputting to a display device, for example, a liquid crystal display panel. it can.

Since the drain driver requires a higher frequency than the gate driver, it is necessary to stop the output by fixing the clock pulse supplied to the drain driver, especially the shift register of the drain driver, to a predetermined potential. Thereby, power consumption can be further reduced.

In each of the above-described embodiments, the case where the non-display period is a horizontal or vertical blanking period has been described. However, the present invention is not limited to this. , A non-display period in which display is not substantially performed in the drain direction, and a non-display period in which display is not substantially performed in the gate direction.

In FIGS. 1 and 4 corresponding to each of the above-described embodiments, the sum of the number of oscillations of the clock pulse, that is, the frequency, is different from the actual one for convenience. Although the number of pixels of the liquid crystal display panel in FIG. 2 is only four in FIG. 2, it is actually tens of thousands to millions of pixels.

[0067]

According to the display device of the present invention, the clock pulse is fixed to a constant potential during the horizontal or vertical retrace period and is not supplied to the driver, so that a display device with reduced power consumption can be obtained. .

[Brief description of the drawings]

FIG. 1 is a timing chart of each signal according to the first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the liquid crystal display device of the present invention.

FIG. 3 is a block diagram of the liquid crystal display device of the present invention.

FIG. 4 is a timing chart of each signal according to the second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a conventional liquid crystal display device.

FIG. 6 is a timing chart of conventional signals.

FIG. 7 is a timing chart showing a conventional clock pulse.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 insulating substrate 13 gate 21 liquid crystal 50 gate driver 51 gate signal line 60 drain driver 61 drain signal line 70 TFT 80 display electrode 91 external LSI 100 liquid crystal display panel 200 display pixel

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G02F 1/133 550 G02F 1/133 550 G09G 3/36 G09G 3/36 H04N 5/66 102 H04N 5/66 102B F term (reference) 2H093 NA31 NA43 NC09 NC22 NC23 NC27 NC29 NC34 NC35 ND05 ND39 5C006 AA16 AC11 AC21 AF72 AF73 BB16 BC11 FA16 FA22 FA47 5C058 AA06 BA04 BA26 5C080 AA10 BB05 DD09 EE25 FF11 JJ04 JJ02 JJ03 JJ03 JJ03

Claims (5)

[Claims] 1. A plurality of gate signal lines and a plurality of drain signal lines arranged to cross each other, a switching element connected to the two signal lines and arranged near each intersection of the two signal lines, and the switching element A display electrode connected to an element, a gate driver for supplying a scanning signal to the gate signal line, a sampling switch for sampling a video signal supplied from outside and applying the sampled signal to the drain signal line, and A drain driver comprising a horizontal shift register to be in a conductive state; and a precharge circuit for supplying a precharge voltage having the same polarity as a voltage applied to the display electrode to the drain signal line. While the signal output to the display electrode is stopped, the voltage from the precharge circuit is displayed on the display. Display device and supplying the poles. 2. A signal output from the drain driver to the display electrode is stopped by fixing a clock pulse supplied to the shift register to a predetermined level during a non-display period. The display device according to the above. 3. The display device according to claim 1, wherein the voltage supplied from the precharge circuit to the drain signal line is an AC driving voltage. 4. The display device according to claim 2, wherein the non-display period is a horizontal non-display period. 5. The display device according to claim 4, wherein the non-display period is a horizontal retrace period or a vertical retrace period.