KR20020094637A - Liquid crystal display and driving method of the same - Google Patents

Abstract

PURPOSE: A liquid crystal display and a driving method thereof are provided which can reduce the generation of noise displayed abnormally without installing an oscillator, while giving a failure detection function to the liquid crystal display. CONSTITUTION: A timing control part(100) outputs a failure detection signal of an on or off level by detecting an input picture signal provided from an external graphic control part. A common electrode voltage selection part(400) selects one of a common electrode voltage of a normal mode or a common electrode voltage of an abnormal mode on the basis of the failure detection signal. A data driver part(200) outputs a data signal, and a scan driver part(300) outputs a scan signal in sequence. And a liquid crystal display panel(500) includes a plurality of data electrode lines and a plurality of scan electrode lines and a plurality of common electrode voltage lines and a switching device connected to the data electrode line and to the scan electrode line and a liquid crystal capacitor connected to the switching device and to the common electrode voltage line. The liquid crystal display panel displays a normal picture according to the data signal if the common electrode voltage of the normal mode is applied, and maintains a full black or a full white state if the common electrode voltage of the abnormal mode is applied.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD OF THE SAME}

The present invention relates to a liquid crystal display and a driving method thereof, and more particularly, to a liquid crystal display and a driving method thereof for removing abnormal display phenomenon.

In general, a fail detection function in a liquid crystal display (LCD) refers to an external image, for example, when an input image signal input from a graphics controller is not normal, and fixes an LCD display state to a specific display to prevent noise. This is how the phenomenon is not displayed.

That is, when the above input image signal is not input or in the promised format, the timing controller recognizes this and generates an independent LCD control signal. In this case, the LCD control signal includes various signals such as a horizontal shift clock (KL) for driving the data driver, a horizontal line start signal (STH), an inversion signal, a latch signal, and a vertical shift clock for driving the scan driver. shift CLK), and various signals including a vertical line start signal (STV).

Therefore, in order to generate the LCD control signal, the oscillator must be mounted outside the LCD module.

However, the mounting of this oscillator is not a problem for mounting LCD monitors that are free from volume and power consumption.However, the size and power consumption of the oscillator are highlighted in portable LCD products requiring thin and low power consumption. There is a difficult problem.

Accordingly, the technical and problem of the present invention are to solve the conventional problems, and an object of the present invention is to reduce the occurrence of abnormally displayed noise even when the oscillator is not mounted when the fail detection function is provided to the liquid crystal display. It is to provide a liquid crystal display device.

Another object of the present invention is to provide a method of driving the above liquid crystal display.

1 is a view for explaining a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a first embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a waveform diagram illustrating an operation according to the first embodiment of the common electrode voltage selector.

4 is a circuit diagram illustrating a second embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a circuit diagram illustrating a third embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a circuit diagram illustrating a fourth embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7A is a diagram for describing a first embodiment of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 7B is a waveform diagram of FIG. 7A.

<Description of the symbols for the main parts of the drawings>

100: timing control unit 200: data driver unit

300: scan driver 400: common electrode voltage selector

500: liquid crystal display panel

According to one aspect of the present invention for realizing the above object of the present invention,

A timing controller which detects an input image signal provided from an external graphic controller and outputs a fail detection signal of an on or off level;

A common electrode voltage selector configured to select one of a common electrode voltage in a normal mode or a common electrode voltage in an abnormal mode and supply the selected common electrode voltage to the common electrode voltage line based on the fail detection signal;

A data driver for outputting a data signal;

A scan driver unit for sequentially outputting scan signals; And

A plurality of data electrode lines, a plurality of scan electrode lines crossing the plurality of common electrode voltage lines, a switching element having one end connected to the data electrode line and the other end connected to the scan electrode line, and one end of the switching element And a liquid crystal capacitor connected to one end of the terminal and the other end connected to the common electrode voltage line. When the common electrode voltage of the normal mode is applied, a predetermined image is normally displayed according to the data signal, and the common image of the abnormal mode is common. When the electrode voltage is applied, the potential difference between the both ends of the liquid crystal capacitor is greater than the saturation voltage of the liquid crystal capacitor, and includes a liquid crystal display panel which maintains a full black or full white state.

Here, in one embodiment of the common electrode voltage selector,

A first resistor having one end connected to an output terminal of the timing controller; A first transistor configured to switch the common electrode voltage in the normal mode input through the emitter terminal based on the fail detection signal input through the first resistor through the base terminal, and output the common electrode voltage through the collector terminal; A second resistor, one end of which is first common to the output terminal of the timing controller and one end of the first resistor; A second transistor configured to receive a fail detection signal input via the second resistor through a base terminal, and an emitter terminal connected to a collector terminal of the first transistor; A third resistor once provided with the common electrode voltage in this abnormal mode; And a base terminal is second common to the collector terminal of the second transistor and the other end of the third resistor, and is switched based on the second common voltage to output a common electrode voltage in an abnormal mode connected to the collector terminal through the emitter terminal. It is preferable to include a third transistor.

In addition, as another embodiment of the common electrode voltage selector,

A first resistor having one end connected to an output terminal of the timing controller; A first transistor having a base terminal connected to the other end of the first resistor and an emitter terminal connected to an input voltage; A second resistor, one end of which is connected to the collector terminal of the first transistor; A second transistor configured to switch the common electrode voltage in the normal mode input through the emitter stage based on the fail detection signal input through the second resistor through the base stage, and output the common electrode voltage through the collector stage; A third resistor, one end of which is first common to the output terminal of the timing controller and one end of the second resistor; A third transistor receiving a fail detection signal input via the third resistor through a base end, and having an emitter end connected to a collector end of the second transistor; A fourth resistor once provided with the common electrode voltage in this abnormal mode; And a base terminal is second common to the collector terminal of the third transistor and the other end of the fourth resistor, and is switched based on the second common voltage to output a common electrode voltage in an abnormal mode connected to the collector terminal through the emitter terminal. It is preferable to include a fourth transistor.

Further, as another embodiment of the common electrode voltage selector,

A first resistor having one end connected to an output terminal of the timing controller; A first transistor configured to switch a common electrode voltage in a normal mode input through an emitter stage based on a fail detection signal input through the first resistor through a base stage, and output the same through a collector stage; And a second resistor having one end connected to the collector terminal of the first transistor, the common electrode voltage of the abnormal mode connected to the other end, and outputting the common electrode voltage of the abnormal mode through the one end.

Further, as another embodiment of the common electrode voltage selector,

A first resistor having one end connected to an output terminal of the timing controller; A first transistor having a base terminal connected to the other end of the first resistor and an emitter terminal connected to an input voltage; A second resistor, one end of which is connected to the collector terminal of the first transistor; A second transistor configured to switch the common electrode voltage in the normal mode input through the emitter stage based on the fail detection signal input through the second resistor through the base stage, and output the common electrode voltage through the collector stage; One end is connected to the collector terminal of the second transistor, the other end is connected to the common electrode voltage of the abnormal mode, it is preferable to include a third resistor for outputting the common electrode voltage of the abnormal mode through the one end.

According to another aspect of the present invention, a liquid crystal display device includes a plurality of data electrode lines, a plurality of scan electrode lines, a plurality of common electrode voltage lines, and one end of the plurality of data electrode lines. A liquid crystal display panel including a liquid crystal display panel including a liquid crystal capacitor connected to a data electrode line and the other end connected to the scan electrode line and one end connected to one end of the switching element and the other end connected to the common electrode voltage line. In the apparatus,

A first latch receiving an input image signal provided from an external graphic controller to output image data, detecting the input image signal to output a fail detection signal of an on or off level, and controlling the latching of the input image signal A timing controller which outputs a signal;

A logic sum operation unit configured to generate a second latch signal by performing an OR operation on the fail detection signal of the on or off level and the first latch signal, and output the generated second latch signal; And

A data driver unit outputting a data signal to the data electrode line by performing a latching operation of an input image signal provided from the timing controller based on the second latch signal; And

And a scan driver for outputting a scan signal to the scan electrode line.

In addition, a method of driving a liquid crystal display device according to another aspect for realizing the above object of the present invention includes a plurality of data electrode lines, a plurality of scan electrode lines and a plurality of common electrode voltage lines crossing the plurality of data electrode lines; A liquid crystal display panel including a liquid crystal capacitor having one end connected to the data electrode line and the other end connected to the scan electrode line, and one end connected to one end of the switching element and the other end connected to the common electrode voltage line; ; A data driver unit for outputting a data signal to the data electrode line; In the driving method of the liquid crystal display device comprising a scan driver for outputting a scan signal to the scan electrode line,

(a) outputting a data signal to the data electrode line based on an input image signal provided from the outside;

(b) sequentially outputting scan signals to the scan electrode lines based on the control signals of the input image signals;

(c) detecting the input image signal and outputting a fail detection signal of an on or off level;

(d) supplying a common electrode voltage in a normal mode to the common electrode voltage line when the off level fail detection signal is applied; And

(e) supplying a common electrode voltage in an abnormal mode to the common electrode voltage line when the on level fail detection signal is applied;

(f) adapting the data signal to display a predetermined image when the common electrode voltage in the normal mode is applied; And

(g) When the common electrode voltage of the abnormal mode is applied, all positions between the both ends of the liquid crystal capacitor become higher than or equal to the saturation voltage of the liquid crystal capacitor regardless of the data signal, thereby maintaining either a full black or full white state. A step is made.

According to the liquid crystal display and the driving method thereof, the fail detection function may be similarly implemented even when the liquid crystal display is provided with a fail detection function to remove the noise when the noise is generated, thereby reducing the thickness of the liquid crystal display device. Can be obtained and power consumption can be reduced.

Then, embodiments will be described so that those skilled in the art can easily implement the present invention.

1 is a view for explaining a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a timing controller 100, a data driver 200, a scan driver 300, a common electrode voltage selector 400, and a liquid crystal display panel. 500.

The timing controller 100 is an input image signal [R (0: N), G (0: N), B (0: N)] input from a graphic controller (not shown) external to the liquid crystal display module, and a frame discrimination signal. The data driver 200, the scan driver 300, and the common electrode voltage selector 400 may receive the vertical sync signal Vsync, the horizontal sync signal Hsync and the main clock signal MCLK, respectively. Outputs a signal to drive.

In more detail, the timing controller 100 receives the input image signals R (0: N), G (0: N), and B (0: N) from the external graphic controller (not shown). A horizontal line start signal STH for commanding input start to 200, a signal LOAD for commanding data to be applied to the liquid crystal display panel 500, and a clock for shifting data in the data driver unit 200. The signal HCLK is output to the data driver 200.

In addition, the timing controller 100 scans the vertical line start signal STV for commanding the start of the gate on signal and the gate clock signal Gate CLK for sequentially performing the gate on signal on each gate line. Output to the driver unit 300.

In addition, when it is checked that the input image signal is normally input, the timing controller 100 outputs a fail detection signal to the common electrode voltage selector 400 so as to select the common electrode voltage of the normal mode, and then inputs the input image signal. If is checked as an abnormal mode that is abnormally input, the fail detection signal is output to the common electrode voltage selector 400 to select the common electrode voltage of the abnormal mode.

For example, the low level fail detection signal may be output to control the selection of the common electrode voltage in the normal mode, and the high level fail detection signal may be output to control the selection of the common electrode voltage in the abnormal mode. Of course, the reverse is also possible.

That is, the timing controller 100 generates a digital signal for driving the data driver 200 and the scan driver 300, outputs the digital signal to the corresponding driver, and shares the fail detection signal according to whether the input image signal is normal. Output to the electrode voltage selector 400.

The data driver 200 receives the input image signals R (0: N), G (0: N), and B (0: N) from the timing controller 100 and stores the received image signals. When a load signal LOAD for commanding to lower the voltage is applied, the voltage corresponding to each data is selected to transfer the data voltages D1, D2, D3,..., And Dm to the liquid crystal display panel 500. . The data driver outputs a data voltage such that the polarities of the pixels arranged on the liquid crystal display panel are inverted different from each other in every frame. In this case, the inversion of the pixels so that the polarities are different every frame is due to the general characteristics of the liquid crystal, as is already known.

The scan driver 300 receives a gate clock signal Gate CLK and a vertical line start signal STV from the timing controller 100, including a plurality of shift registers, level shifters, and buffers, and the liquid crystal display panel ( It opens the way so that the voltage value of each pixel on 500 is transmitted to the pixel.

The common electrode voltage selector 400 selects the common electrode voltage VA in the normal mode or the common electrode voltage Voff in the abnormal mode based on the fail detection signal provided from the timing controller 100 to common the liquid crystal display panel. Output to the electrode line. For example, when the fail detection signal provided from the timing controller is at a low level, it is regarded as a normal mode, and a normal common electrode voltage is selected and output. When the fail detection signal is at a high level, it is regarded as an abnormal mode. Select and output the voltage. Of course, the reverse is also possible.

The liquid crystal display panel 500 is formed in m data lines, n gate lines arranged orthogonal to the data lines, and a predetermined region lattice arranged between the data lines and the gate lines, one end of which is disposed on the gate line. A pixel electrode connected to the other end and connected to the data line, and as the gate voltages G1, G2,..., Gn provided from the scan driver 300 are applied to the corresponding pixel, the data driver 200. In response to the data voltages D1, D2,..., And Dm provided from FIG. 1, the corresponding pixel electrode is driven.

In more detail, the liquid crystal display panel 500 normally displays a predetermined image according to a data signal when the common electrode voltage in the normal mode is applied, and a potential difference between the both ends of the liquid crystal capacitor when the common electrode voltage in the abnormal mode is applied. Is above the saturation voltage of the liquid crystal capacitor to maintain a full black or full white state.

As described above, according to the liquid crystal display device according to the present invention, even if a separate oscillator is not provided to provide a fail detection function to the liquid crystal display device, a normal mode is determined depending on whether the input image signal provided from the outside is normal or abnormal. The abnormal display phenomenon can be eliminated by outputting the common electrode voltage or the common electrode voltage in the abnormal mode to the common electrode line of the liquid crystal display panel.

Next, the various embodiments of the common electrode voltage selector will be described in more detail.

FIG. 2 is a circuit diagram illustrating a first embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 illustrates an operation according to the first embodiment of the common electrode voltage selector described above. It is a waveform diagram for that.

2 and 3, a first embodiment of a common electrode voltage selector 400 of a liquid crystal display according to an exemplary embodiment of the present invention includes a first terminal having a base terminal connected to one end of a first resistor R1. The transistor Q1 and the emitter terminal are common to the collector terminal of the first transistor Q1, and the base terminal is connected to the other end of the first resistor R1 through the second resistor R2 and the base terminal. The emitter terminal is common to the collector terminal of the second transistor Q2, the emitter terminal is common to the collector terminal of the first transistor Q1, and the collector terminal includes a third transistor Q3 connected to the V _off voltage.

In operation, when the input image signal input from the outside is normally input, the output of the timing controller 100 outputs a ground level fail detection signal. At this time, the first transistor Q1 is turned on and the common electrode voltage applied to the common electrode line of the liquid crystal panel becomes VA, thereby performing normal display.

At this time, while the second transistor Q2 is turned on, the VA voltage is applied to the base terminal of the third transistor Q3, but the third transistor Q3 is turned off.

On the other hand, when the input image signal input from the outside is abnormally input, the output of the timing controller 100 outputs a fail detection signal of the VDD level. At this time, the first transistor Q1 and the second transistor Q2 are turned off, and the base terminal of the third transistor Q3 is discharged to the V _off level so that the common electrode voltage becomes the V _off voltage level. That is, when the abnormal signal is input, the common electrode voltage is applied with the V _off voltage.

In the first embodiment of the common electrode voltage selector, the VA voltage connected to the emitter terminal of the first transistor in the general TFT LCD is the base-emitter voltage V _BE of the first transistor and the output voltage VDD output from the timing controller. The smaller case (VA <VDD + V _BE ) has been described on the assumption.

On the other hand, in a typical TFT LCD, when the VA voltage connected to the emitter terminal of the first transistor is greater than the base-emitter voltage V _BE of the first transistor and the output voltage VDD output from the timing controller (VA> VDD + V _BE ) can also be confirmed, as in the second embodiment described below.

FIG. 4 is a circuit diagram illustrating a second embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention. Compared to FIG. 3, a VDD voltage is provided through an emitter stage. One end is connected to the other end of the fourth resistor R4 that receives the fail detection signal from the timing controller 100, and the collector terminal is connected to the common terminal of the first resistor and the second resistor.

As shown in FIG. 4, the second embodiment of the present invention is turned off when the base ends of the first transistor Q1 and the second transistor Q2 are in a high impedance state. Same as the first embodiment described above.

5 is a circuit diagram illustrating a third embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a common electrode voltage of a normal mode inputted through an emitter terminal based on a resistor R1 connected to an output terminal of the timing controller and a fail detection signal input through the resistor through a base terminal. The transistor Q1 outputs through the collector stage and is connected to the collector terminal of the transistor Q1, and the common electrode voltage of the abnormal mode is connected through the other end, and the common mode of the abnormal mode is connected through the one end. The resistor R2 outputs an electrode voltage.

The common electrode voltage when the common electrode and the voltage VA, the turn-off when one is in the turn-on operation, the transistor (Q1) can be carried out the same operation as the first embodiment to ensure that the V _off.

The circuit configuration according to the third embodiment described above has an advantage that the circuit configuration can be simplified as compared with the first embodiment.

Similarly, the second embodiment may be modified to implement the common electrode voltage selector according to the fourth embodiment.

6 is a circuit diagram illustrating a fourth embodiment of a common electrode voltage selector of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 6, in the fourth embodiment of the common electrode voltage selector according to the present invention, one end of the resistor R3 is connected to the output terminal of the timing controller, and the base of the common electrode voltage selector is connected to the other end of the resistor R3. The emitter is based on a fail detection signal input via the transistor Q4 having a terminal connected to the input voltage, a resistor R1 having one end connected to the collector terminal of the transistor Q4, and the resistor R1 input through the base terminal. Transistor Q1 for switching the common electrode voltage of the normal mode input through the terminal and outputting through the collector terminal, and one end is connected to the collector terminal of the transistor Q1, and the common electrode voltage of the abnormal mode is connected through the other end And a resistor R2 for outputting the common electrode voltage in the abnormal mode through the one end.

In the above description, the common electrode voltage according to the normal mode or the common voltage voltage according to the abnormal mode is output based on a fail detection signal according to whether the image signal input from the outside is normal or abnormal to remove the abnormal display phenomenon. It described through the fourth embodiment.

Meanwhile, according to another embodiment of the present invention, when a fail is detected in the liquid crystal display based on the fail detection signal, the latch signal is controlled to output the latched data to the liquid crystal display panel. You can also remove the abnormal display phenomenon.

FIG. 7A is a diagram for describing a first embodiment of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 7B is a waveform diagram of FIG. 7A.

Referring to FIGS. 1 and 7A, an operation may be performed by performing an OR operation on a first latch signal that controls the latching of data output from the timing controller 100 and applied to the liquid crystal display panel and a fail detection signal output from the timing controller 100. The second latch signal is applied to the data driver 200.

That is, as shown in FIG. 7B, while the fail detection signal is at the low level, the second latch signal input to the data driver 200 also maintains the low level, thereby outputting data output from the data driver 200. Keep it normal. In addition, while the fail detection signal is at the high level, the second latch signal input to the data driver 200 also maintains the high level, thereby blocking the output of the noisy data output from the data driver 200, thereby causing abnormal display phenomenon. Can be removed.

As described in another embodiment of the present invention, even if the latch signal output from the timing controller is adjusted and applied to the data driver, abnormal display phenomenon of the liquid crystal display may be eliminated.

In the above description, the common electrode voltage is adjusted and output to the common electrode line of the liquid crystal display panel or the latch signal is output to the data driver in order to eliminate abnormal display phenomenon in the liquid crystal display.

Meanwhile, in a typical TFT LCD, the VA voltage connected to the emitter terminal of the first transistor Q1 is the base-emitter voltage V _BE of the first transistor Q1 and the output voltage VDD output from the timing controller 100. If smaller than (VA <VDD + V _BE ), the first embodiment according to the embodiment of the present invention and the first embodiment according to another embodiment of the present invention may be simultaneously implemented in the liquid crystal display device. A third embodiment according to an embodiment of the present invention and a first embodiment according to another embodiment of the present invention may be simultaneously implemented in a liquid crystal display.

In addition, in a typical TFT LCD, the VA voltage connected to the emitter terminal of the first transistor Q1 is less than the base-emitter voltage V _BE of the first transistor Q1 and the output voltage VDD output from the timing controller 100. If large (VA> VDD + V _BE ), the second embodiment according to the embodiment of the present invention and the first embodiment according to another embodiment of the present invention may be simultaneously implemented in the liquid crystal display, or the present invention A fourth embodiment according to an embodiment of the present invention and a first embodiment according to another embodiment of the present invention may be simultaneously implemented in a liquid crystal display.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, according to the present invention, when a liquid crystal display device is provided with a fail detection function for removing noise when the noise is generated, the fail detection function may be similarly implemented without a separate oscillator. In particular, the thickness of the portable liquid crystal display device can be reduced, and power consumption can be reduced.

Claims (7)

A timing controller which detects an input image signal provided from an external graphic controller and outputs a fail detection signal of an on or off level; A common electrode voltage selector configured to select one of a common electrode voltage in a normal mode or a common electrode voltage in an abnormal mode and supply the selected common electrode voltage to the common electrode voltage line based on the fail detection signal; A data driver for outputting a data signal; A scan driver unit for sequentially outputting scan signals; And A plurality of data electrode lines, a plurality of scan electrode lines crossing the plurality of common electrode voltage lines, a switching element having one end connected to the data electrode line and the other end connected to the scan electrode line, and one end of the switching element And a liquid crystal capacitor connected to one end of the terminal and the other end connected to the common electrode voltage line. When the common electrode voltage of the normal mode is applied, a predetermined image is normally displayed according to the data signal, and the common mode of the abnormal mode And a liquid crystal display panel which maintains a full black or full white state when the potential difference between both ends of the liquid crystal capacitor is greater than the saturation voltage of the liquid crystal capacitor when an electrode voltage is applied. The method of claim 1, wherein the common electrode voltage selector, A first resistor having one end connected to an output terminal of the timing controller; A first transistor configured to switch the common electrode voltage in the normal mode input through the emitter terminal based on the fail detection signal input through the first resistor through the base terminal, and output the common electrode voltage through the collector terminal; A second resistor, one end of which is first common to the output terminal of the timing controller and one end of the first resistor; A second transistor configured to receive a fail detection signal input via the second resistor through a base terminal, and an emitter terminal connected to a collector terminal of the first transistor; A third resistor once provided with the common electrode voltage in this abnormal mode; And The base terminal is second common to the collector terminal of the second transistor and the other end of the third resistor, and is switched based on the second common voltage to output a common electrode voltage in an abnormal mode connected to the collector terminal through the emitter terminal. A liquid crystal display device comprising three transistors. The method of claim 1, wherein the common electrode voltage selector, A first resistor having one end connected to an output terminal of the timing controller; A first transistor having a base terminal connected to the other end of the first resistor and an emitter terminal connected to an input voltage; A second resistor, one end of which is connected to the collector terminal of the first transistor; A second transistor configured to switch the common electrode voltage in the normal mode input through the emitter stage based on the fail detection signal input through the second resistor through the base stage, and output the common electrode voltage through the collector stage; A third resistor, one end of which is first common to the output terminal of the timing controller and one end of the second resistor; A third transistor receiving a fail detection signal input via the third resistor through a base end, and having an emitter end connected to a collector end of the second transistor; A fourth resistor once provided with the common electrode voltage in this abnormal mode; And The base terminal is second common to the collector terminal of the third transistor and the other end of the fourth resistor, and is switched based on the second common voltage to output a common electrode voltage in an abnormal mode connected to the collector terminal through the emitter terminal. A liquid crystal display device comprising four transistors. The method of claim 1, wherein the common electrode voltage selector, A first resistor having one end connected to an output terminal of the timing controller; A first transistor configured to switch the common electrode voltage in the normal mode input through the emitter terminal based on the fail detection signal input through the first resistor through the base terminal, and output the common electrode voltage through the collector terminal; And One end is connected to the collector terminal of the first transistor, the other end is connected to the common electrode voltage of the abnormal mode, the liquid crystal comprising a second resistor for outputting the common electrode voltage of the abnormal mode through the one end Display device. The method of claim 1, wherein the common electrode voltage selector, A first resistor having one end connected to an output terminal of the timing controller; A first transistor having a base terminal connected to the other end of the first resistor and an emitter terminal connected to an input voltage; A second resistor, one end of which is connected to the collector terminal of the first transistor; A second transistor configured to switch the common electrode voltage in the normal mode input through the emitter stage based on the fail detection signal input through the second resistor through the base stage, and output the common electrode voltage through the collector stage; A first resistor connected to the collector terminal of the second transistor, a common electrode voltage of the abnormal mode connected to the other end, and a third resistor outputting the common electrode voltage of the abnormal mode through the one end thereof; Display device. A plurality of data electrode lines, a plurality of scan electrode lines crossing the plurality of common electrode voltage lines, a switching element having one end connected to the data electrode line and the other end connected to the scan electrode line, and one end of the switching element A liquid crystal display device comprising a liquid crystal display panel including a liquid crystal capacitor connected to one end of the second electrode and connected to the common electrode voltage line. A first latch receiving an input image signal provided from an external graphic controller to output image data, detecting the input image signal to output a fail detection signal of an on or off level, and controlling the latching of the input image signal A timing controller which outputs a signal; A logical sum operation unit configured to generate a second latch signal by performing an OR operation on the fail detection signal of the on or off level and the first latch signal, and output the generated second latch signal; And A data driver unit outputting a data signal to the data electrode line by performing a latching operation of an input image signal provided from the timing controller based on the second latch signal; And A scan driver for outputting a scan signal to the scan electrode line Liquid crystal display comprising a. A plurality of data electrode lines, a plurality of scan electrode lines crossing the plurality of common electrode voltage lines, a switching element having one end connected to the data electrode line and the other end connected to the scan electrode line, and one end of the switching element A liquid crystal display panel including a liquid crystal capacitor connected to one end of the second electrode and connected to the common electrode voltage line; A data driver unit for outputting a data signal to the data electrode line; In the driving method of the liquid crystal display device comprising a scan driver for outputting a scan signal to the scan electrode line, (a) outputting a data signal to the data electrode line based on an input image signal provided from the outside; (b) sequentially outputting scan signals to the scan electrode lines based on the control signals of the input image signals; (c) detecting the input image signal and outputting a fail detection signal of an on or off level; (d) supplying a common electrode voltage in a normal mode to the common electrode voltage line when the off level fail detection signal is applied; And (e) supplying a common electrode voltage in an abnormal mode to the common electrode voltage line when the on level fail detection signal is applied; (f) adapting the data signal to display a predetermined image when the common electrode voltage in the normal mode is applied; And (g) When the common electrode voltage of the abnormal mode is applied, all positions between the both ends of the liquid crystal capacitor become higher than or equal to the saturation voltage of the liquid crystal capacitor regardless of the data signal, thereby maintaining either a full black or full white state. step Method of driving a liquid crystal display comprising a.