JP3122950B2 - Liquid crystal control device, liquid crystal display device and projection device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal control device, a liquid crystal display device, and a projection device, and more particularly to data conversion of a video signal.

[Prior Art] FIG. 7 is a schematic configuration diagram of a conventional liquid crystal display device, in which (1) is a personal computer (hereinafter, referred to as a PC) having a CRT for displaying an image, and (2) is a video deck (hereinafter, a VCR). VTR).

(3) is a composite video image signal from VTR (2) (hereinafter referred to as composite image signal) or analog from PC (1)
A switch unit for switching to an RGB signal, (4) a signal processing unit for converting an output signal from the switch unit (3) into a predetermined video signal, and (5) a video signal output from the signal processing unit (4). A buffer for outputting an amplified and AC-inverted video signal, and (6) forms a predetermined timing signal from an analog RGB signal and a synchronizing signal of a composite video signal output from the changeover switch section (3) and outputs the signal to each section. This is a timing forming circuit.

(7) a liquid crystal display unit which drives electrodes of a matrix LCD (13) to be described later by a timing signal from the timing forming circuit (6) and a video signal of the buffer (5), and displays a predetermined video. It is.

FIG. 8 is a diagram for explaining the configuration of the liquid crystal display unit. For simplicity of description, the connection configuration is for only the R signal.

In the figure, reference numeral (8) denotes a first X electrode source line driver, which inputs a video signal output from the buffer section (5) and a timing signal from the timing forming circuit (6), and outputs a matrix LCD (13) to be described later. ), And includes a CMOS circuit (not shown).

The output from this driver is a matrix LCD
Are connected in a comb-like manner in correspondence with the source lines of. In this case, the number of source lines will be described as n.

(9) is a first Y electrode gate line driver, which drives the electrodes of the matrix LCD (13) by a timing signal output from the timing forming circuit (6), and includes a CMOS circuit.

(10) is a second Y electrode gate line driver.
Reference numeral (11) denotes a second X electrode source line driver, which inputs a video signal output from the buffer section (5) and a timing signal from the timing forming circuit (6), and supplies an electrode of a matrix LCD (13) to be described later. And includes a CMOS circuit (not shown).

(13) is a matrix LCD, which outputs a thin film transistor (hereinafter referred to as a TFT) provided for each pixel of the liquid crystal display screen from the X electrode source line driver of (8) and (11) and (9) and (10). Is a matrix LCD that turns on and off on a row-by-row basis by the Y electrode gate line driver to display a clear image on the liquid crystal display screen.

FIG. 9 is a diagram for explaining the frequency characteristics of the first X electrode source line driver.

This figure is a diagram showing a frequency band when a composite video signal is input to the first X electrode source line driver.
It shows that transmission of a signal flat to 5 MHz can be compensated.

This is because, for example, when displaying a composite video signal of about 4 MHz of VTR (2) which is an interlace display, the first X
This indicates that the electrode source line driver (8) can stably output a drive signal to the matrix LCD (13).

The liquid crystal display device configured as described above requires that the frequency of the signal supplied to the matrix LCD (13) does not attenuate as the definition of the matrix LCD (13) increases (for example, 640 × 400 or more). In particular, the clock frequency of the PC display signal becomes very high.

For example, switching the changeover switch section (3) to VTR (2)
If the composite video signal is output to the signal processing unit (4) and the timing forming circuit (6), the frequency band is as shown in FIG. Outputs to (13) and displays clear images, but must display non-interlace
When displaying the analog RGB signal of the PC (1), for example, the changeover switch section (3) is switched to input the analog RGB signal from the PC (1) to the signal processing section (4) and the timing forming circuit (6). Assuming that the signal is input to each driver, the analog R, G, and B signals of the PC (1) are about 10 MHz.
Since the frequency is above z, the frequency characteristics of the driver must be flat up to 10MHz or more.

However, since the frequency characteristics of the driver are stable only up to about 5 MHz, the output waveform is distorted as described below.

FIG. 10 is a view for explaining an output signal of the first X electrode source line driver when a conventional PC video signal is input.

In the figure, (20) is a portion where the high frequency portion of the output signal is distorted due to the frequency characteristics of the first X electrode source line driver (8).

This figure shows that when the video signal from the PC (1) is output to the first X electrode source line driver (8), the waveform is distorted as shown in the figure, and the electrodes of the matrix LCD (13) are driven at a predetermined potential. Indicates that it is no longer possible.

Therefore, when a video signal from the PC (1) is output to the first X electrode source line driver (8), the resolution of an image to be displayed is reduced, and the video is blurred.

[Problem to be Solved by the Invention] In the conventional liquid crystal display device as described above, the matrix
Since the driver that drives the LCD has a frequency characteristic that covers the video signal of the VTR, if the video signal is input from a PC, the frequency band of the driver is narrow, so the high frequency part from the driver will be distorted, There was a problem that the image from the PC was blurred.

The present invention has been made to solve such a problem. Even if a video signal is input from a PC, the video signal from the PC is converted into parallel without changing the frequency characteristics of the driver. It is an object of the present invention to provide a liquid crystal control device, a liquid crystal display device, and a projection device that can clearly display an image without distorting an output signal.

[Means for Solving the Problems] A liquid crystal control device according to the present invention includes an A / D converter for converting analog image data into a digital signal, and dividing the digital signal by k (k is an integer of 2 or more). a data conversion unit that converts and outputs the k image data signals, and a D / A conversion unit that converts the image data signal into an analog signal and supplies the converted analog signal to a liquid crystal driver that drives a liquid crystal. The data conversion unit includes: a storage unit for k blocks each having a plurality of regions; a first switching unit for sequentially switching and outputting the digital data to the storage unit for the k blocks for each pixel unit; A second switching means provided for each block for switching and selecting an area of the storage means for storing the digital data for each scanning period; and a second switching means provided for each block and for storing the digital data. One of the areas not selected by the second switching means is switched and selected for each scanning period unit, and data stored in the area is output to the D / A conversion unit as the image data signal. And third switching means for performing the switching.

Further, the liquid crystal display device of the present invention includes an A / D conversion unit that converts analog image data into a digital signal, and divides the digital signal by k (k is an integer of 2 or more) to obtain k image data signals. A data conversion unit for converting and outputting, a D / A conversion unit for converting the image data signal into an analog signal, and a liquid crystal unit for displaying an image based on the image analog signal output from the D / A conversion unit. Wherein the data conversion unit comprises:
A storage unit for k blocks each having a plurality of regions; a first switching unit for sequentially switching and outputting the digital data to the storage unit for the k blocks for each pixel; A second switching unit for switching and selecting an area of the storage unit in which data is to be stored for each scanning period; and a second switching unit provided for each block and selected by the second switching unit in the storage unit area. And third switching means for switching and selecting one of the non-existing areas for each scanning period unit and outputting the data stored in the area as the image data signal to the D / A conversion unit. And

Also, the projection device of the present invention includes an A / D conversion unit that converts analog image data into a digital signal, and divides the digital signal by k (k is an integer of 2 or more) and converts the digital signal into k image data signals. A data conversion unit for outputting
A D / A conversion unit that converts the image data signal into an analog signal, and a liquid crystal unit that displays an image based on the image analog signal output from the D / A conversion unit, wherein each of the data conversion units is Storage means for k blocks having a plurality of regions, first switching means for sequentially switching and outputting the digital data to the storage means for the k blocks for each pixel unit, and A second switching means for switching and selecting an area of the storage means to be stored for each scanning period; and a second switching means provided for each block and not being selected by the second switching means among the areas of the storage means. Third switching means for switching and selecting one of the regions for each scanning period unit, and outputting data stored in the region as the image data signal to the D / A conversion unit. To.

[Operation] In the present invention, in the data conversion unit having the storage unit of k blocks each having a plurality of regions, the first switching unit sequentially converts the digital data to the storage unit of k blocks for each pixel. The output is switched, and the area of the storage means for storing digital data, which is provided for each block by the second switching means, is switched and selected for each scanning period, and provided for each block by the third switching means. One of the areas of the storage means that is not selected by the second switching means is switched and selected for each scanning period unit, and the data stored in the area is sent to the D / A conversion unit as an image data signal. By outputting, the digital signal of the analog image data converted by the A / D converter is divided into k (k = an integer of 2 or more), converted into k image data signals, and output.

Embodiment FIG. 1 is a schematic configuration diagram of a liquid crystal display device showing a first embodiment of the present invention, and (1) to (7) are the same as the above-mentioned conventional device.

In the figure, (21) is a first changeover switch unit,
A composite video signal from the VTR (2) and a synchronizing signal from the PC (1) are input, and one of them is output by a switching operation.

A timing signal forming unit (22) separates a synchronizing signal from a composite video signal output from the first changeover switch unit (21) or a voltage control oscillator (hereinafter referred to as VCO) from a synchronizing signal of the PC (1). A predetermined timing signal is output using a fez-locked loop (hereinafter, referred to as a PLL) including a PLL.

Reference numeral (23) denotes a PC signal processing unit which receives an analog RGB signal from the PC (1) and adjusts the color, brightness, and contrast of the signal as necessary.

(24) is an A / D conversion unit, which converts an analog RGB signal from the PC signal processing unit (23) into a timing signal forming circuit (22)
, Is converted into serial image data corresponding to the number of pixels of the matrix LCD (13) by a timing signal, and the image data is output.

Reference numeral (25) denotes a data conversion unit which converts the serial video signal output from the A / D converter (24) into the odd-numbered source line image data by the timing signal output from the timing signal forming circuit (22). (Hereinafter, referred to as odd-numbered image data) and image data of even-numbered source lines (hereinafter, referred to as even-numbered image data) are simultaneously output as parallel image data, and include a circuit to be described later.

(26) a D / A conversion unit, which converts the parallel image data output from the data conversion unit (25) into analog image data in accordance with a timing signal from the timing signal forming circuit (22), respectively; It has a predetermined number of D / A conversion circuits for outputting analog image data.

(27) is a second changeover switch unit, which is a D / A conversion unit (2
The image signal is switched to an RGB signal from a video signal processing unit described later by the even image data output from 6) or a switching operation, and includes a changeover switch corresponding to each signal.

Reference numeral (28) denotes a first buffer unit, which current-amplifies an output signal from the second changeover switch unit (27), and uses a timing signal from a timing signal forming circuit (22) to perform one scanning line (hereinafter referred to as 1H). ) Has a plurality of buffers for outputting a signal that is AC-inverted every time to the first X electrode source line driver (8).

Further, the AC inversion every 1H may be performed every frame. That is, the signal may be a signal that is periodically AC-inverted. In this embodiment, it is assumed that the AC is inverted every 1H.

A video signal processing unit (30) reproduces at least the three primary color signals of R, G, and B from the composite video signal output from the VTR (2), and adjusts the color, tint, brightness, contrast, and the like. It is.

Reference numeral (31) denotes a third changeover switch, which outputs one of the odd image data from the D / A converter (26) and the RGB signal from the video signal processor (30) by a switching operation. is there.

(32) is a second buffer unit, which amplifies the output signal from the third changeover switch unit (31) and converts the signal, which is AC-inverted by the timing signal from the timing signal forming circuit (22), into the first signal. It has a plurality of buffers for outputting to the X electrode source line driver (8).

FIG. 2 is a diagram illustrating the configuration of the data conversion unit. In the figure, (24) to (26) are the same as those in FIG. 1, and (35) is a fourth switch, which is an A / D converter (2
4) The odd-numbered image data and the even-numbered image data are output by switching the image data of the R signal output from the A / D conversion circuit for each pixel by a timing signal.

Reference numeral (36) denotes a fifth changeover switch, which inputs odd image data switched by the fourth changeover switch (35), switches every 1H by a timing signal, and outputs odd image data in a 1H period. It is.

This changeover switch is an input changeover switch for inputting odd-numbered image data to a predetermined area of the memory.

(37) a first memory for sequentially storing odd-numbered image data for each 1H output from the fifth changeover switch (36) in the first area or the second area based on a timing signal. is there.

(39) is a sixth changeover switch which performs a changeover operation contrary to the fifth changeover switch (36) by a timing signal and outputs odd image data stored in the first area or the second area. It is.

This changeover switch is an output changeover switch for outputting odd image data from a predetermined area of the memory.

Reference numeral (40) denotes a seventh changeover switch which receives the even-numbered image data switched by the fourth changeover switch (35), switches every 1H according to the timing signal, and outputs the even-numbered image data in the 1H period. It is.

The changeover switch is an input changeover switch for inputting even-numbered image data to a predetermined area of the memory.

(41) is a second memory for sequentially storing even-numbered image data for each 1H output from the seventh changeover switch (40) in a third area or a fourth area based on a timing signal. is there.

Reference numeral (43) denotes an eighth changeover switch, which is switched at the same time as the sixth changeover switch (39) by a timing signal, performs a changeover operation opposite to that of the seventh changeover switch (40), and
Output the even-numbered image data stored in the area or the fourth area.

This changeover switch serves as an output changeover switch for outputting even-numbered image data from a predetermined area of the memory.

(49) is an R signal data converter having the circuits of (35) to (43) described above.

(50) is a data conversion unit for G signal having the same circuit as the circuits (35) to (43) described above.

(55) is a data conversion unit for B signal which has the same circuit as the circuits (35) to (43) described above.

The image data stored in the memory area of the data conversion unit (25) stores image data of n words / 2 × m bits, where n is the number of horizontal pixels of the matrix LCD (13). However, m bits correspond to 2 ^m gradations.

FIG. 3 is a waveform chart for explaining the operation of the data converter.

In the figure, the waveform diagram shown in (a) is the A / D converter (24)
This is the serial image data.

The waveform diagram shown in (b) shows the odd image data from the sixth changeover switch (39), and the serial odd image data (37a) first output from the first area.
(Hereinafter referred to as first odd-numbered image data (37a)) and the following odd-numbered image data and subsequent time-axis expanded by a factor of two, indicating that the frequency is half that of serial image data. It is shown.

The waveform diagram shown in (c) shows the even image data from the eighth changeover switch (43), and the serial even image data (41a) first output from the third area.
(Hereinafter referred to as the first even-numbered image data (41a)) and the subsequent even-numbered image data and the subsequent time-axis expanded by a factor of two, and the frequency is reduced by half compared to the serial image data. It is shown.

The waveform diagram shown in (d) is image data (hereinafter referred to as parallel image data) output from the data conversion unit (25), and the odd-number image data and the eighth image data output from the sixth changeover switch (39). This shows that the even-numbered image data output from the changeover switch (43) is output at the same timing.

(T) indicates the signal time of one pixel,
(2T) indicates that image data for one pixel is output in a period of twice as long (2T).

Note that a seventh changeover switch (4
0), the second memory (41) and the eighth changeover switch (4
The image data from 3) is the same as the odd image data.

FIG. 4 is a waveform chart for explaining an output waveform from the driver, and shows that there is no distortion in the waveform.

The operation of the liquid crystal display device configured as described above will be described below with reference to the drawings.

For example, in order to display an image from the PC (1), the first switch unit (21), the second switch unit (27), and the third switch unit (31) are switched to each other to switch the PC.
It is assumed that the video signal from (1) is input.

Then, the analog RGB signal from the PC (1) is converted into a video signal (not shown) which has been subjected to color adjustment, brightness and contrast adjustment as necessary in the PC signal processing unit (23),
The A / D converter (24) converts an R signal, a G signal, and a B signal included in the video signal into an A / D converter (not shown) based on a timing signal from the timing signal forming unit (22).
And outputs the serial image data digitally converted to the data conversion unit (25).

In this case, it is assumed that 8-bit serial image data is output, and that it is output to the R signal data converter (49).

Next, the serial image data (24a) of the R signal from the A / D converter (24) is output to the fourth signal converter (49) of the R signal.
Are switched for each pixel by the timing signal from the timing signal forming unit (22), and the odd-numbered source line serial image data (odd-number image data) and the even-numbered As the source line serial image data (even image data), the odd image data is output to the fifth switch (36), and the even image data is output to the seventh switch (40).

Next, every time odd-numbered image data is output, the fifth switch (36) stores the odd-numbered image data for the 1H period in the first area of the first memory (37).

Further, every time even-number image data is output from the fourth change-over switch (35), the seventh changeover switch (40) stores even-numbered image data for a 1H period in the third area of the second memory (41). Store.

At this time, even if the odd image data is stored in the first area of the first memory (37), the sixth switch (39)
Retrieves the odd image data stored in the second area of the first memory (37), so that the odd image data stored in the first area is sent to the D / A conversion unit (26). Do not output.

Similarly, even when the eighth switch (43) stores the even-numbered image data in the third area of the second memory (41), the eighth switch (43) operates in the second memory (41). Since even image data stored in the fourth area of 41) is taken out, even image data stored in the third area is not output to the D / A converter (26).

Next, odd-numbered image data is stored in the first area by the fifth changeover switch (36) for 1H period, and even-numbered data is stored in the third area by 1H period by the seventh changeover switch (40). After being stored, the fifth changeover switch (36)
And a seventh changeover switch (40) is switched by the timing signal.

Further, the sixth changeover switch (39) is switched by the timing signal so as to take out odd-numbered image data from the first area as opposed to the fifth changeover switch (36).
The eighth changeover switch (43) is the seventh changeover switch (40)
Conversely, switching is performed so as to extract even-numbered image data from the third area.

Therefore, the first odd image data (37a) shown in FIG.
And the first even image data (41a) shown in FIG. 3 (c).
Is output to the D / A conversion unit (26) as parallel image data at the same time as shown in FIG. 3 (d). The frequency of the image data signal is halved.

Then, in order to output image data for the next line (for the next 1H), the fifth changeover switch (36) and the seventh changeover switch (40) are respectively connected to the first memory (37) of the first memory (37). After storing the data of the third area and the third area, the fifth changeover switch (36) and the seventh changeover switch (40) are operated by the timing signal to respectively change the second area and the second area of the second memory (41). The area is switched to store data in the fourth area, the odd image data is stored in the second area for 1H period, and the even data is stored in the second memory (41) by the seventh switch (40). Image data for the 1H period is stored in the area No. 4 respectively, and at the same time when the sixth changeover switch (39) and the eighth changeover switch (43) are switched as described above, the odd-numbered image data and the even-numbered image data ( (Parallel image data).

Therefore, each memory has two areas, and after extracting 1H of image data, the image storage is completed in the other area, so that the image data can be extracted without any problem.

Hereinafter, the odd-numbered image data up to the final source line (n) and the even-numbered image data up to the final source line (n) are output by the same operation, and the output of the data conversion unit (25) is shown in FIG. As described above, the odd-numbered image data and the even-numbered image data are output to the D / A converter (26) in parallel.

The same applies to the G signal data converter (50) and the B signal data converter (55).

Next, the D / A converter (26) inputs the parallel image data to the respective D / A converters, converts the parallel image data into analog signals, and converts the odd-numbered image data through the third switch unit (31). Output to the second buffer section (32) and at the same time
And outputs the even-numbered image data to the first buffer section (28) via the changeover switch section (27).

Next, when odd image data is output from the third changeover switch unit (31) to the second buffer unit (32), the second buffer unit (32) current-amplifies the signal of the odd image data. In response to the timing signal, a signal that is AC-inverted every 1H is output to the first X electrode source line driver (8).

Further, the first buffer unit (28) supplies the odd image data from the second changeover switch unit (27) to the first buffer unit (2).
When the data is output to 8), the even-numbered image data is current-amplified, and a signal obtained by AC inversion every 1H is output to the second X electrode source line driver (11) according to the timing signal.

Then, the first X-electrode source line driver (8) and the second X-electrode source line driver (11) sequentially and sequentially output odd-numbered image data and even-numbered image data having a frequency of 1/2 compared with the serial image data. Output to the matrix LCD (13).

Therefore, when output as parallel image data, the first
The X electrode source line driver (8) has a frequency characteristic of the eighth.
Even with the characteristics shown in the figure, the X-electrode drive signal without distortion shown in FIG. 4 is output, and the matrix LCD (13) outputs two signals at a time.
It is possible to display the pixels corresponding to the pixels, and it is possible to obtain a clear image in which the image is not deteriorated.

In addition, the first switch unit (21), the second switch unit (27), and the third switch unit (31) are VTRs.
If it is switched to output the composite video signal (not shown) from (2) to the downstream circuit, the analog composite video signal is output to the odd number via the second buffer unit (32) described above. The image data is output to the first X electrode source line driver (8), and the even image data is output to the second X electrode source line driver (1) via the first buffer unit (28).
Output to 1).

FIG. 5 is a schematic configuration diagram for explaining another embodiment of the data converter. Only the R signal will be described. In this figure, n (n) source lines are driven in parallel by k (k) lines.

In the figure, (25) to (43) are the same as those of the data conversion unit in FIG. 2, and (60) has k output units and
This is a plurality of changeover switch units that switch and output each pixel.

(61) a k-th changeover switch (hereinafter referred to as a k-th input changeover switch) which receives serial image data output from the kth output portion of the plurality of changeover switch portions (60) and switches every 1H according to a timing signal; Switch).

Reference numeral (62) denotes a k-th memory, which has two areas for storing image data output from the k-th input changeover switch (61) for each 1H period as in the memory of FIG. is there.

(63) is a k-th output switch, which is simultaneously switched with a plurality of output switches by a timing signal,
In a switching operation opposite to the k-th input changeover switch (61), one of the two areas of the k-th memory (62) is output.

Further, it is assumed that a required number of D / A converters and the like are provided in configuring the present embodiment.

The data conversion unit having the above configuration includes an A / D conversion unit (24)
A plurality of changeover switch units (60) output the analog RGB signals output from the unit to the k-th output unit for each pixel in the same manner as in FIG. 2 by the switching operation.

Then, predetermined image data is output in the order of the fifth changeover switch (36), the seventh changeover switch (40), and the kth input changeover switch (61).

Then, after the input changeover switches from the first changeover switch (36) to the kth input changeover switch (61) store predetermined image data in a predetermined area of each memory, the second changeover is performed.
Similarly to the figure, the output switches from the sixth changeover switch (39) to the k-th output switch (63) are switched, and the image data stored in the predetermined area of each memory is converted to the D / A converter (2).
In 6), k pieces are output in parallel.

That is, by storing image data to be stored in all memories in n words / k × m bits, the frequency output to the driver becomes 1 / k as in FIG. Image data can be output to the matrix LCD (13).

 However, actually, the number of components is increased, so the number is set to about ten.

FIG. 6 is a diagram illustrating a configuration using the present invention in a projection television. In the figure, (1) and (2)
Are similar to those in FIG.

Reference numeral (65) denotes an electric circuit unit having (23) to (32) in FIG. 1, and the second buffer unit (32) and the first buffer unit (28) correspond to the three primary colors of RGB. Each is equipped.

(66) has an X electrode source line driver for RGB color light for inputting a video signal from the buffer unit, and a Y electrode gate line driver for RGB color light for inputting a timing signal from the timing forming circuit (6). And a lens having a corresponding modulated liquid crystal light valve for RGB color light and a lens for projecting image light mixed and synthesized by the modulated liquid crystal light valve onto a screen (not shown).

The electric circuit unit (65) of the projection television configured as described above is configured as shown in FIG.
If 5) is configured as shown in FIG. 2, even if the frequency characteristic of each driver is the frequency characteristic shown in FIG. 7, the analog RGB signal from PC (1) can be converted into the parallel image data described above. This makes it possible to display a clear image on the screen.

 Further, the data conversion section may have the configuration shown in FIG.

Although the above embodiment has been described using the dot sequential driver, a line sequential driver may be used.

Further, in the case of double-speed scanning after digitally processing a video signal in IDTV, EDTV, etc., even if video data is output to the driver using the configuration of the data conversion unit in the video signal processing unit, the video signal is sharp in the conventional frequency band. Video is obtained.

Further, generally, when a video is supported, many gradation levels are required, and when the PC (1) is supported, only a small number of gradation levels are required. Therefore, when digital processing is executed only when the PC (1) is supported as in the present invention, The number of bits of the D / A converter is small.

As described above, according to the present embodiment, the video signal is divided into k (an integer of 2 or more) for one horizontal scan and k parallel video data is output to the driver.
The video is displayed by the output of the driver that sequentially reads the video data whose frequency has become 1 / k from the k buffers simultaneously, so even if the driver has the frequency characteristic corresponding to the composite video signal, the output signal is It is possible to obtain a signal having no distortion and to display a clear image.

Furthermore, since the video is displayed by switching to the composite video signal from the video signal processing unit and output from the driver, it is possible to obtain the effect that the composite video signal can also be handled by switching.

[Effects of the Invention] As described above, according to the present invention, data can be divided and stored, so that the data transfer frequency to the driver can be increased, and each block has a plurality of storage areas. Since the data conversion unit can output image data in parallel at the same output timing, the driver unit at the next stage can be controlled by the same phase signal, so that the operating frequency of the driver can be reduced overall and the consumption can be reduced. The effect that the electric power does not increase is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a liquid crystal display device showing a first embodiment of the present invention, FIG. 2 is a diagram illustrating the configuration of a data conversion unit, and a waveform diagram illustrating the operation of the data conversion unit in FIG. FIG. 4 is a waveform diagram illustrating an output waveform from a driver, FIG. 5 is a diagram illustrating a configuration of another embodiment of a data conversion unit,
FIG. 6 is a diagram illustrating a configuration when a projection television is used, FIG. 7 is a schematic configuration diagram of a conventional liquid crystal display device, FIG. 8 is a diagram illustrating a configuration of a liquid crystal display unit, and FIG. FIG. 10 is a diagram for explaining the frequency characteristics of the first X electrode source line driver, and FIG. 10 is a diagram for explaining the output signal of the first X electrode source line driver when a conventional PC video signal is input. In the figure, (1) is a PC, (2) is a VTR, (3) is a changeover switch unit, (4) is a signal processing unit, (5) is a buffer unit, (6) is a timing forming circuit, and (7) is A liquid crystal display unit, (21) is a first changeover switch unit, (22) is a timing signal forming circuit, (23) is a signal processing unit for PC, and (24) is A / A
D converter, (25) is a data converter, (26) is a D / A converter,
(27) is a second switch unit, (28) is a first buffer unit, (30) is a video signal processing unit, (31) is a third switch unit, and (32) is a second buffer unit. , (35) is the fourth
Switch, (36) is the fifth switch, (37)
Is the first memory, (39) is the sixth changeover switch, (40)
Is the seventh changeover switch, (41) is the second memory, (43)
Is an eighth changeover switch, (49) is a data conversion unit for R signal, (50) is a data conversion unit for G signal, and (55) is a data conversion unit for B signal.

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-64-68794 (JP, A) JP-A-63-71892 (JP, A) JP-A-62-11977 (JP, A) JP-A-1- 167794 (JP, A) JP-A-58-199391 (JP, A)

Claims (3)

(57) [Claims] An A / D converter for converting analog image data into a digital signal; dividing the digital signal by k (k = an integer of 2 or more) to obtain k
A data conversion unit that converts the image data signal into an image data signal and outputs the image data signal, and a D / A conversion unit that converts the image data signal into an analog signal and supplies the converted analog signal to a liquid crystal driver that drives a liquid crystal. A data conversion unit configured to sequentially switch and output the digital data to the k-block storage unit for each pixel unit;
Switching means provided for each block, a second switching means for switching and selecting an area of the storage means for storing the digital data for each scanning period, and a storage means provided for each block, One of the areas of the means not selected by the second switching means is switched and selected for each scanning period unit, and the data stored in the area is used as the image data signal by the D / A conversion unit. And a third switching means for outputting to the liquid crystal control device. 2. An A / D converter for converting analog image data into a digital signal, and dividing the digital signal by k (k = an integer of 2 or more) to obtain k
A data conversion unit that converts and outputs the image data signals, a D / A conversion unit that converts the image data signal into an analog signal, and an image based on the image analog signal output from the D / A conversion unit. A liquid crystal unit for displaying, wherein the data conversion unit sequentially switches and outputs the digital data to the k block storage unit for each pixel unit and a k block storage unit having a plurality of regions.
Switching means provided for each block, a second switching means for switching and selecting an area of the storage means for storing the digital data for each scanning period, and a storage means provided for each block, One of the areas of the means not selected by the second switching means is switched and selected for each scanning period unit, and the data stored in the area is used as the image data signal by the D / A conversion unit. And a third switching means for outputting to the liquid crystal display device. 3. An A / D converter for converting analog image data into a digital signal, and dividing the digital signal by k (k = an integer of 2 or more) to obtain k
A data conversion unit that converts and outputs the image data signals, a D / A conversion unit that converts the image data signal into an analog signal, and an image based on the image analog signal output from the D / A conversion unit. A liquid crystal unit for displaying, wherein the data conversion unit sequentially switches and outputs the digital data to the k block storage unit for each pixel unit and a k block storage unit having a plurality of regions.
Switching means provided for each block, a second switching means for switching and selecting an area of the storage means for storing the digital data for each scanning period, and a storage means provided for each block, One of the areas of the means not selected by the second switching means is switched and selected for each scanning period unit, and the data stored in the area is used as the image data signal by the D / A conversion unit. And a third switching means for outputting to the projection device.