JPH07325551A - Pixel array display device - Google Patents

Abstract

PURPOSE:To suppress the generation of a luminance difference and a decrease in contrast due to the delay of a sampling pulse signal. CONSTITUTION:A horizontal driver 11 includes a timing generator 11A and a sample holding circuit 11B. A horizontal driver 12 includes a timing generator 12% and a sample holding circuit 12B. Analog R, G, and B signals R, G, and B are supplied to sample holding circuits 11B and 12B respectively. A clock signal CLK is passed through variable phase shifters 31 and 32 and supplied as phase-shifted clock signals CLK1 and CLK2 to the timing generators. Consequently, the phases of the clock signals CLK1 and CLK2 supplied to the timing generators 11A and 12A are adjusted. The sampling points of the analog R, G, and B signals R, G, and B are therefore adjusted to proper points.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device in which pixels are arranged, such as a liquid crystal display and a plasma display driven by using a plurality of analog drivers.

[0002]

2. Description of the Related Art Conventionally, a display device (hereinafter referred to as a flat display) in which pixels are arranged, such as a liquid crystal display and a plasma display, has been known.

A horizontal driver for inputting a video signal to derive a pixel signal and a vertical driver for line-sequential scanning are used for a drive circuit of a liquid crystal panel in a liquid crystal display, for example, of the flat displays. In particular, in a drive circuit of a liquid crystal display in which a large number of pixels are provided due to high definition of the display, a plurality of horizontal drivers are used to support a large number of pixels.

An analog driver is generally used as a horizontal driver in order to realize multiple colors and multiple gradations in a liquid crystal panel. In this case, the gray level is displayed on the liquid crystal panel by applying an analog voltage corresponding to the gray level to the analog driver.

FIG. 7 is a block diagram of a conventional liquid crystal panel drive circuit. Referring to FIG. 7, the drive circuit for the liquid crystal panel includes a first horizontal driver 11, a second horizontal driver 12, a vertical driver 2, a liquid crystal panel 3 and a video processing circuit 5.

The liquid crystal panel 3 has pixels arranged in a matrix. The first horizontal driver 11 corresponds to the left half pixel of the liquid crystal panel 3 in the horizontal direction, and the second horizontal driver 12 corresponds to the right half pixel. The first horizontal driver 11 includes a timing generator 11A and a sample hold circuit 11B. The second horizontal driver 12 includes a timing generator 12A and a sample hold circuit 12B.

Each of the sample and hold circuits 11B and 12B includes a set of a predetermined number of elements including a switch SW, a capacitor C and a buffer amplifier BA as one set. The total number of sets of the elements in the sample hold circuits 11B and 12B is the same as the number of pixels arranged in the horizontal direction of the liquid crystal panel 3.

Each of timing generators 11A and 12A receives clock signal CLK. Each of the sample hold circuits 11B and 12B receives the analog R, G, B signals R, G, B output from the video processing circuit 5 at one end of each switch SW.

Further, the sample hold circuit 11B is
The output signal of the timing generator 11A is received as a control signal for each switch SW. Sample and hold circuit 1
2B receives the output signal of the timing generator 12A as a control signal for each switch SW. In each of the sample hold circuits 11B and 12B, a switch SW
The buffer amplifier BA and the capacitor C receive the signal from the other end.

The liquid crystal panel 3 receives the output signal of the vertical driver 2 and the output signals of the buffer amplifiers BA of the first horizontal driver 11 and the second horizontal driver 12, respectively.

Next, the operation of the drive circuit for the liquid crystal panel of FIG. 7 will be described. The sample-hold circuit 1 outputs analog R, G, B signals R, G, B as analog video signals which have been subjected to video processing such as γ correction in the video processing circuit 5.
It is input to each of 1B and 12B. Further, the clock signal CLK is input to each of the timing generators 11A and 12A.

Each of the timing generators 11A and 12A generates a sampling pulse signal having the same frequency as that of the analog R, G, B signals R, G, B based on the input clock signal CLK. The sampling pulse signal is given from the timing generator 11A to the sample hold circuit 11B and from the timing generator 12A to the sample hold circuit 12B.

In each of the sample-hold circuits 11B and 12B, each switch SW is closed at each timing of rising and falling of the sampling pulse signal, and the sampling values of the analog R, G, B signals R, G, B are sampled. Are held in the corresponding capacitors C.

Such a signal holding operation is performed in one horizontal period. Then, in the next horizontal period, the hold value of the capacitor C is output line-sequentially to the liquid crystal panel 3 via the corresponding buffer amplifier BA.

In the liquid crystal panel 3, the first horizontal driver 1
Based on the horizontal scanning by the first and second horizontal drivers 12 and the vertical scanning by the vertical driver 2, analog R,
An image based on the G, B signals R, G, B is displayed.

[0016]

However, the above-mentioned flat display having the drive circuit shown in FIG. 7 has the following problems. The problem will be described below. FIG. 8 is a timing chart showing main signal waveforms in the drive circuit of the liquid crystal panel of FIG.

In FIG. 8, the analog R, G and B signals R, G and B, the sampling pulse signal SP and the clock signal CLK are the first and second horizontal drivers 11 ,.
Shown for each of the twelve. In FIG. 8, x-
The left side of the x-ray is a waveform diagram for the first horizontal driver 11, and the right side thereof is a waveform diagram for the second horizontal driver 12.

The sampling pulse signal SP is sequentially set to 1 for each of the switches SW of the sample and hold circuits 11B and 12B for each pulse of the clock signal CLK.
It is given in pulses.

However, in FIG. 8, the sampling pulse applied to each switch SW in order to clarify the correspondence between the sampling pulse signal SP and the analog R, G, B signals R, G, B and the clock signal CLK. The signal SP is shown by combining in time series.

The first and second horizontal drivers 1 of FIG.
Since each of 1 and 12 is an analog driver,
The sampling pulse signal SP supplied to each of the sample hold circuits 11B and 12B according to electric characteristics such as a circuit constant of a circuit forming the analog driver is
As shown in FIG. 8, it is delayed with respect to the clock signal CLK.

Also, the first and second horizontal drivers 1
When 1 and 12 are provided in different LSI chips, the electrical characteristics differ between the LSI chips. In such a case, there is a delay difference between the sampling pulse signal SP supplied to the sample hold circuit 11B and the sampling pulse signal SP supplied to the sample hold circuit 12B due to the difference in electrical characteristics between the LSI chips. Generally, it will be 10 ns or more.

Here, the delay amount of the sampling pulse signal SP with respect to the clock signal CLK in the first and second horizontal drivers 11 and 12 of FIG. 7 is 5 ns, respectively.
Assume 15 ns. The analog R, G, B signals R, G, B have a bias of 2.5 V and a frequency of 15 M.
It is assumed that the sine wave has a frequency of Hz and an amplitude of 5 Vp-p.

In this case, the potential VA at the sampling point A of the maximum value of the analog R, G, B signals R, G, B on the side of the first horizontal driver in FIG. 8 becomes a value represented by the following equation (1). .

[0024]

[Equation 1]

Further, the potential VB at the sampling point B having the maximum value on the second horizontal driver side has a value represented by the following equation (2).

[0026]

[Equation 2]

In this way, if there is a delay difference in the sampling pulse signal SP between the first and second horizontal drivers,
A large potential difference occurs at the sampled maximum. As a result, there is a problem that a difference in brightness occurs between the left and right sides of the screen of the liquid crystal panel 3.

On the other hand, the potential VC at the minimum sampling point C on the side of the first horizontal driver has a value represented by the following equation (3).

[0029]

[Equation 3]

The potential VD at the minimum sampling point D on the second horizontal driver side has a value represented by the following equation (4).

[0031]

[Equation 4]

Here, paying attention to the potential difference between the sampling points BD, the amplitude of the analog R, G, B signals R, G, B is 5 Vp-p, whereas the potential difference between B-D is Only 0.78V. As a result, there is a problem that the contrast of the screen of the liquid crystal panel 3 is lowered.

In a display device such as a liquid crystal projector which uses three liquid crystal panels corresponding to each of R, G and B signals, a horizontal driver is required for each liquid crystal panel. In such a display device, if a delay difference in sampling pulse signals of the horizontal driver for each of the analog R, G, and B signals occurs, there is a problem that the white balance is lost.

The present invention has been made to solve such a problem, and a pixel array display device capable of suppressing the occurrence of a brightness difference and the deterioration of contrast due to the delay of a sampling pulse signal. The purpose is to provide.

[0035]

According to a first aspect of the present invention, there is provided a pixel array display device, which comprises display means in which pixels are arrayed, driving means and phase adjusting means, and the driving means includes pulse generating means and pulse generating means. Includes sample and hold means.

The driving means receives the video signal and the clock signal and drives the display means in response to these signals.

The pulse generating means included in the driving means generates a sampling pulse signal for sampling the video signal corresponding to each pixel arranged in the predetermined direction of the display means in response to the clock signal.

In response to the sampling pulse signal, the sample-hold means included in the driving means performs sample-hold of the video signal corresponding to each pixel arranged in the predetermined direction of the display means, and displays the hold value. Supply to.

The phase adjusting means adjusts the phase of the clock signal supplied to the driving means. According to a second aspect of the present invention, there is provided a pixel array display device, which comprises a display means in which pixels are arranged, a plurality of driving means and a plurality of phase adjusting means,
Each of the plurality of driving means includes a pulse generating means and a sample hold means.

Each of the plurality of driving means receives the video signal and the clock signal and drives the display means in response to these signals.

The pulse generating means included in each of the plurality of driving means generates a sampling pulse signal for sampling the video signal corresponding to each pixel arranged in the predetermined direction of the display means in response to the clock signal. .

The sample and hold means included in each of the plurality of drive means responds to the sampling pulse signal by
The sample and hold of the video signal is performed for each of the pixels arranged in the predetermined direction of the display means, and the hold value is supplied to the display means.

The plurality of phase adjusting means are provided corresponding to each of the plurality of driving means, and each adjusts the phase of the clock signal supplied to the corresponding driving means.

According to a third aspect of the present invention, there is provided a pixel array display device, which comprises display means in which pixels are arranged, a plurality of driving means and a phase adjusting means, each of the plurality of driving means being a pulse generating means and a pulse generating means. Includes sample and hold means.

The plurality of driving means are cascade-connected to sequentially receive the clock signal and the video signal, and each drive the display means in response to these signals.

The pulse generating means included in each of the plurality of driving means, in response to the clock signal, generates a sampling pulse signal for sampling the video signal corresponding to each pixel arranged in the predetermined direction of the display means. Let

The sample hold means included in each of the plurality of drive means is responsive to the sampling pulse signal,
The sample and hold of the video signal is performed for each of the pixels arranged in the predetermined direction of the display means, and the hold value is supplied to the display means.

The phase adjusting means has a plurality of operating states having different phase amounts and changes the adjusting amount of the phase of the clock signal by switching the operating states at a predetermined timing, whereby a plurality of driving means are provided. Adjust the phase of the clock signal supplied to.

The present invention according to claim 4 is a pixel array display device, wherein the phase adjusting means of the invention according to claim 3 includes a plurality of phase shifting means and switching means.

The plurality of phase shift means have different phase shift amounts,
Each phase-shifts and outputs a clock signal. The switching unit selectively supplies the phase-shifted clock signals output from each of the plurality of driving units to the plurality of driving units, and switches the selected state at a predetermined timing.

According to a fifth aspect of the present invention, there is provided a pixel array display device, which is a first display means in which pixels are arranged, a second display means in which pixels are arranged, and a third display means in which pixels are arranged. A first drive means, a second drive means, a third drive means, a first phase adjustment means, a second phase adjustment means and a third phase adjustment means, the first drive means being the first Pulse generating means and first sample and hold means of
The second driving means includes the second pulse generating means and the second sample and hold means, and the third driving means includes the third pulse generating means and the third sample and hold means.

The first driving means receives the first video signal and the clock signal and drives the first display means in response to these signals. The second drive means receives the second video signal and the clock signal, and drives the second display means in response to these signals. The third driving means receives the third video signal and the clock signal, and drives the third display means in response to these signals.

The first pulse generating means included in the first driving means samples the first video signal corresponding to each of the pixels arranged in the predetermined direction of the first display means in response to the clock signal. Generate a first sampling pulse signal for The first sample-hold means included in the first driving means responds to the first sampling pulse signal by applying the sample-hold of the first video signal to each of the pixels arranged in the predetermined direction of the first display means. Correspondingly, the hold value is supplied to the first display means.

The second pulse generating means included in the second driving means samples the second video signal corresponding to each of the pixels arranged in the predetermined direction of the second display means in response to the clock signal. To generate a second sampling pulse signal. The second sample hold means included in the second drive means responds to the second sampling pulse signal by applying sample hold of the second video signal to each of the pixels arranged in the predetermined direction of the second display means. Correspondingly, the hold value is supplied to the second display means.

The third pulse generating means included in the third driving means samples the third video signal corresponding to each of the pixels arranged in the predetermined direction of the third display means in response to the clock signal. To generate a third sampling pulse signal. The third sample-hold means included in the third driving means responds to the third sampling pulse signal by applying the sample-hold of the third video signal to each of the pixels arranged in the predetermined direction of the third display means. Correspondingly, the hold value is supplied to the third display means.

The first phase adjusting means adjusts the phase of the clock signal supplied to the first driving means. The second phase adjusting means adjusts the phase of the clock signal supplied to the second driving means. The third phase adjusting means adjusts the phase of the clock signal supplied to the third driving means.

[0057]

According to the present invention, the pulse generating means in the driving means generates the sampling pulse signal in response to the input clock signal. And
The sample hold means supplies the clock signal sampled in response to the sampling pulse signal to the display means. The phase of the clock signal supplied to the driving means is adjusted by the phase adjusting means. By adjusting its phase,
It is possible to adjust the sampling points in the video signal.

According to the second aspect of the present invention, the phase of the clock signal supplied to each driving means is adjusted by the corresponding phase adjusting means. Then, in each driving means, the pulse generating means generates a sampling pulse signal in response to the clock signal whose phase is adjusted. Then, the sample hold means supplies the video signal sampled in response to the sampling pulse signal to the display means. By adjusting the phase of the clock signal in this way, it is possible to adjust the sampling point in the video signal.

According to the present invention as set forth in claim 3, since the plurality of driving means are cascade-connected, each driving means sequentially receives the clock signal. The phase adjusting means switches its operating state at a predetermined timing when the driving means for sampling and holding is switched. The phase adjusting means switches the phase shift amount of the clock signal by switching the operation state. Therefore, the phase of the clock signal is adjusted corresponding to each driving means.

In each of the plurality of driving means connected in cascade, the pulse generating means generates the sampling pulse signal in response to the input clock signal. Then, the sample hold means supplies the video signal sampled in response to the sampling pulse signal to the display means.

As described above, since the phase of the clock signal is adjusted by the phase adjusting means, it is possible to adjust the sampling point in the video signal for each driving means.

According to the fourth aspect of the present invention, since the plurality of driving means are cascade-connected, each driving means sequentially receives the clock signal. The clock signal is
The phase is adjusted by the phase adjusting means. In the phase adjusting means, each of the plurality of phase shifting means outputs the phase-shifted clock signal. These clock signals are
Since the amount of phase shift is different, the amount of phase adjustment is different.

In the phase adjusting means, the switching means selectively supplies the phase-shifted clock signals output from the plurality of phase shifting means to the driving means. The phase-shifted clock signal in that case is switched at a predetermined timing, for example, when the driving means for performing sample and hold is switched. Therefore, the phase of the clock signal is adjusted corresponding to each driving means.

In each of the plurality of driving means connected in cascade, the pulse generating means generates the sampling pulse signal in response to the input clock signal. Then, the sample hold means supplies the video signal sampled in response to the sampling pulse signal to the display means.

As described above, since the phase of the clock signal is adjusted by the phase adjusting means, it is possible to adjust the sampling point in the video signal for each driving means.

According to the fifth aspect of the present invention, the first pulse generating means in the first driving means generates the first sampling pulse signal in response to the input clock signal. Then, the first sample-hold means supplies the first video signal sampled in response to the first sampling pulse signal to the first display means.

In the second driving means, the second pulse generating means generates the second sampling pulse signal in response to the input clock signal. Then, the second sample hold means supplies the second video signal sampled in response to the second sampling pulse signal to the second display means.

In the third driving means, the third pulse generating means generates the third sampling pulse signal in response to the input clock signal. Then, the third sample hold means supplies the third video signal sampled in response to the third sampling pulse signal to the third display means.

The clock signals supplied to the first, second and third driving means respectively have the first, second and third clock signals.
The phase is adjusted by the phase adjusting means. By adjusting the phase, it is possible to adjust the sampling points in each of the first, second and third video signals.

[0070]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing a schematic structure of a main part of a circuit constituting a flat display according to the first embodiment.

Referring to FIG. 1, the circuit of this flat display has a decoded video signal VS input from a tuner (not shown) and passed through a video detection circuit (not shown), and an external input terminal (not shown). The analog R, G, B signals R1, G1, B1 and the synchronizing signal SY1 as the video signals input from (1) are supplied.

The circuit of this flat display includes a chroma color demodulation circuit 41, a sync separation circuit 42, a timing control circuit 43, changeover switches 44, 44, 44, 45,
An image processing circuit 5, variable phase shifters 31, 32, a horizontal driver 1, a vertical driver 2 and a liquid crystal panel 3 are included.

The horizontal driver 1 is the first horizontal driver 1
Includes first and second horizontal drivers 12. The image processing circuit 5 includes a user control circuit 51, a γ correction circuit 52,
A polarity switching circuit 53 and a buffer amplifier 54 are included.

The decoded video signal VS is supplied to the chroma color demodulation circuit 41 and the sync separation circuit 42.

The chroma color demodulation circuit 41 demodulates the decoded video signal VS and outputs the analog R, G, B signals R2, G2.
B2 is generated. This analog R, G, B signal R2
Each of G2 and B2 is generated by synthesizing the color difference signal and the luminance signal. Analog R,
The G and B signals R2, G2 and B2 are supplied to the changeover switches 44, 44 and 44, respectively.

The changeover switches 44, 44, 44 have
Analog R, G, B signals R1, G1, B1 are also supplied. Each of the switches 44, 44, 44 is simultaneously switched by a predetermined control signal.

The switches 44, 44, 44 are analogs for causing the liquid crystal panel 3 to display any one set of the analog R, G, B signals R1, G1, B1 and R2, G2, B2 depending on the operation. R, G, B signals R, G,
B is supplied to the user control circuit 51.

The user control circuit 51 is a circuit for adjusting the contrast, bright and tint of the image displayed on the liquid crystal panel 3 according to the user's preference. The user control circuit 51 is supplied with a contrast control signal S1, a bright control signal S2, and a tint control signal S3.

The user control circuit 51 responds to the contrast control signal S1, the bright control signal S2, and the focus control signal S3, respectively, in response to the analog R,
Contrast, bright, and tint adjustment processing is performed on the G, B signals R, G, B.

The adjusted analog R, G, B signals R, G, B are output through the γ correction circuit 52, the polarity switching circuit 53 and the buffer amplifier 54. The output signal is the first and second horizontal drivers 1 of the horizontal driver 1.
It is supplied to each of 1 and 12.

The γ correction circuit 52 performs γ correction processing on the analog R, G, B signals R, G, B. Then, the polarity switching circuit 53 carries out a signal polarity switching process. Then, in the buffer amplifier 54, analog R,
The G, B signals R, G, B are amplified.

The sync separation circuit 42 separates the sync signal SY2 from the composite video signal VS and supplies the separated sync signal SY2 to the changeover switch 45. The synchronizing signal SY1 is also supplied to the changeover switch 45. Changeover switch 45
Switches in response to the same control signal as the control signal supplied to the switch 44, and its operation selectively supplies one of the synchronization signals SY1 and SY2 to the timing control circuit 43.

As a result, when the analog R, G, B signals R1, G1, B1 are selected by the changeover switch 44, the synchronizing signal SY1 is selected by the changeover switch 45, and conversely, the analog R, G signals are changed by the changeover switch 44. ，
When the B signals R2, G2 and B2 are selected, the changeover switch 45 selects the synchronization signal SY2.

The timing generation circuit 43 generates a clock signal for driving the first and second horizontal drivers 11 and 12 in the horizontal driver 1 and the vertical driver 2 based on the supplied synchronization signal. The clock signal is supplied to the vertical driver 2 and also to the first horizontal driver 11 via the variable phase shifter 31, and also to the second horizontal driver 1 via the variable phase shifter 32.
2 is supplied.

Next, the drive circuit of the liquid crystal panel 3 will be described in detail. FIG. 2 is a block diagram of a drive circuit for a liquid crystal panel according to the first embodiment. 2, the same parts as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted.

The drive circuit of FIG. 2 differs from the drive circuit of FIG. 7 in that the variable phase shifter 31 is provided in the signal line of the clock signal supplied to the timing generator 11A and the clock signal supplied to the timing generator 12A. That is, the variable phase shifter 32 is provided in the signal line.

Variable phase shifters 31 and 32 are, for example, variable delay lines or RC phase shifters. In operation, the variable phase shifter 31 advances the phase of the clock signal CLK by a predetermined amount (or delays the phase by a predetermined amount), and is supplied to the timing generator 11A as the clock signal CLK1. In addition, the clock signal CLK
Is advanced by a predetermined amount (or delayed by a predetermined amount) by the variable phase shifter 32, and is supplied to the timing generator 12A as the clock signal CLK2. The variable phase shifter 32 is set such that its phase shift amount is larger than that of the variable phase shifter 31.

FIG. 3 is a timing chart showing main signal waveforms in the drive circuit of the liquid crystal panel of FIG.

In FIG. 3, analog R, G, B signals R, G, B, sampling pulse signal SP, and clock signals CLK1 and CLK2 are shown.

In FIG. 3, the left side of the line xx is the waveform diagram for the first horizontal driver 11, and the right side thereof is the waveform diagram for the second horizontal driver 12. In FIG. 3 as well, similar to FIG. 8, the sampling pulse signals SP are shown combined in time series.

Here, the delay amount of the sampling pulse signal SP in the first horizontal driver 11 with respect to the clock signal CLK1 is 5 ns, and the second horizontal driver 12
It is assumed that the delay amount of the sampling pulse signal SP with respect to the clock signal CLK2 is 15 ns. Also, the analog R, G, B signals R, G, B have a frequency of 15 V with a bias of 2.5 V and an amplitude of 5 Vp-.
Suppose it is a sine wave of p.

This assumption is based on the above (1) to (4).
It is the same as the condition of the formula. Therefore, the clock signal CL
When K is directly supplied to the first horizontal driver 11 and the second horizontal driver 12, as shown in FIG. 8, the luminance difference between the left and right screens of the liquid crystal panel 3 due to the delay of the sampling pulse signal SP and A decrease in contrast will occur.

In the circuit of FIG. 2, the amount of phase advance by the variable phase shifter 31 is set to 5 ns. That is, the amount of phase advance in the variable phase shifter 31 is set to a value that eliminates the delay amount of the sampling pulse signal SP in the first horizontal driver 11.

Further, the amount of advance of the phase shift by the variable phase shifter 32 is set to 15 ns. That is, the amount of phase advance in the variable phase shifter 32 is set to a value that eliminates the delay amount of the sampling pulse signal SP in the second horizontal driver 12.

Such setting is performed by the variable phase shifters 31 and 3
If done at 2, the phase of the clock signal CLK1 is advanced by 5n with respect to the clock signal CLK, and the phase of the clock signal CLK2 is advanced by 15ns with respect to the clock signal CLK.

Therefore, the clock signal CLK is
Sampling pulse signal S based on each of clock signals CLK1 and CLK2 whose phase is advanced with respect to
In P, the delay is eliminated.

Therefore, the potential at the sampling point E of the maximum value of the analog R, G, B signals R, G, B in the first horizontal driver 11 is 5V. The potential at the minimum sampling point G is 0V.

Further, the potential at the sampling point F of the maximum value of the analog R, G, B signals R, G, B in the second horizontal driver becomes 5V. Then, the potential at the sampling point H having the minimum value is 0V.

As described above, since the potential difference between the sampling points E and F is eliminated, there is no luminance difference between the left and right screens of the liquid crystal panel 3. Furthermore, the potential difference between the sampling points E and G and the potential difference between the sampling points F and H are both 5V.
Since it is pp, the contrast is not impaired at all.

In the first embodiment, an example in which the variable phase shifter 31 advances the phase of the clock signal CLK by 5 ns and the variable phase shifter 32 advances the phase of the clock signal CLK by 15 ns has been described. The same effect as the case can be obtained by delaying the phase of the clock signal CLK by a predetermined amount.

Specifically, under the conditions as described above, the variable phase shifter 31 delays the phase of the clock signal CLK by 71.7 ns, and the variable phase shifter 32 delays the phase of the clock signal CLK by 81.7 ns. Just delay it.

Second Embodiment Next, a second embodiment will be described. In the second embodiment, an example will be described in which, in a display device having horizontal drivers connected in cascade, the occurrence of a difference in brightness and the reduction in contrast due to the delay of sampling pulses are eliminated.

FIG. 4 is a block diagram of a drive circuit for a liquid crystal panel according to the second embodiment. The circuit of FIG. 4 is different from that of FIG. 2 in that the horizontal driver 11 and the horizontal driver 12 are cascade-connected, and the variable phase shifter 31,
One variable phase shifter 30 is provided instead of 32.

In the horizontal drivers 11 and 12,
The timing generator 11A and the timing generator 12A are cascade-connected. The clock signal is
First, it is supplied to the timing generator 11A and then to the timing generator 12A via the timing generator 11A.

Therefore, the timing generator 11
A and 12B operate in response to a clock signal provided from one path. The basic operation of these timing generators 11 and 12 is the same as that shown in FIG.

As the variable phase shifter 30, for example, a variable delay line or an RC phase shifter capable of changing the amount of phase shift is used. The variable phase shifter 30 operates in the first
And a second operation state having a second phase shift amount are selectively formed.

The first phase shift amount in this case is the same as the phase shift amount set in the variable phase shifter 31 of FIG. The second phase shift amount in this case is the same as the phase shift amount set in the variable phase shifter 32 in FIG.

The variable phase shifter 30 receives the switching signal φ1 and
The operating state is switched in response to the switching signal φ1. The control signal φ1 changes in signal state in synchronization with the timing when the horizontal driver to be sampled and held shifts from the horizontal driver 11 to the horizontal driver 12.

In response to such a change in the signal state of switching signal φ1, variable phase shifter 30 switches the operating state from the first operating state to the second operating state. As a result, in the variable phase shifter 30, the setting of the phase shift amount is switched from the first phase shift amount to the second phase shift amount.

Next, the operation of the liquid crystal panel drive circuit of FIG. 4 will be described. The variable phase shifter 30 uses the clock signal CL
The phase of K is adjusted and the clock signal is adjusted to the horizontal driver 1
Supply to 1. The clock signal supplied to the horizontal driver 11 is supplied from the horizontal driver 11 to the horizontal driver 12. As a result, the horizontal driver 11 starts sample hold first, and then the horizontal driver 12 starts sample hold.

At the time when the horizontal driver 11 is sampling and holding, the phase shift of the clock signal CLK is performed by the first phase shift amount set in the variable phase shifter 30. Then, when the horizontal driver 12 starts the sample hold, the setting of the phase shift amount of the variable phase shifter 30 is switched from the first phase shift amount to the second phase shift amount.

Therefore, the horizontal driver 11 performs sample and hold based on the clock signal which has been phase-shifted by the first phase shift amount, and the horizontal driver 12 is phase-shifted by the second phase shift amount. The sample and hold is performed based on the clock signal obtained.

Therefore, in the liquid crystal panel drive circuit according to the second embodiment, the same effect as that of the liquid crystal panel drive circuit shown in the first embodiment can be obtained. Therefore, according to the second embodiment, it is possible to prevent a difference in brightness and a decrease in contrast due to the delay of the sampling pulse in the display device including the horizontal drivers connected in cascade.

Third Embodiment Next, a third embodiment will be described. In the third embodiment, another example of the portion for adjusting the phase of the clock signal supplied to the horizontal driver in the display device including the cascaded horizontal drivers will be described. FIG. 5 is a block diagram of a liquid crystal panel drive circuit according to the third embodiment. The liquid crystal panel drive circuit shown in FIG. 5 differs from that shown in FIG. 4 in the phase adjustment circuit 300. This phase adjusting circuit 300 is the same as the variable phase shifter 30 of FIG.
The variable phase shifters 31, 32 and the changeover switch 33 are included.

Each of the variable phase shifters 31 and 32 is
It is similar to that shown in FIG. Therefore,
A first phase shift amount is set in the variable phase shifter 31,
A second phase shift amount is set in the variable phase shifter 32. The variable phase shifter 31 phase-shifts the clock signal CLK by the first phase shift amount, and the phase-shifted clock signal CLK1
Is supplied to the changeover switch 33. The variable phase shifter 32 shifts the clock signal CLK by a second phase shift amount, and switches the clock signal CLK2 having undergone the phase shift by the changeover switch 33.
Supply to.

The change-over switch 33 has a clock signal CLK.
1 and CLK2 as well as control signal φ1. This control signal φ1 is the same as that shown in FIG.
Change-over switch 33 selectively supplies clock signals CLK1 and CLK2 to timing generator 11A in response to control signal φ1.

Next, the operation of the liquid crystal panel drive circuit shown in FIG. 5 will be described. When the horizontal driver 11 is sampling and holding, the changeover switch 33 selects the clock signal CLK1 and supplies the signal to the timing generator 11A. Then, when the horizontal driver 12 starts the sample hold, the changeover switch 33 selects the clock signal CLK2 in response to the change of the control signal φ1 and supplies the selected signal to the timing generator 11A.

As a result, the horizontal driver 11 performs sample hold based on the clock signal CLK1 that has been phase-shifted by the first phase shift amount, and the horizontal driver 12
Is a clock signal C that has been phase-shifted by a second phase-shift amount.
Sample hold is performed based on LK2.

Therefore, in the liquid crystal panel drive circuit according to the third embodiment, the same effect as that of the liquid crystal panel drive circuit according to the second embodiment can be obtained.

Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, an example in which the variable phase shifter 30 used in the second embodiment is applied to a display device using three liquid crystal panels (hereinafter referred to as a three-panel liquid crystal panel display) Show.

A typical example of such a three-panel liquid crystal panel display is a liquid crystal projector. In this liquid crystal projector, an image is formed on the liquid crystal panel for each color signal of R, G and B, and the combined image is projected on the screen.

FIG. 6 is a block diagram of a drive circuit for a liquid crystal panel according to the fourth embodiment. Referring to FIG. 6, horizontal drivers 110R and 120R, vertical driver 2R and liquid crystal panel 3R are for R signals. Their configuration is the same as that shown in FIG. Horizontal driver 1
A variable phase shifter 30R is provided on the signal line through which the clock signal CLK is transmitted to 10R. As a result, the clock signal phase-shifted by the variable phase shifter 30R is supplied to the horizontal driver 110R. The analog R signal R is supplied to each of the horizontal drivers 110R and 120R.

The horizontal drivers 110G and 120G, the vertical driver 2G and the liquid crystal panel 3G are for G signals. Their configuration is the same as that shown in FIG. A variable phase shifter 30G is provided on the signal line through which the clock signal CLK is transmitted to the horizontal driver 110G. As a result, the clock signal phase-shifted by the variable phase shifter 30G is supplied to the horizontal driver 110G. Analog G
The signal G is supplied to each of the horizontal drivers 110G and 120G.

The horizontal drivers 110B and 120B, the vertical driver 2B and the liquid crystal panel 3B are for B signals. Their configuration is the same as that shown in FIG. A variable phase shifter 30B is provided on the signal line through which the clock signal CLK is transmitted to the horizontal driver 110B. As a result, the clock signal phase-shifted by the variable phase shifter 30B is supplied to the horizontal driver 110B. Analog B
The signal B is supplied to each of the horizontal drivers 110B and 120B.

Each of variable phase shifters 30R, 30G and 30B is similar to variable phase shifter 30 shown in FIG. 4, and each is controlled based on common control signal φ1. In this three-panel liquid crystal panel display, images corresponding to analog R, G, B signals R, G, B are displayed on the liquid crystal panels 3R, 3G, 3B by color.

Even in such a three-panel liquid crystal panel display, the horizontal drivers 110R and 110G are operated by the respective functions of the variable phase shifters 30R, 30G and 30B.
And the clock signal provided to each of 110B is delayed. Therefore, similarly to the drive circuits according to the first to third embodiments, it is possible to suppress the occurrence of the brightness difference between the left and right screens and the decrease in the contrast due to the delay of the sampling pulse signal SP.

Further, in this three-plate type liquid crystal panel display, the change of the white balance due to the delay of the sampling pulse signal SP is suppressed by the respective functions of the variable phase shifters 30R, 30G and 30B.

In the above embodiments, an example in which a plurality of horizontal drivers are provided has been described. However, the present invention is not limited to this, and even when there is only one horizontal driver, the analog R, G, B signals are delayed. By doing so, it is possible to properly suppress the occurrence of a brightness difference between the left and right screens and the decrease in contrast in the liquid crystal panel.

Although the liquid crystal panel display has been described in the above embodiments, the present invention can be applied not only to the liquid crystal panel display but also to a flat display such as a plasma display device.

[0131]

According to the present invention described in claim 1, the phase of the clock signal supplied to the driving means is adjusted by the phase adjusting means. Thereby, the sampling point of the video signal based on the sampling pulse signal of the sample hold means can be adjusted as a whole. Therefore, the sampling point corresponding to each pixel can be set to a portion close to the peak value of the video signal. Therefore, it is possible to suppress the occurrence of a brightness difference and the decrease in contrast due to the delay of the sampling pulse signal.

According to the second aspect of the present invention, the phase of the clock signal supplied to each of the plurality of driving means is adjusted by the corresponding phase adjusting means. Thereby, the sampling point of the video signal based on the sampling pulse signal of the sample hold means can be adjusted for each driving means.

Therefore, the sampling point corresponding to each pixel can be set to the peak value of the video signal for each driving means. Therefore, it is possible to suppress the occurrence of a brightness difference and the decrease in contrast due to the delay of the sampling pulse signal.

According to the third aspect of the present invention, in the phase adjusting means, for example, the operation state is switched at a predetermined timing when the driving means for performing sample hold is switched. Therefore, clock signals with different phase shifts
It is supplied to the driving means connected in cascade. Therefore, the phase of the clock signal supplied is adjusted for each drive unit.

Thus, the sampling point of the video signal based on the sampling pulse signal of the sample hold means can be adjusted for each driving means. Therefore, the sampling point corresponding to each pixel can be set to the peak value of the video signal for each driving unit. Therefore, it is possible to suppress the occurrence of a brightness difference and the decrease in contrast due to the delay of the sampling pulse signal.

According to the fourth aspect of the present invention, in the phase adjusting means, a plurality of clock signals having different phase shifts which are phase-shifted by the plurality of phase shift means are selectively supplied to the driving means. . The switching of the selection is performed, for example, at a predetermined timing when the driving means for performing sample hold is switched.

Therefore, clock signals having different phase shift amounts are supplied to the driving means connected in cascade. Thereby, the sampling point of the video signal based on the sampling pulse signal of the sample hold means can be adjusted for each driving means. Therefore, the sampling point corresponding to each pixel can be set to the peak value of the video signal for each driving unit. Therefore, it is possible to suppress the occurrence of a brightness difference and the decrease in contrast due to the delay of the sampling pulse signal.

According to the present invention described in claim 5,
The respective phases of the clock signals supplied to the second and third driving means are adjusted by the first, second and third phase adjusting means. Thereby, in each drive means,
The sampling point of the video signal based on the sampling pulse signal of the sample hold means can be adjusted as a whole. Therefore, the sampling point corresponding to each pixel in each of the first, second and third display means can be set to a portion close to the peak value of the video signal.

Therefore, it is possible to suppress the occurrence of the brightness difference and the decrease in the contrast due to the delay of the sampling pulse signal for each display means. Further, it is possible to suppress a change in white balance when the images on the first, second and third display means are combined.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a main part of a circuit constituting a flat display according to a first embodiment.

FIG. 2 is a block diagram of a drive circuit for a liquid crystal panel according to the first embodiment.

3 is a timing chart showing main signal waveforms in the drive circuit of the liquid crystal panel of FIG.

FIG. 4 is a block diagram of a drive circuit for a liquid crystal panel according to a second embodiment.

FIG. 5 is a block diagram of a drive circuit for a liquid crystal panel according to a third embodiment.

FIG. 6 is a block diagram of a drive circuit for a liquid crystal panel according to a fourth embodiment.

FIG. 7 is a block diagram of a drive circuit of a conventional liquid crystal panel.

8 is a timing chart showing main signal waveforms in the drive circuit of the liquid crystal panel of FIG.

[Explanation of symbols]

1, 11, 12, 110R, 120R, 110G, 12
0G, 110B, 120B Horizontal driver 3, 3R, 3G, 3B Liquid crystal panel 30, 31, 32, 30R, 30G, 30B Variable phase shifter 11A, 12A Timing generator 11B, 12B Sample hold circuit 33 Changeover switch 71, 72, 73 D / A conversion circuit 300 Phase shift control circuit

Claims (5)

[Claims] 1. A display unit in which pixels are arranged, and a drive unit that receives a video signal and a clock signal and drives the display unit in response to these signals, wherein the drive unit responds to the clock signal. Then, pulse generating means for generating a sampling pulse signal for sampling the video signal corresponding to each of the pixels arranged in the predetermined direction of the display means, and in response to the sampling pulse signal, Sample hold is performed corresponding to each of the pixels arranged in the predetermined direction of the display means, and the hold value is supplied to the display means, and the phase of the clock signal supplied to the drive means is included. A pixel array display device comprising a phase adjusting means for adjusting. 2. A display means in which pixels are arranged, and a plurality of drive means for receiving the video signal and the clock signal and driving the display means in response to these signals, each of the plurality of drive means Responding to the clock signal, pulse generating means for generating a sampling pulse signal for sampling the video signal corresponding to each pixel arranged in a predetermined direction of the display means, and responding to the sampling pulse signal. A sample hold means for performing sample hold of the video signal corresponding to each of the pixels arranged in the predetermined direction of the display means and supplying the hold value to the display means. A plurality of phase adjusters that are provided corresponding to each and adjust the phase of the clock signal supplied to the corresponding drive means. Comprising means, pixel array display device. 3. A display means in which pixels are arranged, and a plurality of driving means connected in cascade to sequentially receive a clock signal and a video signal, and each drive means for driving the display means in response to these signals. A pulse generating means for generating a sampling pulse signal for sampling the video signal corresponding to each of the pixels arranged in a predetermined direction of the display means, in response to the clock signal, And sample-hold means for performing sample-hold of the video signal corresponding to each of the pixels arranged in the predetermined direction of the display means in response to the sampling pulse signal and supplying the hold value to the display means. Further comprising phase adjusting means for adjusting the phases of the clock signals supplied to the plurality of driving means, The pixel array display device, wherein the phase adjusting means has a plurality of operating states having different phase shift amounts, and changes the operating state of the clock signal at a predetermined timing to change the adjusting amount of the phase of the clock signal. 4. The phase adjusting means has different phase shift amounts, and each of the phase adjusting means outputs a plurality of phase shift means for shifting and outputting the clock signal and a plurality of phase shift means. 4. The pixel array display device according to claim 3, further comprising switching means for selectively supplying a phase-shifted clock signal to the plurality of driving means and switching the selected state at a predetermined timing. 5. A first display means in which pixels are arranged, a second display means in which pixels are arranged, a third display means in which pixels are arranged, a first video signal and a clock signal, and these First driving means for driving the first display means in response to the signal, and a second video signal and a clock signal for driving the second display means in response to these signals. 2 driving means, and 3rd driving means for receiving the 3rd video signal and clock signal and driving said 3rd display means in response to these signals, said 1st driving means, A first pulse for generating a first sampling pulse signal for sampling the first video signal corresponding to each of the pixels arranged in the predetermined direction of the first display means in response to the clock signal. Generating means, the first In response to the sampling pulse signal, sample hold of the first video signal is performed corresponding to each of the pixels lined up in the predetermined direction of the first display unit, and the hold value is displayed on the first display unit. A first sample-hold means for supplying the second sample, and the second driving means is responsive to the clock signal to correspond to each of the pixels arranged in a predetermined direction of the second display means. Second pulse generating means for generating a second sampling pulse signal for sampling the video signal; and sample holding of the second video signal in response to the second sampling pulse signal. Second sample and hold means which performs the hold value corresponding to each of the pixels arranged in the predetermined direction of the display means and supplies the hold value to the second display means. In the third driving means, in response to the clock signal, the third driving means samples a third video signal corresponding to each of the pixels arranged in the predetermined direction of the third display means. A third pulse generating means for generating a sampling pulse signal; and a pixel holding sample and hold of the third video signal in response to the third sampling pulse signal, the pixels being arranged in the predetermined direction of the third display means. A third sample-hold means for supplying the hold value to the third display means corresponding to each of them, and adjusting the phase of the clock signal supplied to the first drive means. Phase adjusting means, second phase adjusting means for adjusting the phase of the clock signal supplied to the second driving means, and phase adjustment of the clock signal supplied to the third driving means. Pixel array display device, comprising: