JPH0777951A - Device for synchronizing pixel - Google Patents

Abstract

PURPOSE:To provide a pixel synchronizing device capable of optimally sampling even when a sampling pulse is delayed. CONSTITUTION:An input analog signal is subjected to sample-and-hold by sample-hold circuits 41, 42, 43, and a rectangular wave is formed, and the rectangular wave is supplied to sample/hold parts 21B, 22B in horizontal drivers 21, 22. Then, in timing generator parts 21A, 22A in the horizontal drivers 21, 22, the sampling pulse is formed based on an input pulse, and the rectangular wave is subjected to sample-and-hold again according to the sampling pulse. Then, hold values held by the sample/hold parts 21B, 22B are supplied to a display pannel 3 in line sequentiality.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display in which pixels are arranged, such as a liquid crystal display or a plasma display driven by using a plurality of analog drivers.

[0002]

2. Description of the Related Art Conventionally, a flat display, particularly a liquid crystal panel drive circuit, uses a horizontal driver for inputting a video signal and deriving a pixel signal and a vertical driver for line-sequential scanning. In many flat displays, multiple horizontal drivers are used.

Generally, in order to realize multi-color and multi-gradation in a liquid crystal panel, an analog driver is used as a horizontal driver, and an analog voltage corresponding to an intermediate gradation is applied to this analog driver. Displaying halftone.

A conventional drive circuit will be described below with reference to FIGS. 8 and 9.

FIG. 8 shows a drive circuit for the liquid crystal panel,
FIG. 9 shows the timing chart.

In FIG. 8, the R, G, B signals are initially rectangular waves, but the signals are integrated by the signal processing circuit 1 to become analog signals close to a sine wave.

The analog R, G, B signals are input to horizontal drivers 21 and 22. Here, the horizontal drivers 21 and 22 are the timing generator 21A,
22A and sample / hold sections 21B and 22B.

Then, the timing generator sections 21A and 22A of the horizontal drivers 21 and 22 create a sampling pulse having the same frequency as the frequency of the input video signal based on the start pulse, and the sampling pulse is held in the sample / hold sections 21B and 22B. Output to. The sample / hold units 22A and 22B are composed of a switch, a capacitor, and a buffer amplifier, and the switches are closed by the rising and falling of the sampling pulse, and the input R, G, B signals are The hold value is held in the capacitor and the hold value is output to the liquid crystal panel 3 line-sequentially via the buffer amplifier.

However, since the horizontal driver is composed of the analog driver, the sampling pulse supplied to the sample / hold units 21B and 22B is delayed with respect to the input pulse as shown in FIG. And
The delay difference between the sampling pulse supplied to the sample / hold unit 21B and the sampling pulse supplied to the sample / hold unit 22B is generally 10 ns or more, although it depends on the variation in the characteristics of the horizontal driver. I will end up.

Now, the delay difference between the sampling pulses of the horizontal drivers 21 and 22 is 10 ns, the delay amounts with respect to the input pulse are 5 ns and 15 ns, respectively, and the input video signal has a bias of 2.5 V and a frequency of 15 MHz and an amplitude of 5 Vp- Assuming a sine wave of p, the potential VA at point A in FIG.

[0011]

[Equation 1] And the potential VB at point B is

[0012]

[Equation 2] Therefore, a large potential difference is generated at the maximum value, and a luminance difference is generated on the left and right sides of the screen.

On the other hand, the potential VC at point C, which is the minimum value,
, And D at point D are

[0014]

[Equation 3]

[0015]

[Equation 4] Therefore, while the amplitude of the input video signal is 5 Vp-p, the potential difference between B and D is only 0.78 V, and the contrast is lost.

Further, when three liquid crystal panels are used,
The horizontal driver has a horizontal driver 2 for each R, G, B signal.
1 and 22 are required, and the white balance is lost due to the phase difference between the sampling pulses of the horizontal driver for each signal.

[0017]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to obtain a pixel synchronizer capable of performing optimum sampling even if the sampling pulse is delayed.

[0018]

According to the present invention, there is provided a sample hold circuit for sampling and holding an input video signal to create a rectangular wave, and a phase control means for controlling the phase of a sampling clock input to the sample hold circuit. A driver having a sample / hold unit and a timing generator unit which receive the rectangular wave from the sample / hold circuit, and a display panel for displaying an image by a signal from the sample / hold unit. It is a pixel synchronizer.

The present invention also relates to a phase control means for controlling the phase of the input video signal, a sample hold circuit for sample-holding the video signal phase-controlled by the phase control means to create a rectangular wave, and the sample. Pixel synchronizer comprising a driver having a sample / hold unit that receives a rectangular wave from a hold circuit and a timing generator unit, and a display panel that displays an image by a signal from the sample / hold unit. Is.

[0020]

According to the present invention, with the configuration as described above, the input analog signal is sampled and held by the sample and hold circuit to create a rectangular wave, and this rectangular wave is supplied to the sample / hold unit in the horizontal driver. Then, in the timing generator unit in the horizontal driver, a sampling pulse is created based on the input pulse, and the above rectangular wave is sampled and held again in accordance with this sampling pulse. Next, the hold value held by the sample / hold unit is line-sequentially supplied to the display panel.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an embodiment showing a pixel synchronizing device of the present invention, and FIG. 2 is a timing chart thereof. 3 is a specific circuit diagram of the sample hold circuit, and FIG. 4 is its timing chart.

In FIG. 1, a signal processing circuit (not shown)
The analog R, G, and B signals demodulated by are input to the R sample and hold circuit 41, the G sample and hold circuit 42, and the B sample and hold circuit 43, respectively.

Each sample hold circuit 41, 42, 43
A sample hold clock is input to the input terminal via the delay circuit 5, and analog R, G, B signals are sampled at the rising and falling edges of the sample hold clock. Here, the delay amount of the first delay circuit 5 is controlled so that the rising or falling of the sample hold circuit 5 is synchronized with the peaks or troughs of the analog R, G, B signals.

Then, the sample and hold circuits 41 and 4 are provided.
The R, G, and B signals sampled at 2 and 43 are combined according to the pattern of the color filter of the liquid crystal panel and supplied to the horizontal drivers 21 and 22 as a rectangular wave.

The horizontal drivers 21 and 22 are composed of the timing generator sections 21A and 22A and the sample / hold section 2.
1B and 22B, and the above-mentioned rectangular wave is input to the sample / hold units 21B and 22B.

Timing generator sections 21A and 22A
Receives an input pulse and a start pulse via the second delay circuit 6, of which the input pulse is used for creating the sampling pulse of the sample / hold units 21B and 22B, and the start pulse is horizontal from the horizontal driver 21. It is used as a switching pulse to the driver 22.

The rectangular waves input to the sample / hold sections 21B and 22B are sampled and held again based on the input pulse, but the phase of the sampling pulse is different due to variations in the characteristics of each horizontal driver.

Then, the sample-held R, G,
The B signal is line-sequentially supplied to the liquid crystal panel 3 by a signal synchronized with one horizontal synchronizing signal from the vertical driver 7.

Next, the operation of the pixel synchronization device of the present invention will be described.

First, the analog R, G, B signals are sine waves (for example, 1
The signal is close to 5 MHz).

The analog R, G and B signals are supplied to the E, G and F points by the sampling clock shown in FIG. 2B whose delay amount is controlled by the first delay circuit 5 in each of the sample and hold circuits 41, 42 and 43. , And H points are respectively sampled, the values are retained, and the rectangular waves shown in FIG. 2C are created.

Then, the respective rectangular waves are supplied to the horizontal drivers 21 and 22.

The horizontal drivers 21 and 22 are externally supplied with the input pulse and start pulse shown in FIG. 2E, and these pulses are input to the timing generator sections 21A and 22A in the horizontal drivers 21 and 22, respectively. . Then, the timing generator 21A is first activated by the start pulse, and the timing generator 21A supplies the sampling pulse shown in FIG. 2D to the sample / hold 21B. The sample / hold unit 21B samples a rectangular wave based on the above-described sampling pulse.

Here, the sampling pulse is delayed by t1 with respect to the input pulse, but since the signal to be sampled is a rectangular wave, the sampling pulse is t1 rather than points E and G.
Even if sampling is performed at the delayed E'point and G'point, E
Signals at the same level as the points and the points G can be sampled.

When the sampling / holding section 21B of the horizontal driver 21 finishes sampling, the horizontal driver 22 is put into operation.

In the horizontal driver 22, the sampling pulse shown in FIG. 2D is supplied from the timing generator section 22A to the sample / hold section 22B. The sample / hold unit 22B samples a rectangular wave based on the above-described sampling pulse.

Here, the sampling pulse is delayed by t2 with respect to the input pulse, but since the signal to be sampled is a rectangular wave, it is t2 rather than points F and H.
Even if sampling is performed at the delayed F'point and H'point, F
It is possible to sample a signal having the same level as the point and the point H.

Next, the sample and hold circuits 41, 42,
The circuit and operation of the circuit 43 will be described with reference to FIGS. 3 and 4.

Incidentally, FIG. 3 is a concrete circuit diagram of the sample hold circuit, and FIG. 4 is a timing chart thereof.

The input analog video signal shown in FIG. 4A is supplied to the buffer amplifier BF1.

Here, the switches SW1 to SW4 are shown in FIG.
B and the sampling clocks CK1 and CK2 shown in FIG. 4D are supplied, the switches SW1 and SW4 are turned on during the high level period of the sampling clock CK1, and the switches SW2 and SW3 are sampling clocks. CK1 is the inverter I
The sampling clock CK2 inverted by NV is turned on during a high level period.

The video signal potential that has passed through the buffer amplifier BF1 is passed through the switch SW1 during the high level period of the sampling clock CK (the low level period of the sampling clock CK2) and the capacitor C as shown in FIG. 4E.
The potential charged in the capacitor C2 while being charged to 1 is the switch SW4 and the buffer amplifier BF.
It is outputted via 2 as shown in FIG. 4C.

Next, while the sampling clock CK1 is at the low level (the sampling clock CK2 is at the high level), the video signal potential is charged in the capacitor C2 via the switch SW2 as shown in FIG.
The potential charged in the capacitor C1 is the switch SW.
3 and the B amplifier amplifier BF2 as shown in FIG. 4C.

In this way, the sample hold operation of the analog video signal is performed.

Next, a second embodiment of the pixel synchronizing device of the present invention will be described with reference to FIG.

This embodiment is different from the first embodiment in that
By controlling the sampling clock of the sample hold circuit by the delay circuit, the sampling point of the analog video signal is not determined, but delay circuits 51, 52, 53 are provided in the respective analog video signal paths, and the analog circuits are individually provided. The point is to determine the sampling point of the video signal.

With such a configuration, even when an analog video signal having a phase difference is input, it can be controlled individually and more accurate sampling can be performed.

A third embodiment of the pixel synchronizing device of the present invention will be described with reference to FIG.

This embodiment is different from the first embodiment in that
The point where the input video signal uses a digital signal, the D / A conversion circuits 81, 82 and 83 for converting the input digital video signal into an analog signal and the respective signal processing circuits 91 and 9
2 and 93, and D / A conversion circuits 81 and 8
The point is that the delay circuit 5 controls the clocks 2, 83.

With such a structure, highly accurate sampling can be performed even when a digital video signal is input.

A fourth embodiment of the pixel synchronizing device of the present invention will be described with reference to FIG.

This embodiment is different from the first embodiment in that
The point is that three liquid crystal panels are prepared, and the rectangular wave from the sample hold circuit is supplied to the horizontal driver which is the drive circuit of each liquid crystal panel.

With such a structure, highly accurate sampling can be performed even when three liquid crystal panels are used.

[0055]

According to the present invention, with the above configuration, even if the sampling pulse having a delay due to the variation in the characteristics of the horizontal driver is supplied to the sample / hold unit, the optimum sampling of the video signal can be performed. It can be carried out.

[Brief description of drawings]

FIG. 1 is an embodiment of a pixel synchronization device of the present invention.

FIG. 2 is a timing chart of the pixel synchronization device of the present invention.

FIG. 3 is a circuit diagram of a sample hold circuit used in the present invention.

FIG. 4 is a timing chart of a sample hold circuit.

FIG. 5 is a second embodiment of the pixel synchronization device of the present invention.

FIG. 6 is a third embodiment of the pixel synchronization device of the present invention.

FIG. 7 is a fourth embodiment of the pixel synchronization device of the present invention.

FIG. 8 is a circuit diagram of a conventional pixel synchronization device.

FIG. 9 is a timing chart of a conventional pixel synchronization device.

[Explanation of symbols]

 1 signal processing circuit 3 liquid crystal panel 5 first delay circuit 6 second delay circuit 7 vertical driver 21 horizontal driver 21A timing generator section 21B sample / hold section 22 horizontal driver 22A timing generator section 22B sample / hold section 41 R sample Hold circuit 42 G sample hold circuit 43 B sample hold circuit

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[Procedure amendment]

[Submission date] November 4, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Then, the timing generator sections 21A and 22A of the horizontal drivers 21 and 22 create sampling pulses corresponding to the input video signal based on the start pulse and output the sampling pulses to the sample / hold sections 21B and 22B. . The sample / hold units 22A and 22B are composed of a switch, a capacitor, and a buffer amplifier, and the switches are closed by the rising and falling of the sampling pulse, and the input R, G, B signals are The hold value is held in the capacitor and the hold value is output to the liquid crystal panel 3 line-sequentially via the buffer amplifier.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (2)

[Claims] 1. A sample and hold circuit for sampling and holding an input video signal to create a rectangular wave, a phase control means for controlling the phase of a sampling clock input to the sample and hold circuit, and a rectangle from the sample and hold circuit. A pixel synchronizing apparatus comprising: a driver having a sample / hold unit for inputting waves and a timing generator unit; and a display panel for displaying an image by a signal from the sample / hold unit. 2. A phase control means for controlling the phase of an input video signal, a sample hold circuit for sampling and holding a video signal whose phase is controlled by the phase control means to create a rectangular wave, and a sample hold circuit from the sample hold circuit. A pixel synchronization device comprising: a driver having a sample / hold unit that inputs a rectangular wave and a timing generator unit; and a display panel that displays an image by a signal from the sample / hold unit.