JP2838496B2 - Image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image display device using a liquid crystal or the like, and more particularly, to a column direction driving circuit thereof. 2. Description of the Related Art In a color display device using a liquid crystal or the like as a display material, the arrangement of color pixels is generally an arrangement as shown in FIGS. 3 (a) and 3 (b). Where R is red, G
Indicates an edge, and B indicates each blue pixel. In FIG. 3A, pixels of the same color are arranged in the vertical direction, and R, G, and B color pixels are alternately arranged in the horizontal direction. However, with this arrangement of color pixels, the resolution in the vertical direction is inferior. In FIG. 3B, R and R are set in both the vertical and horizontal directions.
G and B color pixels are alternately arranged in parallel to solve the problem in FIG. However, in this arrangement of the color pixels, the resolution in the oblique direction (in FIG. 3B, the obliquely downward left) is inferior. In order to compensate for the drawbacks in image display due to the conventional arrangement of color pixels as described above, a color image display device having an arrangement of color pixels as shown in FIG. 4 has been proposed.
That is, pixels are shifted in each row, and R, R
The G and B color pixels are alternately arranged so that no single color pixel is continuous in any of the vertical, horizontal, and diagonal directions. In FIG. 4, the shift between the j-th row and the (j + 1) -th row is 1/2 pixel. The conventional column-direction driving of a color image display device of color pixels as shown in FIG. 4 will be elucidated. In the column direction, the drive circuit outputs video data as a drive signal. Reference numeral 501 in FIG. 5 is a video signal using a television as an example. Since the video signal of the jHth (H: horizontal synchronizing signal period) and the video signal of the (j + 1) Hth are close to each other, generally they are almost the same video data. 5
02 is an enlarged view of a part of 501. Reference numeral 503 denotes a sampling clock signal for sampling video data, one cycle of which is the same as the time corresponding to one pixel. Sampling is performed at the falling edge of the sampling clock. In the j-th row, the video data of A of the jH-th video signal is written to the pixel of a, and the video data of C is written to the pixel of G. In the (j + 1) -th row, the (j + 1) -H-th video data B,
Where D is to be written to each of the pixels b and d, since the video data is always sampled at the falling edge of the sampling clock 503, the video data A and C are written to each of the pixels b and d. Become. This will reduce the horizontal resolution of the image. SUMMARY OF THE INVENTION In view of the problems of the prior art such as the prior art, an object of the present invention is to increase the resolution in the horizontal direction in a color image display device in which color pixels whose pixel positions are shifted for each pixel row are arranged. And [0006] images display device of the present invention In order to achieve the above object, according a first pixel row in which each color pixel are sequentially arranged in the horizontal direction, the array position with respect to the first pixel row images and the second pixel row each color pixel offset one pitch of 2 minutes with respect to the pixel arrangement of the first pixel row is sequentially arranged in the horizontal direction, ing alternately arranged in the longitudinal direction a display member, the images display <br/> motion signal drive to Kakue element is ing is supplied in synchronization with each color digital to 1 duty of the clock signal half the analog image data of each color A conversion unit that converts the image data into image data; a multiplexer that multiplexes the digital image data of each color converted by the conversion unit in an order corresponding to a color arrangement of each pixel row of the color image display; The digital image to be output Data storage means for synchronizing and storing the clock signal, and output means for outputting the driving signal corresponding to the digital image data stored in the storage means,
The storage means for displaying the data on the first pixel row;
When storing digital image data, and when storing the second pixel row.
When storing the digital image data to be displayed on
And the conversion means and the storage means are supplied to the storage means
It characterized by comprising and an inverting means for inverting each other phase of the clock signal. Further, the clock signal you characterized by comprising been inverted every one horizontal scanning period.
Further, the inverting means outputs, as the clock signal, a signal whose level is inverted every horizontal scanning period and a signal obtained by performing an exclusive OR operation on the clock signal. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 6 is a time chart thereof. Reference numeral 101 denotes a red (R) image data sampling circuit. The circuit includes an A / D converter 104 and an encoder 107. The A / D converter 104 further includes a comparator 105
It comprises a switch 106. The comparator 105 has two inputs, one end is connected to an R signal, and the other end is connected to one tap terminal of a resistor r group connected in series so as to generate a voltage of a desired number of gradations. I have. The comparator 105 compares both inputs, determines the level of the R signal, and outputs a digital signal. sampling·
The switch 106 samples the A / D-converted digital signal using the output signal of the EX-NOR gate 111. Its timing is as shown in FIG. 61
It changes at the rise of 11 signals. A / D converter 104
Is present only desired gray scale number is input to 16 gradations 16 output is 107 of the encoder in the case of For example, encoded in 4-bit code. 102 green (G) image data San flop ring circuit, 103 blue (B) image data sampling circuit also takes the same structure as 101. R, G, B digitized into 4 bits
Is input to the multiplexer 109. The multiplexer 109 multiplexes the image data 108 in accordance with the arrangement of the color pixels in the horizontal and vertical directions of the color image display, and forms 4-bit image data 1
17 is output to the first memory group 114. Reference numeral 113 denotes a shift register which transfers shift data D in response to a shift clock φ. 1
Reference numeral 14 denotes a first memory group, each of which is composed of, for example, a 4-bit latch, and is configured to take in 4-bit image data 117. The capture of the image data corresponds to the output 1 of each stage of the shift register 113.
This is done at 18. Each memory of the second memory group 115 is also configured by, for example, a 4-bit latch, and is configured to receive the 4-bit output 119 of the corresponding memory of the first memory group. 119 is the memory group 1
This is performed by a LOAD signal generated after the capture of the image data 117 is completed in 14. The 4-bit image data 120 captured by the LOAD signal is output to the driver 116. The driver 116 determines the ratio of the ON potential V _ON and the OFF potential V _OFF supplied from outside in the selection period based on the 4-bit image data 120 and outputs the ratio as the column direction drive signal 121 to the color image display. . Reference numeral 110 denotes a toggle F / F (flip flop) to which a signal D is input as a toggle signal. D is also a shift data signal of the shift register 113. D is a short pulse of 1H cycle as shown in FIG. 6, for example, and is close to the start position of image coasting during 1H. L
The OAD signal is slightly ahead of D.
The Q output of the toggle F / F 110 is a signal obtained by dividing D, and repeats “1” and “0” every 1H. CL is a clock signal, one cycle of which corresponds to the time of one pixel. An EX-NOR gate 111 has a CL signal and 1
The input is a 10Q output signal. Therefore, the output of 111 repeats the same phase and the opposite phase with the CL signal every 1H as shown in FIG. Since the R, G, and B sampling circuits sample the signal 111, the 4-bit image data 117 from the multiplexer 109 is
In the jHth, the video signals are in the order of A and C. And 117
Is output 11 of each stage of the shift register 113.
At 8, the data is taken into the first memory group 114. J + 1H
, The 4-bit image data 117 is in the order of B and D of the video signal, and the output 118 of each stage of the shift register 113 is
The data is taken into the first memory group 114. As a result, A and C of the video data are written in the pixels a and c of the j-th row, and B and D are written in the pixels b and d of the j + 1-th row, thereby increasing the resolution in the horizontal direction. be able to. [Reference Example] FIG. 2 is a block diagram showing the configuration of a reference example of the present invention. FIG. 7 is a time chart thereof. Reference numeral 203 denotes a multiplexer, which outputs R, G, and B color signals. 20
In 3, the image data is multiplexed according to the arrangement of the color pixels in the horizontal and vertical directions of the color image display. 2
A shift register 04 transfers shift data D in response to a shift clock φ. 205 is a sampling and holding circuit. One stage includes an analog switch 206, a capacitor 207, and a buffer amplifier 208. Analog switch 206 control signal 210 are output as 210 from each stage of the shift register 204, one end connected to the image data lines from the multiplexer 203, the other end capacitor 207 (one end is grounded) And the buffer um 208. 2
The output of 08 is the column direction drive signal 211. In operation, the output 210 of each stage of the shift register 204
Then, the analog switch 206 is set to 0N, and the image data at that time is written to the capacitor 207. The rebuffer amplifier 208 forms a column direction drive signal 211 based on the image data written to the capacitor 207. A toggle F / F 201 receives a signal D as a toggle signal. D is also a shift data signal of the shift register 204. D is a short pulse with a 1H period as shown in FIG. 7 and is close to the start position of the image coasting during 1H. The Q output 209 of the toggle F / F 201 is a signal obtained by dividing D, and is “1” every 1H,
Repeat "0". CL is a clock signal whose cycle corresponds to the time of one pixel. 202 is EX-NOR
The gate receives the CL signal and the Q output signal 209 of 201. The output of 202 is the shift clock φ of the shift register 204. Therefore, 204φ is
As described above, the same phase and opposite phase are repeated for the CL signal every 1H. In the shift register 204, the shift data D is transferred on the falling edge of the shift lock φ. Therefore, in the jH-th, the image data is sampled in the order of A and C of the video signal, and in the j + 1H-th, the image data is sampled in the order of B and D. As a result, A or C of the video data is written in the pixels a and c in the row j of FIG. 4 or B and D are written in the pixels b and d in the row j + 1 to increase the resolution in the horizontal direction. be able to. As described above, according to the present invention , each
A first pixel row in which color pixels are sequentially arranged in the horizontal direction;
A pixel array in which the array position is the first pixel row for one pixel row
Each color pixel shifted by a half pitch in the horizontal direction
The second pixel rows sequentially arranged are alternately arranged in the vertical direction.
And a driving signal is supplied to each pixel row.
In the supplied image display device, the clock signal is
Inverting means for inverting the first pixel and the second pixel row, and each color
The analog image data of each color is synchronized with the clock signal.
The conversion means for converting to digital image data
Sampling timing of image data according to element
By improving the horizontal resolution of the screen,
Uniform image data supplied to each pixel row
Extremely display product with no display unevenness
A high quality image display device can be obtained. further,
Invert the clock signal and use it as a sampling signal
Due to the extremely simple configuration, the pixel rows are shifted
Low cost image display to drive the image display device
A device is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration block diagram of an embodiment of the present invention. FIG. 2 is a configuration block diagram of a reference example of the present invention. FIG. 3A and FIG. 3B are color pixel arrangement diagrams on a color image display. FIG. 4 is a diagram illustrating a color pixel arrangement in a color image display which is a premise of the present invention. FIG. 5 is a time chart of a conventional video signal sampling. FIG. 6 is a time chart of each part in FIG. 1; FIG. 7 is a time chart of each part in FIG. 2; [Description of Signs] 110, 201 ... Toggle F / F 111, 202 ... EX-OR gate 113, 204 ... Shift register

Claims (1)

(57) [Claims] A first pixel row in which pixels of each color are sequentially arranged in the horizontal direction, and each color whose arrangement position is shifted by a half pitch with respect to the pixel arrangement of the first pixel row with respect to the first pixel row pixel and the second pixel rows which are sequentially arranged in the horizontal direction, vertical direction have the images displayed body ing are alternately arranged, it is supplied <br/> motion signal drive to Kakue element in Do that images display device, conversion means and each color of the digital image data converted by said converting means for analog image data of each color in synchronization with the one-half duty of the clock signal is converted to each color of the digital image data A multiplexer that multiplexes the digital image data sequentially output by the multiplexer in synchronization with the clock signal, and a storage unit that stores the digital image data sequentially output by the multiplexer. Said And output means for outputting the driving signal corresponding to the digital image data stored in the unit, the de of said storage means to be displayed on the first pixel rows
When storing digital image data, and when storing the second pixel row.
When storing the digital image data to be displayed on
And the conversion means and the storage means are supplied to the storage means
Images display you characterized by comprising and an inverting means for inverting each other phase of the clock signal. 2. It said clock signal images display apparatus according to claim 1, characterized in that is inverted every one horizontal scanning period. 3. It said inverting means images display device according to claim 1, wherein the outputting the exclusive OR signal of the signal and clock signal level inverted every one horizontal scanning period as the clock signal.