JP3519514B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying a normal video signal on an active matrix type liquid crystal panel provided with a thin film transistor (hereinafter abbreviated as TFT).

[0002]

2. Description of the Related Art As such a liquid crystal display device, there is one disclosed in, for example, JP-A-3-35218.
The configuration and operation will be described below with reference to the drawings.

FIG. 26 shows a circuit of a conventional liquid crystal display device. In the figure, 1 is a TFT, 2 is a liquid crystal cell, 3 is an auxiliary capacitor,
Reference numeral 4 is a counter electrode, 5 is a pixel electrode, 6 is a scanning electrode for supplying a signal for turning on the TFT 1, and 7 is a signal electrode for supplying a signal to the pixel electrode 5. Reference numeral 8 denotes a block for one pixel including the above elements 1 to 5, and these blocks collectively form a liquid crystal panel 9.

Reference numeral 10 is a vertical scanning circuit for supplying a signal to the scanning electrode 6, and 11 is a horizontal scanning circuit for supplying a signal to the signal electrode 7. Reference numeral 12 denotes a horizontal scanning clock signal (H) for operating the horizontal scanning circuit 11 based on the clock signal (CLK), the horizontal synchronizing signal (/ HD), and the vertical synchronizing signal (/ VD).
clk), a horizontal start signal (ST), and an alternating signal (POL) for inverting the polarity of the image signal (Vs) so as to drive the liquid crystal with an alternating current.

Reference numeral 13 is a vertical start signal (S) for operating the vertical scanning circuit 10 from a clock signal (CLK), a horizontal synchronizing signal (/ HD) and a vertical synchronizing signal (/ VD).
V) is a vertical control circuit. Reference numeral 14 is an AC conversion circuit that generates an AC image signal (Vac) to be applied to the horizontal scanning circuit 11 from the video signal (Vs) and the AC conversion signal (POL). A case will be described in which the number of scan electrodes 6 of the liquid crystal panel 9 is about 240, which corresponds to a scan line of one field of an NTSC interlaced signal.

Details of the horizontal scanning circuit 11 are shown in FIG. In the figure, 17 is a shift register circuit, and 18
Is a 1-channel sample hold circuit, 19 is a sampling switch for sampling an AC image signal (Vac), 20 is a sampling capacitor (Cs) for holding the sampled sampling voltage (Vcs), and 21 is a sampling voltage (Cs). The respective non-inverting circuits for outputting

FIG. 2 shows the signal waveform of each part of this liquid crystal display device.
7 shows. In the figure, (/ VD) shown in (a) is a vertical synchronizing signal input to the horizontal control circuit 12 and the vertical control circuit 13, and (/ HD) shown in (b) is shown to the horizontal control circuit 12 and the vertical control circuit 13. The horizontal synchronizing signal that is input, and (CLK) shown in (c) is a clock signal that is input to the horizontal control circuit 12 and the vertical control circuit 13.

Further, (Vs) shown in (d) is an image signal inputted to the AC converting circuit 14, and (SV) shown in (e) is outputted from the vertical control circuit 13 and the vertical scanning circuit 10 is shown.
Vertical start signal input to, and (SH) (SH)
Is a horizontal start signal that is output from the horizontal control circuit 12 and is input to the horizontal scanning circuit 11 and is also input to the vertical scanning circuit 10 as a clock signal, and (Hclk) shown in (h) is output from the horizontal control circuit 12 and is horizontally scanned. It is a horizontal clock signal input to the circuit 11.

Further, (POL) shown in (i) is an AC signal output from the horizontal control circuit 12 and input to the AC circuit 14, and (Vac) shown in (j) is the AC circuit 1.
An AC image signal output from the horizontal scanning circuit 4 and input to the horizontal scanning circuit 11 and (Vlcd) shown in (k) are a liquid crystal driving signal output from the horizontal scanning circuit 11 and supplied to the signal electrode 7.
Further, (X1) to (X4) shown in (l) to (o) represent scan electrode signals output from the vertical scanning circuit 10 and supplied to the first to fourth lines of the scan electrode 6, respectively. Details of the signals shown in (i) to (k) above are shown in FIG. 4 as an enlarged view A. In (j) and (k) of this figure, (Vcc) is the power supply voltage, and (GND). Is the reference voltage, (V
(cent) indicates a voltage that is ½ of the power supply voltage, and (Vcs) indicates a sampling voltage.

FIG. 28 is an explanatory diagram of an image display method of this liquid crystal display device. FIG. 28A shows that in an NTSC interlaced signal as an image signal (Vs), an odd field signal is applied to an odd field and an even line signal is applied to an even field. FIG. 28B shows the signals to be written in the pixels in the odd field and the even field in order from the first line of the scan electrode 6 and their polarities. FIG. 28C shows a state of the effective value written in each pixel when an image in which an odd field and an even field are continuous is displayed on the liquid crystal panel 9. Here, a case where an image is displayed on a liquid crystal panel having about 240 scanning electrodes corresponding to one field of an interlaced signal will be described.

The operation of the conventional liquid crystal display device configured as described above is as follows. Vertical sync signal (/ V
D), horizontal sync signal (/ HD), and clock signal (C
LK) is input to the horizontal control circuit 12 and the vertical control circuit 13, and the image signal (Vs) is input to the AC circuit 14, respectively, the horizontal control circuit 1
2 outputs a horizontal start signal (SH), a horizontal clock signal (Hclk), and an alternating signal (POL).
Further, a vertical start signal (SV) is sent from the vertical control circuit 13 and an alternating signal (PO) is sent from the alternating circuit 14.
AC image signal (Vs) obtained by reversing the polarity of the image signal (Vs) for each horizontal period (1H) and for each field by L).
c) is output respectively.

In the horizontal scanning circuit 11 shown in FIG. 2, a horizontal clock signal (HClk) and a horizontal start signal (S).
H) causes the shift register circuit 17 to operate, and a signal for sampling the AC image signal (Vac) corresponding to the first line Y1 of the signal electrode 7 is a sample and hold circuit 1.
The sampling switch 19 of No. 8 is controlled, and the sampling voltage (Vcs) is supplied to and held in the sampling capacitor (Cs). The voltage becomes a liquid crystal drive signal (Vlcd) through the non-inverting amplifier circuit 21 and is supplied to the signal electrode Y1.

On the other hand, in the vertical scanning circuit 10, 1H is generated by the horizontal start signal (SH) and the vertical start signal (SV).
During that period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1H are supplied to the respective scan electrodes. Then, as shown in FIG. 28, in an odd field, signals of + polarity 1 line for X1, −polarity 3 lines for X2, + polarity 5 lines for X3, and −polarity 7 lines for X4 are provided. Each is written. In the even field, X1 has two negative polar lines, X2 has four positive polar lines, X3 has six negative polar lines, and X4.
Signals of 8 lines of + polarity are respectively written in.
By repeating these writing operations, X1
, The effective value of 1 + 2 line, X2 is the effective value of 3 + 4 line, X3 is the effective value of 5 + 6 line, and X4 is 7 + 8.
Like the effective value of the line, the interlaced signal is written in the pixel while superposing the odd field and the even field while inverting the polarities, thereby displaying an image of about 240 lines.

[0014]

However, the above-mentioned configuration has a problem when an image is displayed on a liquid crystal panel having about 480 scanning electrodes corresponding to the scanning lines for two fields of the interlaced signal. Occurs. In other words, the odd field is written only on the odd lines and the even field is written on only the even lines, so that the signal is written once in every two fields of each line. Since the driving frequency is halved,
Flicker and uneven brightness on a line-by-line basis increase and display quality deteriorates, and it is not preferable in terms of liquid crystal panel reliability.

In order to solve such a problem, the scanning electrode 6
Although it is conceivable to perform pseudo non-interlaced driving by using an interlaced signal by simultaneously selecting two lines at a time, the auxiliary capacitance 3 is connected to the preceding scan electrode 6 as shown in FIG. This method cannot be adopted in the case of the existing configuration. Further, as another method, there is a method of converting an interlaced signal into double speed and converting into a non-interlaced signal for display, but it has a drawback that the circuit configuration becomes very complicated and the cost increases greatly. Further, this method has a drawback that the operating frequency of the horizontal scanning circuit 11 is required to be increased and power consumption is increased.

The present invention has been made in view of the above situation, and an object thereof is to obtain a high-quality full line display image from a normal interlaced video signal with a simple and low-cost circuit configuration. An object of the present invention is to provide a liquid crystal display device capable of achieving the above.

[0017]

A liquid crystal display device according to the present invention.
In addition, a plurality of scan electrodes and signal electrodes are arranged on the substrate.
Arranged in a stripe shape and partitioned by the scanning electrodes and the signal electrodes
Pixels are provided in the defined area, and the pixels are thin film transistors.
To support the signal retention characteristics of the liquid crystal cell and the liquid crystal cell.
And an auxiliary capacitor for
Liquid crystal having a liquid crystal panel connected to the scanning electrodes of a step
A display device, which supplies a scan signal to the scan electrodes.
Vertical scanning circuit, clock signal, horizontal synchronization signal, and vertical
1 for operating the vertical scanning circuit from the direct synchronization signal
1/2 cycle and 1/3 cycle of the horizontal scanning period are constant cycles
Vertical with mixed and different timing in 4 fields
Scan clock signal and vertical start signal
To include a vertical control circuit for outputting to the inspection circuit.
Characterize.

A method of driving a liquid crystal display device according to the present invention comprises:
Multiple scan electrodes and signal electrodes arranged in a matrix on the substrate
Placed and partitioned by the scanning electrodes and the signal electrodes
A pixel is provided in the region, and the pixel is a thin film transistor.
To assist the liquid crystal cell and the signal retention characteristics of the liquid crystal cell
Of the auxiliary capacitance, and the electrode of the auxiliary capacitance is
The liquid crystal panel connected to the scanning electrodes and the signal electrodes
A horizontal scanning circuit for supplying a liquid crystal driving signal, and the scanning electrode
A vertical scanning circuit that supplies a scanning signal to the
The vertical scanning circuit based on a horizontal synchronizing signal and a vertical synchronizing signal
1/2 period of 1 horizontal scanning period for operating
/ 3 cycle is mixed at a fixed cycle and the field within 4 fields
Vertical scanning clock signals with different timing and vertical scanning
Vertical control circuit for outputting a control signal to the vertical scanning circuit
A method for driving a liquid crystal display device including a circuit,
The horizontal scanning circuit causes an image of one line within one horizontal scanning period.
Data polarity non-inversion signal and polarity inversion signal are repeated multiple times.
Returned and output, and the vertical scanning circuit is within the one horizontal scanning period.
To output a signal to two or more scanning electrodes.
, The polarities are different from each other within one field period.
The image data of the same line can be used for two or more adjacent
Display on scan line, and even before field
It is characterized in that the polarity of the liquid crystal drive signal is inverted.

[0019]

According to the above structure, the horizontal scanning circuit outputs image data for one line with a constant polarity in one horizontal scanning period (1H), and the vertical scanning circuit outputs one horizontal scanning period. Since the operation is performed based on the vertical scanning clock signal (Vclk) having a period equal to or less than 1/2 of (1H), a plurality of scanning electrodes are selected and a plurality of selected lines are displayed during one horizontal scanning period. . By repeating this for each field, the signal is also written in the line where the interlaced signal is separated, so that the operating frequency of the liquid crystal panel becomes one field (that is, one frame of video is displayed in one field), and flicker or The uneven brightness of the line is eliminated. As a result, the display quality is improved and the reliability of the liquid crystal panel is also improved.

A preferred embodiment of the present invention will be described below with reference to the drawings. A circuit of the liquid crystal display device according to the first embodiment of the present invention is shown in FIG. In the figure, 1 is a TFT, 2
Is a liquid crystal cell, 3 is a storage capacitor, 4 is a counter electrode, 5 is a pixel electrode, 6 is a scanning electrode for supplying a signal for turning on the TFT 1, and 7 is a signal electrode for supplying a signal to the pixel electrode 5. Reference numeral 8 denotes a block for one pixel including the above elements 1 to 5, and these blocks collectively form a liquid crystal panel 9.

Reference numeral 10 is a vertical scanning circuit for supplying a signal to the scanning electrode 6, and 11 is a horizontal scanning circuit for supplying a signal to the signal electrode 7. Reference numeral 12 denotes a horizontal scanning clock signal (H) for operating the horizontal scanning circuit 11 based on the clock signal (CLK), the horizontal synchronizing signal (/ HD), and the vertical synchronizing signal (/ VD).
clk), a horizontal start signal (SH), and an AC signal (POL) for inverting the polarity of the image signal (Vs) to AC drive the liquid crystal.

Reference numeral 13 denotes a vertical start signal (S) for operating the vertical scanning circuit 10 from the clock signal (CLK), the horizontal synchronizing signal (/ HD) and the vertical synchronizing signal (/ VD).
V) is a vertical control circuit. Reference numeral 14 is an AC conversion circuit that generates an AC image signal (Vac) to be applied to the horizontal scanning circuit 11 from the video signal (Vs) and the AC conversion signal (POL).

The above components are the same as those of the conventional example shown in FIG. 26, and are designated by the same reference numerals as those in FIG. The difference from the conventional example is that the vertical control circuit 13 gives a vertical scanning clock signal (Vclk) to the vertical scanning circuit 10.
The vertical scanning circuit 10 uses the vertical scanning clock signal (Vcl
It operates according to k).

The details of the horizontal scanning circuit 11 are shown in FIG. This is the same as that described in the conventional example. In the figure, 17 is a shift register circuit, 18 is a 1-channel sample hold circuit, 19 is a sampling switch for sampling an AC image signal (Vac), and 20 is a sampling capacitor (Vcs) for holding a sampled sampling voltage (Vcs). Cs) and 21 are non-inverting circuits that output the sampling voltage (Cs), respectively.

FIG. 3 shows signal waveforms at various parts of this liquid crystal display device. In the figure, (/ VD) shown in (a) is a vertical synchronizing signal input to the horizontal control circuit 12 and the vertical control circuit 13, and (/ HD) shown in (b) is shown to the horizontal control circuit 12 and the vertical control circuit 13. An input horizontal synchronizing signal, (CLK) shown in (c), is a horizontal control circuit 12 and a vertical control circuit 13.
Is a clock signal input to. Further, (Vs) shown in (d) is an image signal input to the AC conversion circuit 14,
(SV) shown in (e) is a vertical start signal output from the vertical control circuit 13 and input to the vertical scanning circuit 10, and (SH) shown in (g) is the horizontal control circuit 12.
The horizontal start signal output from the horizontal control circuit 12 and the horizontal start signal input to the vertical scanning circuit 10 as a clock signal (Hclk) shown in (h) are output from the horizontal control circuit 12 and input to the horizontal scanning circuit 11. Horizontal clock signal. Also, (POL) shown in (i)
Is output from the horizontal control circuit 12 and the alternating circuit 1
4, the alternating signal input to (4), (Vac) shown in (j) is an alternating image signal output from the alternating circuit 14 and input to the horizontal scanning circuit 11, and (Vlcd) shown in (k) is the horizontal scanning circuit 11. It is a liquid crystal drive signal that is output by the output terminal and is supplied to the signal electrode 7. The above signals are the same as the signals of the conventional example shown in FIG.

The waveform of the vertical clock signal Vclk newly added in the configuration of this embodiment shown in FIG. 1 is (f) in FIG.
Is shown in. Further, it can be seen that the scan electrode signals (X1) to (X4) shown in FIGS. 3 (l) to (o) have half the pulse width as compared with the signal of the conventional example shown in FIG. Details of the signals shown in (i) to (k) of FIG. 3 are shown in FIG. 4 as an enlarged view A. This is the same as that described in the conventional example. In (j) and (k) of this figure, (Vcc) is the power supply voltage, (GND) is the reference voltage, and (V)
(cent) indicates 1/2 of the power supply voltage, and (Vcs) indicates the sampling voltage.

FIG. 5 is an explanatory diagram of an image display method of this liquid crystal display device. FIG. 5A shows that in an NTSC interlaced signal as an image signal (Vs), an odd field signal is applied to an odd field and an even line signal is applied to an even field. Figure 3
(B) shows the signals written in the pixels in order from X1 of the scan electrode 6 in the odd 1 field, even 1 field, odd 2 field, and even 2 field, and their polarities. FIG. 3C shows a state of the effective value written in each pixel when an image in which those fields are continuous is displayed on the liquid crystal panel 9. Here, an image is displayed on a liquid crystal panel having scan electrodes corresponding to one field by using an interlace signal.

The operation of the liquid crystal display device of the present embodiment configured as described above is as follows. Vertical sync signal (/
VD), the horizontal synchronizing signal (/ HD), and the clock signal (CLK) are input to the horizontal control circuit 12 and the vertical control circuit 13, and the image signal (Vs) is input to the alternating circuit 14, respectively. The circuit 12 outputs a horizontal start signal (SH), a horizontal clock signal (Hclk), and an alternating signal (POL). In addition, the vertical start signal (SV) and the vertical clock signal (Vclk) are supplied from the vertical control circuit 13 and the image signal (Vs) is supplied from the alternating circuit 14 by the alternating signal (POL) every horizontal period (1H). In addition, the alternating-current image signal (Vac) whose polarity is inverted is output for each field.

In the horizontal scanning circuit 11 shown in FIG. 2, a horizontal clock signal (Hclk) and a horizontal start signal (S
H) causes the shift register circuit 17 to operate, and a signal for sampling the AC image signal (Vac) corresponding to the first line Y1 of the signal electrode 7 is a sample and hold circuit 1.
The sampling switch 19 of No. 8 is controlled, and the sampling voltage (Vcs) is supplied to and held in the sampling capacitor (Cs). The voltage becomes a liquid crystal drive signal (Vlcd) through the non-inverting amplifier circuit 21 and is supplied to the signal electrode Y1.

On the other hand, the vertical scanning circuit 10 sets 1 by the vertical clock signal (Vclk) and the vertical start signal (SV).
During the period of / 2H, the scan electrode 6 is turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 5, in the odd 1 field, X1 and X2 have one positive polarity line, X3 and X4 have three negative polarity lines, and X5.
Signals of + polarity 5 lines are written in X6 and X6, and signals of −polarity 7 lines are written in X7 and X8. In even field 1, X2 and X3 have two negative polarity lines,
Signals of + polarity 4 lines are written in X4 and X5, −polarity 6 lines in X6 and X7, and + polarity 8 lines in X8 and X9, respectively. In the odd 2 field, X1 and X2 have one polar line, X3 and X4
The signals of + polarity 3 lines are written in, the negative polarity 5 lines are written in X5 and X6, and the positive polarity 7 lines are written in X7 and X8. In the even 2 field, signals of + polarity 2 lines for X2 and X3, −polarity 4 lines for X4 and X5, + polarity 6 lines for X6 and X7, and −polarity 8 line for X8 and X9. Are written respectively. By repeating these writing operations, the effective value of 1 + 2 lines is applied to X2, the effective value of 2 + 3 lines is applied to X3, the effective value of 3 + 4 lines is applied to X4, the effective value of 4 + 5 lines is applied to X5, and the effective value of 5 + 6 is applied to X6. The effective value of the line, and the effective value of the line 6 + 7 for X7, the interlaced signal is written in the pixel while inverting the polarities of the odd field and the even field, and writing it to the pixel. A full-line image with good quality is displayed.

As described above, according to this embodiment, by setting the cycle of the vertical clock signal (Vclk) to (1 / 2H) period, the auxiliary capacitance is connected to the scan electrode of the preceding stage. In the panel, image data for one line can be written in two lines, and an interlace signal can be written in each field to obtain a pseudo full-line high-quality image display. Moreover, no special processing is required for the image signal, and the circuit configuration can be realized at a very low cost.

Next, FIG. 6 shows a circuit of a liquid crystal display device according to a second embodiment of the present invention. In the figure, 1 is a TFT, 2 is a liquid crystal cell, 3 is an auxiliary capacitance, 4 is a counter electrode, 5 is a pixel electrode, 6 is a scanning electrode, and 7 is a signal electrode. Reference numeral 8 denotes a block for one pixel including the above elements 1 to 5, and these blocks collectively form a liquid crystal panel 9. Reference numeral 10 is a vertical scanning circuit, 13 is a vertical control circuit, and 14 is an alternating current circuit. The above components are the same as those in the first embodiment shown in FIG. 1, and are designated by the same reference numerals as those in FIG.

The present embodiment shown in FIG. 6 differs from the first embodiment with respect to the horizontal control circuit 15 and the horizontal scanning circuit 16. That is, the horizontal control circuit 15 of the present embodiment.
Is the horizontal control circuit 1 of the first embodiment (FIG. 1).
In addition to the horizontal scanning clock signal (Hclk), the horizontal start signal (SH), and the alternating signal (POL) output by 2, the polarity inversion for inverting the polarity of the image signal (Vs) to AC drive the liquid crystal. A signal (HT) is output and this signal is input to the horizontal scanning circuit 16. Details of the horizontal scanning circuit 16 are shown in FIG. In this figure, 17 is a shift register circuit, 18 is a sample / hold circuit for one channel, 19 is a sampling switch for sampling an AC image signal (Vac), and 20 is a sampling capacitor for holding a sampled sampling voltage (Vcs). (Cs) and 21 are non-inverting circuits for outputting the sampling voltage (Vcs), respectively. The above components are the same as those of the first embodiment shown in FIG. 2 and are given the same numbers as in FIG. The difference from the first embodiment is that
Inversion circuit 2 for inverting the polarity of the sampling voltage (Cs)
2 and that the changeover switch 23 for switching between the output of the non-inverting circuit 21 and the output of the inverting circuit 22 is provided.

FIG. 8 shows the signal waveform of each part of this liquid crystal display device. In this figure, a vertical synchronizing signal (/ VD) shown in (a), a horizontal synchronizing signal (/ HD) shown in (b),
A clock signal (CLK) shown in (c), an image signal (Vs) shown in (d), and a vertical start signal (S) shown in (e).
V), a vertical clock signal (Vclk) shown in (f),
The horizontal start signal (SH) shown in (g), the horizontal clock signal (Hclk) shown in (h), the alternating signal (POL) shown in (i), the alternating image signal (Vac) shown in (j),
Liquid crystal drive signal (Vlcd) shown in (k), (l) to (o)
The scan electrode signals (X1) to (X4) shown in (3) are the same as the signals of the first embodiment shown in FIG. The waveform of the polarity inversion signal (HT) newly added in the present embodiment described in FIG. 6 is shown in (p) of FIG.

Details of the signals shown in (i) to (k) of FIG. 8 are shown in FIG. 9 as an enlarged view B. In (j) and (k) of this figure, (Vcc) is a power supply voltage, (GND) is a reference voltage, (Vcent) is a voltage half the power supply voltage, and (Vc)
s) shows the sampling voltage.

FIG. 10 is an explanatory diagram of an image display method of this liquid crystal display device. FIG. 10A shows that in an NTSC interlaced signal as an image signal (Vs), an odd field signal is applied to an odd field and an even line signal is applied to an even field. FIG. 10B shows the signals written to the pixels in order from the X1 of the scan electrode 6 in the odd 1 field, the even 1 field, the odd 2 field, and the even 2 field, and their polarities. FIG. 10C shows a state of the effective value written in each pixel when an image in which those fields are continuous is displayed on the liquid crystal panel 9. Here, an image is displayed by using an interlace signal on a liquid crystal panel having full-line scanning electrodes corresponding to the scanning lines of two fields.

The operation of the liquid crystal display device of the present embodiment configured as described above is as follows. Vertical sync signal (/
VD), horizontal sync signal (/ HD), clock signal (CL
K) is input to the horizontal control circuit 15 and the vertical control circuit 13, and the image signal (Vs) is input to the AC circuit 14. Then, the horizontal control circuit 15 outputs the horizontal start signal (SH) and the horizontal clock signal (Hcl).
k), the alternating signal (POL) and the polarity inversion signal (HT) are output, and the vertical control circuit 13 outputs a vertical start signal (SV) and a vertical clock signal (Vclk). The alternating circuit 14 outputs an alternating image signal (Vac) in which the polarity of the image signal (Vs) is inverted by the alternating signal (POL) for each 1H and for each field.

In the horizontal scanning circuit 16 shown in FIG. 7, a horizontal clock signal (Hclk) and a horizontal start signal (SH).
Accordingly, the shift register circuit 17 operates, and a signal for sampling the AC image signal (Vac) corresponding to the position at Y1 of the signal electrode 7 controls the sampling switch 19 of the sample and hold circuit 18, and the sampling capacitance (C
The sampling voltage (Vcs) is supplied to s) and held.

While the polarity inversion signal (HT) is at the H level, the changeover switch 23 selects the output of the non-inversion circuit 21, and the sampling voltage (Vcs) passes through the non-inversion circuit 21 and the liquid crystal drive signal (Vlcd) of + polarity. ) Is supplied to the signal electrode 7. On the other hand, while the polarity inversion signal (HT) is at the L level, the changeover switch 23 selects the output of the inversion circuit 22, and the sampling voltage (Vcs) is inverted by the inversion circuit 22 with respect to the intermediate voltage (Vcent). (2V
cent-Vcs) is supplied to the signal electrode 7 as a-polarity liquid crystal drive signal (Vlcd).

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
During this period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 10, in the odd 1 field, X1 has one line of + polarity, X2 has one line of − polarity, X3 has three lines of + polarity, and X4 has −.
Signals of three polar lines, five positive polar lines to X5, five negative polar lines to X6, seven positive polar lines to X7, and seven negative polar lines to X8 are respectively written. In even field 1, X2 has two lines of positive polarity, X
3 for-polarity 2 lines, X4 for + polarity 4 lines,
Signals of −polarity 4 lines are written to X5, + polarity 6 lines to X6, −polarity 6 lines to X7, + polarity 8 lines to X8, and −polarity 8 line signals to X9. . The same writing is performed in the odd 2 field and the even 2 field. Then, by repeating this, the interlaced signal is written in the pixel while overlapping the polarities of the odd field and the even field while inverting the polarities, thereby displaying an image similar to the pseudo non-interlaced driving.

As described above, according to this embodiment, the cycle of the vertical clock signal (Vclk) is set to (1 / 2H) period, the sample-hold circuit 18 is provided with the inverting circuit 22 and the changeover switch 23, and the sample-hold voltage ( Vcs)
By reversing the polarity every (1 / 2H) period, the liquid crystal drive signal (Vlcd) whose polarity is reliably reversed for each field is given to each scan electrode. By writing the interlaced signal in each field, it is possible to obtain a high-quality image display without pseudo full-line flicker. Moreover, no special processing is required for the image signal, which can be realized with a low-cost circuit configuration. Furthermore, since the polarity inversion is surely performed for each field, high reliability can be obtained.

Next, FIG. 11 shows a horizontal scanning circuit according to the third embodiment. In this figure, 17 is a shift register circuit, 18 is a 1-channel sample hold circuit,
Reference numeral 19 is a sampling switch for sampling the AC image signal (Vac), and 20 is a sampling capacitor (C) for holding the sampled sampling voltage (Vcs).
s) and 21 are non-inverting circuits that output the sampling voltage (Cs), respectively. These constituent elements are the same as those in the second embodiment shown in FIG. 7, and are given the same numbers as in FIG. The difference from the second embodiment is that the supply changeover switch 24 for switching the electrode direction of the sampling signal to the sampling capacitor (Cs) and the terminal electrode direction to the intermediate voltage (Vcent) of the sampling capacitor (Cs) are supplied. The point is that a termination changeover switch 25 is provided that is switched in conjunction with the changeover switch 24.

The signal waveform of each part of this liquid crystal display device is shown in FIG.
The waveform is the same as that of the second embodiment shown in FIG. The details of the signals shown in (i) to (k) among them are slightly different, and this is shown in FIG. 12 as an enlarged view B. In (j) and (k) of this figure, (Vcc) is the power supply voltage, and (G)
ND) is a reference voltage, (Vcent) is a voltage that is half the power supply voltage, and (Vcs) is a sampling voltage.

The operation of the present embodiment configured as described above is as follows. The vertical synchronizing signal (/ VD), the horizontal synchronizing signal (/ HD), and the clock signal (CLK) are input to the horizontal control circuit 15 and the vertical control circuit 13, respectively, and the image signal (Vs) is input to the alternating circuit 14. Then, the horizontal start signal (SH), the horizontal clock signal (Hclk), the alternating signal (POL) and the polarity inversion signal (HT) from the horizontal control circuit 15, and the vertical start signal (SV) and the vertical clock from the vertical control circuit 13. The signal (Vclk) changes the image signal (Vs) by 1 from the alternating circuit 14 by the alternating signal (POL) every 1H.
An AC image signal (Vac) whose polarity is inverted is output for each field.

In the horizontal scanning circuit 16 shown in FIG.
Horizontal clock signal (Hclk) and horizontal start signal (S
H) causes the shift register circuit 17 to operate, and a signal for sampling the AC image signal (Vac) corresponding to the position at Y1 of the signal electrode 7 controls the sampling switch 19 of the sample and hold circuit 18, and the sampling capacitance (Cs). ) Is supplied with the sampling voltage (Vcs) and held.

During the period when the polarity inversion signal (HT) is at the H level, the supply changeover switch 24 is set to the sampling capacitor 20 a
A signal is supplied to the electrode side. At that time, the terminal changeover switch 25 selects the b electrode side, and the potential of the b electrode becomes the intermediate voltage (Vcent) and the potential of the a electrode becomes the sampling voltage (Vcs) as shown in (k) of FIG. On the other hand, while the polarity inversion signal (HT) is at L level, the supply changeover switch 2
4 supplies a signal to the b electrode side of the sampling capacitor 20. At that time, the terminal changeover switch 25 selects the a electrode side, and the potential of the a electrode becomes the intermediate voltage (Vcent) as shown in (k) of (FIG. 12). Therefore, the sampling voltage (Vcs) becomes the intermediate voltage (Vcs). This means that the polarity has been inverted with respect to Vcent). In this way, the liquid crystal drive signal (Vlcd) whose polarity is inverted every 1 / 2H via the non-inverting circuit 21.
Are supplied to the signal electrode 7.

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
During this period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 10, in the odd 1 field, one line of + polarity is provided for X1, and-is provided for X2.
1 line of polarity, 3 lines of + polarity for X3, 3 lines of − polarity for X4, 5 lines of + polarity for X5, 5 lines of − polarity for X6, 7 lines of + polarity for X7, X8
7-line signals of negative polarity are written in each.
In even 1 field, X2 has two lines of positive polarity,
X3 has −polarity 2 lines, X4 has + polarity 4 lines, X5 has −polarity 4 lines, X6 has + polarity 6 lines, X7 has −polarity 6 lines, and X8 has + polarity. Of 8
Signals of 8 lines of negative polarity are written in the line and X9, respectively. The same writing is performed in the odd 2 field and the even 2 field. By repeating this, the interlace signal is written in the pixels while the polarities of the odd field and the even field are inverted and overlapped, and the image similar to that in the non-interlaced drive is displayed.

As described above, according to this embodiment, the period of the vertical clock signal (Vclk) is set to (1 / 2H) period, and the sample hold circuit 18 is switched to the supply changeover switch 24 and the terminal for switching the polarity of the sample hold capacitor 20. By providing the changeover switch 25 and reversing the polarity of the sample hold voltage (Vcs) every (1 / 2H) period, the interlace is performed by the liquid crystal drive signal (Vlcd) which is surely reversed every one field in each scan electrode. A signal can be written in each field, and a high-quality image display without pseudo full-line flicker can be obtained. Moreover, no special processing is required for the image signal, which can be realized with a low-cost circuit configuration. Furthermore, since the polarity inversion is surely performed for each field, high reliability can be obtained.

Next, FIG. 13 shows a horizontal scanning circuit according to the fourth embodiment. In this figure, 17 is a shift register circuit, 18 is a 1-channel sample hold circuit,
Reference numeral 19 is a sampling switch for sampling the AC image signal (Vac), and 20 is a sampling capacitor (C) for holding the sampled sampling voltage (Vcs).
s), 21 is a non-inverting circuit that outputs a sampling voltage (Cs), and 24 is a supply switching switch that switches the electrode direction of the sampling signal to the sampling capacitor (Cs). These components are the third component shown in FIG.
11 is the same as that of the first embodiment and is assigned the same number as in FIG. The difference from the third embodiment is that the power supply voltage end changeover switch 26 that changes the end of the sampling capacity (Cs) to the power supply voltage (Vcc) on the a electrode side in conjunction with the supply changeover switch 24, and the sampling capacity ( The point is that a reference voltage termination changeover switch 27 is provided that switches the termination of Cs) to the reference voltage (GND) on the b electrode side in conjunction with the supply changeover switch 24.

FIG. 8 shows the signal waveform of each part of this liquid crystal display device.
The waveform is the same as that of the second embodiment shown in FIG. The details of the signals shown in (i) to (k) among them are slightly different, and this is shown in FIG. 14 as an enlarged view B. FIG. 14) is a detailed signal waveform diagram of an enlarged view B of the signal waveform diagram shown in (FIG. 8) in the liquid crystal display device of the present embodiment. In (j) and (k) of this figure, (Vcc) is the power supply voltage, and (G)
ND) is a reference voltage, (Vcent) is a voltage that is half the power supply voltage, and (Vcs) is a sampling voltage.

The operation of the liquid crystal display device of the present embodiment configured as described above is as follows. Vertical sync signal (/
VD), horizontal sync signal (/ HD), clock signal (CL
K) is input to the horizontal control circuit 15 and the vertical control circuit 13, and the image signal (Vs) is input to the AC circuit 14. Then, the horizontal control circuit 15 outputs the horizontal start signal (SH) and the horizontal clock signal (Hcl).
k), the alternating signal (POL) and the polarity inversion signal (HT) are output, and the vertical control circuit 13 outputs a vertical start signal (SV) and a vertical clock signal (Vclk). The alternating circuit 14 outputs an alternating image signal (Vac) in which the polarity of the image signal (Vs) is inverted by the alternating signal (POL) for each 1H and for each field.

In the horizontal scanning circuit 16 shown in FIG.
Horizontal clock signal (Hclk) and horizontal start signal (S
H) causes the shift register circuit 17 to operate, and a signal for sampling the AC image signal (Vac) corresponding to the position at Y1 of the signal electrode 7 controls the sampling switch 19 of the sample and hold circuit 18, and the sampling capacitance (Cs). ) Is supplied with the sampling voltage (Vcs) and held.

During the period when the polarity inversion signal (HT) is at the H level, the supply changeover switch 24 is set to the sampling capacitor 20 a.
A signal is supplied to the electrode side. At that time, the power supply voltage termination changeover switch 26 is open, the reference voltage termination changeover switch 27 is turned on, and the b electrode side is at the reference voltage (GND).
End in. Then, as shown in (k) of FIG.
The potential of the electrode is the reference voltage (GND) and the potential of the a electrode is the sampling voltage (Vcs). On the other hand, the polarity inversion signal (H
The supply selector switch 24 supplies a signal to the b-electrode side of the sampling capacitor 20 while T) is at the L level. At that time, the reference voltage termination changeover switch 27 is opened,
The power supply voltage termination changeover switch 26 is turned on to terminate the a electrode side to the power supply voltage (Vcc). Then, as shown in (k) of FIG. 14, the potential of the a electrode is equal to the power supply voltage (Vcc).
Therefore, the sampling voltage (Vcs) is set to the intermediate voltage (V
cent) means that the polarity is reversed. In this way, the liquid crystal drive signal (Vlcd) whose polarity is inverted every 1/2 H is supplied to the signal electrode 7 via the non-inverting circuit 21.

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
During this period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 10), in the odd 1 field, +1 line is for X1, −polarity is 1 line for X2, + polarity is 3 lines for X3, and −polarity is 3 lines for X4. , X5 has + polarity 5 lines, X6
For-polar 5 lines, for X7 + polar 7 lines, X
The signals of 7 lines of negative polarity are written in 8 respectively. In even 1 field, X2 has + polarity 2 lines, X3 has −polarity 2 lines, X4 has + polarity 4 lines, X5 has −polarity 4 lines, and X6 has + polarity 6 lines.
Signals of −polarity 6 lines are written in X7, signals of + polarity 8 lines are written in X8, and −polarity 8 lines are written in X9. The same writing is performed in the odd 2 field and the even 2 field. Then, by repeating this, the interlaced signal is written in the pixels while the polarities of the odd field and the even field are inverted and written to the pixels, and a high-quality image similar to that of the non-interlaced drive is displayed in a pseudo manner.

As described above, according to this embodiment, the period of the vertical clock signal (Vclk) is set to (1 / 2H) period, and the sample hold circuit 18 switches the polarity of the sample hold capacitor 20 and the power supply changeover switch 24 and the power source. By providing the voltage termination changeover switch 26 and the reference voltage termination changeover switch 27 and reversing the polarity of the sample-hold voltage (Vcs) having a large amplitude every (1 / 2H) period, each scan electrode is surely polarized every field. By using the inverted liquid crystal drive signal (Vlcd), an interlace signal can be written in each field and a high quality image display without pseudo full line flicker can be obtained.
Moreover, no special processing is required for the image signal, which can be realized with a low-cost circuit configuration. Furthermore, the polarity reversal is surely 1
Since it is performed for each field, high reliability can be obtained.

Next, FIG. 15 shows a circuit of the liquid crystal display device according to the fifth embodiment. In this figure, a TFT 1, a liquid crystal cell 2, an auxiliary capacitor 3, a counter electrode 4, a pixel electrode 5, a scanning electrode 6, a signal electrode 7, a block 8 for one pixel, a liquid crystal panel 9, a vertical scanning circuit 10, a vertical control circuit 13 ,
The horizontal control circuit 15 and the horizontal control circuit 15 are the same as those in the second embodiment shown in FIG. 6, and are denoted by the same reference numerals as in FIG.

In the present embodiment shown in FIG. 15, a digital alternating circuit 2 for generating an alternating digital image signal (Dac) from a digital image signal (Ds) and an alternating signal (POL).
8 and a digital horizontal scanning circuit 29 for sampling the AC digital image signal (Dac) is provided, which is different from the second embodiment.

FIG. 16 shows details of the digital horizontal scanning circuit 29. In this figure, the shift register circuit 17 and the non-inverting circuit 21 are the same as those of the second embodiment shown in FIG. 7, and are given the same numbers as in FIG. The difference from the second embodiment is that a digital AC image signal (Dac) is used.
Data latch circuit 30 for sampling and latching the data, and inverting the output of the data latch circuit 30 by the polarity inversion signal (HT) to output the data inversion signal (Dinv)
A data inversion / non-inversion circuit 31 for outputting a digital data inversion signal (Dinv) to an analog signal D /
The point is that the A circuit 32 and the 1-channel digital sample hold circuit 33 are provided.

FIG. 1 shows the signal waveform of each part of this liquid crystal display device.
7 shows. In this figure, a vertical synchronizing signal (/ VD) shown in (a), a horizontal synchronizing signal (/ HD) shown in (b),
A clock signal (CLK) shown in (c), a vertical start signal (SV) shown in (e), a vertical clock signal (Vclk) shown in (f), and a horizontal start signal (S shown in (g).
H), a horizontal clock signal (Hclk) shown in (h),
(I) AC signal (POL), (p) polarity inversion signal (HT), (k) liquid crystal drive signal (Vlc)
d), scan electrode signals (X1) to (l) to (o)
(X4) is the same as the signal of the second embodiment shown in FIG. Unlike the second embodiment, (d)
The signal shown in (1) is a digital image signal (Ds), and the signal shown in (q) is a digital AC image signal (Dac). Figure 1
Digital data inversion signal (Din
v) is shown in (r).

The operation of the liquid crystal display device of the present embodiment configured as described above is as follows. Vertical sync signal (/
VD), horizontal sync signal (/ HD), clock signal (CL
K) is input to the horizontal control circuit 15 and the vertical control circuit 13, and the digital image signal (Ds) is input to the digital AC circuit 28. Then, the horizontal control circuit 15 outputs a horizontal start signal (SH), a horizontal clock signal (HClk), an alternating signal (POL) and a polarity inversion signal (HT), and the vertical control circuit 13 outputs a vertical start signal (SV). The vertical clock signal (Vclk) is output. The digital AC circuit 28 outputs a digital AC image signal (Dac) in which the polarity of the digital image signal (Ds) is inverted every 1H and every field by the AC signal (POL).

Digital horizontal scanning circuit 16 shown in FIG.
, The shift register circuit 17 operates by the horizontal clock signal (Hclk) and the horizontal start signal (SH),
A signal for sampling the digital AC image signal (Dac) corresponding to the position of Y1 of the signal electrode 7 controls the data latch circuit 30 of the digital sample hold circuit 33, and the digital data is latched in the data latch circuit 30. The data inversion / non-inversion circuit 31 outputs the non-inversion digital data inversion signal (Dinv) while the polarity inversion signal (HT) is at the H level, and the D / A circuit 3
The signal is converted into an analog signal at 2 and supplied to the signal electrode 7 as a + polarity liquid crystal drive signal (Vlcd) through the non-inverting circuit 21. On the other hand, while the polarity inversion signal (HT) is at L level,
Outputs the inverted digital data inversion signal (Dinv),
The D / A circuit 32 converts the analog signal into a non-inverting circuit 21.
Is supplied to the signal electrode 7 as a negative polarity liquid crystal drive signal (Vlcd).

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
During this period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 10, in the odd 1 field, X1 has one line of + polarity, X2 has one line of − polarity, X3 has three lines of + polarity, and X4 has −.
Signals of three polar lines, five positive polar lines to X5, five negative polar lines to X6, seven positive polar lines to X7, and seven negative polar lines to X8 are respectively written. In even field 1, X2 has two lines of positive polarity, X
3 for-polarity 2 lines, X4 for + polarity 4 lines,
Signals of −polarity 4 lines are written to X5, + polarity 6 lines to X6, −polarity 6 lines to X7, + polarity 8 lines to X8, and −polarity 8 line signals to X9. . Similarly, the odd 2 field and the even 2 field are similarly written. By repeating this, the interlaced signals are written in the pixels while inverting the polarities of the odd field and the even field and writing them in the pixels, thereby displaying a high-quality image similar to pseudo non-interlaced driving. There is.

As described above, according to this embodiment, the period of the vertical clock signal (Vclk) is set to (1 / 2H) period, and the data latch circuit 30 and the data inversion / non-inversion circuit 31 are provided in the digital sample hold circuit 33. The D / A circuit 32 is provided, and the polarity of the digital data is inverted every (1 / 2H) period by the data inversion / non-inversion circuit 31, so that the polarity of the liquid crystal is surely inverted for each field in each scan electrode. A drive signal (Vlcd) is given. By writing the interlaced signal in each field, it is possible to obtain a high-quality image display without pseudo full-line flicker. Moreover, no special processing is required for the image signal, which can be realized with a low-cost circuit configuration. Furthermore, the polarity reversal is surely 1
Since it is performed for each field, high reliability can be obtained.

Next, FIG. 18 shows a circuit of the liquid crystal display device according to the sixth embodiment. In this figure, a TFT 1, a liquid crystal cell 2, an auxiliary capacitor 3, a counter electrode 4, a pixel electrode 5, a scanning electrode 6, a signal electrode 7, a block 8 for one pixel, a liquid crystal panel 9, a vertical scanning circuit 10, a vertical control circuit 13 ,
The horizontal control circuit 15 and the digital AC conversion circuit 28 are the same as those in the fifth embodiment shown in FIG. 15, and are assigned the same numbers as those in FIG.

The eighteenth embodiment is different from the fifth embodiment in that a digital horizontal scanning circuit 34 having a new configuration,
Another point is that a reference switching circuit 35 that switches a reference serving as a reference when a digital signal is converted into an analog signal by the D / A circuit 32 is provided.

FIG. 19 shows details of the digital horizontal scanning circuit 34. In this figure, the shift register circuit 1
7, the non-inverting circuit 21, the data latch circuit 30, the D / A circuit 32, and the digital sample hold circuit 33 are the same as those of the fifth embodiment shown in FIG.
The same number as 6 is attached. The difference from the fifth embodiment is that the D / A circuit 32 is configured to switch the reference when converting a digital signal into an analog signal according to the REF signal input. Figure 20
Shows the analog signal output-digital input signal characteristics of the D / A circuit 32. In this figure, the horizontal axis is the input of the D / A circuit 32 (that is, the output of the data latch circuit 30), and here, there are 64 values of 6 bits. The vertical axis is D /
Analog signal output of A circuit 32 (that is, liquid crystal drive signal Vlc
d). In the characteristic A and the characteristic B which are switched according to the REF signal input, the relationship of the analog signal output with respect to the digital input is inverted.

FIG. 2 shows the signal waveform of each part of this liquid crystal display device.
Shown in 1. In this figure, a vertical synchronizing signal (/ VD) shown in (a), a horizontal synchronizing signal (/ HD) shown in (b),
A clock signal (CLK) shown in (c), a digital image signal (Ds) shown in (d), a vertical start signal (SV) shown in (e), and a vertical clock signal (Vcl shown in (f).
Horizontal start signals (SH) and (h) shown in k) and (g)
The horizontal clock signal (Hclk) shown in FIG. 3, the alternating signal (POL) shown in (i), and the polarity inversion signal (H) shown in (p).
T) and the digital AC image signal (Dac) shown in (q),
Liquid crystal drive signal (Vlcd) shown in (k), (l) to (o)
The scanning electrode signals (X1) to (X4) shown in (7) are the same as the signals of the fifth embodiment shown in FIG.
A digital latch signal (Dlatch) which is the output of the data latch circuit 30 shown in (s) and D / shown in (t).
The reference signal (REF) of the A circuit 32 is different from that of the fifth embodiment.

The operation of the liquid crystal display device of the present embodiment configured as described above is as follows. Vertical sync signal (/
VD), horizontal sync signal (/ HD), clock signal (CL
K) is input to the horizontal control circuit 15 and the vertical control circuit 13, and the digital image signal (Ds) is input to the digital AC circuit 28. Then, the horizontal control circuit 15 outputs a horizontal start signal (SH), a horizontal clock signal (HClk), an alternating signal (POL) and a polarity inversion signal (HT), and the vertical control circuit 13 outputs a vertical start signal (SV). The vertical clock signal (Vclk) is output. The digital AC circuit 28 outputs a digital AC image signal (Dac) in which the polarity of the digital image signal (Ds) is inverted every 1H and every field by the AC signal (POL).

The digital horizontal scanning circuit 34 shown in FIG.
, The shift register circuit 17 operates by the horizontal clock signal (Hclk) and the horizontal start signal (SH),
A signal for sampling the digital AC image signal (Dac) corresponding to the position of Y1 of the signal electrode 7 controls the data latch circuit 30 of the digital sample hold circuit 33, and the digital data is latched in the data latch circuit 30. In the D / A circuit 32, the analog output signal increases with respect to the increase of the digital latch signal (Dlatch) during the period of the reference signal (REF) having the characteristic A shown in FIG. The liquid crystal drive signal (Vlcd) is supplied to the signal electrode 7. On the other hand, while the reference signal (REF) has the characteristic B shown in FIG. 20, the analog output signal decreases as the digital latch signal (Dlatch) increases, and the negative polarity liquid crystal drive signal (Vlcd) is passed through the non-inverting circuit 21. ) Is supplied to the signal electrode 7.

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
During this period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 10, in the odd 1 field, X1 has one line of + polarity, X2 has one line of − polarity, X3 has three lines of + polarity, and X4 has −.
Signals of three polar lines, five positive polar lines to X5, five negative polar lines to X6, seven positive polar lines to X7, and seven negative polar lines to X8 are respectively written. In even field 1, X2 has two lines of positive polarity, X
3 for-polarity 2 lines, X4 for + polarity 4 lines,
Signals of −polarity 4 lines are written to X5, + polarity 6 lines to X6, −polarity 6 lines to X7, + polarity 8 lines to X8, and −polarity 8 line signals to X9. . Similarly, the same writing is performed in the odd 2 field and the even 2 field. Then, by repeating this, the interlaced signal is written in the pixels while inverting the polarities in the odd field and the even field, and is written in the pixel, thereby displaying a high-quality image similar to pseudo non-interlaced driving. There is.

As described above, according to this embodiment, the period of the vertical clock signal (Vclk) is set to (1 / 2H) period, and the digital sample hold circuit 33 is provided with the data latch circuit 30 and the D / A circuit 32. Characteristics A of the reference signal (REF) shown in FIG. 20 every (1 / 2H) period.
By switching between the scan electrode and the characteristic B, the liquid crystal drive signal (Vlcd) whose polarity is reliably inverted is given to each scan electrode for each field. As described above, by writing the interlaced signal in each field with a simple circuit configuration, it is possible to obtain a high-quality image display without pseudo full-line flicker. Moreover, no special processing is required for the image signal, which can be realized with a low-cost circuit configuration. Furthermore, since the polarity inversion is surely performed for each field, high reliability can be obtained.

Next, FIG. 22 shows a circuit of the liquid crystal display device according to the seventh embodiment. In this figure, a TFT 1, a liquid crystal cell 2, an auxiliary capacitor 3, a counter electrode 4, a pixel electrode 5, a scanning electrode 6, a signal electrode 7, a block 8 for one pixel, a liquid crystal panel 9, a vertical scanning circuit 10, a vertical control circuit 13 , Horizontal control circuit 15, digital horizontal scanning circuit 3
4 and the reference switching circuit 35 are the same as those of the sixth embodiment shown in FIG.
The same number as 8 is attached. The present embodiment shown in FIG. 22 differs from the sixth embodiment in that the digital alternating circuit 28 is omitted.

FIG. 2 shows the signal waveform of each part of this liquid crystal display device.
3 shows. In this figure, a vertical synchronizing signal (/ VD) shown in (a), a horizontal synchronizing signal (/ HD) shown in (b),
A clock signal (CLK) shown in (c), a digital image signal (Ds) shown in (d), a vertical start signal (SV) shown in (e), and a vertical clock signal (Vcl shown in (f).
Horizontal start signals (SH) and (h) shown in k) and (g)
Horizontal clock signal (Hclk) shown in FIG. 3, polarity inversion signal (HT) shown in (p), liquid crystal drive signal (Vlc) shown in (k).
d), scan electrode signals (X1) to (l) to (o)
(X4) is the same as the signal of the sixth embodiment shown in FIG.

The operation of the liquid crystal display device of this embodiment having the above structure is as follows. Vertical sync signal (/
VD), horizontal sync signal (/ HD), clock signal (CL
K) is input to the horizontal control circuit 15 and the vertical control circuit 13, and the digital image signal (Ds) is input to the digital horizontal scanning circuit 34. Then, the horizontal control circuit 15 outputs a horizontal start signal (SH), a horizontal clock signal (Hclk), and a polarity inversion signal (HT), and the vertical control circuit 13 outputs a vertical start signal (SV) and a vertical clock signal (Vclk). Is output.

Digital horizontal scanning circuit 3 shown in FIG.
4, the shift register circuit 17 operates by the horizontal clock signal (Hclk) and the horizontal start signal (SH), and the signal for sampling the digital image signal (Ds) corresponding to the position of Y1 of the signal electrode 7 is a digital sample. The data latch circuit 30 of the hold circuit 33 is controlled, and the digital data is latched in the data latch circuit 30. In the D / A circuit 32, the analog output signal increases with respect to the increase of the digital latch signal (Dlatch) during the period of the reference signal (REF) having the characteristic A shown in FIG. The liquid crystal drive signal (Vlcd) is supplied to the signal electrode 7. On the other hand, while the reference signal (REF) has the characteristic B shown in FIG. 20, the analog output signal decreases as the digital latch signal (Dlatch) increases, and the negative polarity liquid crystal drive signal (Vlcd) is passed through the non-inverting circuit 21. ) Is supplied to the signal electrode 7.

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
During this period, the scan electrodes 6 are turned on, and the signals X1, X2, X3, and X4 shifted by 1 / 2H are supplied to the respective scan electrodes. Then, as shown in FIG. 10, in the odd 1 field, X1 has one line of + polarity, X2 has one line of − polarity, X3 has three lines of + polarity, and X4 has −.
Signals of three polar lines, five positive polar lines to X5, five negative polar lines to X6, seven positive polar lines to X7, and seven negative polar lines to X8 are respectively written. In even field 1, X2 has two lines of positive polarity, X
3 for-polarity 2 lines, X4 for + polarity 4 lines,
Signals of −polarity 4 lines are written to X5, + polarity 6 lines to X6, −polarity 6 lines to X7, + polarity 8 lines to X8, and −polarity 8 line signals to X9. . Similarly, the same writing is performed in the odd 2 field and the even 2 field. By repeating this, the interlaced signals are written in the pixels while inverting the polarities of the odd field and the even field and writing them in the pixels, thereby displaying a high-quality image similar to pseudo non-interlaced driving. There is.

As described above, according to this embodiment, the cycle of the vertical clock signal (Vclk) is set to (1 / 2H) period, the digital sample hold circuit 33 is provided with the data latch circuit 30 and the D / A circuit 32, Characteristics A of the reference signal (REF) shown in FIG. 20 every (1 / 2H) period.
By switching between the characteristic B and the characteristic B, the polarity inversion for AC driving of the liquid crystal is simultaneously performed, and the liquid crystal drive signal (Vlcd) whose polarity is reliably inverted for each field is given to each scan electrode. By writing the interlaced signal in each field, it is possible to obtain a high-quality image display without pseudo full-line flicker. Moreover, since a circuit for converting a digital image signal into an alternating current is not required, it can be realized with a simplified and low-cost circuit configuration. Further, since the polarity inversion is surely performed for each field, high reliability can be obtained.

Next, FIG. 24 shows a signal waveform of the liquid crystal display device according to the eighth embodiment. In this figure, a vertical synchronizing signal (/ VD) shown in (a), a horizontal synchronizing signal (/ HD) shown in (b), a clock signal (CLK) shown in (c),
(D) digital image signal (Ds), (e) vertical start signal (SV), (g) horizontal start signal (SH), (h) horizontal clock signal (Hcl)
k), polarity inversion signal (HT) shown in (p), liquid crystal drive signal (Vlcd) shown in (k), and scan electrode signals (X1) to (X4) shown in (l) to (o). It is the same as the signal of the seventh embodiment shown in FIG. (U) ~
The scan electrode signals (X5) to (X10) shown in (z) are the same as the scan electrode signals (X1) to (X4).

A signal different from that of the seventh embodiment is the vertical clock signal (Vclk) shown in (f). In the seventh embodiment, a pulse is output every 1 / 2H of a constant cycle, whereas the vertical clock signal (Vclk) of this embodiment outputs a pulse at a cycle of 1 / 2H or 1 / 3H.

FIG. 25 is an explanatory diagram of an image display method of this liquid crystal display device. FIG. 25 (a) shows that in an NTSC interlaced signal as a digital image signal (Ds), an odd field signal is given to an odd field and an even line signal is given to an even field. FIG. 25B shows the signals written to the pixels in order from X1 of the scan electrode 6 in the odd 1 field, the even 1 field, the odd 2 field, and the even 2 field, and their polarities. FIG. 25C shows the state of the effective value written in each pixel when an image in which those fields are continuous is displayed on the liquid crystal panel 9. Here, the same signal of one line of the interlaced signal is written to three lines or two lines during one field period, thereby displaying an enlarged image on the liquid crystal panel.

The operation of the liquid crystal display device of this embodiment having the above configuration is as follows. Vertical sync signal (/
VD), horizontal sync signal (/ HD), clock signal (CL
K) is input to the horizontal control circuit 15 and the vertical control circuit 13, and the digital image signal (Ds) is input to the digital horizontal scanning circuit 34. Then, the horizontal control circuit 15 outputs a horizontal start signal (SH), a horizontal clock signal (Hclk), and a polarity inversion signal (HT), and the vertical control circuit 13 outputs a vertical start signal (SV) and a vertical clock signal (Vclk). Is output.

The digital horizontal scanning circuit 34 shown in FIG.
, The shift register circuit 17 operates by the horizontal clock signal (Hclk) and the horizontal start signal (SH),
A signal for sampling the digital image signal (Ds) corresponding to the position of Y1 of the signal electrode 7 controls the data latch circuit 30 of the digital sample hold circuit 33, and the digital data is latched in the data latch circuit 30.

In the D / A circuit 32, the analog output signal increases with respect to the increase of the digital latch signal (Dlatch) during the period of the reference signal (REF) having the characteristic A shown in FIG. A polar liquid crystal drive signal (Vlcd) is supplied to the signal electrode 7. On the other hand, while the reference signal (REF) has the characteristic B shown in FIG. 20, the analog output signal decreases with the increase of the digital latch signal (Dlatch), so that the negative polarity liquid crystal drive signal (Vlcd) is passed through the non-inverting circuit 21. ) Is supplied to the signal electrode 7.

In the vertical scanning circuit 10, 1 / 2H is generated by the vertical clock signal (Vclk) and the vertical start signal (SV).
, Or the scanning electrode 6 is turned on for 1/3 H
Signals X1 and X shifted by every 2H or 1 / 3H
2, X3 and X4 are supplied to the respective scan electrodes. Then, as shown in FIG. 25, in the odd 1 field, X
1 has a positive polarity line, X2 has a negative polarity line,
X3 has a positive polarity line, X4 has a negative polarity line, X5 has a positive polarity line, X6 has a negative polarity line, X6 has a negative polarity line, X7 has a positive polarity line, and X8 has a negative polarity line. Of 5
Line, X9 has + polarity 7 lines, X10 has − polarity 7 lines, X11 has + polarity 7 lines, X12 has − polarity 9 lines, X13 has + polarity 9 lines, X1
A signal of −polarity 11 line is written in 4, a signal of + polarity 11 line in X15, a signal of −polarity 11 line in X16, a signal of + polarity 13 line in X17, and a signal of −polarity 13 line in X18. .

In the even 1 field, X2 has two positive polarity lines, X3 has two negative polarity lines, X4 has two positive polarity lines, X5 has four negative polarity lines, and X6 has four positive polarity lines.
4 lines of polarity, 4 lines of − polarity for X7, 6 lines of + polarity for X8, 6 lines of − polarity for X9, X10
8 lines of + polarity for X11, 8 lines of − polarity for X11,
X12 has + polarity 8 lines, X13 has-polarity 10
Line, 10 lines of + polarity for X14, − for X15
10 lines of polarity, 12 lines of + polarity for X16, X
The signals of 12 lines of negative polarity are written in 17 respectively.

In the odd 2 field, X1 has one line of + polarity, X2 has one line of − polarity, X3 has three lines of + polarity, X4 has three lines of − polarity, and X5 has +.
3 lines of polarity, 5 lines of − polarity for X6, 5 lines of + polarity for X7, 7 lines of − polarity for X8, 7 lines of + polarity for 9, 9 lines of − polarity for X10, X1
1 has + polarity 9 lines, X12 has −polarity 9 lines, X13 has + polarity 9 lines, X14 has −polarity 11 lines, X15 has + polarity 11 lines, and X16 has −polarity. , 13 lines of + polarity are written in X17, and signals of 13 lines of − polarity are written in X18.

In the even two fields, X2 has two lines of positive polarity, X3 has two lines of negative polarity, X4 has four lines of positive polarity, X5 has four lines of negative polarity, and X6 has +.
4 lines of polarity, 6 lines of − polarity for X7, 6 lines of + polarity for X8, 6 lines of − polarity for X9, X10
8 lines of + polarity for X11, 8 lines of − polarity for X11,
X12 has 10 lines of positive polarity, and X13 has 1 line of negative polarity.
0 line, 10 lines of + polarity for X14, 12 lines of − polarity for X15, 12 lines of + polarity for X16,
Signals of 12 lines of negative polarity are written in X17. And by repeating this,
The effective value of 1 + 1 + 2 + 2 lines for X2 and 1+ for X3
Effective value of 2 + 2 + 3 lines, effective value of 2 + 3 + 3 + 4 lines for X4, effective value of 3 + 3 + 4 + 4 lines for X5, effective value of 4 + 4 + 5 + 5 lines for X6, effective value of 4 + 5 + 5 + 6 lines for X7, 5 + 6 + 6 + for X8
7 lines effective value, X9 6 + 6 + 7 + 7 lines effective value, X10 7 + 7 + 8 + 8 lines effective value, X1
1 is the effective value of 7 + 8 + 8 + 9 lines, X12 is 8+
Effective value of 9 + 9 + 10 lines, 9 + 9 + 10 for X13
+10 line effective value, 10 + 10 + 11 + for X14
Effective value of 11 lines, 10 + 11 + 11 + 1 for X15
The signals of the effective values of the two lines are written respectively. Then, the same signal is written in a plurality of lines by superposing the interlaced signal while inverting the polarities in the odd field and the even field, and further, by shifting the writing timing for each field, a smooth enlarged image display can be obtained.

As described above, according to this embodiment, the vertical clock signal (Vclk) has two types of cycles, that is, a (1 / 2H) period and a (1 / 3H) period, and has a constant period and a timing for each field. 20 is provided, the data latch circuit 30 and the D / A circuit 32 are provided in the digital sample hold circuit 33, the reference signal (REF) is synchronized with the vertical clock signal (Vclk), and the characteristic A shown in FIG.
By switching between the characteristic B and the characteristic B, the polarity inversion for AC driving of the liquid crystal is also performed at the same time, and the liquid crystal drive signal (Vlcd) whose polarity is reliably inverted for each field is given to each scan electrode. By writing the interlaced signal in each field and writing the same line signal in a plurality of lines, it is possible to display a high-quality and smooth enlarged image without flicker. Moreover, since a complicated image processing circuit for enlarged display is not required, it can be realized with a low-cost circuit configuration. Furthermore, since the polarity inversion is surely performed for each field, high reliability can be obtained.

In the first to eighth embodiments described above, the NTSC interlaced signal is used as the image signal, but the present invention is not limited to this, and can be applied to the case where a video signal of another system is used. You can Further, in the eighth embodiment, the same effect can be obtained by using a non-interlaced signal instead of the interlaced signal. Further, the present invention can be similarly applied to a color liquid crystal panel having RGB pixels.

[0090]

As described above, according to the present invention,
In a liquid crystal panel having a structure in which a storage capacitor is connected to a scanning electrode in the preceding stage, by writing the same signal in a plurality of lines with different numbers in one field and shifting the timing for each field, an interlaced image signal is used. Pseudo non-interlaced enlarged display is possible, and smooth and flicker-free high-quality image display is possible in NTSC / PAL conversion and display aspect conversion .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

2 is a circuit diagram of a horizontal scanning circuit in the liquid crystal display device of FIG.

FIG. 3 is a signal waveform diagram of each part of the liquid crystal display device of FIG.

FIG. 4 is a detailed waveform diagram of some of the signals in FIG.

5 is a diagram for explaining a display method of the liquid crystal display device of FIG.

FIG. 6 is a circuit diagram of a liquid crystal display device according to a second embodiment.

7 is a circuit diagram of a horizontal scanning circuit in the liquid crystal display device of FIG.

FIG. 8 is a signal waveform diagram of each part of the liquid crystal display device of FIG.

9 is a detailed waveform diagram of some of the signals in FIG.

10 is a diagram for explaining a display method of the liquid crystal display device of FIG.

FIG. 11 is a circuit diagram of a horizontal scanning circuit of the liquid crystal display device according to the third embodiment.

FIG. 12 is a detailed waveform diagram of some signals of the liquid crystal display device of FIG.

FIG. 13 is a circuit diagram of a horizontal scanning circuit of a liquid crystal display device according to a fourth embodiment.

FIG. 14 is a detailed waveform diagram of some signals of the liquid crystal display device of FIG.

FIG. 15 is a circuit diagram of a liquid crystal display device according to a fifth embodiment.

16 is a circuit diagram of a horizontal scanning circuit in the liquid crystal display device of FIG.

FIG. 17 is a signal waveform diagram of each part of the liquid crystal display device of FIG.

FIG. 18 is a circuit diagram of a liquid crystal display device according to a sixth embodiment.

19 is a circuit diagram of a horizontal scanning circuit in the liquid crystal display device of FIG.

20 is a reference characteristic diagram of a D / A circuit in the liquid crystal display device of FIG.

21 is a signal waveform diagram of each part of the liquid crystal display device of FIG.

FIG. 22 is a circuit diagram of a liquid crystal display device according to a seventh embodiment of the present invention.

23 is a signal waveform diagram of each part of the liquid crystal display device of FIG.

FIG. 24 is a signal waveform diagram of each part of the liquid crystal display device according to the eighth embodiment of the present invention.

25 is a diagram for explaining a display method of the liquid crystal display device of FIG.

FIG. 26 is a circuit diagram of a liquid crystal display device according to a conventional example.

27 is a signal waveform diagram of each part of the liquid crystal display device of FIG.

28 is a diagram for explaining a display method of the liquid crystal display device of FIG.

[Explanation of symbols]

1 TFT 2 Liquid crystal cell 3 auxiliary capacity 4 Counter electrode 5 pixel electrodes 6 scanning electrodes 7 signal electrodes 8 1 pixel 9 LCD panel 10 Vertical scanning circuit 11 Horizontal scanning circuit 12 Horizontal control circuit 13 Vertical control circuit 14 AC circuit

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-6-175619 (JP, A) JP-A-7-30836 (JP, A) JP-A-5-173503 (JP, A) JP-A-2- 312466 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/66 G09G 3/36

Claims (2)

(57) [Claims] 1. A plurality of scanning electrodes and signal electrodes on the substrate are arranged in <br/> matrix, before Symbol pixel is provided in the regions partitioned by the scanning electrode and the signal electrode, the pixel thin film transistor and it consists of a storage capacitance for assisting signal holding characteristic of the liquid crystal cell and the liquid crystal cell, before Symbol auxiliary capacitor
Have the liquid crystal panel electrodes is Ru is connected to the scan electrode of the front stage
A liquid crystal Display apparatus, before Symbol a vertical scanning circuit for supplying a scanning signal to the scanning electrodes, the clock signal, a horizontal synchronizing signal, and a horizontal scanning for operating or al the vertical scanning circuit vertical synchronizing signal the period 1
/ 2 period and mixed and vertical scanning clock signal timing is different in the 4 field period constant period of 1/3, and including that of a vertical control circuit which outputs a vertical start signal to the vertical scanning circuit Characteristic liquid crystal display device. 2. A plurality of scan electrodes and signal electrodes are provided on a substrate.
The scan electrodes and the signal electrodes are arranged in a matrix.
Pixels are provided in the area defined by and, and the pixels are thin films.
Transistor, liquid crystal cell, and signal holding characteristics of the liquid crystal cell
And an auxiliary capacity for assisting the
A liquid crystal panel whose electrodes are connected to the scanning electrodes in the preceding stage,
Horizontal scanning circuit for supplying a liquid crystal driving signal to the signal electrode
And a vertical scanning circuit for supplying a scanning signal to the scanning electrodes.
And clock signal, horizontal sync signal, and vertical sync signal.
1 horizontal scanning period for operating the vertical scanning circuit
½ cycle and ⅓ cycle are mixed in a fixed cycle and
Vertical scan clock with different timing in 4 fields
Output signal and vertical start signal to the vertical scanning circuit
And a vertical control circuit for driving the liquid crystal display device, wherein the horizontal scanning circuit has one horizontal scanning period.
Several times repeatedly outputs and one line polarity non-inverted signal of the image data and the polarity inversion signal within the vertical scanning circuit outputs a signal to two or three or more of the scanning electrodes in said one horizontal scanning period By doing, within one field period,
Polarity is displayed on two or three or more scanning lines adjacent the image data including the different lines from each other, and also wherein this <br/> and for inverting the polarity of the liquid crystal drive signals between field Driving method for liquid crystal display device.