JPH04195086A - Matrix type display device and control circuit used therein - Google Patents

Abstract

PURPOSE:To allow the execution of ordinary display and macrodisplay by using a vertical scanning circuit of simple constitution by controlling the phase of a horizontal scanning clock simultaneously with the change over of a vertical clock frequency. CONSTITUTION:Frequency dividers 532, 533 for the clock waveform CK obtd. by a PLL 5 are reset in synchronization with a horizontal synchronizing signal and are synchronized in phase with the horizontal synchronizing signal. A switch 403 of a control circuit is changed over reverse from the ordinary display and the phase of the horizontal scanning clock is kept constant over the entire horizontal scanning period in the case of the two-fold macrodisplay. The clock of the frequency twice higher than the frequency of the ordinary display is supplied as the horizontal scanning clock of 6 phases to a shift register by using the rise and fall of the clock waveform obtd. by multiplying the horizontal synchronizing signal. Further, the macrodisplay is executed by executing the change over control together with the vertical scanning clock by a switch 401. Images are displayed in enlargement in this way by using the vertical scanning circuit of the simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application] The present invention particularly relates to a matrix type display device having an enlarged display function and a control integrated circuit used therein.

[Conventional technology]

Conventionally, television images with 625 scanning lines (the number of effective display scanning lines in a field: approximately 280) are displayed on a matrix display panel with a vertical 28o pixel specification for broadcasting areas (for example, Germany). 525 scanning lines (approximately 24 effective display scanning lines within the field)
When displaying a television image signal of 0 lines), the matrix display panel is driven by setting a horizontal scanning period for driving one row of pixels and a horizontal scanning period for simultaneously driving two rows of pixels. A method of enlarging an image and displaying it on the entire surface of a matrix display panel was developed in Japanese Patent Laid-Open No. 56-14.
It is described in Publication No. 297.

In addition, the scanning clock frequency of the matrix display panel was set to 2.
A method for displaying images by switching to double magnification was published in Japanese Patent Application Laid-Open No. 57-689.
It is described in Publication No. 79.

[Problems to be Solved by the Invention] In the first prior art described above, in order to enlarge and display an image, shift registers are divided into groups of N stages as a vertical scanning circuit, and the shift registers of each group are divided into groups of N stages. Used as an input signal to switch between the output of the Nth stage of the front group and the output of the N-1st stage,
It used a special and complex structure. For this reason, it was necessary to prepare a special and complex vertical scanning circuit that is different from the vertical scanning circuits commonly used in the past (vertical scanning circuits consisting of shift registers that output signals in sequence). . Furthermore, since the magnification factor is determined by the configuration of the vertical scanning circuit, it is difficult to set an arbitrary magnification factor.

In the second prior art described above, enlarged display is achieved by switching the vertical scanning clock frequency without using a special vertical scanning circuit. However, this does not take into account color matrix display devices in which three primary color filters are sequentially arranged in each pixel, for example in a triangular arrangement, and problems such as horizontal resolution deterioration and color mixture may occur in enlarged display. was there. Also, compared to the normal display,
In the enlarged display, due to the increase in the frequency of the vertical scanning clock,
There was also the problem of brightness changes due to the shortened selection time for each pixel.

The purpose of the present invention is to solve the problems of the prior art described above,
Provided is a matrix type display device that can display an enlarged image with good horizontal resolution and color reproduction at any magnification by switching its scanning clock frequency using a simple vertical scanning circuit, and also provides a control device used therein. Its purpose is to provide integrated circuits.

[Means for Solving the Problems] In order to achieve the above object, in the present invention, when switching between normal display and enlarged display, the phase of the horizontal scanning clock is controlled in addition to switching the vertical clock frequency.

Regarding reduction of pixel selection time in enlarged display,
Pixels in multiple rows were driven in parallel by applying a start signal to a shift register used in a vertical scanning circuit to multiple vertical scanning clock signals.

[Effect]

In the present invention, in normal display where the horizontal position of the pixel array is different in adjacent rows, good horizontal resolution is obtained by changing the sampling timing of the signal given to the pixels of each row every horizontal scanning period, and the horizontal position of the pixel array is different between adjacent rows. In an enlarged display that gives the same signal to two rows of pixels at different horizontal positions,
A good image can be obtained by making the sampling timing of the signals given to the pixels of each row the same in all horizontal scanning periods.

In addition, in enlarged display, by applying the start signal of the shift register used in the vertical scanning circuit to multiple vertical scanning clock signals and driving multiple rows of pixels in parallel, the pixel selection time can be maintained at the same level as in normal display. However, changes in brightness can be prevented.

[Example] An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, l is a matrix display panel, for example, an active matrix type liquid crystal display panel in which scanning electrodes are arranged in the horizontal direction, signal electrodes are arranged in the vertical direction, and a TPT (thin film transistor) and a liquid crystal element are arranged at each intersection. It is a display panel. 2 is a horizontal scanning circuit, for example, a shift register 2 whose output changes at the rising edge of a clock.
01, and a sample/hold circuit array 202 that samples the video signal at the output timing of the shift register 201. 3 is a vertical scanning circuit;
For example, it is composed of a shift register 301 whose output changes at the rising edge of a clock and a vertical output circuit 302.

641 is a video signal input terminal, 606 is a horizontal synchronizing signal input terminal, 607 is a vertical synchronizing signal input terminal, 7 is a frequency inversion circuit, 55 is a PLL circuit, 52 and 54 are frequency dividers, 53 is a phase shift circuit, 56 51 is a timing signal forming circuit, 51 is an enlarged display signal forming circuit, 401 to 404 are changeover switches, and 57 is an OR circuit. 58 and 59 are delay circuits. FIG. 2 is an example showing in more detail a portion consisting of the matrix display panel 1, horizontal scanning circuit 2, and vertical scanning circuit 3 shown in FIG.

The matrix display panel 12 has pixels corresponding to the three primary colors of red (R), green (C), and blue (B) arranged in a triangle shape as shown in FIG. Pixels of the same color are connected, and each pixel
As shown in Figure A, a transistor 121, an additional capacitor 122 formed between the transistor 121 and the previous scanning electrode, and a pixel electrode 1 that drives a liquid crystal element (not shown).
23. This is an active matrix type liquid crystal display panel capable of color display. In this embodiment, a liquid crystal element is used as the display element, but it is obvious that other display elements such as EL and plasma displays can be similarly considered.

The signal electrodes of this matrix display panel 12 are
odd-numbered signal electrodes Yl, which are drawn out alternately from above and below;
Y3. ... are connected to the horizontal scanning circuit 21, even numbered signal electrodes Y2 . Y4. ... are connected to the horizontal scanning circuit 22. The scanning electrodes Xi, X2, . . . are drawn out from the left side and connected to the vertical scanning circuit 3.

The horizontal scanning circuits 21 and 22 each have a shift register 2.
11 and 221, and sample and hold circuits 212 and 222. Shift registers 211 and 221 have horizontal scanning clock input terminals 691, 693, and 6, respectively.
95. The display unit as a whole is driven by a three-phase horizontal scanning clock input from 692°694.696.
Driven by a 6-phase clock. Note that 697 and 698 are horizontal scanning start signal input terminals of the shift registers 221 and 222, respectively.

The sample and hold circuits 212 and 222 transfer the three primary color signals as image signals applied to the common three primary color signal input terminals 661, 662, and 663 to the shift registers 211 and 2.
21, and each signal electrode Yl, Y2 . Supply to Y3...

Further, the vertical scanning circuit 3 includes a shift register 30I and a vertical output circuit 302. Note that 601 is a vertical scanning start signal input terminal of the shift register 301;
605 is a vertical scanning clock input terminal.

FIG. 3 is an example showing in more detail the control section consisting of the enlarged display signal forming circuit 51, the vertical scanning clock changeover switch 401, and the horizontal scanning clock changeover switch 403 shown in FIG.

The enlarged display signal forming circuit 51 includes a phase control loop circuit (hereinafter abbreviated as PLL) 55, a changeover switch 402, frequency dividers 531, 533, 534, and a frequency divider 532.
and a latch 54 that captures and holds data at the rising edge.
1 to 548, inverter 561, and OR gate 565
~567. Further, the PLL 55 includes a phase comparator 551, a low frequency filter (hereinafter abbreviated as LPF) 552, a voltage controlled oscillator (hereinafter abbreviated as vCO) 553, and a frequency divider 554. Note that 606 is a horizontal synchronization signal input terminal.

4 and 6 are waveform diagrams showing an example of the waveform of each part signal during normal display in the embodiment consisting of FIGS. 1, 2, and 3, and FIGS. FIG. 4 is a waveform diagram showing one waveform of each signal at the time of enlarged display in the embodiment shown in FIGS.

In FIGS. 4 and 5, (r) is the reset pulse waveform output from the frequency divider 554, and (CK) is the V CO
Clock waveforms output from 553, (ql), (q2
) are the output signal waveform of the frequency divider 532 and (q
3) is the main signal waveform of latch 548, (q4) is the output signal waveform of latch 547, (q5) is the output signal waveform of frequency divider 533, (ul), ..., (u6) is , the clock waveforms output from the latches 541, . . . , 546, (vl), . . . , (v3), respectively.
) are the inverters 562 .・・・・・・、5
64, the inverted waveform (sh) is the horizontal scanning start signal waveform applied to the horizontal scanning start signal input terminals 697 and 698 shown in FIG.
h3) are respectively ○R gates 565.・・・・・・
This is the clock waveform output from the 567.

First, referring to FIG. 3, the vertical scanning clock generation operation will be described.

When a horizontal synchronization signal is applied to the terminal 606, the PLL 55, which is composed of a phase comparator 551, an LPF 552, a VCO 553, and a frequency divider 554, divides the horizontal synchronization signal into a number corresponding to the number of display pixels, for example, 480 horizontal pixels. Then, the signal is multiplied by about 600, and a clock waveform (CK) whose phase is synchronized with the horizontal synchronizing signal is obtained as the output of the VCO 553.

A frequency divider 5 divides this clock waveform (CK).
54, a twice-enlarged vertical scanning clock waveform (e) having twice the frequency of the horizontal synchronizing signal is obtained, and a vertical scanning clock waveform (f ) is output to the terminal 605 as shown in FIG. 7(f). On the other hand, in the case of normal display, the 2x enlarged vertical scanning clock waveform (e) is further divided by 2 by a frequency divider 531 to obtain a normal vertical scanning clock waveform (d), and the normal vertical scanning clock waveform (d) is displayed using the changeover switch 401. Clock waveform (
f) is output to the terminal 605 (Fig. 6(f))
.

6 and 7, (a) is the output signal waveform of the horizontal scanning circuit 2 of FIG. 1 or 2, in which the output signal changes within the waveform change period 16, and the signal determination period T
, a predetermined image signal Si (i=1,2.3・
...) is output stably.

(c) is a vertical scanning start signal waveform applied to the input terminal 601, and (f) is a vertical scanning clock waveform applied to the input terminal 605. (xi),..., (x6)
are the output signal waveforms of the shift register 301, and correspond to the vertically arranged output terminals of the shift register 301 in order from the top, II HI
At + level, the vertical output circuit 302 is connected to the corresponding output terminal.
"Select" the scan electrode connected via II L
``It is set to ``unselected'' at level.

The following description assumes that the image signal is an NTSC interlaced television signal.

In the normal display, switches 401 and 403 .
404 are connected as shown in the figure, and as shown in FIG. During period T1 when the output signal waveform (xl) of the shift register 301 is at the 11 HIT level, the image signal S is output. Driven by ten. ``The pixels in the second row are driven by the negative polarity image signal S1- of the second horizontal scanning period during the period T3, and are sequentially driven one row at a time by the image signal of one horizontal period. In the subsequent second field, as indicated by the signal waveform names with dashes 11+11, a signal having a polarity opposite to that of the first field is applied, and each pixel is driven with alternating current.

On the other hand, in the enlarged display, the switch 401 in FIG.
and 403 and 404 are connected in the opposite direction as shown in the figure, and as shown in FIG. 7, the frequency of the clock waveform (f) applied to the shift register 301 is twice that of FIG. 6. In the -th pixel, in the first field, the positive polarity image signal 8.1+ of the 61st horizontal scanning period is output from the horizontal scanning circuit 2, and the output signal waveform (Xi) of the shift register 301.

During periods U, , U, when (x2) is at "H" level, they are driven by image signals S, 0, respectively. After two more horizontal scanning periods, the positive polarity image signal S of the 63rd horizontal scanning period
1. + is applied to the pixels in the first and second rows during periods T, , T, respectively. Generally, images have a strong correlation in the vertical direction, and the image signals S l l+ and S.

Considering that the level difference between 10 and 10 is small, in the enlarged display,
The period during which the pixels in the first row are driven is (U1+Ti), which is almost the same as the normal display shown in FIG.

As described above, in the waveform example shown in FIG. 7, it can be seen that by driving two rows of pixels with an image signal of one horizontal period, an enlarged display twice as large in the vertical direction can be realized.

Also, the reason why the timing of the image signal applied to the pixels in the -th row is delayed from the first horizontal scanning period in the normal display to the 63rd horizontal period in the enlarged display by the delay circuit 58 in FIG. This is for enlarging and displaying the central part of the image.

Next, the horizontal scanning clock generation operation shown in FIG. 3 will be explained.

When performing normal display, the signal waveforms of each part are as shown in FIG. 4, and the changeover switch 403 is connected as shown in FIG. The clock waveform (GK) obtained by the PLL 55 is frequency-divided by 6 by a frequency divider 532 with reset and a frequency divider 533 with reset, and an output signal waveform (q5) with a duty ratio of 50% is obtained. 3 divider 5
Both the 32°2 frequency divider 533 and the frequency divider 5 in the PLL 55
The output waveform (q
5) is synchronized in phase with the horizontal synchronization signal.

Latches 541, 542, and 543 whose data changes at the rising edge of the clock waveform (CK) and which are connected in cascade
Among them, the first stage latch 541 has the above-mentioned output signal waveform (
q5), one cycle of the clock waveform (CK) (
A clock waveform (ul) delayed by a time corresponding to one pixel in normal scanning.

(u2) and (u3) are obtained.

Furthermore, the data changes at the rising edge of the clock waveform obtained by inverting the clock waveform (CK) by the inverter 561, and the latches 544 and 545 are connected in cascade.
, 546, the previous clock waveforms (ul), (u2), (u
3), clock waveforms (u4), (u5), and (u6) each shifted by 1.5 cycles of the clock waveform (CK) are obtained.

The changeover switch 402 divides the horizontal synchronization signal into a 2-frequency divider 534.
Even the signal whose frequency is divided by 2 is controlled.

Therefore, in horizontal scanning synchronization, the changeover switch 402 is connected as shown in the figure, and the clock waveform (ul),
(u2) and (u3) are connected to the horizontal scanning clock input terminals 691, 693, 695 through the changeover switches 402, 403.
At the same time, the inverters 562, 563, 5
64, their inverted waveforms (vl), (v2), (v
3) and horizontal scanning clock input terminals 692, 694.
696. In this way, the clock signal is supplied to shift registers 211 and 221 in FIG. 2 as a six-phase horizontal scanning clock. Also, at this time, shift registers 211 and 22
A horizontal scanning start signal waveform (Sh) is applied to horizontal scanning start signal input terminals 697 and 698 of No. 1.

In the next horizontal scanning period, the changeover switch 402 is connected in the opposite way to that shown, and the clock waveform (u4) is generated.

(u5) and (u6) are selector switches 402 and 403
through horizontal scanning clock input terminals 691, 693.6
95 and at the same time, inverter 562.563
, 564, their inverted waveforms (vl'), (
v2') and (v3') are obtained and applied to horizontal scanning clock input terminals 692, 694, and 696. In this way, the clock signal is supplied to shift registers 211 and 221 in FIG. 2 as a six-phase horizontal scanning clock. At this time, the horizontal scanning start signal waveform (sh'
) is applied.

In this way, every l horizontal scanning period, the shift register 21
The reason for shifting the 6-phase horizontal scanning clock applied to 1 and 221 by 1.5 pixels of the clock waveform (CK) is that the pixel arrangement on the matrix display panel 12 in FIG. 2 is 1.5 pixels per row.
This is to cope with pixel misalignment and improve horizontal resolution.

Note that in order to make the pixel arrangement correspond to the phase shift of the horizontal scanning clock, the frequency divider 5 (not shown in FIG. 3) is
34 needs to be reset with a signal synchronized with the vertical scanning start signal.

Next, a case where double enlarged display is performed will be described. When performing double enlarged display, the signal waveforms of each part are as shown in FIG. 5, and the changeover switch 403 is connected in the opposite way to that shown in FIG. In this case, considering that the magnification is doubled not only in the horizontal direction but also in the vertical direction, pixels in adjacent rows whose pixel arrangement is shifted are driven with the same image signal, so the entire horizontal scanning period is , the phase of the horizontal scanning clock is constant.

Output signal waveform (ql) of the 3 frequency divider 532 with reset,
(q2) are respectively input to the clock f548, 547 whose data changes at the rising edge of the clock waveform obtained by inverting the clock waveform (CK) by the inverter 561, and the output signal is delayed by approximately half a cycle of the clock waveform (OK). Waveform(
q3).

(q4) is obtained. These waveforms (ql), (q2),
(q3), (q4), OR gates 565, 56
6.567, the clock waveform (GK
) is defined as one period, and the clock waveform (GK
) clock waveforms (hl) and (h
2), (h3) are obtained and applied to the horizontal scanning clock input terminals 691, 693, 695 through the changeover switch 403, and at the same time, their inverted waveforms (v1), (v2), (v3) and horizontal scanning clock input terminals 692, 694, 69
6. In this way, a clock with twice the frequency as in the normal display is transmitted to the shift register 21 in FIG.
1 and 221 as a six-phase horizontal scanning clock. Further, at this time, a scan start signal waveform (sh) is applied to the horizontal scan start signal input terminals 697 and 698 of the shift registers 211 and 221.

In this way, the horizontal scanning circuit 21 uses both the rising and falling edges of the clock waveform obtained by multiplying the horizontal synchronization signal.
By forming a horizontal scanning clock of 22 and 22, half the number of multiplication is required compared to a control section that uses only the rising edge of the clock waveform, so there is an advantage that a more stable PLL can be formed relatively easily.

As described above, the embodiment shown in FIG. 1 has the advantage of being able to easily switch between good normal display and enlarged display using a matrix color panel.

In the waveform example shown in FIG. 7, it is assumed that the vertical direction is doubled, but the normal vertical scanning clock and the double enlarged vertical scanning clock are alternately switched every horizontal scanning period by the switch 401. By switching, the display can be enlarged 1.5 times, and by switching only one horizontal scanning period out of 3 horizontal scanning periods to the double enlarged vertical scanning clock and the rest to the normal vertical scanning clock, the display can be enlarged 1.33 times. The enlarged display of
In addition, if only one horizontal scanning period out of four horizontal periods is switched to a 2x enlarged vertical scanning clock and the rest to a normal vertical scanning clock, 1.25x enlarged display becomes possible, and enlarged display at any magnification. becomes possible.

Therefore, when displaying a PAL signal with approximately 280 effective scanning lines in the field on a liquid crystal panel with 280 pixels in the vertical direction, non-enlarged display is performed using a vertical scanning clock equal to the horizontal scanning period, and the effective scanning line in the field is Number of lines: approximately 240
When displaying TD NTSC signals, 5 horizontal scanning periods are used as a unit, and 4 horizontal scanning periods remain for non-enlarged display.
By outputting two vertical scanning clocks in the horizontal scanning period, vertically enlarged display is performed, and images can be displayed with the correct aspect ratio without any screen defects for both PAL and NTSC signals. Of course, it is clear that if a triple magnified vertical scanning clock having a frequency three times that of the normal vertical scanning clock is provided as the vertical scanning clock, a triple magnified display can be achieved.

By the way, in this embodiment, the matrix display panel 1
Each pixel of 2 is connected to a transistor 1 as shown in FIG. 2A.
21, an additional capacitor 122 formed between the transistor 121 and the previous scanning electrode, and a pixel electrode 123 for driving a liquid crystal element (not shown). Therefore, there were problems as described below.

Incidentally, here, the first
Transistor 1 whose gate is connected to the row scan electrode XI
21 and the pixel including the transistor 121 are not formed because there is no scanning electrode in the previous stage and the additional capacitor 122 cannot be formed.

FIG. 8 is a waveform diagram showing an example of the waveform of each part signal in FIG. 2A.

An image signal shown in the waveform (Yl) is applied to the signal electrode Yl, and waveforms (Xi) and (X2) are applied to the scanning electrodes XI and X2, respectively.
) are sequentially applied, the transistor 121 whose drain is connected to the signal electrode Yl and whose gate is connected to the scanning electrode
) is obtained.

At this time, the scanning electrode x2 is at the selection voltage ■. . Immediately before , the transistor 121 is off, and the scanning electrode
1 is superimposed on the voltage waveform of the pixel electrode 123 through the additional capacitor 122 (shaded portion of the waveform (g)). This voltage change amount ΔVC is
Selection voltage V CON of scanning electrode XI, non-selection electrode ■G
OFF, the capacitance C1□ of the additional capacitor 122, and the parasitic capacitance CLC connected to the pixel electrode 123, such as the liquid crystal cell capacitance or the parasitic capacitance of a transistor, is expressed as follows.

Taking a 5-inch NTSC liquid crystal television (horizontal 480 pixels, vertical 240 pixels) as an example of a matrix type display device, C, +, += 1.7 p F, Ct, c
=0.3pF, (VCON VCOFF) = 25
ΔVc=21V, which is a large value. Therefore, the period T during which ΔVc is superimposed is one field T
1/Medium During normal display, 1 horizontal period (~Tv/2
62), which is small, but it is a value that cannot be ignored as an increase in the effective value voltage of waveform (g). This effective value increase ΔV r
m s is obtained by calculating the effective value of the waveform (g), and in the above case, it becomes about 0.2 to 1 V.

This means that if the selection times for one row are different, the effective value increment ΔV ram will be different, resulting in a change in brightness on the display screen. In the embodiment shown in FIG. 1, the delay circuit 59 and the OR circuit 57 select each row twice during double enlarged display, so that the selection time for each row in each field is the same between normal display and enlarged display. The above luminance change was prevented.

However, as described above, such measures are difficult when displaying an image at a magnification other than 2 times, such as 1.5 times, or when images have low correlation in the vertical direction. At this time, the delay circuit 59 and OR circuit 57 in FIG. 1 were omitted, and a brightness correction circuit 71 was provided before the polarity inversion circuit 7. The configuration shown in FIG. 9 is desirable. A specific configuration in which the luminance correction circuit 71 and the polarity inversion circuit 7 are combined is shown in FIG.

In FIG. 1O, 75, 76, and 77 are DC regeneration polarity inverting circuits, respectively, consisting of a DC regeneration circuit consisting of a capacitor 436 and a clamp switch 432, and a polarity inversion circuit consisting of a transistor 437 and resistors 448 and 449. It consists of a circuit. Here, the clamp switch 432 is conductive during the blanking period or pedestal period of the image signal, and the image signal during those periods is set as the potential of the reference voltage generation circuit 78, thereby realizing DC reproduction of the image signal. . Note that as the clamp switch 432, for example, a diode, a transistor, an analog switch, or the like is used.

Three primary color signals as image signals are applied to the terminals 651, 652, and 653, respectively, and the DC reproduction polarity inversion circuit 75
, 76, 77, switches 433, 434, 4
35 switches the polarity at a constant cycle, and then 3
Applied to primary color signal input terminals 661, 662, 663,
Sample hold circuit 2 of horizontal scanning circuit 2 shown in FIG.
02.

Reference numeral 78 denotes a reference voltage generation circuit that provides a DC level for the DC regeneration circuit, which includes a constant current source 440, a variable resistor 442 for adjusting overall brightness, 3 variable resistors 445 and 446 for correcting brightness variations between primary color signals. 447, a brightness correction switch 431 during enlarged display, and a resistor 441. A potential difference is generated across the variable resistors 445, 446, and 447 by multiplying the parallel combined resistance value and the current value of the constant current source 440, and within the range of this potential difference, brightness variations among the three primary color signals are corrected. are doing.

The variable resistor 442 is for adjusting the overall brightness, and by changing the resistance value, the variable resistors 445, 446,
447 intermediate tap voltages are changed simultaneously. At this time, since the constant current source 440 is used, the variable resistor 442
No matter how the value of changes, the variable resistors 445, 446
, 447 do not change, allowing stable brightness adjustment.

The switch 431 is turned off during normal display and turned on during enlarged display, and the potential difference obtained by multiplying the resistance value of resistor 441 by the current value of constant current source 440, and the variable resistor 445 during enlarged display compared to normal display. ,446,447
By raising the intermediate tap voltage of the transistor 437 and the base voltage of the transistor 437, etc., the polarity inverting circuit 75
, 76°77, the voltage amplitude between the positive polarity and negative polarity signals is increased to perform brightness correction.

In this way, in the embodiment of FIG. 9, when performing enlarged display, the switch 43 is
1, no change in brightness occurs on the display screen when switching between normal display and enlarged display.

By the way, when using an active matrix type liquid crystal display panel as a matrix display panel, the liquid crystal element must be driven with alternating current. At this time, in order to reduce the flicker level, it is advantageous to invert the polarity of the image signal applied to the pixels for each row.

In the embodiment of FIG. 1 or FIG. 9, the signal waveform (a) output from the horizontal scanning circuit 2 to the signal electrode, respectively.
is changed every horizontal scanning period, so in the case of normal display (non-enlarged display), in order to invert the polarity of the image signal added by the pixels for each row, for example, the waveform example shown in Fig. 6 is used. Thus, it is sufficient to simply invert the polarity of the image signal itself input to the horizontal scanning circuit 2 every horizontal scanning period.

However, in the case of enlarged display, for example, as shown in the waveform example in FIG. 7, the polarity is reversed every two lines, and flicker may become more noticeable. Furthermore, in the waveform example shown in FIG. 7, in both the first field and the second field, the combination of two lines driven by the image signal during the horizontal scanning period is fixed, and interlaced scanning, which is a characteristic of television signals. The effect of vertical resolution improvement cannot be expected.

Therefore, FIG. 11 shows an example of the configuration of a display device that can invert the polarity of the image signal applied to the pixels for each row even in the case of enlarged display.

25 simultaneously samples positive and negative polarity image signals within one horizontal scanning period, and outputs them to the train bus in the first and second half of the next horizontal scanning period, respectively. This is a double-speed line sequential scanning circuit, and a specific example of its configuration is described in detail in Japanese Patent Application Laid-Open No. 63-26084, which was proposed by the present inventors, so a detailed explanation will be omitted.

FIG. 12 shows an example of the operating waveforms of the embodiment shown in FIG. 11. (a
) is the output of the horizontal scanning circuit 25, that is, the liquid crystal panel 1
2, and (b) is the waveform of the train bus at input terminal 6.
13 is an enlarged control signal waveform given to 13.

A clock with twice the horizontal scanning frequency is connected to the terminal 610.
For example, a control signal applied from the PLL 55 shown in FIG. 3 and frequency-divided by a quarter period 535 controls a sample-and-hold circuit in the horizontal scanning circuit.

That is, focusing on the output Y1 of the first grain, in the first horizontal scanning period, the sample and hold circuits H8 and H sample the green positive polarity G+ and green negative polarity G- signals, respectively. If the switch 406 is in the illustrated state at this time, the logic circuit 236
The switch SA is selected, and the green positive polarity G1+ of the first horizontal scanning period is output. Meanwhile, sample and hold circuits Hc and HD start sampling operations. In the third horizontal scanning period, the logic circuit 236 causes the switch SD
is selected, and the green negative polarity G, - of the second horizontal scanning period is output. At the same time, sample and hold circuits HA and H8 start sampling operation again.

In this way, the horizontal scanning circuit 23 obtains an output waveform similar to that of the horizontal scanning circuit 21 in FIG. 2.

In the fourth horizontal scanning period, the enlargement control signal (b) is
When the signal becomes HIf, the switch 406 and the switch 401 are reversely connected, and a signal with twice the frequency of the normal display is given to the logic circuit 236 and the vertical scanning circuit 3. Therefore, the logic circuit 236 selects switch SA during the first half of the fourth horizontal scanning period and selects switch SB during the second half.
During this horizontal scanning period, green positive polarity G3+ and green negative polarity G, - signals of the third horizontal scanning period are transmitted to the horizontal scanning circuit 23.
is obtained as the output of This is called double-speed line sequential scanning.

In this manner, according to the embodiment shown in FIG. 11, even in enlarged display, polarity reversal driving for each row is possible, so that good image display with less flicker can be obtained.

Furthermore, as shown in the operational waveform example of FIG. 12, in the waveform of the second field indicated with a dash ('),
By shifting the interval between the enlargement control signal (b) and the vertical scanning start signal (c) by one horizontal scanning period, in enlarged display,
Since interlaced scanning can be realized, there is an advantage that vertical resolution can be improved.

Next, FIG. 13 shows a display section of a matrix type display device as yet another embodiment of the present invention.

This embodiment differs from the embodiment shown in FIG. The second point is that double-speed linear sequential horizontal scanning circuits 23 and 24 are provided that can drive two rows of pixels in one horizontal scanning period of the image signal, and secondly, the voltage applied to all scanning electrodes in the vertical scanning circuit 33 is is set to the non-selection voltage V all at once regardless of the output state of the shift register 301. AND gate 331 to turn OFF
The point is that it has been established.

Now, the operation of the display section of this embodiment will be explained.

14 is a waveform diagram showing an example of the waveform of each part signal during normal display in FIG. 13, and FIG. 15 is a waveform diagram showing an example of the waveform of each part signal during enlarged display in FIG. 13.

First, the operation during normal display will be explained using FIG. 14.

During normal display, the double-speed line sequential scanning circuits 23 and 24 sample the image signals to be applied to pixels in two rows during one horizontal scanning period using sample and hold circuits 232 and 233, and convert them into waveforms (a) and (a+). As shown, (2) the signal is output to the signal electrodes in the first half and the second half of the horizontal scanning period to perform double-speed line sequential scanning. At this time, matrix display panel I
In 3, since the horizontal positions of two adjacent rows of pixels connected to the same signal electrode are shifted by 1.5 pixels, it is necessary to sample the image signal at a timing shifted by 1.5 pixels in the sampling. There is.

Therefore, shift registers 231 and 241 have twice as many outputs as shift registers 221 and 211 in FIG. 2.

In the waveform (a), Sl is the image signal sampled in the first horizontal scanning period and given to the pixel selected by the scanning electrode X2 in the second row, and S1τ is the image signal sampled at a timing 1.5 pixels later than that. (Actually, there is no pixel to which an image signal is written by the first row scan electrode XI.)
Each represents the image signal given to the . Similarly,
In waveform (a'), S81. S3.4τ is the image signal given to the pixel selected by the second row scan electrode
The image signals provided by the pixels selected from the scanning type iX3 in the row are respectively shown.

On the other hand, when a vertical scanning clock waveform (f) having a period half of one horizontal scanning period is applied to the terminal 605 and a vertical scanning start signal waveform (c) is applied to the terminal 601, the shift register 301
The output of is the waveform (Xi).

Selection signal waveforms indicated by (X2), . . . shifted by half the horizontal scanning period are sequentially obtained. During normal display, if HIT is sent as a control signal to the terminal 608.
When the level is given, the selection signal waveform is sequentially applied to each scanning electrode Xi, X2°, etc. by the vertical output circuit 302, and each pixel is driven by the image signal output to each signal electrode. Ru.

In the next field, interlaced scanning is performed by shifting the combinations of two rows of pixels driven by image signals of the same horizontal scanning period. The waveform example at this time is the 14th waveform example.
The waveforms are shown with a dash (') in the figure.

In addition, in this way, using the image signal of the horizontal scanning period,
A method of driving pixels in a row and an example of a double-speed line sequential scanning circuit used therefor are described in the above-mentioned Japanese Patent Laid-Open No. 63-2608.
It is detailed in Publication No. 4.

Next, the operation during enlarged display will be explained using FIG. 15.

The waveform during enlarged display differs from the waveform during normal display. Firstly, the vertical scanning clock waveforms (f) and (f') applied to the terminal 605 have a double pulse at the beginning of each horizontal scanning period. is inserted, and secondly, the terminal 601
The vertical scanning start signal waveform (c) applied to the
The output signal waveforms of the shift register 301 are (XI), (X2), etc.
* is a double pulse, and thirdly, the terminal 60
8, the control signal waveforms applied to the horizontal scanning circuits 23 and 24 are waveforms (m) and (m') without "H" level, and fourthly, the output signals of the second field in the horizontal scanning circuits 23 and 24. The waveform (a') is the first field output signal waveform (a)
Similarly, the sampling timing of the image signal output in the first half of each horizontal scanning period is delayed by 1.5 pixels than the sampling timing of the image signal output in the second half.

When performing enlarged display, the input of the vertical output circuit 302 is the output signal waveform (Xl), (X2) of the shift register 301.
, ...... and the control signal waveform (m), A
Since it was taken at the ND gate 331, the second
Each scanning electrode is selected at the timing indicated by diagonal lines in FIG. Therefore, for example, in the first half of the 62nd horizontal scanning period, the pixels connected to the scanning electrodes x1 and X3 are
Pixel signal S sampled in the 61st horizontal scanning period,
8τ, and in the second half of the 62nd horizontal scanning period,
Pixels connected to scanning electrodes X2 and x4 are driven by an image signal s6° sampled in the 61st horizontal scanning period. Therefore, since four rows of pixels are driven by an image signal of one horizontal scanning period, the vertical magnification is doubled compared to normal display in which two rows of pixels are driven by an image signal of one horizontal scanning period. It will be displayed.

Furthermore, by shifting the combination of four rows of pixels driven by image signals of one horizontal scanning period by two rows for each field, interlaced scanning can be performed in the same way as in normal display.

Note that, if the display is to be enlarged twice in the horizontal direction, it is obvious that the frequency of the horizontal scanning clock should be doubled.

Next, as mentioned above, the sampling timing of the first half output and the second half output of each horizontal scanning period is equal in the first field and the second field in the enlarged display, and can be changed in the first field and the second field in the normal display. .

The first example is a double-speed linear sequential scanning circuit and its peripheral scanning circuit.
It is shown in Figure 6 and Figure 17. Both the embodiments shown in FIGS. 16 and 17 have substantially the same configuration as the double-speed line sequential scanning circuit shown in FIG. 11 described above.

In the embodiment shown in FIG. 16, the shift register 231 outputs a number of outputs Q I I Q @ IQ5 . approximately equal to the number of lines of the drain bus drawn out from above the liquid crystal panel 13 .・
...and outputs Q1τ, Q, τ whose phases are shifted from the above outputs according to the pixel positions of odd and even rows.

······have. The switches 407 and 408 are controlled as follows by a control circuit 537 having a field discrimination signal input terminal 621 and a normal display/enlarged display instruction signal input terminal.

The switch 407 is connected as shown in the diagram for all fields during enlarged display and the first field during normal display, and by making the connection opposite to that shown in the diagram only for the second field during normal display, the condition regarding the sampling timing shift is satisfied. be able to.

Furthermore, in the embodiment shown in FIG. 16, the alternating signal applied to the logic circuit 236 is switched by a switch 408 in order to facilitate alternating the video signal applied to each pixel.

Note that the switching is such that the connections shown in the figure are made for all fields during normal display and the first field during enlarged display, and only the second field during enlarged display is connected in the opposite manner to that shown.

The embodiment shown in FIG. 17 is an example realized using a shift register 251 that does not have an output corresponding to a phase shift, and 72 is a delay that delays the video signal according to the pixel positions of odd and even rows. The circuit 73 is a polarity inversion circuit that inverts the polarity every horizontal scanning period or every field.

In the embodiment shown in FIG. 17, the switch 408 is connected as illustrated in all fields during enlarged display and the first field during normal display, and only the second field during normal display is connected in the opposite manner to the one shown in the figure, thereby making it possible to The conditions regarding timing deviation can be satisfied.

FIGS. 18 and 20 are control circuit diagrams for forming various control signals used in the configuration of the embodiment shown in FIG. 13, and FIGS. 19 and 21 are examples of the control circuits shown in FIGS. 18 and 20, respectively. FIG.

In the control circuit of FIG. 18, compared to the control circuit of FIG. 3, the phase shift circuit 53 and switch 402 are omitted, and the double clock (15
In order to form the diagram (f)), delay circuits 571, 572,
573, 574 and logic circuits 576, 577, 578,
Further, a delay circuit 575 and a logic circuit 579 are arranged to form a vertical scanning circuit mask signal (FIG. 15(m)).

Next, the operation of the control circuit shown in FIG. 18 will be explained using the example of operation waveforms shown in FIG. From the PLL 54, a signal waveform (e) having a frequency twice the horizontal scanning frequency is output to the frequency divider 531.
A signal waveform (d.) of the horizontal scanning frequency is obtained. This waveform (d.) is processed by delay circuits 571 to 574,
Delayed waveform (d,), (d,), (d,)
, we get (d,).

At this time, waveforms (d, , ), (d, , ), and (g) are obtained from the outputs of the logic circuits 576, 577, and 578, respectively. This waveform (g) is an enlarged vertical scanning clock waveform, which is appropriately switched from the normal vertical scanning clock signal by the switch 401, and is applied to the vertical scanning circuit.

On the other hand, the waveform (e) is input to the delay circuit 575 and the time D
The waveform (h) is delayed by M, and the logic circuit 579 obtains a mask waveform (m) for the vertical scanning circuit with a pulse width DM.

At this time, the total delay time of delay circuits 571 to 574 is equal to the total value.

Between them, the relationship Do≦DM is required.

FIG. 20 shows the vertical scanning circuit 33 of FIG. 13 during enlarged display.
21 shows an example of a control circuit that forms a signal to be applied to the vertical scanning start signal input terminal 601, and FIG. 21 shows an example of its operating waveform.

590 generates a field discrimination signal (fl) and a vertical scanning start signal (for normal display) from a horizontal synchronizing signal applied to a terminal 606 and a vertical synchronizing signal applied to a terminal 607.
sn), 580 is a delay circuit, 58
1 is a shift register, 582 to 585 are logic circuits, 58
6 is a latch, and 404 and 405 are switches.

The enlarged vertical scanning clock waveform (f) shown in FIG. ) is given to the shift register 581,
Waveform (S,).

(S,), (S,), (S,), (S,), (S,).

are obtained one after another. At the time of enlarged display, the switch 404 is connected in the opposite direction to that shown in the figure, and in the first field,
The switch 405 is connected as shown in the figure, and the waveform (S26) obtained from the logic circuits 582 and 583 is given to a latch 586 whose clock is an inverted waveform of the extended vertical scanning clock, and the extended vertical scanning start signal (C ) is obtained.

In the second field, the switch 405 is connected in the opposite direction to that shown in the figure, and the waveform obtained by the logic circuit 584 (33
5') is applied to latch 586, and an enlarged vertical scan start signal (C'') is obtained.

As described above, according to the control circuit examples shown in FIGS. 18 and 20, it is possible to easily obtain a good enlarged display using the matrix display device shown in FIG. 13.

Further, by incorporating such a control circuit into an IC (integrated circuit), enlarged display can be easily realized.

[Effects of the Invention] According to the present invention, a general and simple vertical scanning circuit (
For example, an image can be enlarged and displayed using a circuit configured by a combination of a simple shift register and a vertical output circuit, and an arbitrary enlargement magnification can be set.

Further, according to the present invention, it is also possible to perform enlarged display in color, or to reduce the difference in brightness between displayed images during normal display and during enlarged display.

Furthermore, when the matrix type display device according to the present invention is applied to a color television, a display, or an electronic viewfinder, there is an effect that a new added value of an enlarged display function can be added to them.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a matrix type display device as an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the matrix display panel and scanning circuit portion in FIG. 1, and FIG. 2 is an enlarged view showing a part of the matrix display panel, FIG. 3 is a block diagram showing a specific example of the control circuit part in FIG. 1, and FIGS. 6 and 7 are waveform diagrams showing examples of waveforms of each part signal in normal display and enlarged display, respectively, of each part signal in Fig. 2. 8 is a waveform diagram showing an example of the waveform of each part signal in FIG. 2A, FIG. 9 is a configuration diagram showing a matrix type display device as another embodiment of the present invention, and FIG. FIG. 11 is a circuit diagram showing a specific configuration of the luminance correction circuit provided in the embodiment shown in the figure, FIG. 11 is a configuration diagram showing a matrix type display device as another embodiment of the present invention, and FIG.
FIG. 13 is a waveform diagram showing an example of the waveform of each part signal in the figure. FIG. 13 is a configuration diagram of a matrix display panel and a scanning circuit portion showing another embodiment of the present invention. FIG. 13A is a waveform diagram of the matrix display panel in FIG. 13. An enlarged view showing a part enlarged,
FIG. 14 and FIG. 15 are waveform diagrams showing examples of waveforms of each part signal in FIG. 13 during normal display and enlarged display, respectively;
16 and 17 are circuit diagrams showing specific configuration examples of the double-speed line sequential scanning circuit in FIG. 13, respectively, and FIG. 18 and FIG. FIGS. 19 and 21 are waveform diagrams showing one waveform example of each signal in FIGS. 18 and 20, respectively. 1.12.13...Matrix display panel, 2,21
．． 22, 23, 24.25...Horizontal scanning circuit, 3°3
3... Vertical scanning circuit, 51... Control circuit, 55...
・PLL, 71... Brightness correction circuit, 121... Transistor, 122... Additional capacitor, 201, 211,
221゜231.241,251,301,581...
・Shift register 202, 212, 222, 232, 2
42, ) (A, HPI, Hc, Ho, - sample hold circuit, 302... vertical output circuit, 401,
402゜403.404,405,406,407,4
08.432. ...Switch, 58,59,571゜572.573,574,575...Delay circuit, 52
．． 54.55... Branch circuit, 53... Phase shift circuit. 537... Field discrimination circuit. Shima 2 Tubei 4 Kunimu 5 Figure (sh) Defu Otsu 8] 47 Figure 2 Yasu 8YilJ Kuzu IO Figure $ l1 Figure Kuzu /2 1Z $ 14 Hou Nihai /7 Eisan /wo ni s 20 Figure $ 21 Figure

Claims (1)

[Claims] 1. A horizontal scanning circuit that samples a plurality of primary color image signals based on the timing of an input horizontal scanning clock and sequentially supplies the signals to a plurality of signal electrodes extending in the vertical direction; a vertical scanning circuit that sequentially supplies a selection signal to a plurality of scanning electrodes extending in the horizontal direction based on the timing of a vertical scanning clock; are respectively connected to signal electrodes and scanning electrodes that intersect with each other, and capture the primary color image signals obtained from the connected signal electrodes by the selection signals obtained from the connected scanning electrodes;
a plurality of display elements driven by the captured primary color image signals, and a matrix type display device capable of enlarging and displaying an image obtained by the image signals using the plurality of display elements, a normal display At the time, the clock of the horizontal scanning clock supply circuit equipped with a phase shift circuit that converts the phase amount with respect to the horizontal synchronization signal every horizontal scanning period is selected, and when the display is enlarged, the horizontal scanning with a fixed phase relative to the horizontal synchronization signal is selected. 1. A matrix type display device comprising a switch for selecting a clock of a clock supply circuit and, during enlarged display, selecting a clock of a horizontal scanning clock supply circuit having a phase fixed with respect to a horizontal synchronization signal. 2. A horizontal scanning circuit that samples an image signal based on the timing of an input horizontal scanning clock and sequentially supplies it to a plurality of signal electrodes extending in the vertical direction; , a vertical scanning circuit that sequentially supplies a selection signal to a plurality of scanning electrodes extending in the horizontal direction, and a matrix type display device having a display element arranged at the intersection of the signal electrode and the scanning electrode, in which a vertical scanning clock frequency changeover switch is provided. At the same time, in conjunction with the switch, a signal that passes through a delay circuit provided in the vertical scanning start signal forming circuit and a circuit that forms the logical sum of the input/output signals of the delay circuit and a signal that does not pass are switched, thereby starting the vertical scanning. A matrix type display device characterized by input to a circuit. 3. A horizontal scanning circuit that samples image signals and sequentially supplies them to a plurality of signal electrodes extending in the vertical direction based on the timing of an input horizontal scanning clock; In a vertical scanning circuit that sequentially supplies selection signals to a plurality of scanning electrodes extending in the horizontal direction, and in a matrix type display device in which a display element is arranged at the intersection of the signal electrode and the scanning electrode, the vertical scanning circuit supplies all the scanning electrodes. It has a control input terminal that is set to a non-selected state, and has a circuit that superimposes a pulse having a pulse width of 1/8 or less of the period of the vertical scanning clock on the vertical scanning clock during normal display, and the period during which the superimposition is performed. more than the time,
A matrix type display device, characterized in that a signal is applied to the control input terminal to set all scanning electrodes to a non-selected state. 4. A horizontal scanning circuit that samples an image signal based on the timing of an input horizontal scanning clock and sequentially supplies it to a plurality of signal electrodes extending in the vertical direction; , a vertical scanning circuit that sequentially supplies a selection signal to a plurality of scanning electrodes extending in the horizontal direction, and a matrix type display device having a display element arranged at the intersection of the signal electrode and the scanning electrode. A vertical scan changeover switch that switches a clock and outputs it as the vertical scan clock to the vertical scan circuit, and a brightness correction circuit that corrects the brightness of the image signal, and the vertical scan clock changeover switch changes the frequency of the vertical scan clock. By switching, the image can be enlarged and displayed at least in the vertical direction, and the correction operation performed by the brightness correction circuit can be performed in synchronization with the switching of the vertical scanning clock during non-enlarged display (normal display). A matrix type display device characterized in that the display is different between the display mode and the enlarged display mode. 5. The control circuit for a matrix display device has a PLL circuit that multiplies the horizontal synchronizing signal, and a divided second clock obtained by inputting the first clock formed by the PLL circuit to a frequency divider. and a third clock whose phase is shifted, which is obtained by inputting the second clock into a phase shift circuit (delay circuit), are switched every horizontal scanning period to form a fourth clock; A control integrated circuit having a circuit that outputs a divided fifth clock obtained by further inputting the first clock to another frequency divider, and a fourth clock that are switched by an enlarged display signal switching signal. 6. In a control circuit for a matrix display device capable of enlarged display, a vertical scanning start signal during non-enlarged display (normal display) is input to a first delay circuit, and the output of the first delay circuit is input to a second delay circuit. What is claimed is: 1. A control circuit that outputs a waveform obtained by inputting the outputs of the first delay circuit and the second delay circuit to the logic circuit as a vertical scanning start signal during enlarged display. 7. In a matrix display device capable of enlarged display, in a horizontal scanning circuit that samples an image signal and supplies it to a plurality of signal electrodes in a matrix display panel based on the timing of an input horizontal scanning clock, the horizontal scanning circuit is characterized in that it has a plurality of sample and hold circuits per output, and the order of reading from the sample and hold circuits is determined by a logic circuit that receives a field discrimination signal and a signal specifying enlarged/non-enlarged display. Horizontal scanning circuit and its control circuit.