JP2646523B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device between a substrate on which a column electrode is formed and a counter substrate on which a plurality of pixel electrodes selected by a common electrode or a row electrode orthogonal to the column electrode are formed. The present invention relates to an image display device using a liquid crystal interposed between the image display devices.

[Conventional technology]

As shown in FIG. 2, a conventional image display device has a D (1)
A substrate formed with a plurality of column electrodes indicating the connection terminals, potentials to D (N), a liquid crystal display body sandwiched between the opposed substrate formed with the common electrode of an electrode terminal and potential at V _C (6) The data to the column electrodes is serially transferred by the shift register (5) at the clock CL with the data D, and the data D (1) to
After a group of data transfer corresponding to D (N) is completed, the shift register is kept stationary for a certain period of time, and a parallel output of each bit is added to D (1) to D (N).

V _DD , V _SS (V _DD > V _SS ) are the power supply terminal and potential of (5), and D (J) − applied to the pixel of (6) after transferring data D at V _C = V _SS. V _C voltages (J = 1 to N), the next V _C = V
_{In the DD} frame, the sign is inverted by transferring the inverted data from the previous frame, and the AC driving of the liquid crystal is performed.

[Problems to be solved by the invention]

Therefore, the voltage applied to the pixel is displayed (lit).
There are problems in the configuration in which only two values, that is, erased and non-illuminated, are provided, and changing the voltage to realize a display with light and shade gradations.

[Means for solving the problem]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and is an image display device including an active element and a display using liquid crystal, wherein a matrix is arranged such that a row electrode group and a column electrode group are orthogonal to each other. Active elements are provided corresponding to the matrix of row electrodes and column electrodes, pixel electrodes and common electrodes facing the pixel electrodes are provided, liquid crystal is sandwiched between the opposing substrates, and connected to the column electrodes. The digital / analog converter includes a decoder, a voltage dividing circuit, and a switch, and one of the first power supply terminal and the second power supply terminal of the voltage dividing circuit is made equal to the potential of the common electrode. A voltage between these two power supply terminals is set as a reference voltage, and a connection point is provided for outputting the potential adjusted to the optical characteristics of the liquid crystal by dividing the reference voltage by a resistor. The switch is located in Digital image data composed of n bits per bit is supplied to a digital / analog converter through a shift register and a latch, passes through a decoder, is converted into a decoder output for each column, and switches are controlled by the decoder output to connect. Either of the potentials at the points is selected as analog image data and sent to the column electrodes, and the polarity of the reference voltage is inverted at a predetermined cycle with respect to the potential of the common electrode, and the liquid crystal is AC driven, and 2 Provided is an image display device that performs ^n- gradation display.

FIG. 1 is a configuration diagram of an image display device of the present invention,
(1) is a shift register, (2) is a latch, (3) is a digital / analog converter, and (4) is a liquid crystal display.

(4) D (1) to D (N) (3) and connected to the substrate forming a plurality of column electrodes with the lead, between the opposed substrate formed with the common electrode of an electrode terminal and potential in V _C Data D (J) to the column electrodes (J = 1 to N)
Transfers the data D ₀ , D ₁ , D ₂ in series with the clock CL according to (1), and transfers D ₀ ^S (1), D ₁ ^S (1), D ₂ ^S (1) to D ₀ ^S (N ), D
After ending a group of data transfer corresponding to ₁ ^S (N) and D ₂ ^S (N), the output of each bit of (1) is changed to a write enable signal W
Is written in parallel to (2), and the output D ₀ (J), D of (2)
₁ (J), D ₂ (J) (J = 1 to N)
It is obtained by analog conversion.

V _DD and V _SS (V _DD > V _SS ) are the power supply terminals and potentials of (1) and (2), and V _CC is set to V _CC ≦ _VSS, and the power supply terminal of (3) together with V _DD · become potential, V _R is the reference voltage input of defining the analog output with respect to the common electrode potential V _C of (4) (3).

[Action]

In the present invention, a voltage between terminals between the first power supply terminal and the second power supply terminal of the voltage dividing circuit is a reference voltage, and this reference voltage is divided by a resistor to generate a potential adjusted to the optical characteristics of the liquid crystal. A connection point for outputting is provided, and the polarity of the reference voltage is inverted at a predetermined cycle with respect to the common electrode potential, so that the liquid crystal is AC-driven.

FIG. 3 is a timing chart showing the operation of a system for changing the sign of digital image data as a reference example. (1) is composed of three sets of shift registers to transfer D ₀ , D ₁ , D ₂ , CL reads D ₀ , D ₁ , D ₂ with V _SS , and reads data to the next stage with V _DD Has been transferred. D (J) is V _CC
To V _R , V _C alternately takes V _CC and V _R potentials for each frame, and D ₀ , D ₁ , and D ₂ are data inverted from the previous frame for each even frame , The digital inputs D ₀ (J), D ₁ (J), D ₂ (J) to (3) which are written in parallel to W and written in (2) by J (J = 1 to N)
Has become a value obtained by complementarily inverted value of the previous frame, since the output of the digital / analog converter is configured such that the inverted value of relative V _C in such an input conversion , the voltage D (J) -V _C according to the pixel is inverted is the immediately preceding frame and the code for each even frame, the AC driving of the liquid crystal have been made.

FIG. 1 shows an image display device of 8 gradations because digital / analog conversion of 3-bit data is performed. Generally, an image display of 2 ⁿ gradations by inputting n-bit data is performed. A device is obtained.

〔Example〕

Such an image display device of the present invention is applied to an image display device that drives liquid crystal using a plurality of transistors or active elements such as diodes formed on the same substrate as switches.

FIG. 4 shows a configuration of a pixel of an image display device driven by a transistor formed for each pixel.
J) to (I + 1, J + 1). (7) is a transistor, (8) is a storage capacity of a display voltage, (9)
Is a pixel electrode, (10) is a common electrode on the substrate facing (9), (11) is a liquid crystal, (12) is a row electrode for transmitting a gate signal, and (13) is a column electrode for transmitting a source signal. is there.

The transistor turned on by the gate signal G (I) transmits the source signals D (J) and D (J + 1) to each pixel electrode, and the voltage between (10) and the parallel capacitance of (8) and (11). It is stored as a display voltage, and an image is displayed at the stored voltage when the display is off.

And one electrode (8) (10) are connected in common, and it has become a potential of V _C, the gate-drain capacitance (8) and parallel capacitance (11) is (7) since sufficiently large, (9) (10) display voltage is arranged between the keep constant nearly independent between, on the potential change of V _C that transistor is off.

FIG. 5 is a configuration diagram of an image display device having the pixels shown in FIG. 4, and is an embodiment of the present invention. According to FIG. 1, (14) is a shift register, (15) is a latch, (16)
(17) and (18) constitute a digital / analog converter,
(20) indicates the pixels (7), (8), (9), and (1) shown in FIG.
2) Substrate and multiple common electrodes (1) are arranged in matrix so that row electrode group and column electrode group are orthogonal to each other.
A display body composed of liquid crystal (11) sandwiched between opposed substrates formed with (0), and (19) is a shift register that sends out a gate signal for sequentially turning on a transistor group connected to the same row electrode for each row. .

G (1) ~G (M) represents the connection terminal, the potential of the plurality of rows of the row electrode group _{(20), V G, V} EE (V G> V SS ≧ V EE) is (1
9) a power supply terminal, the potential of, and shifts the data D _G clock CL _G, have created a gate signal G (1) ~G (M) . Latch output D ₀ (J), D ₁ (J), D ₂ (J) (J = 1
To N) are d ₁ (J), d ₂ (J), d ₃ by the decoder (16).
_{(J), d 4 (J} ), d 5 (J), d 6 (J), d 7 (J), d
₈ (J) 8 outputs, connected to the potentials of V ₁ , V ₂ , V ₃ , V ₄ , V ₅ , V ₆ , V ₇ , V ₈ output from the connection point of the voltage dividing circuit (17) The analog image data D (J) to be sent to the source electrode of (20) is generated by controlling the switch (18) to be operated and selecting the potential.

The power supply for the digital / analog converter composed of (16), (17) and (18) is taken at V _CC = V _SS in FIG.
Divides the voltage between the V _R -V _C terminals with a resistor in accordance with the optical characteristics of the liquid crystal of (20). As shown in the timing chart of FIG. 6, the data D ₀ , D ₁ , and D ₂ are converted to the clock CL
Are transferred in series by D ₀ ^S (1), D ₁ ^S (1), D ₂ ^S (1)
To D ₀ pixels ^{_{S (N), D 1 S}} (N), after the end of the group of data transfer corresponding to ^{_{D 2 S (N), (}} 19) the gate signal line is V _G becomes the same row (20) Turn on the transistors in the group,
The output of each bit of (14) is written in parallel to (15) by the write enable signal W, and the outputs D ₀ (J), D
₁ (J), D ₂ (J) (J = 1 to N)
The analog converted data D (J) is stored in the pixel electrode through the column electrode.

Data of the next line while the gate signal of this line is in the V _G is transferred (14), the transistor of the pixel group of the row gate signal becomes V _EE is turned off, the gate signal of the next line is V When made of _EE in V _G write out the next write enable signal output (14) to (15), (16) (17) (18)
Is transmitted to the pixel. Such a sequence is repeated M times by the gates of G (1) to G (M), and the display voltage of all pixels of (20) is determined in one frame.

In this embodiment, the data cycle to the pixels is one frame in which various display data is stored in all pixels, one frame in which uniform erase data is stored in all pixels, and display data which is symmetrically inverted with respect to the data based on the common electrode potential. It consists of 4 frames, 1 frame to put all pixels and 1 frame to put erased data into all pixels. Driving at 30Hz or more to prevent flicker on the display whose frequency defines this cycle (20) Have been.

The common electrode potential V _C is two frames before V _SS and two frames after V _RO in accordance with this cycle, and a digital / analog converter comprising (16), (17), and (18) that determines an analog output for V _C. Of the reference potential V _R of the previous two frames V
_RO , the latter two frames V _SS, and the value of the reference voltage between V _R -V _C as the former two frames V _RO -V _SS , the latter two frames V _SS -V _RO ,
The liquid crystal is inverted at a predetermined cycle every two frames to perform AC driving of the liquid crystal. That is, the polarity of the reference voltage is inverted.

The effective voltage applied to the liquid crystal in the pixel is a voltage between V _{C of} display data and V _X , and a voltage between V _{C of} erase data and V ₀ (V ₀
= V ₁ -V _C) to the since the ^{_{(V X 2 + V 0 2}} ) 0.5 / 2 0.5, (17) defines a resistance ratio such gradation display is achieved by the effective value, V ₁ ~V _Eight potentials are output. Therefore, the potential of one row J column of the pixel electrodes D (1 J) is inverted D (1J) -V _C every 2 frames with V _C has a 50% duty AC waveform.

FIG. 7 shows a pixel configuration of an image display device of a driving system different from that of FIG. 4, and shows four pixels (I, J) to (I + 1, J + 1). (21) is a transistor, (22) is a display voltage storage capacity, (23) is a pixel electrode, (24) is a column electrode on the substrate facing (23), (25) is a liquid crystal, and (26) is a gate. A row electrode for transmitting a signal, (27) is a column electrode connected to (24) on the one side electrode of (22) on the substrate on which the transistors opposed to (24) are integrated, and connected to (24). 28)
Is the source signal V _a for transmitting the source signals. Transistors turned on by the gate signal, the parallel capacitance of convey the potential of the source signal V _a to the pixel electrodes, the column electrodes D (J), D a difference voltage between the signals from the (J + 1) (22) and (25) The display voltage is stored as a display voltage, and an image is displayed at the stored voltage when the display is off.

As described in FIG. 4, since the parallel capacitance of (22) and (25) is sufficiently larger than the gate-drain capacitance of (21), it is stored between (23) and (24). The display voltage is (24) (27) while the transistor is off
Is kept almost independent of the potential change of.

FIG. 8 is a block diagram of an image display device having the pixels shown in FIG. 7, showing a first embodiment of the present invention, and FIG. 9 is a timing chart showing the operation thereof.

(29) to (35) correspond to FIGS. 5 (14) to (20), respectively, but the difference from the above embodiment is that (35)
Is a substrate in which a plurality of (24) column electrodes of the pixel shown in FIG. 7 are formed, and (21) (22) (23) (26) (27) (28) A display comprising a liquid crystal (25) sandwiched between opposed substrates formed with a plurality of pixel electrodes selected by row electrodes orthogonal to the column electrodes (24), arranged in a matrix so as to be orthogonal; (35) (31) constituting the digital / analog converter which is formed for each column electrode (32) of (33), is that it is fixed reference voltage V _R -V _SS (32) .

Placed in the pixel electrode common source signal V _a to the plurality of column electrodes the transistor of the pixel group to turn on the gate signal V _G becomes the same row (35) of one row (34) Therefore, selected by the row electrode Column electrode D so that the analog voltage applied to the liquid crystal is determined with respect to the potential of the pixel electrode.
(J) Data is added through (J = 1 to N).

Data of the next line while the gate signal of this line is in the V _G is transferred (29), a gate signal V _EE (≦ 2V _SS -
V _RO) and becomes to transistors of the pixel group is off the line, the gate signal of the next line is composed of V _EE to V _G, out write enable signal W parallel output of each bit of the (29) to (30) Write, (30) output (31) (32) (33)
The data converted by the digital / analog converter is transmitted to the pixels.

The data cycle to the pixels in the reference example 1 includes one frame in which various display data is stored in all pixels, and display data that is symmetrically inverted with respect to the data in the previous one frame based on the potential of the pixel electrode selected by the row electrode. Put in all pixels 1
It consists of a total of two frames.

The source signal V potential of the pixel electrodes selected by the row electrodes according to _a previous frame V _SS, after one has become a frame V _RO, the input D _0, D _1, D ₂ is 1 frame after the shift register The digital input D to the digital / analog converter, which is written in the latch by W and output in parallel because the data is inverted from the previous one frame,
₀ (J), D ₁ (J), and D ₂ (J) are values that are complementarily inverted in the subsequent one frame with respect to the values in the preceding one frame. _k (J) → d _9-k (J)
(K = 1 to 8), the switch selection is changed, and since the voltage divider circuit sets the potentials of V _{1 to} V ₈ to V _k −V _SS = V _R −V _9−k , the digital The output voltage of the analog converter is inverted at a predetermined period for each frame with respect to the potential of the pixel electrode selected by the row electrode, and the liquid crystal is AC-driven.

Assuming that the voltage of one frame before the liquid crystal is V _X ,
Frame -V _X, and the (32) lighting of liquid crystal, a voltage defining the unlit fit as the aforementioned properties between V _R -V _SS, divided by the resistance to the gradation display is performed, a line Driving is performed at a duty of 100% as shown by the voltage D (J) -D (1J) applied to the liquid crystal of the pixels in the J column.

FIG. 10 is a timing chart of Reference Example 1 of the present application, which is a modification of the timing chart shown in FIG. Potential of the pixel electrodes selected by the row electrodes according to the source signal V _a is V _SS or V _RO, since the signal of the column electrodes D (J) are in a V _SS ~V _RO, pixel selected by the row electrodes one frame from when the potential of the electrode is V _SS, the potential D of the pixel electrode through a period of non-selection (IJ) (I = 1~M, J = 1~N) 2
V _SS −V _{RO to} V _RO , D for one frame from V _RO
(IJ) is at V _SS 22V _RO −V _SS .

In FIG. 9, the gate signal for controlling the transistor for each pixel is used to select a pixel and turn on the transistor.
V _G (> V _RO ) and V _EE (≦ 2V _SS −V _RO ) to deselect the pixel and turn off the transistor.
In Figure 10, focuses on the potential of the D (IJ), one frame from the time the potential of the pixel electrode selected by the row electrodes is V _SS,
To turn on the transistor, V _G + V _SS -V _RO (>
V _SS ) and V _EE (≦ 2V _SS −
V _RO ), and one frame from the time of V _RO is V _G (> V _RO ) to turn on the transistor, and V _EE + V _RO −V _SS (≦ V _SS ) to turn off the transistor. the pulse height of the gate signal V _G for each _{+ V SS -V RO -V EE (} <V
_G- V _EE ), and each gate signal of G (1) to G (M) is output.

In FIG. 5 and FIG. 8, the digital / analog converter has one voltage dividing circuit, and the decoder and the switch are formed for each column electrode of the display body. A circuit may be provided to perform digital / analog conversion.

Also, what is referred to as a common electrode / potential in the configurations of FIGS. 1 and 5 is a pixel electrode / potential selected by a row electrode orthogonal to the column electrodes of the configuration shown in FIG. Can be achieved in a similar manner. The same applies to the case where the pixel electrodes and potentials selected by the row electrodes orthogonal to the column electrodes in the configuration in FIG. 8 are the common electrodes and potentials in the configurations shown in FIGS. 1 and 5.

Therefore, it is assumed that this point is taken into consideration in the following reference examples, and a substrate on which a plurality of column electrodes are formed,
An image display device using a liquid crystal display sandwiched between opposed substrates having a common electrode is described, and a substrate having a plurality of column electrodes formed thereon and a plurality of pixel electrodes selected by row electrodes orthogonal to the column electrodes are described. And an image display device using a liquid crystal display body sandwiched between opposed substrates formed with the above.

Next, a description will be given with reference to FIGS. 11 to 16. Note that common circuit elements and driving methods used in each example can be applied in combination in other examples. First, Fig. 11 shows Figs. 5 (16) (17) (18), Fig. 8 (31)
(32) (33) shows an alternative digital / analog converter, and FIG. 12 shows an operational amplifier used in the circuit shown in FIG. In contrast to the digital / analog converter shown in FIGS.
The figure shows a current selection method.

Each of them is composed of an integrated circuit of a complementary connection insulated gate field effect transistor. (36) is an operational amplifier which inverts the reference voltage V _R -V _CC and controls the current source transistors (38), (41), (43), (45) and (47) at the output, and The non-inverting input is the voltage between the electrodes of the resistor (39).

(37), (40), (42), (44), and (46) are (38),
(41), (43), (45), (47) is a switch transistor that turns on and off the current path, the on-resistance is sufficiently lower than the current source transistor, (38) / (41 + 2L)
(L = 0-3) channel width / channel length ratio and (3
7) / (40 + 2L) is made substantially equal.

The gate voltage is V _SS (37) is always on, and the current flowing to (39) by (38) is determined by (36) so that the voltage between the electrodes of the resistor is V _R -V _CC .

Current source transistors in an integrated circuit is positioned proximate the performance obtained by normalizing the channel width / channel length is equal, since it is as a gate input the operational amplifier output V ₀ in common, the channel width of the current source transistor /
Channel lengths are (38) β, (41) β _p , (43) β ₀ , (45)
β _1, (47) and β _2, (48) resistance R Tosureba output D of _{(J) = (V R -V} CC) R (Pβ p + D 0 (J) β 0 + D 1
(J) β ₁ + D ₂ (J) β ₂ ) / rβ + V _CC , (P, D ₀ (J), D
₁ (J) and D ₂ (J) are 0 for V _DD and 1) for V _SS , and r, R,
By setting β _p , β ₀ , β ₁ , β ₂ to appropriate values, P, D
An output obtained by digital / analog conversion of the digital input of ₀ (J), D ₁ (J), D ₂ (J) is obtained.

For example, r = R, β ₂ = 2β ₁ = 4β ₀ , β = β ₀ + β ₁ +
Assuming β ₂ , digital inputs V _{SS to} V _DD and V _CC to (V _R −V
_CC ) (1 + β _p / β) + V _CC The analog voltage of (V _R −
It is output with 3-bit weighting of unit voltage of V _CC ) / 7.

For (36), an operational amplifier having a bias stage and a differential amplifier stage can be used simply, and the circuits illustrated in FIG. 12 are close to each other and have exactly the same shape as P-channel transistors (54), N-channel transistors (52), (53) which are close to and have exactly the same shape, with (55) as the active load
N channel connecting were connected to a differential amplifier stage having a source connected to a constant current source of N-channel transistor (51), gate-drain and gate of the (51) _- of the differential input V ₊ to the gate, V An operational amplifier comprising a bias stage in which a P-channel transistor (49) serving as a load resistor is connected to the transistor (50).

Although the digital / analog converter is formed for each column electrode of the liquid crystal display, (36) can be shared by a plurality of columns of digital / analog converters as in the voltage dividing circuit described above. The resistor (48) that determines the
It is arranged on the integrated circuit so as to be close to (39).

_{(V R -V CC) β p} / β is FIG. 5, V ₁ -V _C of Figure 8, V ₁ -V
Used to set a predetermined voltage corresponding to _SS , V _R -V ₈ and is reached by switching (40) with P and controlling (41) with P.

FIG. 13 is a block diagram of an image display device having the digital / analog converter shown in FIG. 11 for each column of the liquid crystal display composed of the pixels shown in FIG. FIG. 14 is a timing chart thereof. (56)
Figures (57), (59) and (60) are shown in Fig. 5 (14) (15) (1
9) It corresponds to (20).

In step (56), the data D ₀ , D ₁ , and D ₂ are serially transferred by the clock CL, and D ₀ ^S (1), D ₁ ^S (1), D ₂ ^S (1) to D ₀ ^S (N), D ₁ ^S
(N), D ₂ ^S (N) After ending a group of data transfer,
(59) the gate signal line of turning on the transistors of the pixel group (60) of V _G becomes the same row.

Each bit output of (56) is written to (57) by the write enable signal W, and its outputs D ₀ (J), D ₁ (J), D ₂
The data D (J) obtained by digital / analog conversion of (J) (J = 1 to N) for each column in (58) as shown in FIG. 11 is stored in the pixel electrode through the column electrode.

Data Taigyo while the gate signal of this line is in the V _G is transferred to (56), the transistor of the pixel group of the row gate signal becomes V _EE is turned off, the gate signal of the next line is V converted data output to the (57) by writing (58) of the becomes V _G from _EE out next write enable signal (56) is transmitted to the pixel.

The data cycle to the pixels in this reference example is a total of two frames of one frame in which display data, which is symmetrically inverted with respect to the data with respect to one frame common power supply potential V _{C in} which various display data is stored in all pixels, is stored in all pixels. And is driven at a predetermined frequency, for example, 30 Hz.

The common electrode potential V _C is one frame V _CC before and one frame V _RO after this cycle in accordance with this cycle, and the inputs D ₀ , D ₁ , D ₂ to the shift register are inverted from the previous one frame in the rear frame. The digital inputs D ₀ (J), D ₁ (J), D ₂ (J) to the digital / analog converter which are written into the latches by W and output in parallel because of the
Is a value complementary to the value of the preceding one frame in the subsequent one frame, and the switch input P for setting a predetermined voltage is also set to the voltage in the preceding one frame V _SS ,
_{Since the} voltage is not set by _DD , the reference voltage input
The output of the digital / analog converter, which is constant at V _RO -V _CC , is inverted at a predetermined period for each frame with respect to the potential of the common electrode, and the liquid crystal is AC-driven.

The channel width / channel length of the current source transistor of the digital / analog converter shown in FIG. 11 is determined to an appropriate value (in FIG. 14, β = β _p + β ₀ + β ₁ + β ₂ and β _p , β ₀ <β _{1 <defines} a beta _2), in accordance with the optical characteristics of the liquid crystal to gradation display, so that the analog output is issued for the digital input. Thus, one row J column of the pixel electrodes D (1 J) is inverted every 1 frame with _{V C, D (1J) -V} C is a duty of 100% of the AC waveform.

FIG. 15 is a timing chart according to the second embodiment of the present invention, which is a modification of the timing chart shown in FIG. When the common electrode potential V _C is V _CC , the pixel electrode potential is 2 V _CC −V _RO
VV _RO , and when V _C is V _RO , it is V _CC 22V _RO −V _CC .

In FIG. 14, the gate signal for controlling the transistor for each pixel is used to select a pixel and turn on the transistor.
V _G (> V _RO ) and V _EE (≦ 2V _CC −V _RO ) to deselect the pixel and turn off the transistor.
In FIG. 15, when the common electrode potential V _C is V _CC , V _G + V _CC −V _RO (> V _RO ) to turn on the transistor, V _G to turn off the transistor, and V _EE to turn off the transistor. (2 ≦ V _CC −V _RO ), when V _C is V _RO , _EE + V _RO −V _CC (≦ V _CC ) to turn on the transistor, and the height of the gate signal pulse is V _G + V _CC − V _RO −V
Retracted _{EE (<V G -V EE)} , has issued a respective gate signals G (1) ~G (M) .

FIG. 16 is a timing chart showing the operation of the image display device of Reference Example 3 having the same configuration as the image display device shown in FIG. FIG. 16 is different from FIG. 14 in that the clock CL input to the shift register, the data D ₀ , D ₁ , D ₂ , the signal W for enabling data writing to the latch, and the digital / analog converter are predetermined. The switch input P for setting the output voltage obtained is a similar signal, but the power supply V _CC and the reference voltage input V _{R of} the digital / analog converter are one.
Changes for each frame, the common electrode potential V _C is constant.

In the digital / analog converter shown in FIG. 11, both the reference voltage input V _R and the output D (J) are determined with respect to the power supply potential V _CC , and V _R −V _CC is kept constant. In the change, D (J) -V _CC is fixed.

In FIG. 16, in one frame before P is V _SS , V _R is V _RO , V _CC is (V _RO + V _CO ) / 2,
In the frame, since the inputs D ₀ , D ₁ , and D ₂ to the shift register are data inverted from the previous data, the digital input D to the digital / analog converter which is written to the latch by W and output in parallel is output. ₀ (J), D ₁ (J), D
₂ (J) is the value obtained by complementarily inverted value of the previous frame one frame after, P is V _DD, V _R is the _{(V RO + V CO) /} 2, V CC
And it is V _CO, a common electrode potential V _C is regardless of the frame _{(V RO + V CO) /} 2 of it which is constant, the channel width / channel length of the digital / analog converter β = β _{p +} β
₀ + β ₁ + β ₂ , the potential entering the pixel is (V _RO + V _CO ) / 2 to V _RO ,
Inverted before and symmetrically relative to the V _C in one frame later (V
_RO + V _CO) / _{2~V CO,} and the liquid crystal AC driving which inverts at a predetermined period for each frame have been made.

Therefore, the potential D (1J) of the pixel electrode in row 1 and column J is V _C
Inverted every 1 frame to, D (1J) -V _C shows a 100% duty of the AC waveform.

In order to perform color display with the pixel display devices of the present invention, the embodiment, and the reference examples 1 to 3 described above, a transparent common electrode or a column electrode is formed on a substrate in which R
The three primary color filters (red), G (green), and B (blue) are arranged corresponding to the pixel electrodes on the counter substrate, and sequentially arranged according to the arrangement of the color filters corresponding to the pixel electrodes selected by the row electrodes. Color data D ₀ and D synchronized with clock CL
_This is achieved by transferring ₁ and D ₂ to a shift register and putting the digital / analog converted output after latching into the pixel electrodes of the selected row.

That is, a light source is arranged behind the color filter of the liquid crystal display, and the liquid crystal arrangement for each pixel is controlled by the voltage applied to the liquid crystal.
A color image is displayed by changing the amount of light transmitted through a color filter and a liquid crystal.

〔The invention's effect〕

As described above, the image display device of the present invention has a configuration in which the digital / analog converter is arranged for each column electrode of the liquid crystal display, so that it is possible to perform gradation display by changing the voltage applied to the liquid crystal for each pixel. By inputting data into the pixel electrodes of the liquid crystal display in a line-sequential operation, the period during which image data is latched, converted from digital to analog, and input to the pixel electrodes is determined by the frame period / the number of rows of pixels. Since time is allowed, the number of rows and columns of pixels can be increased to realize a large display capacity and a large area display.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the image display device of the present invention. FIG. 2 is a configuration diagram of a conventional image display device. FIG. 3 is a timing chart showing the operation of the image display device (reference example). FIG. 4 is a configuration diagram of a pixel of an image display device driven by a transistor formed for each pixel. FIG. 5 is a block diagram of an image display apparatus according to an embodiment of the present invention having the pixels of FIG. FIG. 6 is a timing chart showing the operation of the image display device of FIG. FIG. 7 is a configuration diagram of a pixel of an image display device driven by a transistor formed for each pixel. FIG. 8 is a configuration diagram of an image display device of Reference Example 1 of the present invention having the pixels of FIG. FIG. 9 is a timing chart showing the operation of the image display device of FIG. FIG. 10 is a timing chart showing the operation of the image display device of FIG. 8 as in FIG. FIG. 11 is a reference example of a digital / analog converter used for an image display device. FIG. 12 shows an operational amplifier used in the digital / analog converter shown in FIG. FIG. 13 is a block diagram of an image display device of Reference Example 2 having the pixels of FIG. 4 and the digital / analog converter of FIG. FIG. 14 is a timing chart showing the operation of the image display device of FIG. FIG. 15 is a timing chart showing the operation of the image display device of FIG. 13 as in FIG. FIG. 16 is a timing chart showing the operation of the image display device of Reference Example 3 having the same configuration as the image display device of FIG. [Explanation of Signs] 1: Shift register 2: Latch 3: Digital / analog converter 4: Liquid crystal display D (1) to D (N): Column electrode W indicating connection terminal between (3) and (4) : Write enable signal of (2) V _R : Reference voltage input of (3) V _C : Common electrode terminal and potential V _DD , V _{SS of} (4): Power supply terminal and potential V _{DD of} (1) and (2) , V _CC : (3) power supply terminal / potential

Claims (11)

(57) [Claims] 1. An image display device comprising an active element and a display using liquid crystal, wherein a row electrode group and a column electrode group are arranged in a matrix so as to be orthogonal to each other, and the active element is arranged in a row electrode and a column electrode. A pixel electrode and a common electrode facing the pixel electrode are provided corresponding to the matrix of the electrode, a liquid crystal is sandwiched between the opposed substrates, and a digital / analog converter connected to the column electrode is provided with a decoder and A voltage circuit and a switch, one of a first power supply terminal and a second power supply terminal of the voltage divider circuit is made equal to a potential of the common electrode, and a voltage between these two power supply terminals is a reference voltage. A connection point for dividing the reference voltage by a resistor to output a potential adjusted to the optical characteristics of the liquid crystal is provided; a switch between the connection point and a column electrode is arranged; Digital The image data is supplied to a digital / analog converter through a shift register and a latch, passes through a decoder, is converted into a decoder output for each column, and a switch is controlled by the decoder output. It is selected as image data and sent to the column electrodes, and the polarity of the reference voltage is inverted at a predetermined cycle based on the potential of the common electrode, and the liquid crystal is AC-driven, and ²ⁿ gray scale display is performed. An image display device characterized by the above-mentioned. 2. The image display device according to claim 1, wherein the predetermined period is one frame or two frames. 3. The image display device according to claim 1, wherein the shift register transfers n-bit digital image data in series and outputs the data in parallel with n bits per column. 4. The method according to claim 1, wherein the number of voltage dividing circuits is one.
Item 4. The image display device according to item 2 or 3. 5. The image display device according to claim 1, wherein a voltage dividing circuit is provided for each of a plurality of decoders and switches. 6. The image display device according to claim 1, further comprising a color filter corresponding to each pixel electrode, and performing color display. 7. A digital filter in which three primary color filters of R (red), G (green), and B (blue) are arranged, and color data corresponding to the arrangement of the color filters corresponding to the pixel electrodes selected by the row electrodes. 7. The image display device according to claim 6, wherein the image data is transferred to a shift register. 8. The image display device according to claim 1, wherein the active element is a transistor. 9. The method according to claim 1, wherein n = 3.
The image display device according to any one of the above items. 10. The image display apparatus according to claim 1, wherein the image display apparatus has one frame for putting display data on the whole screen and one frame for putting uniform erase data on the whole screen. . 11. The image display device according to claim 1, wherein a data cycle to the pixel is driven at 30 Hz or more.