JPH07281641A - Active matrix type liquid crystal display - Google Patents

Abstract

PURPOSE:To reduce the power consumption of an active matrix type liquid crystal display. CONSTITUTION:A pulse width modulation signal complied with the gradation of a video input signal is generated by means of a pulse width converting part in a display signal circuit 300, a driving voltage for a liquid crystal cell is sent to a data signal line DL-i for a period set by the pulse width modulation signal by means of a switch part and the data signal line DL-i and a pixel electrode 11 become a high impedance state in the other period. A lamp driving voltage is applied on a common electrode 22 from a lamp voltage generating circuit 400 and a TFT-LCD p[art TC1 performs multilevel display based on the potential difference between the common electrode 22 and the pixel electrode 11. When the data signal line DL-i becomes a high impedance state, the potential of the data signal line DL-i is changed by following up the lamp driving voltage owing to the wiring capacity. The wiring capacity suppresses the spread of the potential difference between the common electrode 22 and the pixel electrode 11 in the high impedance state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference 1; Journal of Television Society, 42 [1] (1988).
P. 10-29 Reference 2; Electronic Technology, (1993-3.) P. The 45-49 active matrix type liquid crystal panel has attracted attention because of its excellent full-color image display performance, and various proposals have been made. Hereinafter, with reference to the drawings, an outline of a TFT-LCD configured by combining a thin film transistor (hereinafter referred to as TFT) and a liquid crystal display element (hereinafter referred to as LCD) known as a typical active matrix type liquid crystal panel will be described. explain. FIG. 2 is a perspective view showing a schematic structure of the conventional TFT-LCD described in Document 1 above. In a TFT-LCD, which is one of active matrix type liquid crystal panels, for example, a transparent back substrate 10 and a front substrate 20 are arranged to face each other. On the back substrate 10, a plurality of data signal lines DL-i (i is an integer from 1 to m) and a plurality of scanning signal lines SSL-j (j is an integer from 1 to n) intersect with each other through an insulating layer. The TFTs 12 are arranged, and the TFTs 12 are connected to their intersections as switching elements corresponding to the respective pixel electrodes 11. Front substrate 20
Above, in the portion facing the pixel electrode 11 of each display cell,
Red (R), green (G), and blue (B) color filters 21 corresponding to display colors are provided, and a transparent common electrode (hereinafter, referred to as common electrode) 22 is provided thereon. On both surfaces of the back substrate 10 and the front substrate 20, alignment films that have been subjected to an alignment treatment in appropriate directions are provided, and the alignment films of both substrates 10 and 20 are arranged so as to face each other with a liquid crystal layer 30 interposed therebetween. The periphery of the space is sealed. further,
Polarizing films 13 and 23 are attached to the rear surfaces of the rear substrate 10 and the front substrate 20, respectively, so that their polarization axes are parallel or perpendicular to each other. Each such TFT-L
In the CD, the backlight BL is applied from the back side of the rear substrate 10 and sandwiched between the electrodes 11 and 22 due to the potential difference between the voltage of the pixel electrode 11 and the voltage of the common electrode 22 given through each TFT 12. The liquid crystal of the liquid crystal layer 30 is switched to display an image.

FIG. 3 shows a TN (Twisted) structure in the TFT-LCD shown in FIG. 2 in which two polarizing films 13 and 23 are attached so that their polarization axis directions are parallel to each other.
FIG. 3 is a diagram showing the electro-optical characteristics of a Nematic liquid crystal cell.
The TN liquid crystal cell used in the TFT-LCD has a threshold voltage V _{TH at} which the light transmittance sharply increases with respect to the data potential difference between the voltage V _P of the pixel electrode 11 and the voltage V _COM of the common electrode 22, and There is a saturation voltage V _{SAT at} which the fluctuation of the transmittance disappears, and in the voltage range ΔV of V _{TH to} V _SAT , the light transmittance changes due to the voltage fluctuation. Although not shown, the TN liquid crystal cell has a characteristic of not responding when an electric field in one direction is continuously applied. Therefore, it is necessary to alternately write the positive polarity and the negative polarity. In order to achieve a complete on-state, V _SAT < _VP − in the positive polarity
To set a voltage condition of V _SAT <V _COM −V _P in V _COM and negative polarity and achieve a complete OFF state, V _TH > V _P −V _COM in positive polarity and V _TH > V in negative polarity.
Set voltage condition of _COM -V _P, performs switching of the liquid crystal cell. Further, when gradation display is performed, the voltage condition is variably controlled under the condition of V _SAT > V _P −V _COM > V _{TH in} the positive polarity and V _SAT > V _COM −V _P > V _{TH in} the negative polarity. Is set to. FIG. 4 is a TFT-LCD shown in FIG.
FIG. 6 is a schematic circuit diagram of a conventional active matrix type liquid crystal display using the. As shown in FIG. 4, each TFT
As the switching means of 12, the scanning signal circuit 100 is connected to the scanning signal line SL-j, and the display signal circuit 200 is connected to the data signal line DL-i. TFT1
A liquid crystal cell 31 is connected between 2 and the common electrode 22.

FIG. 5 is a diagram showing an equivalent circuit of the liquid crystal cell in FIG. 4, in which the parasitic capacitance component of the liquid crystal cell is shown. Each liquid crystal cell 31 has a parasitic capacitance C of the TFT 12.
And _GS, and the capacitance C _GC existing between the scanning signal line SL-j and the common electrode 22, and a capacitor C _DC which exist between the data signal line DL-i and the common electrode 22, the scanning signal line SL-j and the data signal It has a capacitance C _GD existing between the lines DL-i and a capacitance C _LC existing between the pixel electrode 11 and the common electrode 22. FIG. 6 is a drive timing chart of the active matrix type liquid crystal display shown in FIG. 4, and the operation of FIG. 4 will be described with reference to this figure. Figure 4
As shown in, the scanning signal circuit 100 and the display signal circuit 200 provided as the switching means of each TFT 12
Among them, the scanning signal circuit 100 sends the gate selection signal of the TFT 12, the scanning signal line SL-j is selected, and the on-voltage VG ₍₊₎ and the off-voltage VG _(-) are sequentially supplied in time sequence. Further, the display signal circuit 200 sends out a luminance data signal,
Positive polarity write voltage V _{D (+)} and negative polarity write voltage V _{D (-)}
Are supplied to the pixel electrode 11 via the TFT 12. T
The voltage V of the pixel electrode 11 written by the FT12
_As shown in FIG. 6, _P is affected by the parasitic capacitance C _GS of the TFT 12 to which the selection signal is supplied when the gate selection signal of the TFT 12 changes from the ON state to the OFF state.
ΔV ₁ (ΔV ₁ = (C _GS / C _LC + C _GS )) × (V _{G (+)} +
A voltage change of V _{G (-)} ) occurs. Therefore, the potential difference between the pixel electrode 11 and the common electrode 22 is
The voltage V _COM is supplied to the common electrode 22 so that the positive polarity writing and the negative polarity writing become even with respect to the fluctuation of the voltage V _P.

FIG. 7 is a diagram showing the configuration of the output stages of the analog driver and the digital driver in the display signal circuit of FIG. 4 which outputs the luminance data signal for gradation display shown in Document 2. FIG. 7A is an example of the output stage of the analog driver. This driver is for analog video signal AS
Compose a sample-hold section that holds the potential of 2
The capacitors 41 and 42, the current source 43 forming the buffer output section, the operational amplifier 44, and the transistor 45 are provided, and the six switches SW1 to SW6 for controlling the connection between these respective elements are provided. There is. The analog driver inputs a voltage corresponding to a halftone in gradation display as an analog signal AS and outputs a voltage assigned to each pixel from an output terminal Out. The input video signal AS is stored in the sample hold unit and then supplied to the buffer output unit, which has a function of driving and outputting the video signal AS. Since this analog driver is composed of an analog buffer, it is possible to increase the number of gradations, but on the other hand, the operational amplifier 44 is driven by the current source 43, so that there is a drawback that the power consumption becomes large, and the drive circuit It is difficult to achieve high integration in the IC of some parts.

On the other hand, FIG. 7B shows an example of the circuit configuration of the output stage of the 8-level digital driver. The digital driver inputs a voltage level corresponding to the intermediate gradation as a digital code, performs digital / analog conversion, and outputs a desired voltage level. This digital driver has a clock signal CK and a start pulse SP.
And a data register 51 for sequentially taking in the digital color video signal DS1 by the timing signal from the timing generator 50.
have. The data register 51 is connected to a data register 52 that simultaneously captures and stores the data stored in the data register 51 by the latch strobe signal STB, and the output of the data register 52 is the decode and the decode and shift that shifts the decode result. Level shift circuit 5
Connected to 3. The output side of the decoding and level shift circuit 53 receives the grayscale voltages V0 to V7.
It is connected to a digital / analog conversion circuit 54 having individual analog switches 54-0 to 54-7. In the digital / analog conversion circuit 54, 8-level voltages V0 to V7 supplied from the outside according to the output of the decoding and level shift circuit 53 are converted into analog switches 54-0.
~ A voltage corresponding to the data selected by the analog switch 54-7 is output from the output terminal. In the driver of this configuration, since the output stage is configured by analog switches, power consumption is reduced, but on the other hand, when multi-gradation is to be achieved, it is necessary to input an external power supply corresponding to the number of gradation reproductions.
Therefore, if the drive circuit is integrated into an IC, the area occupied by the wiring system of the power input line inside the IC increases, which is not economical.

[0007]

However, the conventional gray scale driving method or driving circuit of the active matrix type liquid crystal display has the following problems. When the luminance data signal for the active matrix liquid crystal panel is supplied in analog as shown in (a) of FIG. 7, high image quality can be achieved by increasing the number of gradations, but power consumption is large. There is. Also,
As shown in FIG. 7B, when a digital code DS1 corresponding to a halftone is input and digital / analog conversion is performed to output gradation voltage levels V _{0 to} V ₇ ,
There is a problem that an external power supply for generating the voltage level is required, and it becomes difficult to achieve high integration due to the power supply line and the like as the image quality is improved. That is, a liquid crystal display with low power consumption, high image quality, and high integration could not be realized.

[0008]

In order to solve the above-mentioned problems, a first invention is to form a translucent rear substrate and a plurality of them which are formed on the rear substrate so as to intersect each other through an insulating layer. Data signal lines and scanning signal lines, a plurality of thin film transistors respectively connected to the pixel electrodes corresponding to the intersections of the data signal lines and the scanning signal lines, and arranged to face the back substrate. A transparent front substrate, a color filter corresponding to a display color provided in a portion of the front substrate facing the pixel electrode of each liquid crystal cell, and a transparent common electrode provided on the color filter. An alignment film that is arranged to face each of the back substrate and the front substrate and is aligned in a predetermined direction; and a liquid crystal layer interposed between the alignment films on the back substrate and the front substrate, Rear of back and front substrate An active matrix liquid crystal panel having a polarizing film attached thereto, and a display for outputting a driving voltage of each liquid crystal cell to the pixel electrode via the data signal line and the thin film transistor according to a video input signal. The active matrix liquid crystal panel includes a signal circuit, a scanning signal circuit that outputs a scanning signal that controls the conduction state of each thin film transistor to the scanning signal line, and a common electrode driving circuit that drives the common electrode. The following means are provided in an active matrix type liquid crystal display which is driven by an alternating current and performs gradation display corresponding to the input signal. That is, the display signal circuit includes a pulse width conversion unit that generates a pulse width modulation signal that sets a pulse width according to the gray scale of the video input signal, and a period of the liquid crystal cell that is set for the pulse width modulation signal. The common electrode drive circuit is configured to include a switch unit that sends a drive voltage to the data signal line and sends a high impedance state to the data signal line except during a drive voltage sending period of the liquid crystal cell. A lamp drive voltage that sequentially increases or decreases depending on the polarity in the AC drive is sent to the common electrode.

According to a second aspect of the invention, an auxiliary capacitance and an auxiliary capacitance line for applying a voltage to the auxiliary capacitance are provided for each of the pixel electrodes in the first invention, and each of the auxiliary capacitance lines is provided with the lamp. The drive voltage is applied. In a third aspect of the invention, the width of either one or both of the data signal line and the scanning signal line in the first and second aspects is narrowed only at the intersecting portion. The fourth invention is
At the intersection of the auxiliary capacitance line and the data signal line in the second aspect of the invention, one or both of the auxiliary capacitance line and the data signal line are made thicker. According to a fifth aspect of the present invention, the scan signal circuit according to the first or second aspect of the present invention is AC-driven, and a lamp voltage drive unit that generates a lamp drive voltage that sequentially increases or decreases according to the polarity thereof is provided. And a scanning signal conversion unit that superimposes a lamp driving voltage. In a sixth aspect based on the fifth aspect, an auxiliary capacitance is provided between the pixel electrode and a scanning signal line preceding the scanning signal line connected to the pixel electrode via a thin film transistor.

[0010]

According to the first aspect of the invention, since the active matrix type liquid crystal display is constructed as described above, a pulse width modulation signal according to the gradation level of the video input signal is generated by the pulse width conversion section in the display signal circuit. Then, the drive voltage of the liquid crystal cell is sent to the data signal line by the switch section for the period set in the pulse width modulation signal. In addition, except during the set period, the data signal line and the pixel electrode are in the high impedance state by the switch section. A lamp driving voltage that sequentially increases or decreases according to the polarity in AC driving is supplied to the common electrode from the common electrode driving circuit. Each TFT-LCD performs gradation display based on the potential difference between the common electrode and the pixel electrode. Since the lamp driving voltage is supplied to the common electrode, the potential difference between the common electrode and the pixel electrode varies depending on the length of the set period.
That is, the potential difference between the potential of the pixel electrode and the common electrode changes according to the gradation level of the video input signal. Further, when the set period ends and a high impedance state is set, the potential of the data signal line changes in accordance with the lamp driving voltage due to the wiring capacitance between the data signal line and the common electrode. That is, this wiring capacitance suppresses the spread of the potential difference between the common electrode and the pixel electrode.

According to the second aspect of the invention, the auxiliary drive capacitor provided for each of the pixel electrodes in the first aspect of the invention and the lamp drive voltage are applied to the auxiliary capacitance, and the auxiliary capacitance is in a high impedance state data signal line. The voltage of is changed according to the lamp drive voltage. According to the third aspect of the invention, since the width of either one or both of the data signal line and the scanning signal line is narrowed only at the intersection, the wiring capacitance between the data signal line and the scanning signal line is reduced. It According to the fourth aspect of the invention, the width of either or both of the auxiliary capacitance line and the data signal line is widened at the intersection of the auxiliary capacitance line and the data signal line in the second aspect. The wiring capacitance between the auxiliary capacitance line and the data signal line increases. According to the fifth aspect, the lamp drive voltage generated by the lamp voltage drive section is supplied to the scanning signal line in the first or second aspect of the invention by being superimposed on the scanning signal line by the scanning signal conversion section. According to the sixth invention, since the ramp voltage is applied to the auxiliary capacitance provided for the fifth invention by the scanning signal line in the preceding stage, the potential of the pixel electrode is high when the data signal line is in the high impedance state. Changes according to the lamp drive voltage. Therefore, the above problem can be solved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing an outline of an active matrix type liquid crystal display of a first embodiment of the present invention, in which elements common to FIG. It is attached. In this display, the liquid crystal cell 31 is n × m (n and m are
Positive integer) TFT-LCDs arranged in matrix
The scan signal S1-j (j is an integer from 1 to n) which is a time-sequential gate selection signal is supplied to the unit TC1 via a plurality of scan signal lines SL-j (j is an integer from 1 to n). In the conventional scanning signal circuit 100 similar to that shown in FIG. 4 and a plurality of data signal lines DL-i (i is an integer from 1 to m) different from FIG. 4, the pulse width is changed according to the gradation display data. The display signal circuit 300 supplies the changed luminance data signal S2-i (i is an integer from 1 to m) to each liquid crystal cell 31. On the other hand, the TFT-LCD section TC1 has the same configuration as that of the conventional FIG. That is, TF
In the T-LCD, the back substrate 10 and the front substrate 20 are arranged to face each other. A plurality of data signal lines DTL1, a plurality of scanning signal lines SL-j, a pixel electrode 11 and a TFT 12 are connected on the rear substrate 10. Front substrate 2
0, the red, green, and blue color filters 21 corresponding to the display colors are provided in the portions facing the pixel electrodes 11 of the respective display cells.
Is provided, and a transparent common electrode 22 is further provided thereon,
It is provided.

On both surfaces of the back substrate 10 and the front substrate 20, alignment films that are oriented in appropriate directions are provided, and the alignment films of both substrates 10 and 20 are arranged so as to face each other with a liquid crystal layer 30 in between. The peripheries of the two substrates are sealed.
Further, on the back surfaces of the back substrate 10 and the front substrate 20, the polarizing films 1 are arranged so that their polarization axes are parallel or perpendicular to each other.
3 and 23 are attached respectively, as in FIG. Further, in this display, the common electrode 22 is connected to the lamp voltage generation circuit 400 which is a common electrode drive circuit. The lamp voltage generation circuit 400 supplies a lamp driving voltage having a lamp waveform.

FIG. 8 is a block diagram showing the configuration of the display signal circuit shown in FIG. 1, and FIG. 9 is a block diagram of the pulse conversion unit shown in FIG.
It is a circuit diagram which shows an output. The display signal circuit 300 includes a pulse width conversion unit 310 that inputs digital gradation display data DS and a plurality of control signals, and a switch unit 320 that is configured by an analog switch that inputs a reference voltage V _s .
The reference voltage V _s is output only during the output period of the pulse width corresponding to the weighting of the gray scale display data DS, and the luminance data signals S2-i that are in the high impedance state during the other periods are sent to the data signal lines DL-i, respectively. Is. The pulse width conversion circuit 310, as shown in FIG.
A line memory circuit 311 that stores the gradation display data D _{1 to DN} having bit weights in synchronization with the signal LOAD, and a count-up that is cleared by the inverted signal of the signal LOAD and is synchronized with the pulse width control clock signal CPG. And a clock number counter 312 that operates. A match circuit 313 is provided on the output side of the line memory circuit 311 and the clock number counter 312, and the clock number counter 3
The 12 N output terminals q _{1 to} q _N are connected to inverters I ₁ to I _N.
It is connected to each one input terminal of the exclusive OR gate G ₁ ~G _N 2 inputs of the coincidence circuit in 313 via the I _N. Further, the output terminals _Q 1 to Q _N of the line memory circuit 311 are connected to the other input terminal of the direct gate G ₁ ~G _N. In the matching circuit 313, the
It has a D gate Ga, and the output of the gate G ₁ ~G _N and the clock signal CPG is connected to the input side. AN
The output of the D gate Ga is connected to the reset terminal R of the flip-flop 314, and the fetch signal LOAD is input to the set terminal of the flip-flop 314. The flip-flop 314 outputs the pulse width modulation signal PO-i, and the output of the flip-flop 314 is
It is connected to the switch unit 320. Switch part 320
Is composed of a plurality of analog switches SW320-j corresponding to a plurality of data signal lines DL-i. Each switch SW320-j (j is an integer from 1 to m) receives each data signal line D based on the pulse width modulation signal PO-i.
Analog switch SW32 connected to TL1
In this configuration, the open / close period of 0-j is controlled. Each of the switches SW320-j has one side connected to the reference voltage Vs and the other side connected to the data signal line DL-i corresponding to each cell, and is turned on for a pulse width period corresponding to the weighting of the gray scale display data. Each has a function of supplying the reference voltage V _s to the line DL-i. Then, each switch SW320-j puts the data signal line DL-i into a high impedance state except during the pulse width period.

FIG. 10 is a circuit diagram showing the ramp voltage generating circuit in FIG. This circuit is a circuit that sends out a voltage V _COM having a ramp waveform to the common electrode 22. The voltages V _{dd1 (+)} and V _{dd1 (+)} that set the maximum and minimum values of the ramp voltage, respectively.
Two series switches 401, 4 connected between _{dd1 (-)}
Have 02. The connection node of the switches 401 and 402 in series is connected to a resistor 403, and the resistor 403 is connected to the (−) input terminal of a two-input first operational amplifier 404. The (+) input terminal of the operational amplifier 404 is grounded. The resistor 403 is connected to be grounded when the switch 405 is opened and closed, and the output of the operational amplifier 404 is negatively fed back to the (−) input terminal via the capacitor 406. The ramp voltage generation circuit 400 of FIG. 10 also includes a variable resistor 407 connected between the reference voltages V _{dd2 (+)} and V _{dd2 (−)} that set the DC component voltage of the ramp waveform. The divided voltage of the second operational amplifier 408 is
Input to (+) input terminal. Of the operational amplifier 408
The (-) input terminal has a configuration in which the output of the operational amplifier 408 is negatively fed back to form a voltage follower circuit, and a voltage level that does not change due to a load is generated. The outputs of the operational amplifiers 404 and 408 are resistors 409 and 41, respectively.
0 is connected to the (-) input terminal of the second input third operational amplifier 411 to form an adder circuit, and the (+) input terminal of the operational amplifier 411 is grounded. The output of the operational amplifier 411 is connected to the power MOS buffer 412, and the power MOS buffer 41 capable of obtaining a sufficient output current.
The voltage V _{COM of the} ramp waveform is sent out via 2. That is, the ramp voltage generating circuit 400 includes three switches 401, 402, 405 and an operational amplifier 404.
, A resistor 403, and a capacitor 406 form a ramp waveform, and two operational amplifiers 408 and 411 and two resistors 40
The voltage level is set by 9, 410 and the variable resistor 407, and the power MOS buffer 412 supplies the lamp drive voltage V _COM set at each voltage level to the common electrode 22 as a conversion power supply voltage.

FIG. 11 is a diagram showing voltage waveforms of the liquid crystal cell in FIG. 1, in which the pulse width modulation signal PO-i, the voltage X _{i of the} scanning signal line SL-j, and the voltage of the data signal line DL-i. Y
_i , the voltage V _COM of the common electrode 22, the voltage V _P of the pixel electrode 11, and the potential difference V _LC between the pixel electrode 11 and the common electrode 22 are shown. The operation of the TFT-LCD display of FIG. 1 will be described with reference to this figure. The scanning signal circuit 100 performs scanning to sequentially scan each scanning signal line S.
L-j is turned on and activated. Each TF of liquid crystal cell
The voltage Xi of the scanning signal line SL-j connected to T12 is
As shown in FIG. 11, one scanning period is “H”. In the display signal circuit 300, the gradation display data D _{1 to DN} are accumulated in the line memory circuit 311, and the gradation display data D _{1 to DN} are synchronized with the capture signal LOAD in the matching circuit 3.
It is sent to the input terminals of the gate G ₁ ~G _N in 1. At the same time, the clock number counter 312 and the flip-flop 314 are initialized in synchronization with the signal LOAD, and the clock number counter 312 counts up the pulse width control clock CPG. The coincidence circuit compares the grayscale display data with the output of the clock counter 312, and at the time of coincidence, changes the initial state of the flip-flop 314, for example, from “1” to “0”. That is, the pulse width conversion circuit 310 converts the gradation display data into the pulse width modulation signal PO-i which becomes the ON signal only during the period corresponding to the weighting. Switch part 3
Each switch SW320-j in 20 has its opening / closing period controlled based on the pulse width modulation signal PO-i, and outputs the reference voltage V _s in the conductive state as shown in FIG. 11. Then, when the switches SW320-j are opened, the data signal lines DL-i are set to the high impedance state. That is, the pulse width conversion circuit 31 of the display signal circuit 300
The pulse width modulation signal PO-i corresponding to each intermediate gradation value from 0
However, only the period tw in FIG.
1 to 320-m to be supplied, the analog switches 320-1 to 320-m, the luminance data signal _{Y i} of the signal lines DL-i as a reference voltage V _s in the writing period tw
Supply to. When the period tw ends, the data signal line DL-i is in a high impedance state, and thus the voltage is held by the charge accumulated in the wiring capacitance associated with the data signal line DL-i.

On the other hand, in the ramp voltage generating circuit 400, when the ramp waveform is generated, only the switch 405 is turned on, so that the operational amplifier 404 becomes
Set the (-) input terminal and (+) input terminal to the same potential, and set the initial value output to 0V. The resistor 403 and the capacitor 406 form an integrating circuit, and by turning off the switch 405 and turning on the switch 402, the operational amplifier 40
The output of 4 is increased from 0V to the voltage Vdd1 (+) to generate a ramp waveform. The integrating circuit of the resistor 403 and the capacitor 406 also turns off the switch 405 and turns off the switch 40.
By turning 1 on, the output of the operational amplifier 404 drops from 0V toward the voltage Vdd1 (−). Then, the three switches 401, 402, and 405 return to the initial state by turning off the switch 401 or 402 and turning on the switch 405 after an arbitrary time has elapsed. As described above, the ramp generation circuit 400 controls each of the switches 401, 402, and 405 and optimizes the time constant set by the resistor 403 and the capacitor 406, so that the desired positive or negative polarity is obtained. The voltage V _COM of the ramp waveform having the potential gradient of is supplied to the common electrode 22. The common electrode 22, a lamp driving voltage is supplied, the wiring capacitance C _DC which exist between the data signal line DL-i and the common electrode 22 induces lamp driving voltage to the data signal line DL-i. That is, the data signal line D in the high impedance state
The voltage Y _i of L-i causes a voltage change by following the lamp driving voltage waveform. Letting ΔV _{COM be} the change amount of the lamp drive voltage immediately after the end of the period tw, the data signal line DL−
The voltage change amount ΔV _D of i is ΔV _D = ΔV _COM × (C _DC /
(C _DC + C _GD )). That is, the data signal line DL-i
Wiring capacitance C _DC between the common electrode 22 and the scan signal line S
Of the wiring capacitance C _GD between L-j and the data signal line DL-i,
The divided value of the two wiring capacitances corresponds to the amount of change in the voltage Y _i of the data signal line DL-i.

The voltage V _P of the pixel electrode 11 written by the TFT 12 is ΔV ₁ due to the parasitic capacitance C _GS of the TFT 12 when the voltage of the scanning signal line SL-j changes from the ON state to the OFF state. = (C _GS / (C _LC + C _GS )) ×
A voltage fluctuation is caused by (VG _{(+) -} VG _(-) ). Therefore, the potential difference V _LC between the pixel electrode 11 and the common electrode 22 is
The center value of the voltage V _COM applied to the common electrode 22 is adjusted so as to be uniform during writing of the positive polarity and the negative polarity. The voltage V _P of the pixel electrode 11 and the common electrode 2
Due to the voltage V _COM applied to the TFT 2 through the TFT 12, the potential difference V _LC changes according to the length of the period tw. After the end of the period tw, the potential difference V _LC maintains a constant level, and when one scanning time ends, the potential difference V _LC has a waveform that changes in voltage. The liquid crystal panel is displayed based on the potential difference V _LC . As described above, in the present embodiment, the display signal circuit 30
A signal having a pulse width of 0 from 0 to a period tw set according to the gradation value is transmitted, and in other periods, a signal Y _i having a high impedance is supplied to the data signal line DL-i and also to the common electrode 22. Since the lamp driving voltage V _COM is applied, multi-gradation display can be realized without requiring a power supply for each gradation value. In addition, since the output stage of the display signal circuit 300 can be formed by an analog switch, a display with low power consumption and capable of multi-gradation display can be realized.

Second Embodiment FIG. 12 is a circuit diagram showing the outline of an active matrix type liquid crystal display according to the second embodiment of the present invention.
Elements common to those in FIG. 1 according to the embodiment of FIG. The circuit of this liquid crystal display is the first except that it has a TFT-LCD section TC2 different from that of FIG.
The configuration is the same as that of the embodiment. TFT-LCD section TC2
In the first embodiment, an auxiliary capacitance electrode (not shown) is provided on the back surface of each pixel electrode 11 of the TFT-LCD section TC1 via an insulating film, and each data signal line DL-i and an insulating layer (not shown).
Auxiliary capacitance lines CL, which are arranged in a straight line through and are connected to auxiliary capacitance electrodes, are provided, and auxiliary capacitances C _h are formed by the respective auxiliary capacitance electrodes / insulating films / pixel electrodes 4,
The potential V _COM of the common electrode 22 is applied to the auxiliary capacitance line CL.

Next, the operation of the liquid crystal display shown in FIG. 12 will be described. Similar to the first embodiment, scanning is performed to sequentially activate each scanning signal line SL-j by turning it on.
In the display signal circuit 300, the pulse width conversion circuit 310
Converts the gradation display data into a pulse width modulation signal PO-i which becomes an ON signal only for a period corresponding to the weighting. Each switch 320-j in the switch unit 320 outputs the reference voltage V _s when it is in the conductive state, as shown in FIG. 11. When the switches 320-j are opened, the data signal lines DL-i are set to the high impedance state. That is, the pulse width conversion circuit 310 of the display signal circuit 300 supplies the pulse width modulation signals PO-i corresponding to the respective intermediate gradation values to the analog switches 320-1 to 320-m, and the analog switches 320-1 to 320-m. ~ 320-m is
In the writing period tw, the luminance data signal Y _i that is the reference voltage V _s is supplied to each signal line DL-i. When the period tw ends, the data signal line DL-i is set to the high impedance state. When in the high impedance state, the voltage of the data signal line DL-i is held by the charges accumulated in the associated wiring capacitance. Here, the common electrode 2
Since the 2 and the auxiliary capacitance line CL lamp voltage is supplied, via the wiring capacitance and the data signal DL-i between the data signal line DL-i and the common electrode 22 to the wiring capacitance C _s between the auxiliary capacity line CL Thus, the ramp voltage is supplied to the data signal line DL-i. The voltage Yi of the data signal line DL-i in the high impedance state is the ramp voltage generation circuit 400.
A voltage change occurs following the waveform of.

The writing period tw exit ramp drive voltage amount of change [Delta] V _COM from immediately after, and when each data signal line wiring capacitance between the auxiliary capacitance line CL to's and C _DS, the data signal line DL-i voltage The amount of change ΔV _D1 is ΔV _D1 = ΔV _COM
× ((C _DC + C _DS ) / (C _DC + C _DS + C _GD ))
Therefore, the divided value of the wiring capacitance C _GD between the data signal DL-i and the scanning signal line SL-j becomes smaller than that in the first embodiment, and the data signal line DL immediately after the period tw ends.
The difference V _LC between the potential difference between the voltage Yi of −i and the voltage V _COM of the common electrode 22 and the potential difference between the voltage Yi and the voltage V _COM when the scanning signal line SL-j is turned off is 1
It is even smaller than the embodiment. Scan signal line SL-j
When the voltage on the TFT changes from the ON state to the OFF state, the TFT
The voltage V _P of the pixel electrode 11 written by 12 causes a voltage fluctuation under the influence of the parasitic capacitance C _GS of the TFT 12 when the voltage of the scanning signal line SL-j changes from the ON state to the OFF state. Therefore, the pixel electrode 11 and the common electrode 22
The central value of the voltage V _COM applied to the common electrode 22 is adjusted so that the potential difference V _LC between them becomes equal during writing of positive polarity and negative polarity. The voltage V _{P of the} pixel electrode 11
And the voltage V _COM applied via TFT12 to the common electrode 22, the potential difference V _LC is a voltage change corresponding to the length of the period tw. After the end of the period tw, the potential difference V _LC maintains a constant level, and when one scanning time ends, the potential difference V _LC has a waveform that changes in voltage. The liquid crystal panel is displayed based on the potential difference V _LC . As described above, since the auxiliary capacitance C _h is provided in each pixel electrode 11 of the liquid crystal panel and the lamp driving voltage is applied to each auxiliary capacitance C _h via the auxiliary capacitance line CL, the data signal line DL-i. The potential V _P of the pixel electrode 11 can be reliably changed in the same manner as the waveform of the lamp drive voltage in the higher impedance state than in the first embodiment in which the waveform of the lamp drive voltage is caused to follow by the wiring capacitance associated with. Therefore, there is an advantage that an active matrix type liquid crystal display with high display quality and high image quality can be realized.

Third Embodiment FIG. 13 is a circuit diagram showing an outline of an active matrix type liquid crystal display of a third embodiment of the present invention.
Elements common to those in FIG. 1 according to the embodiment of FIG. This liquid crystal display has the same configuration as that of the first embodiment except that it has a TFT-LCD section TC3 different from that shown in FIG. FIG. 14 shows the TFT-L of FIG.
It is a figure explaining CD, and the same code | symbol is attached | subjected to the element common to the conventional FIG. This embodiment is different from the first embodiment in that at the intersections of the respective orthogonally arranged data signal lines DL-i and scanning signal lines SL-j of the first embodiment, as shown in FIG. Both or one of the data signal line DL-i and the scanning signal line SL-j is thinly formed. Therefore, the wiring capacitance C _GD1 between the data signal line DL-i and the scanning signal line SL-j is smaller than the corresponding wiring capacitance C _GD in the first embodiment.

Next, the operation of the type liquid crystal display of FIG. 13 will be described. Similar to the first embodiment, scanning is performed to sequentially activate each scanning signal line SL-j by turning it on. In the display signal circuit 300, the pulse width conversion circuit 3
Reference numeral 10 converts the gradation display data into a pulse width modulation signal PO-i which becomes an ON signal only for a period corresponding to the weighting. Each switch 320-j in the switch unit 320 outputs the reference voltage V _s when it is in the conductive state, as shown in FIG. 11. When the switches 320-j are opened, the data signal lines DL-i are set to the high impedance state. That is, the pulse width conversion circuit 3 of the display signal circuit 300
10 to the pulse width modulation signal PO− according to each intermediate gradation value
i is supplied to the analog switches 320-1 to 320-m, respectively, and the analog switches 320-1 to 320
-M supplies the luminance data signals _{Y i} as a reference voltage V _s in the writing period tw for each signal line DL-i. When the period tw ends, the data signal line DL-i is set to the high impedance state. In the high impedance state, the voltage is held by the charges accumulated in the wiring capacitance associated with the data signal line DL-i. Here, the common electrode 22, since the lamp voltage is supplied, the lamp voltage is supplied to the data signal line DL-i via the wiring capacitance C _DC between the data signal line DL-i and the common electrode 22 . Data signal line DL in high impedance state
The voltage Yi of −i causes a voltage change by following the waveform of the ramp voltage generating circuit 400.

Letting ΔV _COM be the amount of change in the lamp drive voltage immediately after the end of the write period tw, the data signal line D
The voltage change amount ΔV _D2 of L−i is ΔV _D2 = ΔV _COM × (C
_DC / (C _DC + C _GD1 )). Data signal line DL-i
13, the wiring capacitance C _DC between the data signal line DL-i and the common electrode 22 and the wiring capacitance C between the data signal line DL-i and the scanning signal line SL-j are as shown in FIG.
_Although it is _GD1 , since the wiring capacitance C _GD1 is smaller than the wiring capacitance C _GD of the first embodiment, the wiring capacitance C _DC becomes dominant. Then, since C _DC >> C _GD1 , ΔV _D = ΔV
The data signal line D becomes _COM immediately after the period tw ends
The difference between the potential difference between the voltage V _{CO M,} and the potential difference between the voltage Yi and the voltage V _COM when the scanning signal line SL-j is turned off in the L-i voltage Yi and the common electrode 22 becomes small. When the voltage of the scanning signal line SL-j changes from the ON state to the OFF state, the voltage V _P of the pixel electrode 11 written by the TFT 12 causes a voltage fluctuation due to the influence of the parasitic capacitance C _GS of the TFT 12. Therefore, the central value of the voltage V _COM applied to the common electrode 22 is adjusted so that the potential difference V _LC between the pixel electrode 11 and the common electrode 22 becomes uniform during the writing of the positive polarity and the negative polarity. Pixel electrode 11
Of the voltage V _P and the voltage V _COM applied to the common electrode 22 via the TFT 12, the potential difference V _LC changes in accordance with the length of the period tw. After the end of the period tw, the potential difference V _LC maintains a constant level, and when one scanning time ends, the potential difference V _LC has a waveform that changes in voltage. The liquid crystal panel is displayed based on the potential difference V _LC . As described above, in the present embodiment, the data signal line DL-i and the scanning signal line SL are arranged at the intersection of each data signal line DL-i and the scanning signal line SL-j with respect to the first embodiment. Both or one of -j is formed thin, and the wiring capacitance C _GD1 between the data signal line DL-i and the scanning signal line SL-j is reduced. Therefore, in the high impedance state, the potential V _P of the pixel electrode 11 can be surely changed in the same manner as the waveform of the lamp driving voltage, and in addition to the advantages of the first embodiment, high display quality and high image quality can be achieved. The active matrix type liquid crystal display can be realized.

Fourth Embodiment FIG. 15 is a circuit diagram showing an outline of an active matrix type liquid crystal display according to a fourth embodiment of the present invention.
Elements common to those in FIGS. 1 and 12 of the first embodiment and the second embodiment are designated by common reference numerals. This liquid crystal display has the same configuration as that of the first and second embodiments except that it has a TFT-LCD section TC4 different from that of FIG. FIG. 16 is a diagram illustrating the TFT-LCD of FIG. In the present embodiment, as shown in FIG. 14, the structure of each liquid crystal cell is such that the data signal line DL-i and the scanning signal line SL- are formed at the intersection of each data signal line DL-i and the scanning signal line SL-j. Both or one of j is formed thin as in the third embodiment, and the auxiliary capacitance electrode and the auxiliary capacitance line CL are provided in the same configuration as that of the second embodiment shown in FIG. A storage capacitor C _h is formed by the insulating film / pixel electrode 11, and the potential V _COM of the common electrode 22 is applied to the storage capacitor line CL.

Next, the operation of the liquid crystal display of this embodiment will be described. Similar to the first and second embodiments, scanning is performed to sequentially activate each scanning signal line SL-j by turning it on. In the display signal circuit 300, the pulse width conversion circuit 310 converts the grayscale display data into a pulse width modulation signal PO-i which is an ON signal only for a period according to the weighting. Each switch 320-j in the switch unit 320 is
As shown in FIG. 11, the reference voltage Vs is output in the conductive state. When the switches 320-j are opened, the data signal lines DL-i are set to the high impedance state. That is, the pulse width conversion circuit 3 of the display signal circuit 300
10 to the pulse width modulation signal PO− according to each intermediate gradation value
i is supplied to the analog switches 320-1 to 320-m, respectively, and the analog switches 320-1 to 320
-M supplies the luminance data signals _{Y i} as a reference voltage V _s in the writing period tw for each signal line DL-i. When the period tw ends, the data signal line DL-i is set to the high impedance state. In the high impedance state, the voltage is held by the charges accumulated in the wiring capacitance associated with the data signal line DL-i. Here, since the lamp voltage is supplied to the common electrode 22 and the auxiliary capacitance line CL, the wiring capacitance between the data signal line DL-i and the common electrode 22 and between the data signal DL-i and the auxiliary capacitance line CL. The ramp voltage is supplied to the data signal line DL-i via the wiring capacitance. The voltage Yi of the data signal line DL-i in the high impedance state is the same as the ramp voltage generation circuit 4
A voltage change occurs following the waveform of 00.

The writing period tw exit ramp drive voltage amount of change [Delta] V _COM from immediately after, and when each data signal line wiring capacitance between the auxiliary capacitance line CL to's and C _DS, the data signal line DL-i voltage The amount of change ΔV _D3 is ΔV _D3 = ΔV _COM
X ((C _DC + C _DS ) / (C _DC + C _DS + C _GD1 )). The wiring capacitance associated with the data signal line DL-i is shown in FIG.
4, the wiring capacitance C _DC between the data signal line DL-i and the common electrode 22, the wiring capacitance C _GD1 between the data signal line DL-i and the scanning signal line SL-j, and the data signal line DL-i.
And the wiring capacitance C _DS between the auxiliary capacitance and the auxiliary capacitance, and the influence of the wiring capacitance C _GD1 becomes smaller than that in the third embodiment. Therefore, the potential difference between the voltage Yi of the data signal line DL-i and the voltage V _COM of the common electrode 22 immediately after the end of the period tw and the voltage Y when the scanning signal line SL-j is turned off.
The difference between i and the potential difference of the voltage V _COM becomes smaller.
When the voltage of the scanning signal line SL-j changes from the ON state to the OFF state, the pixel electrode 1 written by the TFT 12
The voltage V _P of 1 is affected by the parasitic capacitance C _GS of the TFT 12,
Causes voltage fluctuations. Therefore, the central value of the voltage V _COM applied to the common electrode 22 is adjusted so that the potential difference V _LC between the pixel electrode 11 and the common electrode 22 becomes uniform during the writing of the positive polarity and the negative polarity. Due to the voltage V _P of the pixel electrode 11 and the voltage V _COM given to the common electrode 22 via the TFT 12, the potential difference V _LC changes in voltage corresponding to the length of the period tw. After the end of the period tw, the potential difference V _LC
Maintains a constant level and has a waveform that changes voltage when one scanning time is completed. The liquid crystal panel is displayed based on the potential difference V _LC .

As described above, this embodiment is different from the first embodiment in that each data signal line DL-i and scanning signal line SL-.
At the intersection of j, either or both of the data signal line DL-i and the scanning signal line SL-j are thinly formed, and
The auxiliary capacitance electrode, the auxiliary capacitance line CL, and the auxiliary capacitance C _h are formed in the same configuration as in the second embodiment, and the auxiliary capacitance line C is formed.
The potential V _COM of the common electrode 22 is applied to L. for that reason. The influence of the wiring capacitance C _GD1 between the data signal line DL-i and the scanning signal line SL-j is further reduced as compared with the third embodiment. Therefore, in the high impedance state, the potential V _P of the pixel electrode 11 can be surely changed in the same manner as the waveform of the lamp driving voltage, and an active matrix type liquid crystal display with high display quality and high image quality can be realized. it can.

Fifth Embodiment FIG. 17 is a circuit diagram schematically showing an active matrix type liquid crystal display according to the fifth embodiment of the present invention.
Elements common to those in FIG. 1 according to the embodiment of FIG. This liquid crystal display is provided with a scanning signal circuit 500 different from that of the first embodiment shown in FIG. 1, and the other circuits have the same configuration as that of the first embodiment. Figure 18
FIG. 18 is a configuration block diagram showing a scanning signal circuit in FIG. 17.
The scanning signal circuit 500 includes a conversion unit 510 that is a lamp voltage driving unit and a scanning signal driver 520 that is a scanning signal conversion unit that is connected to the output side of the conversion unit 510. A control signal conversion unit 511 for inputting the scanning control signal SC from the input terminal and a power supply voltage conversion unit 512 connected to the scanning power supply potential V are provided. Control signal conversion circuit 5
11 and the output of the power supply voltage conversion circuit 512 are supplied to the scanning signal driver 520, respectively.

FIG. 19 is a circuit diagram showing the structure of the control signal conversion circuit in FIG. This control signal conversion circuit 511
Is the two photocouplers 5 to which the logic power supply V _L and the conversion logic power supplies V _{CL (+)} and V _{CL (-)} are applied.
11a and 511b. These photocouplers 511a and 511b receive the scanning clock signal CK and the scanning data signal DT, respectively, and convert the scanning voltage to the conversion logic power supply levels V _{CL (+)} and V _{CL (− )} and the conversion scanning clock signal HCK and conversion. It has a function of generating the scan data signal HDT and supplying them to the driver unit 520. On the other hand, the power supply voltage conversion circuit 512 has the same configuration as the lamp voltage generation circuit 400 of FIG. 10, and has a function of supplying the lamp drive voltage to the driver unit 520. The scan signal driver 520 superimposes the ramp waveform on the converted scan clock signal and the converted scan data signal according to the polarity and sends the superimposed scan waveform to each scan signal line SL-j.

Next, FIG. 20 is a diagram showing voltage waveforms of the liquid crystal cell in FIG. 17, and the operation of the liquid crystal display of FIG. 17 will be described with reference to this diagram. Display signal circuit 300
In, the pulse width conversion circuit 310 converts the gray scale display data into a pulse width modulation signal PO-i which becomes an ON signal only for a period according to the weighting. Each switch 320-j in the switch unit 320 outputs the reference voltage V _s in the conductive state as shown in FIG. And each switch 3
When 20-j is opened, each of the data signal lines DL-i is set to a high impedance state. That is, the pulse width modulation signal PO-i corresponding to each intermediate gradation value is output from the pulse width conversion circuit 310 of the display signal circuit 300 to the analog switch 3.
20-1 to 320-m, and the analog switches 320-1 to 320-m are supplied to the write period tw.
The luminance data signal Y _i, which is the reference voltage V _s , to each signal line D
Supply to L-i. When the period tw ends, the data signal line DL-i is set to the high impedance state.
In the high impedance state, the data signal line DL-
The voltage is held by the charges accumulated in the wiring capacitance associated with i.

The wiring capacitance associated with the data signal line DL-i is the capacitance C between the data signal line DL-i and the common electrode 22.
_DC and the capacitance C _GD between the data signal line DL-i and the scanning signal line SL-j, the scanning signal line SL- _j is supplied with the voltage X _j on which the lamp driving voltage is superimposed, and the data signal line DL
This means that the lamp drive voltage has been supplied to all the wiring capacities associated with -i. Therefore, in the high impedance state, the ramp voltage is supplied to the data signal line DL-i, and the voltage Yi of the data signal line DL-i follows the waveform of the ramp voltage generation circuit 400 and causes a voltage change. The voltage Y of the data signal line DL-i immediately after the end of the period tw
The potential difference between i and the voltage V _COM of the common electrode 22 is equal to the potential difference between the voltage Yi and the voltage V _COM when the scanning signal line SL-j is turned off. Voltage V in this state
Displayed on _LC . When the voltage of the scanning signal line SL-j changes from the ON state to the OFF state, the voltage V _P of the pixel electrode 11 written by the TFT 12 causes a voltage fluctuation due to the influence of the parasitic capacitance C _GS of the TFT 12. Therefore, the central value of the voltage V _COM applied to the common electrode 22 is adjusted so that the potential difference V _LC between the pixel electrode 11 and the common electrode 22 becomes uniform during the writing of the positive polarity and the negative polarity. As a result, the voltage V _LC supplied to the liquid crystal cell is as shown in FIG.
It becomes like 0. As described above, in the present embodiment, since the lamp driving voltage is superimposed on the scanning signal line as compared with the first embodiment, the potential V _P of the pixel electrode 11 in the high-impedance state is surely changed to the waveform of the lamp driving voltage. It is possible to realize the high-quality active matrix type liquid crystal display which can be changed in the same manner and which has a higher display quality than the first embodiment.

Sixth Embodiment FIG. 21 is a circuit diagram showing the outline of the active matrix type liquid crystal display of the sixth embodiment of the present invention.
Elements common to the elements in FIG. 17 of the embodiment of FIG. The circuit of this liquid crystal display is shown in FIG.
Unlike, except that the TFT-LCD section TC2 is provided,
The configuration is similar to that of the fifth embodiment. TFT-LCD section T
C2 has the same configuration as that used in the second embodiment. That is, in the fifth embodiment, an auxiliary capacitance electrode (not shown) is provided on the back surface of each pixel electrode 11 of the TFT-LCD section TC1 via an insulating film, and each data signal line DL-i and an insulating layer (not shown) are provided. Auxiliary capacitance lines CL, which are directly arranged via the auxiliary capacitance electrodes and are connected to the auxiliary capacitance electrodes, are provided, and auxiliary capacitances C _h are respectively formed by the respective auxiliary capacitance electrodes / insulating films / pixel electrodes 4, and the auxiliary capacitance lines CL are common. The potential V of the electrode 22
It is designed to apply _COM . The operation of the liquid crystal display of FIG. 21 is similar to that of the fifth embodiment, but the wiring capacitance C _GD between the data signal DL-i and the scanning signal line SL-j is used.
Becomes smaller than that in the fifth embodiment, and the potential difference between the voltage Yi of the data signal line DL-i and the voltage V _COM of the common electrode 22 immediately after the end of the period tw and the scanning signal line SL.
The voltage Yi and the voltage V when -j is turned off
The difference from the potential difference from _COM is even smaller than in the fifth embodiment. As described above, since the auxiliary capacitance C _h is provided in each pixel electrode 11 of the liquid crystal panel and the lamp driving voltage is applied to the auxiliary capacitance C _h via the auxiliary capacitance line CL as compared with the fifth embodiment. A waveform of the lamp driving voltage is tracked by the wiring capacitance associated with the data signal line DL-i.
In the higher impedance state, the potential V _P of the pixel electrode 11 can be surely changed in the same manner as the waveform of the lamp driving voltage, and an active matrix type liquid crystal display with high display quality can be realized. There is an advantage that can be done.

Seventh Embodiment FIG. 22 is a circuit diagram showing the outline of an active matrix type liquid crystal display of the seventh embodiment of the present invention.
Elements common to the elements in FIG. 17 of the embodiment of FIG. This liquid crystal display has the same structure as that of the fifth embodiment except that it has a TFT-LCD section TC5 different from that shown in FIG. TFT-LCD section TC5
Is provided with an auxiliary capacitance electrode (not shown) on the back surface of each pixel electrode 11 via an insulating film, and the scanning signal line S connected to the pixel electrode 11 corresponding to the auxiliary capacitance electrode via the TFT 12.
The scanning signal line SL-j-1 in the preceding stage of L-j and the auxiliary capacitance electrode are connected to form an auxiliary capacitance C _h . That is,
An auxiliary capacitance C _h is provided between each pixel electrode and the preceding scanning signal line SL-j-1. The operation of the liquid crystal display of FIG. 22 is the same as that of the fifth embodiment, but the lamp drive voltage is applied to the auxiliary capacitance C _h from the preceding scanning signal line SL-j-1 and the data in the high impedance state is obtained. Signal DL-
The potential of i is changed. Therefore, the voltage Yi of the data signal line DL-i and the common electrode 2 immediately after the period tw ends.
The difference between the potential difference with the second voltage V _COM and the potential difference between the voltage Yi and the voltage V _COM when the scanning signal line SL-j is turned off is smaller than that in the fifth embodiment.

As described above, in this embodiment, the auxiliary capacitance C _h is added to each pixel electrode 11 of the liquid crystal panel as compared with the fifth embodiment.
The provided previous scan signal line SL with respect to each of the auxiliary capacitance C _h
The lamp driving voltage is applied from -j-1. Therefore, the potential V _P of the pixel electrode 11 in the high-impedance state is more reliably made to be the waveform of the lamp drive voltage than in the fifth embodiment in which the waveform of the lamp drive voltage is tracked by the wiring capacitance associated with the data signal line DL-i. There is an advantage that an active matrix type liquid crystal display of high image quality with high display quality can be realized, which can be changed in the same manner. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) In the second, fourth, and sixth embodiments, either one or both of the auxiliary capacitance line CL and the data signal line DL-i at the intersection of the auxiliary capacitance line CL and the data signal line DL-i. By increasing both widths, the wiring capacitance Cs between the auxiliary capacitance line CL and the data signal line DL-i is increased in FIG. 16, and the followability to the lamp driving voltage of the data signal line DL-i is improved. You can (2) Even if the TFT-LCD sections TC1 to TC5 in the first to seventh embodiments are liquid crystal displays having other configurations having similar signal lines, the respective embodiments can be applied. (3) Each scanning signal circuit 1 in the first to seventh embodiments
00, 500, the display signal circuit 300, and the ramp voltage generation circuit 400 can be applied in the same manner as in the first to seventh embodiments even if they are configured by other circuits that supply the same drive waveform.

[0036]

As described in detail above, according to the first aspect of the present invention, the drive voltage of the liquid crystal cell is supplied to the data signal line during the period corresponding to the video input signal, and the high impedance state is kept during the period other than the period. Since the active matrix type liquid crystal display is equipped with the display signal circuit for outputting to the signal line and the common electrode driving circuit for supplying the lamp driving voltage to the common electrode, the output stage of the display circuit for each data signal line is, for example, an analog switch. Can be composed of Therefore, a liquid crystal display with low power consumption, high image quality, and high integration can be realized. According to the second invention, the active matrix liquid crystal display of the first invention is provided with the auxiliary capacitance and the auxiliary capacitance line, and the lamp driving voltage is applied to the auxiliary capacitance line. The followability of the line to the lamp driving voltage is improved, and it is possible to display a higher quality and higher quality image than the first aspect of the invention. According to the third invention, in contrast to the first or second invention, the width of either one or both of the data signal line and the scanning signal line is narrowed only at the intersections. Therefore, the wiring capacitance between the data signal line and the scanning signal is reduced without increasing the resistance of each data signal line and the scanning signal. Therefore, the followability to the lamp driving voltage of the data signal line in the high impedance state is further improved, and a high-quality and high-quality image is displayed as compared with the active matrix type liquid crystal display of the first or second invention. You can

According to the fourth aspect of the invention, the width of one or both of the auxiliary capacitance line and the data signal line is widened at the intersection of the auxiliary capacitance line and the data signal line in the second aspect. Therefore, the followability to the lamp drive voltage of the data signal line in the high impedance state is further improved as compared with the active matrix liquid crystal display of the second invention, and a high quality and high quality image can be displayed. According to the fifth invention, since the scanning signal circuit in the first or second invention is configured to superimpose the lamp driving voltage on the scanning signal, the first or second invention is different from the first or second invention. Alternatively, the followability of the data signal line to the lamp drive voltage in the high impedance state is improved as compared with the second aspect, and a high quality and high quality image can be displayed. According to the sixth invention, in the fifth invention, since the auxiliary capacitance is provided between the pixel electrode and the scanning signal line in the preceding stage of the scanning signal line connected to the pixel electrode via the thin film transistor, As compared with the fifth aspect of the invention, the followability of the data signal line to the lamp driving voltage in the high impedance state is improved, and a high quality and high quality image can be displayed.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram of an active matrix type liquid crystal display showing a first embodiment of the present invention.

FIG. 2 is a perspective view showing a schematic structure of a conventional TFT-LCD.

3 is a diagram showing electro-optical characteristics of the TN liquid crystal cell of FIG.

FIG. 4 is a schematic circuit diagram of a conventional active matrix type liquid crystal display.

5 is a diagram showing an equivalent circuit of the liquid crystal cell in FIG.

6 is a drive timing chart of the active matrix type liquid crystal display shown in FIG.

7 is a diagram showing a configuration of output stages of an analog driver and a digital driver in the display signal circuit of FIG.

8 is a configuration block diagram showing a display signal circuit in FIG. 1. FIG.

9 is a circuit diagram showing one output of the pulse conversion unit in FIG.

FIG. 10 is a circuit diagram showing a ramp voltage generating circuit in FIG.

11 is a diagram showing voltage waveforms of the liquid crystal cell in FIG.

FIG. 12 is a circuit diagram schematically showing an active matrix type liquid crystal display according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram showing the outline of an active matrix type liquid crystal display according to a third embodiment of the present invention.

FIG. 14 is a diagram illustrating the TFT-LCD of FIG.

FIG. 15 is a circuit diagram schematically showing an active matrix type liquid crystal display according to a fourth embodiment of the present invention.

16 is a diagram illustrating the TFT-LCD of FIG.

FIG. 17 is a circuit diagram showing the outline of an active matrix type liquid crystal display according to a fifth embodiment of the present invention.

18 is a configuration block diagram showing a scanning signal circuit in FIG.

19 is a circuit diagram showing a configuration of a control signal conversion circuit in FIG.

20 is a diagram showing voltage waveforms of the liquid crystal cell in FIG.

FIG. 21 is a circuit diagram showing an outline of an active matrix type liquid crystal display according to a sixth embodiment of the present invention.

FIG. 22 is a circuit diagram schematically showing an active matrix type liquid crystal display according to a seventh embodiment of the present invention.

[Explanation of symbols]

 10 Rear Substrate 11 Pixel Electrode 12 TFT 13,23 Polarizing Film 20 Front Substrate 21 Color Filter 22 Common Electrode 30 Liquid Crystal Layer 100,500 Scanning Signal Circuit 300 Display Signal Circuit 400 Lamp Voltage Generating Circuit DL-i Data Signal Line SL-j Scanning Signal line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiromasa Sugano 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (6)

[Claims] 1. A translucent rear substrate, a plurality of data signal lines and scanning signal lines which are arranged and formed on the rear substrate so as to intersect each other with an insulating layer interposed therebetween, and each of the data signal lines and scanning. A plurality of thin film transistors respectively connected to the intersections of the signal lines corresponding to respective pixel electrodes, a translucent front substrate arranged to face the rear substrate, and pixels of each liquid crystal cell on the front substrate. A color filter corresponding to a display color provided in a portion facing the electrode, a translucent common electrode provided on the color filter, and a surface of the back substrate and the front substrate are provided to face each other. An alignment film that has been subjected to an alignment treatment in a predetermined direction, a liquid crystal layer interposed between the alignment film on the back substrate and the front substrate side, and a polarizing film attached to the back surface of the back substrate and the front substrate, respectively. Having active matrix -Type liquid crystal panel, a display signal circuit that outputs a driving voltage of each liquid crystal cell to the pixel electrode via the data signal line and the thin film transistor according to a video input signal, and a conduction state of each thin film transistor is controlled. And a common electrode drive circuit for driving the common electrode, and a gray scale display corresponding to the input signal by AC driving the active matrix type liquid crystal panel. In the active-matrix liquid crystal display, the display signal circuit sets a pulse width conversion unit that generates a pulse width modulation signal that sets a pulse width according to the gradation of the video input signal, and the pulse width modulation signal. The driving voltage of the liquid crystal cell is sent to the data signal line for a predetermined period,
The liquid crystal cell is composed of a switch unit which sends a high impedance state to each of the data signal lines except during a driving voltage sending period, and the common electrode driving circuit sequentially increases or decreases depending on the polarity in the AC driving. An active matrix type liquid crystal display, characterized in that the lamp driving voltage is transmitted to the common electrode. 2. An auxiliary capacitance and an auxiliary capacitance line for applying a voltage to the auxiliary capacitance are provided for each of the pixel electrodes, and the lamp driving voltage is applied to each of the auxiliary capacitance lines. The active matrix type liquid crystal display according to claim 1. 3. The active matrix type liquid crystal display according to claim 1, wherein either one or both of the data signal line and the scanning signal line have a narrow width only at the intersecting portion. 4. The active element according to claim 2, wherein either or both of the auxiliary capacitance line and the data signal line have a large width at the intersection of the auxiliary capacitance line and the data signal line. Matrix type liquid crystal display. 5. The scan signal circuit includes a lamp voltage drive unit that generates a lamp drive voltage that sequentially increases or decreases according to the polarity of AC drive, and a scan signal conversion that superimposes the lamp drive voltage on the scan signal. 3. The active matrix type liquid crystal display according to claim 1 or 2, wherein the active matrix type liquid crystal display is formed of: 6. An auxiliary capacitance is provided between the pixel electrode and a scanning signal line preceding the scanning signal line connected to the pixel electrode via a thin film transistor.
The active matrix liquid crystal display described.