JP3160143B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix liquid crystal display device, and more particularly to a liquid crystal display device of the digital gradation display.

[0002]

As a conventional liquid crystal display device of active matrix type digital tone, such as those described in Nikkei BP published "Flat Panel Display 91 173 pp 180 pp" is standard.

FIG . 2 shows an example of a conventional liquid crystal display device. An active matrix liquid crystal display device can be roughly divided into a pixel matrix portion, a signal line driver circuit, and a scan line driver circuit. Hereinafter, the operation will be described with reference to the drawings.

In a pixel matrix, signal lines and scanning lines are arranged in a matrix, and pixel TFTs are arranged at intersections thereof.
The gate of the pixel TFT is connected to the scanning line, the source is connected to the signal line, and the drain is connected to the pixel electrode. In general, a liquid crystal capacitance between a pixel electrode and a counter electrode cannot have a large value, and therefore, a storage capacitor for holding electric charges is arranged near the pixel electrode. When a voltage exceeding the threshold voltage of the TFT is applied to the scanning line and the TFT is turned on, TF
The drain and source of T are short-circuited, the voltage of the signal line is applied to the pixel electrode, and the liquid crystal and the storage capacitor are charged. When the TFT is turned off, the drain is open,
The charge stored in the liquid crystal and the storage capacitor is held until the next time the TFT is turned on.

[0005] Figure 3 shows an example of a signal line driver circuit 4 and tone. Basic operation even if will be described here in the case of 4-gradation but the gradation number is different is the same. Digital tone signal is shifted from the input terminal 302 and 303 register 310,31
1 is input. Outputs of the shift registers 310 and 311 are input to shift registers 312 and 313 and latch circuits 314 and 315 of the next stage, and the latch circuits hold data for a certain period. This holding period is determined by the horizontal synchronization signal input to the input terminal 304. The output signal of the latch circuit is input to the decoder 316, and the 2-bit digital signal is converted into four voltage selection signals by the decoder. This voltage either switch transistor 317-320 is selected by the selection signal, either the potential of the gradation voltage lines 305 to 308 is transmitted to the signal line 309.

FIG . 4 shows an example of a scanning line driving circuit. The scanning line driving circuit includes a shift register and NAND circuits 403 and 40.
4. It is composed of inverter type buffers 405 and 406 , inputs a start pulse synchronized with a vertical synchronization signal and a clock synchronized with a horizontal synchronization signal, and sequentially drives scanning lines.

[0007]

Problems to be Solved by the Invention The above-mentioned conventional liquid crystal display device has the following two problems.
The first problem is that when the TFT is in an off state, a leak current flows between the drain and the source, and the electric charge of the pixel is discharged and the potential fluctuates.

FIG. 5 shows the drain current and gate voltage characteristics of a general N-channel TFT. As can be seen from FIG. 5, even when the gate voltage is negative, the current flows to the drain.
Is flowing. This current causes the discharge of electric charges. Although the description has been given of the N-channel TFT, the same applies to the P-channel TFT.

Normally, since the writing cycle of the pixel is 100 Hz or less, the holding time is 10 msec or more. To take as long as possible holding time, the holding capacity to the liquid crystal in parallel
Although it is common to put a can not only up 0.1pF~0.2pF together with the retention capacity of the liquid crystal. Assuming that the holding time of the pixel is 16.6 msec (60 Hz), the voltage applied to the liquid crystal is 5 V, the holding ratio is 99%, and the capacitance is 0.2 pF, the allowable leak current of the TFT is 5 × (1−0.99). × 0.2 pF / 16.6 msec = 0.6 pA, and it is difficult to realize this value including the operating temperature range and the variation of the TFT, so that the electric charge of the pixel is discharged and the image quality is deteriorated. .

The second problem is that in the operation of the TFT, when the scanning line potential changes from a high potential to a low potential or from a low potential to a high potential, the drain potential is reduced by the capacitance between the gate and drain of the TFT. Is drawn in the direction in which the scanning line potential changes by ΔV shown in FIG. △ V = V × Cgd / ( Cgd + Clc + Cstg) where, V is the capacitance value Clc is the capacitance value This phenomenon of capacitance Cstg storage capacitor of the liquid crystal between the gate and the drain of the fluctuation range Cgd of the scanning line potential TFT, FIG. 6 As shown in (2), the potential of the pixel electrode shifted below the center, causing deterioration of the liquid crystal.

The liquid crystal display device of the present invention solves these two problems. The purpose of the present invention is to be able to hold data regardless of the length of the holding time and to reduce the number of scanning lines. An object is to provide a liquid crystal display device in which a holding potential does not change due to a change in potential.

[0012]

Means for Solving the Problems A liquid crystal display device of the present invention, as the time gradation method to gradation display method, the voltage applied to the pixel is only binary and, for one pixel,
It has one digital storage circuit, and its output is connected to a pixel electrode.

[0013]

According to the present invention, the potential of the signal line is taken into the digital storage circuit by the signal of the scanning line, and the potential is held for a certain period. Since the pixel electrode is connected to the output of the digital storage circuit, a high potential or a low potential of the digital storage circuit is applied as long as the storage circuit is in a holding state.

[0014]

FIG . 1 shows an embodiment of the present invention. The time gray scale method is a method of issuing a halftone switching temporally white as shown in FIG. The operation of the signal line driving circuit of this embodiment will be described. Time modulated digital tone signals are input from the input terminal 102 to the shift register 109, the output of the shift register 109 are input to the shift register 110 and latch circuit 111 of the next stage, the latch circuit 111 is a period of time data Is held. This holding period is determined by the horizontal synchronization signal input to the input terminal 103. Outputs of the latch circuits 111 and 112 are buffer circuits 113, 114, 115 and 116 of an inverter type.
Are output to the signal lines 106 and 107 via the. The data of the signal line is converted into digital storage circuits 117, 118, 119, and 120 arranged near each pixel electrode by a scanning line signal.
Get absorbed in. This storage state is held until the next scanning line signal is received.

FIG . 8 shows an example of a pixel area and a digital storage circuit. This digital storage circuit has TFTs 807 and 80
8 and two inverters composed of TFTs 809 and 810. When the TFT 806 is turned on, the storage circuit and the signal line 802 are short-circuited and data is taken in. Since the output of the storage circuit is directly connected to the pixel electrode, the potential of the pixel electrode is fixed to one of the high potential side and the low potential side of the power supply potential of the storage circuit. As described above, since the potential of the pixel is not stored in the capacitor as in the conventional example and is held by the data of the storage circuit instead of holding the potential, the potential fluctuation due to the leak current of the pixel TFT and the TF
No potential change due to T-off occurs, and the image quality is improved.

Since the liquid crystal element 811 is deteriorated when a DC voltage is applied for a long period of time, in this embodiment, the power supply potentials 803 and 804 of the digital storage circuit are set to have the same amplitude as the output amplitude and a specific frequency (vertical synchronization frequency). Such)
, And the voltage applied to the liquid crystal is 0 on average.
I am trying to be. This relationship is shown in FIG . Figure
10 (A) is a logical output of the digital storage circuit, FIG.
FIG. 10B shows a high-potential-side power supply voltage of the digital storage circuit, and FIG.
FIG. 10C shows a low-potential-side power supply voltage of the digital storage circuit,
(D) shows the waveform of the voltage applied to the liquid crystal, respectively.
I have. Normally, when driving a liquid crystal, an applied voltage of about 5 V
Is necessary, but when the time gray scale is used, the light transmittance 100
% And 0%, the applied voltage is, for example, 2V of 0V and 5V.
Value. The logic output in FIG.
The low-potential-side power supply becomes the high-potential-side power supply at a low level. This
And the power supply shown in FIGS. 10B and 10C
FIG. 10D shows a waveform obtained by combining the driving. Yo
In this case, the output of the digital storage circuit is the power supply potential.
Input, the high-potential-side power supply voltage terminal 803 of the memory circuit
5V, the low potential side power supply voltage terminal 804 and the opposite
The potential of the pole terminal 805 may be set to 0V. As mentioned above
In addition, liquid crystal deteriorates when DC is applied for a long time, so AC drive
However, the potential of the counter electrode terminal 805 is fixed to 0 V.
And through the power supply voltage terminal as shown in FIG.
AC voltage, for example, a specific frequency such as the vertical synchronization frequency
It is driven by several AC voltages. Here, the counter electrode terminal 805
Is fixed to 0 V, and the low potential side voltage of the digital storage circuit is fixed.
-5V to the source voltage terminal 804, the high potential side power supply voltage terminal 80
If a voltage of 0V is applied to 3, black is displayed
5V is applied to the liquid crystal and the output of the digital storage circuit
Needs to be -5V. Also, to display white
Requires that the output of the digital storage circuit be 0V.
You. Thereby, the potential of the counter electrode terminal 805 is set as a reference.
Then, a voltage of -5 V or 0 V is applied to the liquid crystal.
Will be. Next, after a certain time, the low-potential-side power supply voltage terminal
0V at 804 and 5V at the high potential side power supply voltage terminal 803
Then, 5V is applied to the liquid crystal to display black,
The output of the digital storage circuit needs to be 5V. Ma
In order to display white, the output of the digital storage circuit
Needs to be set to 0V. With this, the counter electrode terminal
+ 5V or 0V is applied to the liquid crystal based on the potential of
ing. As is clear from the above explanation,
Voltage is zero on average to avoid liquid crystal degradation
Can be.

FIG . 9 shows a second example of the storage circuit. TFT
An inverter is constituted by 908 and 910 and resistors 907 and 909, and a storage circuit is constituted. Example shown in FIG.
However, the high potential side power supply voltage terminal 903 and the low potential side power supply voltage terminal
The voltage is applied to the terminal 904 and the counter electrode
By driving, it operates in the same manner as the embodiment shown in FIG.
You. In the case of this embodiment, it is possible to use only one type of polarity of the TFT in the pixel matrix.

[0018]

As described in the foregoing, the present invention is a time gradation display method of the gradation display method, and, for one pixel electrode, it is possible to give the potential by one by one of the digital storage device In addition, there is an effect that the potential of the pixel electrode can be kept constant, and thereby an effect that the image quality is improved.

[Brief description of the drawings]

FIG. 1 shows an embodiment of a signal line driving circuit of a liquid crystal display device of the present invention.

FIG. 2 shows a block diagram of an active matrix liquid crystal display device.

FIG. 3 shows an example of a conventional signal line driving circuit.

FIG. 4 illustrates an example of a scanning line driver circuit.

FIG. 5 shows drain current and gate voltage characteristics of a TFT.

FIG. 6 shows retention characteristics of a pixel.

Figure 7 shows the operation of a time gradation.

FIG. 8 shows an embodiment of a pixel and a digital storage circuit.

FIG. 9 illustrates an embodiment of a pixel and a digital storage circuit.

FIG. 10 shows digital storage circuit power supply voltage and liquid crystal voltage characteristics. Clock input terminal: 101 Start pulse input terminal: 102 Horizontal synchronization signal input terminal: 103 Scan line: 104, 10
5 signal lines: 106, 10
7 Counter electrode connection terminal: 108 Shift register: 109, 11
0 Latch circuit: 111, 11
2 Inverter type buffer: 113 to 11
6 Digital storage circuit: 117-12
0 liquid crystal: 121-12
4 Pixel matrix: 200 Signal line: 201 to 20
3 scanning lines: 204-20
6 TFT: 207-21
0 liquid crystal: 211-21
4 Retention capacity: 215 to 21
8 Clock input terminal: 301 Start pulse input terminal: 302, 30
3 horizontal synchronizing signal input terminal: 304 gradation voltage terminal: 305-30
8 Signal line connection terminal: 309 Shift register: 310-31
3 Latch circuit: 314, 31
5 Decoder: 316 TFT: 317-32
0 Clock input terminal: 401 Start pulse input terminal: 402 NAND: 403, 40
4 Inverter type buffer: 405, 40
6. Scanning line connection terminals: 407, 40
8 Scanning line: 801 Signal line: 802 Storage circuit power supply terminal: 803, 80
4 Counter electrode terminal: 805 TFT: 806 to 81
0 Liquid crystal: 811 Scan line: 901 Signal line: 902 Storage circuit power supply terminal: 903, 90
4 Counter electrode terminal: 905 TFT: 906, 90
8,910 Liquid crystal: 911 Resistor: 907, 90
9

Claims (6)

(57) [Claims] 1. A liquid crystal display comprising: a first substrate having an insulating surface; a second substrate having an insulating surface; and a liquid crystal provided between the first substrate and the second substrate. In the device, a plurality of pixel electrodes, a plurality of signal lines, a plurality of scanning lines, and a plurality of digital storage circuits including a plurality of TFTs are provided over the first substrate; A counter electrode is provided on the substrate, data is input from the signal line to the digital storage circuit by a scanning line signal from the scanning line, and the digital storage circuit scans the next scanning line after the scanning line signal. The data is held until another data different from the data is input to the digital storage circuit from the signal line by a signal, and the digital storage circuit stores the digital storage by the signal input from the signal line. High potential side power supply potential of the power supply of the road, or the power source potential of low potential side power supply is supplied to the pixel electrode, the high-potential side power source and the low potential side power supply is characterized by being driven ac Liquid crystal display. 2. A liquid crystal display comprising: a first substrate having an insulating surface; a second substrate having an insulating surface; and a liquid crystal provided between the first substrate and the second substrate. In the device, a plurality of pixel electrodes, a plurality of signal lines, a plurality of scanning lines, a plurality of digital storage circuits including a plurality of inverters, a source region, a drain region, and a gate electrode are provided over the first substrate. A plurality of switching TFTs, a counter electrode is provided on the second substrate, and a source region or a drain region of the switching TFT is connected to the signal line or the digital storage circuit. A gate electrode of the switching TFT is connected to the scanning line; a digital storage circuit is connected to each of the pixel electrodes; and each of the inverters has a plurality of TFTs. , The scanning line signal from the scan line of the switching TFT
Data is input to the digital storage circuit from the signal line by the input to the gate electrode of the switching TFT, and the digital storage circuit inputs the next scanning line signal of the scanning line signal to the gate electrode of the switching TFT. until holding the data that the digital memory circuit, the signal input from the signal line, the select the high potential side power supply power supply potential or the power source potential on the low potential side power supply, the digital storage circuit It is supplied to the pixel electrode, the high-potential side power source and the low potential side power source, a liquid crystal display device, characterized in that driving exchanges. 3. A liquid crystal display comprising: a first substrate having an insulating surface; a second substrate having an insulating surface; and a liquid crystal provided between the first substrate and the second substrate. In the device, a plurality of pixel electrodes, a plurality of signal lines, a plurality of scanning lines, a plurality of digital storage circuits including a plurality of inverters, a source region, a drain region, and a gate electrode are provided over the first substrate. A plurality of switching TFTs, a counter electrode is provided on the second substrate, each inverter has a plurality of TFTs and a plurality of resistors, and a source region of the switching TFT. Alternatively, a drain region is connected to the signal line or the digital storage circuit, a gate electrode of the switching TFT is connected to the scanning line, and the digital storage circuit is It is connected to the electrode, the scanning line signal from the scan line of the switching TFT
Data is input to the digital storage circuit from the signal line by the input to the gate electrode of the switching TFT, and the digital storage circuit inputs the next scanning line signal of the scanning line signal to the gate electrode of the switching TFT. until holding the data that the digital memory circuit, the signal input from the signal line, the select the high potential side power supply power supply potential or the power source potential on the low potential side power supply, the digital storage circuit It is supplied to the pixel electrode, the high-potential side power source and the low potential side power source, a liquid crystal display device, characterized in that driving exchanges. 4. The liquid crystal display device according to claim 3, wherein the plurality of TFTs of the inverter have the same polarity. 5. The liquid crystal display device according to claim 1, wherein the number of said plurality of pixel electrodes is equal to the number of said plurality of digital storage circuits. 6. A liquid crystal display device according to claim 1, wherein display is performed by a time gray scale method.