JP3318667B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to an improvement in a driving circuit provided in the liquid crystal display.

[0002]

2. Description of the Related Art Conventional liquid crystal display devices include, for example, TFTs.
(Thin film transistor: Thin Film Transistor) type active matrix type is known.

FIG. 17 is a block diagram showing the entire configuration of a liquid crystal display device for processing this type of 3-bit image data.

In FIG. 1, reference numeral 100 denotes a TFT type liquid crystal display panel, 101 and 102 denote gate drivers and data drivers for driving the liquid crystal display panel 100, and 103 denotes a display control for controlling both drivers 101 and 102. Circuit, 104
Reference numeral 105 denotes a grayscale voltage source for applying a predetermined grayscale voltage to the data driver 102, and 105 denotes a main unit including a microcomputer body or the like.

The main unit 105 supplies the display control circuit 103 with 3-bit image data for each of R, G, and B, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a synchronization clock Clock. It has become.

In response to these signals, the display control circuit 103 sends a gate start pulse GSP and a gate clock GCK to the gate driver 101.
The data start pulse DSP, the data clock DCK, and the output pulse LP are sent to the data driver 102 together with the image data for color display by the gradation voltage source 10.
4, a polarity switching polarity signal POL is provided.

The gray scale voltage source 104 is basically a rectangular wave generating circuit and generates eight types of gray scale voltages of V _{O to} V ₇ . the polarity of the gradation voltages V ₀ ~V ₇ in accordance with the polarity signal POL from the display control circuit 103 are inverted.

Here, in the present embodiment, the TFT type liquid crystal display panel 100 has m rows (3 × n) as shown in FIG.
Matrix configuration of a striped array of columns, thus m
It is assumed that it is composed of × (3 × n) pixels. (That is, R,
There are n columns of G and B, respectively, which are periodically arranged in the order of R, G and B for each column. If each pixel is replaced with a simplified equivalent circuit, as shown in FIG. 19, each pixel is composed of a TFT 110 as a switch element and a capacitor 112. One electrode of the capacitor 112 is a pixel electrode 112a, and the other electrode is a counter electrode (common electrode) 112b formed on the glass surface.

Then, to write data to each pixel,
After turning on the TFT 110, a required voltage is applied to the capacitor 112 via the data line.

Both electrodes 112a, 11 of the capacitor 112
A liquid crystal layer (not shown), which is a dielectric, exists between 2b, and its transmittance is determined by the potential difference between the two electrodes 112a, 112b.

In addition, if a DC voltage is continuously applied to the liquid crystal for a long time, the characteristics of the liquid crystal deteriorate.
By switching the polarity of the gradation voltages V _{0 to} V ₇ generated from the pixel electrode 04 by the polarity signal POL, so-called AC driving is performed so that positive and negative voltages are alternately applied to the pixel electrode 112a. Has become.

After charging the pixel electrode 112a, T
Even when the FT 110 is turned off, the charged charge is stored in the pixel electrode 112a, and the two electrodes 112a, 112b
A predetermined voltage continues to be applied to the liquid crystal layer between them.

The gate driver 101 includes a liquid crystal display panel 1
00 is sequentially turned on / off for each line.
In the example shown in FIG. 18, m rows can be driven by combining _two chips 101 ₁ and 101 ₂ in order to reduce costs and increase design flexibility.

FIG. 20 shows the overall configuration of the gate driver 101.

The gate driver 101 includes a shift register 114 and m number of level conversion circuits 116 _{1 for} converting the respective m outputs of the shift register 114 to a voltage level necessary for controlling on / off of the TFT 110. ~ 1
It consists of 16m.

A gate start pulse GSP for starting the output of the gate driver 101 is supplied to the shift register 11.
4, the high-level output sequentially shifts inside the shift register 114 every time the gate clock GCK rises.

Since each of the level conversion circuits 116 _{1 to} 116 m constituting the gate driver 101 has the same configuration, FIG. 21 shows one i-th level conversion circuit from the top. Figure 116 shows a detailed block diagram of 116i.

The level conversion circuit 116i includes analog switches ASWH and ASWL which are turned on when the output of the shift register 114 is at a high level, respectively. Each analog switch ASWH and ASWL has a high-level voltage VGH and , Low-level voltage VG
L has been input.

If one output of the shift register 114 is at a high level, one switch ASWH is turned on, and a high-level voltage VGH is output. Conversely, if the other output of the shift register 114 is at a high level, the other switch ASWL is turned on, and a low-level voltage VGL is output.

On the other hand, the data driver 102 applies a required voltage to the pixel electrode 112a via the data line. In the example shown in FIG. 18, the data driver 102 aims to reduce costs and increase design flexibility. , 8 chips 102 _{1 to} 102 ₈
Are combined to drive (3 × n) columns.

FIG. 22 shows the overall configuration of the data driver 102.

The data driver 102 generates a sampling pulse Tsmp based on the data start pulse DSP and the data clock DCK.
0, and sampling and holding circuits 122 ₁₁ , 122 ₁₂ , 122 ₁₃ , 122 ₂₁ ,..., Which store and hold image data.
122 _n1 , 122 _n2 and 122 _n3 . Although the shift register 120 is shown in a simplified manner, the shift register 120 can be realized with a configuration similar to that of the shift register 114 of the gate driver 101.

The data driver 102 of this embodiment has a structure in which R, G, and B image data are simultaneously sampled by one sampling pulse Tsmp.
Sampling and holding circuits 122 ₁₁ , 122 ₁₂ , 122
₁₃ , 122 ₂₁ ,..., 122 _n1 , 122 _n2 , 122 _n3 are provided in total (3 × n).

Each of the sampling and holding circuits 122 ₁₁ , 122 ₁₂ , 12 constituting the data driver 102 described above.
2 ₁₃ , 122 ₂₁ ,..., 122 _n1 , 122 _n2 , 122
_n3 is for 3 bit input and 1 bit output,
Because both have the same configuration, here, one second of one sample and hold circuit 122 ₁₁ from above, with reference to the block diagram of FIG. 23, 3
The bit image data is stored in the sampling storage means Msmp at the rise of the sampling pulse Tsmp, and the output pulse LP
At the rising edge of the storage means MH. The data transferred to the holding storage unit MH is held until the next output pulse LP rises, during which the next data is stored in the sampling storage unit Msmp. The data held in the holding storage unit MH is output from the output circuit unit OCP to the gradation voltage V _0.
And output is converted to ~V _7.

FIG. 24 shows a more detailed configuration of the output circuit unit OCP.

The output circuit OCP includes a decoder DEC as a logic circuit and eight analog switches ASW _{0 to} ASW _7.
Consists of a gray scale voltage V supplied from the gradation voltage source 104, respectively for the analog switches ASW ₀ ~ASW _7
0 ~V ₇ is input.

[0027] Each output S ₀ to S ₇ of the decoder DEC is inputted to the control terminals of the corresponding analog switches ASW ₀ ~ASW _7, the analog switches ASW ₀ to A
SW _7, the control signal is turned on at a high level. For example, if the value of the data is "4", since S ₄ becomes high level, the analog switch ASW ₄
Is turned on, and the gray scale voltage V ₄ is output from the circuit OCP. When the TFT 110 is on, the gradation voltage V ₄ is applied to the capacitor 112.

Next, a basic operation of the liquid crystal display device having the above configuration will be described with reference to FIGS.

FIG. 25 is a timing chart based on the vertical synchronization signal Vsync, and FIGS. 26 and 27 are timing charts based on the horizontal synchronization signal Hsync.

The gate start pulse GSP is input to the gate driver 101 so that the output G (1) of the first row becomes high during the second horizontal period Th = H (2). Hereinafter, each time the gate clock GCK rises every horizontal period, the high-level output sequentially shifts,
Each row is sequentially scanned to turn on the TFT 110.

On the other hand, in the data driver 102, when the data start pulse DSP is input to the shift register 120, the shift register 120 responds to this and sequentially outputs the sampling pulse Tsmp every time the data clock DCK rises. Shift.

The sampling pulse Tsmp generated last for a certain chip is input as a data start pulse DSP for the next chip. As a result, each chip 102 constituting the data driver 102
When one of the ₁ to 102 ₈ is sampling operation, the remaining chips are stops for sampling operation.

Here, in the data driver 102, the horizontal period Th = H (1) in which the image data of the first row is transmitted.
The data that was sampled and stored and held in
It is output all at once by the rising edge of the output pulse LP in the next horizontal period Th = H (2). Meanwhile, data driver 1
02 samples the data in the second row, and thereafter repeats sampling and output sequentially.

Therefore, in the data driver 102, the image data of the i-th row transmitted during the i-th horizontal period Th = H (i) and sampled by each sampling pulse Tsmp is converted into the output pulse LP Thus, the signals are output all at once in the next horizontal period Th = H (i + 1). During the horizontal period H (i + 1), the gate driver 101 outputs the output G of the i-th row.
Since (i) is at the high level, the output of the data driver 102 at this time is written to each pixel in the i-th row.

As can be seen from the above description, the period from when the output pulse LP goes high to when it goes high next is:
This corresponds to one output period in which the data driver 102 outputs a voltage for one data, and this one output period is usually equal to one horizontal period Th. Then, the gradation voltages V _{0 to} V
₇ , the polarity of the potential viewed from the common electrode voltage Vcom is inverted every one horizontal period Th. For example, in the case of FIG. 25, when focusing on the output S (j) of the j-th column of the data driver 102, the polarity of the potential is inverted for each row, and the pixel of the (i-1) -th row is positive. When charging, the next pixel in the i-th row is negatively charged.

As described above, in this example, the so-called row inversion drive in which the positive and negative polarities of the gray scale voltage are inverted every horizontal period (output period) Th, and the polarity is also inverted every vertical period Tv. In this way, each pixel is AC-driven.

For example, in the case of FIG. 25, when attention is paid to the pixels P (1, j), P (2, j),... Of the same j-th column, each pixel P (1, j) is set every horizontal period Th. , P (2, j),..., And the charged electric charge continues to be stored, and the next vertical period T
The polarity of each pixel P (1, j), P (2, j),... This makes it possible to obtain an image that is averaged between adjacent rows and has no flicker.

When the time period for positively charging the potential of the pixel electrode with respect to the common electrode is a positive driving time period, the time period for negatively charging is a negative driving time period, and when the polarity signal POL is at a high level, the period is positive. And the low level corresponds to the negative drive time.

In FIGS. 25 to 27, the hatched portions in the image data and the output S (j) of the data driver are as follows.
This means that the value differs depending on the image to be displayed or the output terminal.

The basic operation of the liquid crystal display device is as described above. In the conventional device, however, the data driver 102 is controlled by the data driver 102 regardless of the image display period Tw for displaying image data. , Always, data start pulse D
The configuration is such that both the SP and the data clock DCK are input and the sampling operation is continued.

That is, in the conventional device, each of the chips 102 _{1 to} 102 ₈ constituting the data driver 102 has a period (= Tv−Tw) other than the image display period Tw in which the image data is input, in the vertical period Tv. Also, in (2), unnecessary sampling of image data was continued, so that power was wasted.

The present inventors have provided the following two devices in order to minimize such wasteful power consumption (see Japanese Patent Application No. 7-327039).

(1) In the first device, as shown in FIGS. 25 to 27, the period (= Tv-Tw) other than the image display period Tw in the vertical period Tv constitutes the data driver 102. The data start pulse DSP is not input to the shift register 120 to eliminate the generation of the sampling pulse Tsmp, and all the sampling and holding circuits 122
₁₁ , 122 ₁₂ , 122 ₁₃ , 122 ₂₁ ,..., 122 _n1 , 1
The sampling operation at 22 _n2 and 122 _n3 is stopped.

That is, the horizontal period Th in which the image data of the m-th row in the image display period Tw is transmitted to the data driver 102
= H (m) is completed and the data start pulse DSP is input to the shift register 120 until the horizontal period Th = H (1) in which the image data of the first row of the next image display period Tw is transmitted. Only when the horizontal period Th = H (1) during which the image data of the first row is transmitted to the data driver 102, the data start pulse DS is supplied to the shift register 120.
P has been entered.

In this manner, each of the chips 102 _{1 to} 102 ₈ of the data driver 102 samples unnecessary image data during periods other than the image display period Tw in the vertical period Tv that do not directly contribute to display. Is gone,
Since all are in the standby state, wasteful consumption of power can be suppressed.

(2) FIG. 28 and FIG.
As shown in FIG. 9, during a period other than the image display period Tw in the vertical period Tv (= Tv−Tw), the sampling clock is input to the shift register 120 constituting the data driver 102 so that the data clock DCK is not input. The occurrence of Tsmp is eliminated, and all sampling and holding circuits 122 ₁₁ and 122 _11
12 , 122 ₁₃ , 122 ₂₁ ,..., 122 _n1 , 122 _n2 , 1
The sampling operation at 22 _n3 is stopped.

That is, the horizontal period Th in which the image data of the m-th row in the image display period Tw is transmitted to the data driver 102
= H (m), and until the horizontal period Th = H (1) in which the image data of the first row of the next image display period Tw is transmitted, the shift register 120 receives the data clock DCK.
Is input, and the image data in the first row is
The data clock DCK is input to the shift register 120 only when the horizontal period Th = H (1) is transmitted.

Also in this device, during a period that does not directly contribute to display other than the image display period Tw in the vertical period Tv,
Each of the chips 102 _{1 to} 102 ₈ of the data driver 102 does not sample unnecessary image data,
Since all are in the standby state, wasteful consumption of power can be suppressed.

By the way, as the size and definition of the liquid crystal display device increase and the number of pixels of the liquid crystal display panel 100 increases, the probability of occurrence of each pixel defect in manufacturing the liquid crystal display panel 100 also increases. For example, if a defect occurs in the TFT 110 and the TFT is not turned on even when an on-voltage is applied to the gate G, the voltage of the source S is not always applied to the pixel electrode. The gate G and the drain D of the TFT 110
If a leak occurs between them, a high on-voltage of the gate G is applied to the pixel electrode.

As shown in FIG. 30, when the liquid crystal display panel 100 is of a normally white mode, the higher the voltage applied to the liquid crystal, the lower the light transmittance.
The lower the voltage, the higher the light transmittance. Therefore, when a high voltage is applied to the electrode of the defective pixel, it becomes a black point, and when a low voltage is applied, it becomes a bright point. In the normally black mode, the higher the voltage applied to the liquid crystal, the higher the light transmittance, and the lower the voltage, the lower the light transmittance. Therefore, when a high voltage is applied to the electrode of the defective pixel, it becomes a bright point, and when a low voltage is applied, it becomes a black point. Since such bright spots or black spots are displayed differently from the normal data of the normal display pixels, defects are conspicuous and greatly hinder use.

In order to correct such a pixel defect, conventionally, for example, in Japanese Patent Application Laid-Open No. 58-184758, a gate G of a defective TFT 110 is physically separated from a scanning signal line by using a laser or the like. , Source S
And a technique in which the drain D is short-circuited. By doing so, the average voltage of the image signal during the vertical period is applied to the pixel electrode, and the defect can be made less conspicuous than the bright spot or black spot. As described in the above-mentioned Japanese Patent Application Laid-Open No. 58-184758, defects of a pixel in which the source S and the drain D are intentionally short-circuited and a pixel in which the source S and the drain D are short-circuited during manufacturing are made less noticeable. For example, Japanese Patent Application Laid-Open No. Hei 6-138439 has been proposed as a driving method therefor. JP-A-6
Japanese Patent Publication No. 138439 proposes a technique in which a correction video signal for correcting a voltage applied to an electrode of a defective pixel is supplied to the data driver 102 during a vertical blanking period.

[0052]

However, the prior art disclosed in the above publication is based on the premise that the liquid crystal display device continues the sampling operation regardless of the inside and outside of the image display period Tw in the vertical period Tv. The apparatus of the above (1) and (2) provided by the present inventors, that is, the period (= T) other than the image display period in the vertical period Tv
(v−Tw), in a device in which the sampling operation of the data driver 102 is stopped, even if correction data is given to the data driver 102 in a period other than the image display period Tw in the vertical period Tv, Since the data driver 102 does not perform the sampling operation, no effect is obtained.

That is, the image display period Tw in the vertical period Tv
In a device that stops the sampling operation of the data driver 102 during a period other than
From 2 _{11 to} 122 n ₃ , the data sampled in the last horizontal period Th = H (m) of the image display period Tw becomes the first horizontal period Th of the image display period Tw in the next vertical period Tv.
Until the data is updated at H (1), the output is continued with the same contents. For this reason, when a defect occurs in the TFT 110 and, for example, the source and the drain are short-circuited and are always in a conductive state, the image display period Tw in the vertical period Tv
In the other periods, a voltage corresponding to the data sampled in the last horizontal period Th = H (m) of the image display period Tw in the vertical period Tv is applied to the defective pixel, Defective pixels may be noticeable or inconspicuous.

According to the present invention, there is provided an apparatus in which the sampling operation of all the chips constituting the data driver is stopped during at least a part of the period other than the image display period in the vertical period, thereby reducing unnecessary power consumption. It is an object of the present invention to solve the above problem by reliably making defective pixels inconspicuous and improving display quality.

[0055]

In order to solve the above-mentioned problems, the present invention employs the following structure in a liquid crystal display device having a gate driver and a data driver for driving a liquid crystal display panel.

That is, in the liquid crystal display device according to the first aspect, during a part of the vertical period other than the image display period, specific data is supplied to the data driver, and the specific data is supplied to the data driver by the data driver. During the period following the part of the period other than the image display period , the horizontal synchronization signal and the vertical synchronization signal are used to stop the sampling operation of the data driver .
Creates a pass regulation signal and images during the vertical period
In addition to the display period, other than the image display period during the vertical period
The pass regulation signal is set to the pass permission level even during a part of the period
In order to delay the pass permission level of the pass
Means for creating a passage regulation signal having a function for
Of the image data of the data driver by inputting the
The data start pulse for starting sampling
First permitting means for permitting input to the driver.
ing.

In the liquid crystal display device according to the second aspect, the liquid
Driver and data driver for driving crystal display panel
Image display during a vertical period in a liquid crystal display device equipped with
In some periods other than the period, specific data
Data driver and the data driver.
Sampling of constant data, and outside of the image display period
The period following said partial period in the data driver
In order to stop the sampling operation of
And the vertical synchronization signal to create a passage regulation signal.
In addition to the image display period during the vertical period,
The pass regulation signal is also applied to some periods other than the middle image display period.
Permit the passage of pass-through signals to achieve the pass permission level
A pass regulation signal with a function to delay the level
Inputting the passage regulation signal
Data clock for sampling driver image data
Are allowed to enter the data driver.
And a step.

According to a third aspect of the present invention, in the liquid crystal display device according to the first or second aspect, an image during a vertical period is provided.
Some periods other than the display period are the first
The horizontal period.

According to a fourth aspect of the present invention, there is provided the liquid crystal display device according to the first or second aspect, wherein the passage defining signal is generated.
Means for outputting the gate voltage of the first row.
Timing of the passage permission level of the passage regulation signal for
It has a function to speed up the tuning.

In the liquid crystal display device according to the fifth aspect , the
3. The liquid crystal display according to claim 1, wherein the vertical period
During some periods other than the middle image display period, the data drive
Data star for starting sampling of motive image data
Pulse is allowed to enter this data driver.
First permitting means, and the image data of the data driver.
The data clock for sampling is connected to this data driver.
A second permitting means for permitting the input is provided.

In the above configuration, even when there is a defective pixel in the liquid crystal display panel, specific data for defect correction is input to the data driver during a certain period other than the image display period in the vertical period, and the identification is performed. If you sample the data of, the specific data sampled,
Output is continued with the same contents until the image display period in the next vertical period. Then, since a voltage based on the specific data for defect correction is applied to the defective pixel, bright spots and black spots caused by the defective pixel become less noticeable. Moreover, the data driver is in a standby state without performing the sampling operation in most of the period other than the image display period during the vertical period.
Unnecessary power consumption can be eliminated.

[0062]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a timing chart showing the operation of a liquid crystal display according to Embodiment 1 of the present invention based on a vertical synchronization signal Vsync. 2 and 3 show the horizontal synchronizing signal Hsy.
6 is a timing chart showing an operation based on nc.

The difference from the timing charts shown in FIGS. 25 to 27 is that the image display period Tw in the vertical period Tv is different.
During the first outer horizontal period Th, the data driver 102
Data for defect correction and data start pulse D
This means that the SP is input and the data for defect correction is sampled only once outside the image display period Tw.

That is, after the horizontal period Th = H (m) in which the image data of the m-th row, which is the last row of the image display period Tw, is transmitted to the data driver 102, the data start is performed once extra. A pulse DSP is input and one horizontal period T
Data for defect correction is sampled over h.

Thereafter, the data start pulse DSP is not input to the shift register 120 until the horizontal period Th = H (1) during which the image data of the first row of the next image display period Tw is transmitted. The data start pulse DSP is input to the shift register 120 only after the horizontal period Th = H (1).

From the data driver 102, the voltage corresponding to the last sampled defect correction data is supplied to the first horizontal period Th = H of the next image display period Tw.
Output is continued until (1). However, the positive and negative polarities of this voltage are determined by the polarity signal P from the display control circuit 103.
The AC driving is performed by inverting every horizontal period Th by OL.

Here, in the liquid crystal display panel 100, since a pixel having a low transmittance tends to be less noticeable as a defective pixel than a panel having a high transmittance, data for defect correction is displayed as a color as close to a black point as possible. It is preferable to set the contents so as to be performed. (By doing so, when displaying, not a black point, but an intermediate color closer to black and defective pixels are less noticeable.) For example, when the liquid crystal display panel 100 is in a normally white mode,
Since the light transmittance is lower as the voltage applied to the liquid crystal is higher, the data content is set so that a higher voltage (for example, about 5 V in FIG. 30) is applied to the electrode of the defective pixel.
In the normally black mode, the lower the voltage applied to the liquid crystal, the lower the light transmittance. Therefore, a low voltage (for example, about 0.5 V in FIG. 30) is applied to the electrode of the defective image. Set the data contents as follows. In the present example, such data for defect correction is formed in advance in the display control circuit 103 and the data driver 1
02.

Here, the TFT 110 constituting a certain pixel
Considering a case where a defect has occurred and the source and the drain are short-circuited and a continuous conduction state is assumed, the defective pixel has an image display period Tw in one vertical period Tv.
The voltage based on the data sampled by the data driver 102 and the data driver 102 outside the image display period Tw.
It can be considered that the average value with the voltage based on the data sampled in the above is applied. In the image display period Tw in the vertical period Tv, since the voltage based on the data for image display is sampled, the data cannot be arbitrarily changed.
The voltage sampled by the data driver 102 during periods other than (= Tv−Tw) does not directly contribute to image display, and can be arbitrarily changed.

Therefore, when the data driver 102 samples appropriate defect correction data during a certain period outside the image display period Tw as described above, the voltage at that time continues to be output after the sampling. So
As an average value of the voltages for one vertical period Tv with respect to the defective pixel, for example, the transmittance can be made slightly lower, and the presence of the defective pixel can be made inconspicuous.

Further, the data driver 102 operates for a short period after the image display period Tw has elapsed (in this example, one horizontal period T).
Since only the sampling operation for h) is performed, wasteful power consumption hardly increases.

In the first horizontal period Th outside the image display period Tw in the vertical period Tv, the first permitting means A for inputting data for defect correction and the data start pulse DSP to the data driver 102 is described. 4 is shown in the block diagram of FIG. 4, and its operation is shown in the timing charts of FIGS.

The first counter 201 outputs the horizontal synchronizing signal Hsy.
Reset at the falling edge of nc and start counting again. This count is performed for each rising edge of the clock CK, the result is a pulse output from the output terminal C ₀ -C ₉ as a binary signal (In FIG. 5, due to space limitations, C ₀ -C Only the output of No. ₂ is shown, and the outputs of C _{3 to} C ₉ are omitted).

Here, the set value in consideration of the elapsed time Ta (see FIGS. 2 and 3) from the falling of the horizontal synchronizing signal Hsync to the input of the data start pulse DSP is previously set to the first comparator 301. The signals are input as binary signals H _{0 to} H ₉ , and when the output from the first counter 201 matches the set value, a pulse is output from the output terminal OUT of the first comparator 301. .

The first flip-flop 221 controls the first comparator 3 according to the rising timing of a signal obtained by inverting the level of the clock CK by the inverter 212.
01 output is latched. Then, the first comparator 301
When a pulse is output from the first flip-flop 221, the data that is latched and output by the first flip-flop 221 is the data start pulse DSP.

The second counter 202 is reset at the rise of the vertical synchronization signal Vsync, and starts counting again. This count is performed for each falling edge of the horizontal synchronization signal Hsync, the result is a pulse output from the output terminal C ₀ -C ₉ as a binary signal (In FIG. 6, due to space limitations, C ₀ -C showed only ₂ of the output, C ₃ -C ₉
Output is omitted).

Here, the elapsed time Tb from the rising of the vertical synchronization signal Vsync to the input of the gate start pulse GSP in the image display period Tw in the vertical period Tv is supplied to the second comparator 302 in advance (see FIG. 1). Set value considering 2
Pulses are output from the output terminal OUT of the second comparator 302 when the output from the second counter 202 and the set value coincide with each other and are input as signals V _{0 to} V _{9 in} base numbers.

The second flip-flop 222 latches the output of the second comparator 302 each time the signal obtained by inverting the level of the horizontal synchronization signal Hsync by the inverter 213 rises.

The second flip-flop 222 is provided for the following necessity.

As described above, the data sampled during a certain horizontal period Th = H (i) is obtained in the next horizontal period Th = H (i).
In (+1), the i-th row is designated by the gate driver 101, and the data driver 102 simultaneously outputs the i-th row. In consideration of this point, one horizontal period Th is more than the timing when the high-level gate voltage of the first row is output from the gate driver 101.
This is because the output of the fourth flip-flop 224 described later is set to a high level to open the second AND gate 232.

The third flip-flop 223 converts the output signal from the output terminal of C ₈ on the upper side of the first counter 201 and the output signal from the output terminal of C ₉ into the inverter 211.
The output of the second flip-flop 222 is latched at the rising edge of the clock generated by passing the inverted signal through the first AND gate 231. Then, when a pulse is output from the second comparator 222, what is latched and output by the third flip-flop 223 becomes a gate start pulse GSP.

The third counter 203 newly starts counting after being reset at the falling edge of the inverted output of the second flip-flop 222. This count is performed for each falling edge of the horizontal synchronization signal Hsync, the result is a pulse output from the output terminal C ₀ -C ₈ as binary signals (In FIG. 7, due to space limitations, C ₀ -C showed only ₂ of the output, the output of the C ₃ -C ₈ is omitted).

Here, the decoder 303 operates as a third counter 2
03 is an image display period Tw in the vertical period Tv in advance.
The pulse is output from the output terminal OUT only when the value reaches a predetermined value set in correspondence with the above.

Then, the output of the decoder 303 is inverted in level by the inverter 214, and the fourth flip-flop 224 is reset by the fall of the output. The fourth flip-flop 224 is set at the falling edge of the inverted output of the second flip-flop 222. Therefore, the output of the fourth flip-flop 224 is at a high level only during a period corresponding to the image display period Tw in the vertical period Tv.

The fifth flip-flop 225 is provided for further delaying a period corresponding to the image display period Tw by one horizontal period Th, and is provided with a horizontal synchronizing signal Hsy.
The output of the fourth flip-flop 224 is latched each time a signal whose nc is inverted by the inverter 213 rises. Therefore, the output of the fifth flip-flop 225 is a period other than the first horizontal period in the image display period Tw in the vertical period Tv, and a period corresponding to the first horizontal period Th after the elapse of the image display period Tw. At a high level (see FIGS. 7 and 8).

Fourth and fifth flip-flops 224, 224
25, are input to the OR gate 241, and the output is applied to one input terminal of the second AND gate 232. Therefore, the AND gate 232 outputs the data start pulse for a period corresponding to Tw + Th in the vertical period Tv. DS
The passage of P is permitted, and the passage of the data start pulse DSP is blocked in other periods. Therefore, in a period (= Tv−Tw) outside the image display period Tw, the data start pulse DSP is input only in the first horizontal period Th.

Further, the third AND gate 233 receives the outputs of the fourth and fifth flip-flops 224 and 225 (the output of 224 is an inverted output) together, so that the image display period in the vertical period Tv is obtained. 1 after Tw has elapsed
A high-level signal is output only during a period corresponding to the horizontal period Th (see FIG. 8). And this third AND gate 2
The output of 33 is applied to the data selector 401.

The data selector 401 selects data for image display applied to one terminal A when the signal from the third AND gate 233 is at a low level, and selects data for defect correction when the signal is at a high level. Is selected. Therefore, in the image display period Tw, the data for image display is input to the data driver 102, and the data for defect correction is data driven during the first horizontal period Th of the period (= Tv-Tw) outside the image display period Tw. Vessel 102
Will be entered.

The first permitting means A may be provided inside or outside the data driver 102.

Embodiment 2 FIGS. 9 and 10 are timing charts showing the operation of the liquid crystal display device according to Embodiment 2 of the present invention based on the horizontal synchronization signal Hsync.

The difference from the timing charts shown in FIGS. 28 and 29 is that the image display period Tw in the vertical period Tv is different.
During the first outer horizontal period Th, the data driver 102
Is input with the defect correction data and the data clock DCK for sampling the image data, and the defect correction data is sampled only once outside the image display period Tw.

That is, during the first horizontal period Th after the end of the horizontal period Th = H (m) in which the m-th row of image data, which is the last row of the image display period Tw, is transmitted to the data driver 102, A data clock DCK is input to sample defect correction data. The data for defect correction has the contents described in the first embodiment.

Thereafter, the data clock DCK is applied to the shift register 120 until the horizontal period Th = H (1) in which the image data of the first row of the next image display period Tw is transmitted.
Is input, and the data clock DCK is input to the shift register 120 only after the first horizontal period Th = H (1).

Also in this case, similarly to the first embodiment, the voltage corresponding to the last sampled data for defect correction is supplied from the data driver 102 to the next image display period Tw.
Is output until the first horizontal period Th = H (1). However, the polarity of this voltage is determined by the polarity signal POL from the display control circuit 103 for one horizontal period Th.
Each time it is inverted and driven by AC.

In the second embodiment as well, the average value of the voltage as viewed in one vertical period Tv with respect to the defective pixel can be, for example, a slightly lower transmittance, and the presence of the defective pixel can be made inconspicuous. Becomes possible.

Moreover, the data driver 102 operates for a short period after the image display period Tw has elapsed (in this example, one horizontal period T).
Since only the sampling operation for h) is performed, wasteful power consumption hardly increases.

In the first horizontal period Th outside the image display period Tw in the vertical period Tv, specific data of the second permitting means B for inputting the data for defect correction and the data clock DCK to the data driver 102 is shown. 11 is shown in the block diagram of FIG. 11, and the operation is shown in the timing chart of FIG.

In the configuration of the first embodiment shown in FIG. 4, the output of the data start pulse DSP is limited by the second AND gate 232, but in the second embodiment,
The data clock DCK is output by the fourth AND gate 234.
Output is limited.

That is, in the case of this example, the fourth AND gate 234 causes the image display period Tw during the vertical period Tv and the data (Tw + Th) corresponding to one horizontal period Th after the elapse of the period Tw. The passage of the clock DCK is permitted, and the data clock DCK is
(See FIG. 12).

Since the other structure is the same as that of the first embodiment, the same reference numerals are given to the portions corresponding to FIG. 4 and the description is omitted.

The second permitting means B may be provided inside or outside the data driver 102.

Modification (1) As a modification of the first permitting means A shown in FIG. 4, a first permitting means A 'can be formed as shown in FIG.

In the configuration shown in FIG. 13, the third counter 203, the composite device 303, the fifth flip-flop 225, and the third AND gate 233 shown in FIG. This pulse GSPO is output to the inverter 2 using a pulse GSPO output when the last m rows are designated (the pulse GSPO has a pulse width corresponding to one horizontal period Th).
14 to a fourth flip-flop 224.

Therefore, the fourth flip-flop 224
From this, a signal which becomes high level only during a period corresponding to the image display period Tw in the vertical period Tv is output, and is supplied to the OR gate 241. In addition, the above-mentioned pulse GSPO
Is similarly supplied to the OR gate 241 via the inverters 214 and 215, and as a result, the OR gate 241
Outputs a signal permitting the passage of the data start pulse DSP only during a period corresponding to Tw + Th in the vertical period Tv, and this signal is given to the second AND gate 232, so that the output period of the data start pulse DSP is reduced. Will be limited. In addition, the above pulse GSP
O is also given to the data selector 401 via the inverters 214 and 215, so that a period outside the image display period Tw
In the first horizontal period Th of (= Tv−Tw), data for defect correction is input to the data driver 102.

(2) As a modification of the second permitting means B shown in FIG. 11, a second permitting means B 'can be formed as shown in FIG.

In the structure shown in FIG. 15, FIG.
, The third counter 203, the composite device 303, the fifth flip-flop 225, and the third AND gate 233 are omitted, and the pulse output when the gate driver 101 specifies up to the last m rows. This pulse GSPO is input to the fourth flip-flop 224 via the inverter 214 using GSPO (however, this pulse GSPO has a pulse width corresponding to one horizontal period Th).

Therefore, the fourth flip-flop 224
From this, a signal which becomes high level only during a period corresponding to the image display period Tw in the vertical period Tv is output, and is supplied to the OR gate 241. In addition, the above-mentioned pulse GSPO
Is similarly supplied to the OR gate 241 via the inverters 214 and 215, and as a result, the OR gate 241
Outputs a signal permitting the passage of the data clock DCK for a period corresponding to Tw + Th in the vertical period Tv, and this signal is applied to the second AND gate 234, whereby the output period of the data clock DCK is limited. Will be. Further, since the above pulse GSPO is also provided to the data selector 401 via the inverters 214 and 215, a period outside the image display period Tw (= Tv−T
In the first horizontal period Th of w), data for defect correction is input to the data driver 102.

(3) In order to solve the problem of the present invention, it is possible to adopt a configuration in which the above two embodiments 1 and 2 are combined.

(4) The sampling of the data for defect correction is not limited to the first horizontal period Th outside the image display period Tw in the vertical period Tv as in this example.
Defective pixels can be made inconspicuous in a relatively early period after the end of the image display period Tw, such as the second horizontal period and the third horizontal period. Further, it is apparent that the present invention is essentially included in the case where sampling is performed not only for one horizontal period Th but also for several horizontal periods Th. At this time, the means for permitting the data start pulse DSP and the data clock DCK can be realized by slightly changing the above-described one.

The present invention also includes a method in which a part of the image display period Tw in the vertical period Tv is not sampled to make the defective pixel inconspicuous by the above-described method.

(5) In this example, the data for defect correction is
Although it is formed in advance in the display control circuit 103 and provided to the data driver 102, even if it is not necessary to specially prepare the data for defect correction, it is necessary to provide the data outside the display period in the vertical period of the image signal. It is also conceivable that part of the data can be used as it is as defect correction data. Although the purpose is achieved only by providing the data for defect correction only during the sampling period, it is not harmful to supply the data during the non-sampling period. Obviously, even this method is included in the present invention.

[0111]

According to the present invention, the following effects can be obtained.

In a part of the vertical period other than the image display period, specific data for defect correction is supplied to the data driver to perform a sampling operation of the specific data, and the other period other than the image display period is performed. In most cases, the sampling operation of the data driver is stopped. Therefore, after sampling the data for defect correction, the first horizontal period Th = H of the image display period in the next vertical period is performed. Until (1)
Since appropriate data for defect correction is output from the data driver to the defective pixel, the defective pixel can be made inconspicuous.

Further, outside the image display period in the vertical period, the sampling period of the data for defect correction is very small, and after sampling, the sampling of the data driver is performed until the image display period in the next vertical period. Since the operation is stopped, useless power consumption can be reduced as much as possible.

[Brief description of the drawings]

FIG. 1 is a timing chart showing an operation based on a vertical synchronization signal Vsync in a first embodiment of a liquid crystal display device of the present invention.

FIG. 2 is a timing chart illustrating an operation based on a horizontal synchronization signal Hsync in the first embodiment of the liquid crystal display device of the present invention.

FIG. 3 is a timing chart showing the operation based on the horizontal synchronization signal Hsync in Embodiment 1 of the liquid crystal display device of the present invention continued from FIG. 2;

FIG. 4 is a block diagram showing a specific configuration of a first permission unit.

FIG. 5 is a timing chart for explaining the operation of a first permitting unit in FIG. 4;

FIG. 6 is a timing chart for explaining the operation of a first permitting unit in FIG. 4;

FIG. 7 is a timing chart for explaining the operation of a first permitting unit in FIG. 4;

FIG. 8 is a timing chart for explaining the operation of the first permitting unit in FIG. 4;

FIG. 9 is a timing chart illustrating an operation based on a horizontal synchronization signal Hsync in a second embodiment of the liquid crystal display device of the present invention.

FIG. 10 is a timing chart showing the operation based on the horizontal synchronization signal Hsync in the second embodiment of the liquid crystal display device of the present invention continued from FIG. 9;

FIG. 11 is a block diagram showing a specific configuration of a second permission unit.

FIG. 12 is a timing chart for explaining the operation of a second permission unit in FIG. 11;

FIG. 13 is a block diagram showing a modification of the first permitting unit of the first embodiment.

FIG. 14 is a timing chart for explaining the operation of a first permitting unit in FIG. 13;

FIG. 15 is a block diagram showing a modification of the second permitting unit of the second embodiment.

FIG. 16 is a timing chart for explaining the operation of a second permitting unit in FIG. 15;

FIG. 17 is a block diagram illustrating an overall configuration of a liquid crystal display device.

FIG. 18 is a plan view showing an arrangement of a liquid crystal display panel and a gate driver and a data driver for driving the liquid crystal display panel.

FIG. 19 is an equivalent circuit diagram of a TFT type liquid crystal display element.

FIG. 20 is a block diagram illustrating an overall configuration of a gate driver.

FIG. 21 is a circuit diagram of a level conversion circuit constituting the gate driver of FIG. 20;

FIG. 22 is a block diagram illustrating an overall configuration of a data driver.

FIG. 23 is a block diagram of a sampling and holding circuit forming the data driver of FIG. 22;

FIG. 24 is a circuit diagram of an output circuit unit constituting the sampling and holding circuit of FIG. 23;

FIG. 25 is a timing chart showing an operation based on the vertical synchronization signal Vsync when the data start pulse is not input to the data driver outside the image display period during the vertical period in the liquid crystal display device.

FIG. 26 is a timing chart showing an operation based on the horizontal synchronizing signal Hsync in a case where a data start pulse is not input to the data driver outside the image display period during the vertical period in the liquid crystal display device.

FIG. 27 shows, in the liquid crystal display device, an operation based on the horizontal synchronizing signal Hsync in a case where the data start pulse is not input to the data driver outside the image display period during the vertical period. It is a timing chart.

FIG. 28 is a timing chart showing an operation based on the horizontal synchronization signal Hsync when the data clock is not input to the data driver outside the image display period during the vertical period in the liquid crystal display device.

FIG. 29 is a timing chart showing the operation based on the horizontal synchronizing signal Hsync in the liquid crystal display device when the data clock is not input to the data driver outside the image display period during the vertical period, as shown in FIG. 28; It is a chart.

FIG. 30 is a characteristic diagram showing a relationship between transmittance and applied voltage (absolute value) in each type of normally white and normally black liquid crystal display panels.

[Explanation of symbols]

100: liquid crystal display panel, 101: gate driver, 10
2: Data driver, GSP: Gate start pulse, G
CK: gate clock, DSP: data start pulse, DCK: data clock, A, A ': first permitting means, B, B': second permitting means.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 5/66 102 H04N 5/66 102B (56) References JP-A-6-12035 (JP, A) JP-A-1-128098 (JP, A) JP-A-7-140937 (JP, A) JP-A-57-207286 (JP, A) JP-A-60-50573 (JP, U) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) G09G 3/00-3/38 G02F 1/133 505-580 H04N 5/66-5/70

Claims (5)

(57) [Claims] 1. A liquid crystal display device comprising a gate driver and a data driver for driving a liquid crystal display panel, wherein, during a part of a vertical period other than an image display period, specific data is supplied to the data driver. The specific data is sampled by the data driver while being supplied to the data driver, and the sampling operation of the data driver is stopped during a period following the partial period other than the image display period.
For this purpose, the pass signal is defined by the horizontal and vertical synchronization signals.
Not only the image display period during the vertical period
Also in some periods other than the image display period during the vertical period
In order to set the passage regulation signal to the passage permission level, the passage regulation
Has a function to delay the signal passing permission level
By inputting the passage regulation signal and the passage regulation signal, the data driver
Data start pulse for starting sampling of image data
Is a first allowable means for allowing input to the data driver.
The liquid crystal display device characterized by having a stage. 2. A gate driver for driving a liquid crystal display panel.
And the liquid crystal display device that includes a data driver, some period other than the image display period in the vertical period, the specific
Data to the data driver, and
The driver samples this particular data.
After the part of the period other than the image display period
Stop the sampling operation of the data driver
For this purpose, the pass signal is defined by the horizontal and vertical synchronization signals.
Not only the image display period during the vertical period
Also in some periods other than the image display period during the vertical period
In order to set the passage regulation signal to the passage permission level, the passage regulation
Has a function to delay the signal passing permission level
By inputting the passage regulation signal and the passage regulation signal, the data driver
The data clock for sampling the image data
Second permitting means for permitting input to the driver.
The liquid crystal display device, characterized in that that. 3. The liquid crystal display device according to claim 1 , wherein
Oite, the image display part of the period other than the period during the vertical period, the image table
A liquid crystal display device, which is a first horizontal period outside the indicated period . 4. The liquid crystal display device according to claim 1, wherein the passage regulating signal generating means includes a gate voltage of a first row.
Is allowed to pass the passage regulation signal
A liquid crystal display device having a function to advance a possible level timing . 5. The liquid crystal display device according to claim 1, wherein in a part of the vertical period other than the image display period, a data start pulse for starting sampling of image data of the data driver is provided. First permitting means for permitting input to the data driver; and second permitting means for permitting a data clock for sampling image data of the data driver to be input to the data driver. A liquid crystal display device comprising: