JP2001166741A - Semiconductor integrated circuit device and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device permitting a high speed operation and a large screen of a liquid crystal element. SOLUTION: This is a semiconductor integrated circuit device for supplying gradation voltages corresponding to display data to each video signal line of a liquid crystal element, and the semiconductor integrated circuit device is arranged for each output terminal to be electrically connected with aforementioned each video signal line, and comprises plural gradation voltage output means for outputting gradation voltages corresponding to the display data, plural pre-charge voltage generation means for generating pre-charge voltages corresponding to the gradation voltages outputted from each gradation voltage output means, and switching means for outputting from each output terminal the pre-charge voltages generated by each pre-charge voltage generation means within a first prescribed period during one horizontal scanning period and outputting from each output terminal the gradation voltages outputted from each gradation voltage output means during the other period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to a video signal line driving means (drain driver) of a liquid crystal display device capable of multi-tone display.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device having an active element (for example, a thin film transistor) for each pixel and switchingly driving the active element is widely used as a display device of a notebook type personal computer or the like. This active matrix type liquid crystal display device applies a video signal voltage (a gray scale voltage corresponding to display data; hereinafter, referred to as a gray scale voltage) to a pixel electrode via an active element. There is no need to use a special driving method for preventing crosstalk unlike a simple matrix type liquid crystal display device, and multi-tone display is possible. TF is one of the active matrix type liquid crystal display devices.
T and (T hin F ilm T ransister) mode liquid crystal display panel (TFT-LCD), a drain driver disposed above the liquid crystal display panel, a gate is disposed on the side surface of the liquid crystal display panel - DOO driver and interface There is known a TFT type liquid crystal display module including the following. In this TFT type liquid crystal display module, a gradation voltage generation circuit is provided in a drain driver, and one gradation voltage corresponding to display data is selected from a plurality of gradation voltages generated by the gradation voltage generation circuit. And a gray scale voltage selection circuit (decoder circuit) for selecting
And an amplifier circuit to which two gradation voltages are input.
Such a technique is described in, for example, Japanese Patent Application No. 8-86666.
No. 8 is described.

[0003]

In a liquid crystal display device such as a TFT type liquid crystal display module, if the pixel writing voltage is insufficient, the display quality of a display screen displayed on the liquid crystal display panel is significantly deteriorated. However, in recent years,
In a liquid crystal display device such as a display module, the resolution of the liquid crystal display panel is set to 1024 × 768 pixels in the XGA display mode in accordance with a demand for a larger screen of the liquid crystal display panel.
1280 x 1024 pixels in SXGA display mode, UXG
A higher resolution of 1600 × 1200 pixels in the A display mode is required. For this reason, the number of horizontal scans within one vertical scan period increases, and accordingly, the write time per horizontal scan gradually decreases, and a shortage of the pixel write voltage has become a serious problem. In order to solve such a problem, the present applicant provides a precharge circuit between a gray scale voltage selection circuit of a drain driver and an amplifier circuit, and performs a first predetermined period (hereinafter referred to as a first period) in one horizontal scanning period. A liquid crystal display device has been proposed in which a precharge voltage is supplied from the precharge circuit to each of the drain signal lines during the precharge period, thereby eliminating the insufficient pixel write voltage. 11-19221
No. 2).

However, in the proposed liquid crystal display device, during the precharge period, the precharge voltage supplied from the precharge circuit is basically a fixed voltage, and each drain signal is supplied within one horizontal scan period. No consideration is given to the voltage level of the gradation voltage applied to the line. For this reason, there is a problem that the pixel writing voltage becomes insufficient depending on the voltage level of the gradation voltage applied to each video signal line within one horizontal scanning period. The drain driver is generally mounted on one side of the liquid crystal display panel. However, with the demand for a larger screen of the liquid crystal display panel, the load resistance and load capacitance of the video signal line have been increased. I have. Therefore, even if the same precharge voltage is supplied to the drain signal line during the precharge period, a pixel farther from the drain driver is charged by the precharge voltage than a pixel closer to the drain driver. Since the charging voltage is reduced, in some cases, the writing voltage is insufficient at a pixel far from the drain driver, and there is a problem that the display quality of the display screen displayed on the liquid crystal display panel is significantly deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a semiconductor integrated circuit device used in a liquid crystal display device, which can operate at high speed, and It is an object of the present invention to provide a technology capable of increasing the screen size of a display element. Another object of the present invention is to provide a technique that enables a liquid crystal display device to operate at a high speed and increase the size of a liquid crystal display element. Another object of the present invention is to provide a technology that enables a display quality of a display screen displayed on a liquid crystal display element to be improved in a liquid crystal display device. The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention relates to a semiconductor integrated circuit device used in a liquid crystal display device, wherein a precharge voltage generated by each precharge voltage generating means is set within a predetermined period (precharge period) at the beginning of one horizontal scanning period. Switching means for outputting a voltage to each video signal line, and outputting the gradation voltage selected by each of the gradation voltage selection means to each video signal line during the other period.
According to the means, the precharge voltage supplied to each video signal line of the liquid crystal display element during the precharge period is set to the voltage level of the gradation voltage supplied to each video signal line within one horizontal scanning period. Since the voltage is determined according to the voltage level of the gray scale voltage, the writing time of each pixel can be made substantially constant, high-speed operation can be performed, and the liquid crystal display device can have a large screen.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit device used in a liquid crystal display device, wherein each gray scale voltage selecting means selects the gray scale voltage within one horizontal scanning period in a region near a display element on the semiconductor integrated circuit device side. The pre-charge voltage supplied from the power supply line is supplied to each of the video signal lines during the first predetermined period (pre-charge period) in one horizontal scanning period of the region other than the neighboring region. A switching unit that outputs to the video signal line, and outputs a gray scale voltage selected by each gray scale voltage selection unit to each video signal line within a period other than a predetermined period in one horizontal scanning period of a region other than the neighboring region; It is characterized by the following. According to the above means, during the precharge period, a larger precharge voltage is supplied to a pixel that is farther from the semiconductor integrated circuit device, so that the writing time of each pixel is independent of the distance from the semiconductor integrated circuit device. Can be almost constant, high-speed operation can be performed, and a large screen of the liquid crystal display element can be realized.

Further, the present invention is a liquid crystal display device including any one of the semiconductor integrated circuit devices as the video signal line driving means. According to the means, it is possible to quickly charge and discharge the pixels far from the video signal line driving means, so that high-speed operation of the liquid crystal display device is possible, and it is possible to enlarge the liquid crystal display element, The display quality of the display screen can be improved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. [Embodiment 1] <Basic configuration of display device to which the present invention is applied> FIG. 1 is a block diagram showing a basic configuration of a TFT type liquid crystal display module to which the present invention is applied. In FIG. 1, reference numeral 10 denotes a liquid crystal display panel (TFT-LCD). The liquid crystal display panel 10 includes a TFT substrate on which pixel electrodes and thin film transistors are formed, and a filter substrate on which counter electrodes, color filters, and the like are formed. The two substrates are laminated together with a sealing material provided in a frame shape in the vicinity of the peripheral portion between the two substrates with a predetermined gap therebetween, and between the two substrates through a liquid crystal sealing opening provided in a part of the sealing material. The liquid crystal is sealed and sealed inside the sealing material, and a polarizing plate is attached outside the both substrates. On a glass substrate of the TFT substrate, a plurality of drain drivers 130 and a gate driver constituted by a semiconductor integrated circuit device (IC) are mounted. The interface unit 100 mounted on the interface board is disposed behind the liquid crystal display panel 10.

<Structure of liquid crystal display panel 10 shown in FIG. 1>
FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel 10 shown in FIG. As shown in FIG. 2, the liquid crystal display panel 10 has a plurality of pixels formed in a matrix. Each pixel includes two adjacent signal lines (a drain signal line (D) or a gate signal line (G)) and two adjacent signal lines (a gate signal line (G) or a drain signal line (D)). And is arranged in the intersection area with. Each pixel has a thin film transistor (TFT1, TFT2), and the source electrode of the thin film transistor (TFT1, TFT2) of each pixel is connected to the pixel electrode (ITO1). Since a liquid crystal layer is provided between the pixel electrode (ITO1) and the common electrode (ITO2), a liquid crystal capacitance (CLC) is equivalently provided between the pixel electrode (ITO1) and the common electrode (ITO2). Connected. Furthermore, thin film transistors (TFT1,
An additional capacitor (CADD) is connected between the source electrode of the TFT 2) and the previous gate signal line (G).

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel 10 shown in FIG. In the example shown in FIG.
Although an additional capacitance (CADD) is formed between the gate signal lines (G) and the source electrodes in all stages, in the equivalent circuit of the example shown in FIG. 3, between the common signal line (CN) and the source electrodes Are different in that a storage capacitor (CSTG) is formed in the storage capacitor. Although the present invention can be applied to both, in the former method, the former gate signal line (G) pulse jumps into the pixel electrode (ITO1) via the additional capacitance (CADD), whereas the latter method. In this case, since there is no dive, better display is possible. 2 and 3 show an equivalent circuit of a vertical electric field type liquid crystal display panel. In FIGS. 2 and 3, AR is a display area. 2 and 3
Is a circuit diagram, which is drawn corresponding to the actual geometric arrangement. In the liquid crystal display panel 10 shown in FIGS. 2 and 3, the thin film transistors (T
The drain electrodes of FT) are connected to drain signal lines (D), respectively, and each drain signal line (D) is connected to a drain driver 130 that applies a gradation voltage to the liquid crystal of each pixel in the column direction. The gate electrode of the thin film transistor (TFT) in each pixel arranged in the row direction is
Each gate signal line (G) is connected to the gate signal line (G), and each gate signal line (G) is connected to the gate electrode of the thin film transistor (TFT) of each pixel in the row direction for one horizontal scanning time by a scanning drive voltage (positive bias voltage or negative (Bias voltage).

<Outline of Configuration and Operation of Interface Unit 100 shown in FIG. 1> The interface unit 100 shown in FIG.
It comprises a display control device 110 and a power supply circuit 120. The display control device 110 includes one semiconductor integrated circuit (L
SI), based on the display control signals and display data (R, G, B) of the clock signal, display timing signal, horizontal synchronization signal, and vertical synchronization signal transmitted from the computer main body. Drain driver 13
0 and the gate driver 140 is controlled and driven.
When a display timing signal is input, the display control device 110 determines that the display timing signal is a display start position, and sends a start pulse (display data capture start signal) to the signal line 135.
To the first drain driver 130 via
Further, the received simple one-column display data is transferred to the drain driver 130 via the display data bus line 133.
Output to At this time, the display control device 110 generates a display data latch clock (CL2) (hereinafter simply referred to as a clock (CL2)) which is a display control signal for latching display data in a data latch circuit of each drain driver 130.
Called. ) Is output via the signal line 131.

The display data from the main computer is 6
Bits are transferred in units of one pixel, that is, data of red (R), green (G), and blue (B) as one set for each unit time. The latch operation of the data latch circuit in the first drain driver 130 is controlled by the start pulse input to the first drain driver 130. When the latch operation of the data latch circuit in the first drain driver 130 ends, a start pulse is input from the first drain driver 130 to the second drain driver 130, and the second drain driver 130 The latch operation of the data latch circuit is controlled. Hereinafter, similarly, the latch operation of the data latch circuit in each drain driver 130 is controlled to prevent erroneous display data from being written to the data latch circuit.

When the input of the display timing signal is completed or when a predetermined time passes after the input of the display timing signal, the display control device 110 determines that the display data for one horizontal line is completed. An output timing control clock (CL1) which is a display control signal for outputting display data stored in the data latch circuit of the drain driver 130 to the drain signal line (D) of the liquid crystal display panel 10 (hereinafter simply referred to as a clock (CL1) ) Is output to each drain driver 130 via a signal line 132.

When the first display timing signal is input after the input of the vertical synchronizing signal, the display control device 110 determines that the first display timing signal is the first display line, and determines the first display timing signal via the signal line 142. A frame start instruction signal (FLM) is output to 140. Further, based on the horizontal synchronization signal, the display control device 110 sequentially applies a positive bias voltage to each gate signal line (G) of the liquid crystal display panel 10 every one horizontal scanning time so as to apply a positive bias voltage.
A clock (CL3), which is a shift clock of one horizontal scanning time cycle, is output to the gate driver 140 via 41. Thereby, a plurality of thin film transistors (TFT) connected to each gate signal line (G) of the liquid crystal display panel 10
Are conducted for one horizontal scanning time. By the above operation,
An image is displayed on the liquid crystal display panel 10.

<Structure of power supply circuit 120 shown in FIG. 1> FIG.
The power supply circuit 120 includes a positive voltage generation circuit 121, a negative voltage generation circuit 122, a common electrode (counter electrode) voltage generation circuit 123, and a gate electrode voltage generation circuit 124. The positive voltage generation circuit 121 and the negative voltage generation circuit 122
Each of the positive voltage generating circuits 121 is formed of a series resistance voltage dividing circuit.
0 to V ″ 4), the negative voltage generation circuit 122 outputs, for example, a five-level negative polarity reference voltage (V ″ 5 to V ″ 9). “0” to “V” 4) and the negative gray scale reference voltage (V “5 to V” 9) are supplied to each drain driver 130. In addition, each drain driver 130 receives a signal from the display control device 110. Is also supplied via a signal line 134. The common electrode voltage generation circuit 123 supplies a drive voltage to be applied to the common electrode (ITO2), and the gate electrode voltage generation circuit 124 supplies A driving voltage (a positive bias voltage and a negative bias voltage) to be applied to the gate electrode of the thin film transistor (TFT) is generated.

<Configuration of Drain Driver 130 shown in FIG. 1> FIG. 4 is a block diagram showing a schematic configuration of an example of the drain driver 130 shown in FIG. Note that the drain driver 130 is configured by one semiconductor integrated circuit (LSI). In the figure, a positive polarity gradation voltage generation circuit 15
1a generates a positive-polarity 64 gray-scale voltage based on a positive-polarity 5-value gray-scale reference voltage (V "0 to V" 4) input from the positive voltage generation circuit 121, Bus line 1
Output to the output circuit 157 via 58a. The negative-polarity gray-scale voltage generation circuit 151b receives the negative five-level gray-scale reference voltage (V "5 to V") input from the negative voltage generation circuit 122.
Based on 9), a negative gradation voltage of 64 gradations is generated and output to the output circuit 157 via the voltage bus line 158b. The control circuit 1 of the drain driver 130
The shift register circuit 153 in the display control device 1
On the basis of the clock (CL2) input from the control circuit 10, a signal for capturing data of the input register circuit 154 is generated and output to the input register circuit 154.

The input register circuit 154 receives a clock (C) input from the display control device 110 based on the data fetch signal output from the shift register circuit 153.
In synchronization with L2), 6-bit display data for each color is latched by the number of output lines. Storage register circuit 155
Is a clock (CL) input from the display control device 110.
According to 1), the display data in the input register circuit 154 is latched. The display data captured by the storage register circuit 155 is input to the output circuit 157 via the level shift circuit 156. The output circuit 157
Select one gray scale voltage (one gray scale voltage out of 64 gray scales) corresponding to the display data based on the 64 gray scale voltages of positive polarity or 64 gray scale voltages of negative polarity do it,
Output to each drain signal line (D).

<Method of AC Drive of Liquid Crystal Display Module Shown in FIG. 1> Generally, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed.
As a result, an afterimage phenomenon is caused, and the life of the liquid crystal layer is shortened. In order to prevent this, in the liquid crystal display module, the voltage applied to the liquid crystal layer is converted into an alternating voltage every certain time, that is, based on the voltage applied to the common electrode, the voltage applied to the pixel electrode is The voltage is changed to the positive voltage side / negative voltage side at regular intervals. As a driving method for applying an AC voltage to the liquid crystal layer, two methods, a common symmetry method and a common inversion method, are known. The common inversion method is a method of alternately inverting the voltage applied to the common electrode and the voltage applied to the pixel electrode to positive and negative.
The common symmetry method is a method in which the voltage applied to the common electrode is made constant, and the voltage applied to the pixel electrode is alternately inverted to positive and negative with respect to the voltage applied to the common electrode. . The common symmetry method uses the pixel electrode (ITO1)
The amplitude of the voltage applied to the LCD is twice as large as that of the common inversion method, and there is a drawback that a driver with a low breakdown voltage cannot be used unless a liquid crystal with a low threshold voltage is developed. The dot inversion method or the N-line inversion method, which is excellent in quality, can be used.

FIG. 5 shows a case where the dot inversion method is used as a driving method of the liquid crystal display module. The liquid crystal driving voltage (ie, the pixel electrode (ITO1)) output from the drain driver 130 to the drain signal line (D) is used. FIG. 3 is a diagram for explaining the polarity of applied gradation voltages. When the dot inversion method is used as a driving method of the liquid crystal display module, as shown in FIG. 5, for example, in an odd line of an odd frame, a common signal is supplied from the drain driver 130 to an odd drain signal line (D). Electrode (ITO2)
A liquid crystal driving voltage (indicated by ● in FIG. 5) of a negative polarity with respect to a liquid crystal driving voltage (VCOM) applied to the common electrode (ITO2) is applied to the even-numbered drain signal lines (D).
Is applied to the liquid crystal drive voltage (VCOM) applied to the positive electrode. Further, in the even-numbered lines of the odd-numbered frame, the drain driver 130 applies a positive liquid crystal drive voltage to the odd-numbered drain signal lines (D) and a negative liquid crystal drive voltage to the even-numbered drain signal lines (D). Is applied.

The polarity of each line is inverted for each frame. That is, as shown in FIG. 5, in an odd line of an even frame, a positive polarity is applied from the drain driver 130 to an odd drain signal line (D). , And a negative-polarity liquid crystal drive voltage is applied to the even-numbered drain signal lines (D). Further, in the even lines of the even frame, the drain driver 130 applies a negative liquid crystal drive voltage to the odd drain signal lines (D) and a positive liquid crystal drive voltage to the even drain signal lines (D). Is applied. By using the dot inversion method, the voltages applied to the adjacent drain signal lines (D) have opposite polarities, so that the current flowing through the common electrode (ITO2) or the gate electrode of the thin film transistor (TFT) is not adjacent to each other. The power consumption can be reduced by canceling each other. Further, since the current flowing through the common electrode (ITO2) is small and the voltage drop does not increase, the voltage level of the common electrode (ITO2) is stabilized, and the deterioration of display quality can be minimized.

<Characteristic Configuration of Liquid Crystal Display Module of the Present Embodiment> FIG. 6 is a diagram showing a basic configuration of the output circuit 157 of the drain driver 130 of the liquid crystal display module of the first embodiment of the present invention. FIG. 6 shows a configuration per drain signal (D).
Reference numeral 20 denotes, for example, an output pad of the drain driver 130 (semiconductor chip) electrically connected to the n-th drain signal line. As shown in FIG. 6, the output circuit 157 of the drain driver 130 according to the present embodiment includes a decoder circuit 261, an output amplifier circuit 263, and a precharge circuit provided between the decoder circuit 261 and the output amplifier circuit 263. 230. Here, the precharge circuit 230 includes a level shift circuit 231 and switch circuits (232, 233). The switch circuit 232 is turned on by a pulse (Cpc) during a precharge period in one horizontal scanning period, and the output of the level shift circuit 231 is input to the output amplifier circuit 263 during the precharge period. Also, the switch circuit 23
3 is turned on during a period other than the precharge period in one horizontal scanning period, and the output of the decoder circuit 263 is input to the output amplifier circuit 263 during the period other than the precharge period. Thus, the level shift circuit 231 supplies the drain signal line (D) to the drain signal line (D) during the precharge period.
A grayscale voltage corresponding to the display data output from the decoder circuit 263 and a voltage whose voltage level is shifted are supplied. Then, after the end of the precharge period, the output amplifier circuit 263 follows the output of the decoder circuit 261 and supplies a gray scale voltage corresponding to the display data to the drain signal line (D).

<Output Circuit 1 of Conventional Liquid Crystal Display Module>
Configuration of 57> FIG. 7 is a diagram showing a configuration of an output circuit 157 of the drain driver 130 of the conventional liquid crystal display module. Note that FIG. 7 also shows only one output system, and 33 indicates an output pad. In the conventional liquid crystal display module, a decoder circuit 31 is separated from an output amplifier circuit 32 by a precharge circuit 30 during a precharge period, and a fixed precharge voltage (Vpre) is input to the output amplifier circuit 32. Is done.
Thus, the precharge voltage (Vpre) is supplied to the drain signal line (D) during the precharge period. 8 to 11 are diagrams showing a voltage change of the pixel electrode (ITO1) of the pixel during one horizontal scanning period. In these figures, (a) shows the drain driver 1
The voltage fluctuation of the pixel at the near end (or near) close to 30 is
(B) shows the voltage fluctuation of the pixel at the far end far from the drain driver 130. In these figures, the final potential indicates the voltage level of the gray scale voltage supplied to the drain signal line during one horizontal scanning period, and the PC period indicates a precharge period. FIG. 8 shows the voltage fluctuation of the pixel electrode (ITO1) when there is no precharge circuit. This FIG.
As is apparent from the above, when there is no precharge circuit, the time (tDD) until the pixel at the far end far from the drain driver 130 reaches the final potential is long.

FIG. 9 shows a precharge circuit 30 shown in FIG.
5 shows the voltage fluctuation of the pixel electrode (ITO1) when the pixel is provided. As is apparent from FIG. 9, when the precharge circuit 30 shown in FIG. 7 is provided, the pixel is charged by the fixed precharge voltage (Vpre) during the precharge period. The time (tDD) until the pixel at the far end far from the drain driver 130 reaches the final potential can be made shorter than the case shown in FIG. FIG. 10 shows the final potential and the common electrode (ITO).
7 shows a voltage variation of the pixel electrode (ITO1) in the case where the precharge circuit 30 shown in FIG. 7 is provided when the potential difference from the common voltage (VCOM) supplied to 2) is small and close. In a normally white type liquid crystal display panel, a white level is represented when the potential difference between the final potential and the common voltage (VCOM) is the smallest. As is clear from FIG. 10, when the potential difference between the final potential and the common voltage (VCOM) is small, the pixel electrode (ITO1) reaches the final potential after being once charged to the precharge voltage (Vpre). Therefore, as a result, the time (tDD) until the pixel at the far end far from the drain driver 130 reaches the final potential cannot be made shorter than the case shown in FIG. That is, the precharge circuit 3 shown in FIG.
At 0, there is no effect when the potential difference between the gradation voltage supplied to the drain signal line during one horizontal scanning period and the common voltage (VCOM) is small.

FIG. 11 shows the voltage fluctuation of the pixel electrode (ITO1) when the precharge circuit 230 of the present embodiment is provided. This FIG. 11 shows the final potential, as in FIG.
The voltage fluctuation of the pixel electrode (ITO1) when the potential difference from the common voltage (VCOM) is small is shown. In this embodiment mode, a grayscale voltage whose voltage level has been shifted by the level shift circuit 231 is supplied to the pixel during the precharge period. As a result, in the present embodiment, the gray scale voltage supplied to the drain signal line (D) during one horizontal scanning period,
When the potential difference from the common voltage (VCOM) is small, the time (tDD) until the pixel at the far end far from the drain driver 130 reaches the final potential can be made shorter than the case shown in FIG. Further, even when the potential difference between the gray scale voltage supplied to the drain signal line in one horizontal scanning period and the common voltage (VCOM) is large, the gray scale voltage itself whose voltage level is shifted by the level shift circuit 231 is used. However, it is needless to say that the time until the pixel at the far end far from the drain driver 130 reaches the final potential (tDD) can be made shorter than that shown in FIG. In the above description, the case where the positive gradation voltage is written to the pixel within one horizontal scanning period has been described. However, even when the negative gradation voltage is written to the pixel, the far end far from the drain driver 130 may be used. (TD) until the pixel of FIG.
It goes without saying that D) can be made smaller than the case shown in FIG. However, in this case, it should be noted that the magnitude relationship between the voltages is opposite around the common voltage (VCOM).

FIG. 12 is a circuit diagram showing a specific circuit configuration of precharge circuit 230 of the present embodiment. FIG.
In the circuit configuration shown in FIG. 2, a positive polarity circuit includes a high voltage decoder circuit 278 that outputs a positive polarity gray scale voltage, and a p-type M
OS transistor (hereinafter simply referred to as PMOS)
(PM11) and a PMOS (PM12), an output amplifier circuit composed of an operational amplifier (OP11), and a PM constituting a switch circuit.
It is composed of OS (PM13, PM14). Similarly, the negative polarity circuit includes a low voltage decoder circuit 279 that outputs a positive polarity gray scale voltage, and an n-type MOS transistor (hereinafter, referred to as an n-type MOS transistor).
Simply referred to as MMOS. ) (NM11) and NMO
S (NM12), an output amplifier circuit including an operational amplifier (OP12),
The NMOS (NM13, NM1) constituting the switch circuit
4). Here, the PMOS (PM13) and the NMOS (NM14) are driven by the control signal (Cen), and the PMOS (PM14) and the NMOS (NM1) are driven.
3) is driven by the control signal (Cpc).

In this embodiment, the control signal (Cp
c) is the clock (CL1) and the control signal (Ce)
n) uses an inverted clock of the clock (CL1), but these control signals (Cen, Cpc) may be generated from the clock (CL1). Also,
The transfer gate circuits (TG1 to TG4) transmit a positive gradation voltage and a negative gradation voltage, for example, to the first drain signal line (D) and the fourth drain signal line every one horizontal scanning period.
Alternately with the drain signal line (D)
Output to the output pad 220. A control signal (ACKE) for controlling the transfer gate circuits (TG1 to TG4)
P, ACKOP) is generated from the AC signal (M).

In the positive polarity circuit shown in FIG. 12, the PMOS (PM13) is turned on during the precharge period,
The gradation voltage whose voltage level has been increased by the threshold voltage (Vth) of the OS (PM12) is supplied to the drain signal line (D). In the negative polarity circuit, the NMOS (NM13) is turned on during the precharge period, and the NMOS (NM13) is turned on.
The grayscale voltage whose voltage level is reduced by the threshold voltage (Vth) of (NM11) is supplied to the drain signal line (D). In FIG. 12, Vb1 is the PMO
The bias voltage Vb2 applied to the gate electrode of S (PM11) is the bias voltage applied to the gate electrode of NMOS (NM12).

[Second Embodiment] FIG. 13 is a diagram showing a basic configuration of an output circuit 157 of a drain driver 130 in a TFT type liquid crystal display module according to a second embodiment of the present invention. Note that FIG. 13 shows the configuration per drain signal (D), and the output pad 220 shown in FIG. 6 is omitted. Hereinafter, the output circuit 157 of the drain driver 130 according to the present embodiment will be described focusing on differences from the first embodiment. As shown in FIG. 13, the output circuit 15 of the present embodiment
The precharge circuit 330 includes a comparison circuit 331 to which display data is input, and a switch circuit (332 to 336).
It is composed of In the present embodiment, for example, the voltage level of the gradation voltage is divided into three stages, and each of the three stages is divided into VPre1 to VP
The precharge voltage of re3 is supplied to the drain signal line (D).

Generally, the gray scale voltage supplied to the drain signal line (D) depends on display data. Therefore, in this embodiment, a comparison circuit to which display data is input is used to determine at which stage the voltage level of the gray scale voltage supplied to the drain signal line (D) during one horizontal scanning period corresponds. In step 331, one of the switch circuits (334 to 336) is turned on, and one of the precharge voltages Vpre1 to Vpre3 is supplied to the drain signal line (D) based on the result of the determination by the comparison circuit 331. I do. Thereby, in the present embodiment, the drain signal line (D) is
During the precharge period, a precharge voltage according to the voltage level divided into three stages of the gray scale voltage is supplied. After the precharge period, the output amplifier circuit 263 follows the output of the decoder circuit 261 and outputs the drain voltage. Signal line (D)
Is supplied with a gradation voltage corresponding to the display data. As described above, also in the present embodiment, it is possible to obtain the same effect as in the first embodiment.

FIG. 14 is a circuit diagram showing a specific circuit configuration of an example of the output circuit 157 of the drain driver 130 according to the present embodiment. In the circuit shown in FIG. 14, the voltage level of the gray scale voltage is divided into two stages, and each of the two stages is divided into Vpre1, Vpr within the precharge period.
The precharge voltage of e2 is supplied to the drain signal line (D). That is, in the circuit shown in FIG. 14, when the value of the most significant bit (MSB) of the display data is “0”, the NMOS
(NM22) is turned on, and during the precharge period, V
The precharge voltage of pre2 is supplied to the drain signal line (D). Also, the most significant bit (MS) of the display data
When the value of B) is "1", the NMOS (NM21) is turned on, and the precharge voltage of Vpre1 is supplied to the drain signal line (D) during the precharge period. Therefore, even with the circuit shown in FIG. 14, the same effect as in the first embodiment can be obtained.

[Embodiment 3] As shown in FIGS. 8 to 11, the time (tDD) for a pixel to reach the final potential during one horizontal scanning period is longer for a pixel at a far end far from the drain driver 130. Is big. Therefore, in the present embodiment, the display area of the liquid crystal display panel is divided into a plurality of areas, and the farther from the drain driver 130, the higher the precharge voltage supplied to the drain signal line (D) during the precharge period. It is something to do. For this reason, in the present embodiment, a counter circuit 160 for determining to which region the line currently being scanned belongs is provided in the drain driver 130. FIG. 15 is a diagram showing a counter circuit 160 of the drain driver 130 in the TFT type liquid crystal display module according to the third embodiment of the present invention. The counter circuit 160 of the present embodiment is a 10-bit counter circuit that counts a clock (CL1), and is reset by a frame start instruction signal (FLM). The ninth output (Q8) and the tenth output (Q9) of the counter circuit 160 are input to a NOR circuit (NOR11), and the output of the NOR circuit (NOR11) becomes a control signal (NPC). Also, the tenth output (Q
9) is inverted by an inverter circuit (IV11) to become a control signal (/ Qo), and is further inverted by an inverter circuit (IV).
The control signal (Qo) is inverted by 12). here,
(/ Qo) represents an inverted output of (Qo).

FIG. 16 shows a TFT according to the third embodiment of the present invention.
Driver 1 in a liquid crystal display module of the display system
FIG. 14 is a circuit diagram showing a specific circuit configuration of 30 output circuits 157. Ninth output of counter circuit 160 (Q8)
When both the 10th output (Q9) and the tenth output (Q9) are “0”, the control signal (NPC) is at the High level (hereinafter, simply referred to as the H level).
3) is turned off, and the NMOS (NM34) is turned on. Therefore, in this embodiment, the precharge voltage is not supplied to the drain signal line (D) during the precharge period until the ninth output (Q8) of the counter circuit 160 becomes “1”. The ninth output (Q
8) Or, when the tenth output (Q9) becomes “1”, the control signal (NPC) becomes Low level (hereinafter simply referred to as L level).
3) turns on, and the NMOS (NM34) turns off.

Therefore, in the present embodiment, when the ninth output (Q8) of the counter circuit 160 becomes "1", the precharge voltage is supplied to the drain signal line (D) within the precharge period. In this case, the counter circuit 16
If the tenth output (Q9) of “0” is “0”, the control signal (Qo) becomes L level, so that the PMOS (PM3
2) is off, the PMOS (PM31) is on, and PM
Since a bias voltage of Vb2 is applied to the gate electrode of OS (PM30), the PMOS (PM30) is turned off. Therefore, when the ninth output (Q8) of the counter circuit 160 is “1” and the ninth output (Q9) is “0”, the PMO is calculated from the grayscale voltage during the precharge period.
The voltage whose voltage level has been increased by the threshold voltage (Vth) of S (PM12) is supplied to the drain signal line (D). Also, the tenth output (Q
9) is “1”, the control signal (Qo) goes high, so that the PMOS (PM32) is turned on and the PMOS (P
M31) is turned off, and the bias voltage of VLCD is applied to the gate electrode of the PMOS (PM30).
The PMOS (PM30) is turned on. Therefore, the ninth output (Q8) of the counter circuit 160 is “1”,
When the output (Q9) is “1”, the voltage lower than the voltage of the VLCD by the threshold voltage (Vth) of the PMOS (PM12) during the precharge period is the drain signal line ( D).

FIG. 17 is a diagram for explaining the precharge voltage supplied to each pixel in the present embodiment. In FIG. 17, a square represents a display area (AR). The near-end area shown in FIG. 17 is an area where the ninth output (Q8) of the counter circuit 160 is “0”,
This is a region where the precharge voltage is not supplied to the drain signal line (D) during the precharge period. The intermediate area is an area where the ninth output (Q8) of the counter circuit 160 is “1” and the ninth output (Q9) is “0”, and during the precharge period, the PMOS (PM12) This is a region where the grayscale voltage whose voltage level has been increased by the threshold voltage (Vth) is supplied to the drain signal line (D).
Similarly, the far-end area is an area where the ninth output (Q8) of the counter circuit 160 is “1” and the ninth output (Q9) is “1”.
From the threshold voltage (Vt) of the PMOS (PM12).
The voltage whose voltage level is reduced by h) is supplied to the drain signal line (D).

<Modification of Liquid Crystal Display Module of the Present Embodiment> FIG. 18 is a specific example of another example of the output circuit 157 of the drain driver 130 in the TFT type liquid crystal display module of the third embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a circuit configuration. The output circuit 157 shown in FIG. 18 changes the precharge voltage supplied to the drain signal line (D) according to the value of the display data (that is, the voltage level of the gray scale voltage) during the precharge period. It is like that. In FIG. 18, when the ninth output (Q8) of the counter circuit 160 is “1”, the NMOS (NM3
3) turns on, and the NMOS (NM34) turns off. When the tenth output (Q9) of the counter circuit 160 is "0", the NMOS (NM41) is turned on and the NMO
S (NM44) turns off. Here, NMOS (NM
41) is connected to Vpre1 via an NMOS (NM42).
And the precharge voltage of Vpre2 is supplied via the NMOS (NM43). The most significant bit of the display data is applied to the gate electrode of the NMOS (NM42), and the inverted value of the most significant bit of the display data is applied to the gate electrode of the NMOS (NM43).

Therefore, when the NMOS (NM41) is on and the value of the most significant bit of the display data is "0", the precharge voltage of Vpre2 is supplied to the drain signal line (D) during the precharge period. When the value of the most significant bit of the display data is "1", the precharge voltage of Vpre1 is supplied to the drain signal line (D) during the precharge period. Similarly, the counter circuit 1
When the ninth output (Q8) of the 60 is “1” and the tenth output (Q9) is “1”, the NMOS (NM41) is turned off and the NMOS (NM44) is turned on. When the value of the most significant bit of the display data is “0”, the NMOS
(NM45) is off, the NMOS (NM46) is on, and when the value of the most significant bit of the display data is "1", the NMOS (NM45) is on and the NMOS (NM4)
6) is turned off. Therefore, the NMOS (NM44)
Is on and the value of the most significant bit of the display data is “0”, the precharge voltage of Vpre4 is supplied to the drain signal line (D) during the precharge period, and the most significant bit of the display data is When the value of the bit is "1", the precharge voltage of Vpre3 is supplied to the drain signal line (D) during the precharge period. In the present embodiment, the counter circuit 160 is connected to each drain driver 130
Has been described, but the counter circuit 160
May be provided in any one of the gate drivers 140 or the display control device 110.

[Embodiment 4] In this embodiment, the present invention uses a switched capacitor circuit for the output circuit 157, and uses a single amplifier circuit for an amplifier circuit for a switched capacitor circuit and an output amplifier circuit. This is an embodiment in which the present invention is applied to a drain driver 130 that also serves as a drain driver. FIG.
FIG. 14 is a circuit diagram showing a basic configuration of an output circuit 157 of a drain driver 130 in a TFT type liquid crystal display module according to a fourth embodiment of the present invention. In FIG. 19,
The configuration per drain signal (D) is shown, and the output pad 220 shown in FIG. 6 is not shown. As shown in FIG. 19, an NMOS (N) is connected between the inverting input terminal (−) of the operational amplifier (OP21) and the output terminal.
M59) and a parallel circuit of the capacitor (CA1) are connected, and one terminal of the capacitors (CA2, CA3) is connected to the inverting input terminal (-) of the operational amplifier (OP21). The other terminal of the capacitor (CA2) is connected to the decoder circuit B via the NMOS (NM55), the NMOS (NM51), and the NMOS (NM56).
(362) and the NMOS (NM5
5) and the decoder circuit A via the NMOS (NM52).
(361).

Similarly, the other terminal of the capacitor (CA3) includes an NMOS (NM57) and an NMOS (NM53),
And a decoder circuit B via the NMOS (NM58)
(362) and the NMOS (NM5
7) and the decoder circuit A via the NMOS (NM54).
(361). The non-inverting input terminal (+) of the operational amplifier (OP21) is connected to the decoder circuit A (361), and the output of the operational amplifier (OP21) is an NMOS.
It is connected to the output pad via (60). The output of the decoder circuit A (361) is supplied to the sub-amplifier circuit 363.
And the output of the sub-amplifier circuit 363 is NMOS
(NM61) is connected to the output pad. Here, the operational amplifier (OP21) doubles as an amplifier circuit for the switched capacitor circuit and an output amplifier circuit, and the sub-amplifier circuit 363 is a precharge amplifier.

The gate electrode of the NMOS (NM51)
The least significant bit value (Dn) of the display data is applied, and NM
The inverted value of the least significant bit value (Dn) of the display data is applied to the gate electrode of the OS (NM52). NMOS
A bit value (Dn + 1) one upper than the least significant bit of the display data is applied to the gate electrode of (NM53).
The inverted value of the bit value (Dn + 1) immediately above the least significant bit of the display data is applied to the gate electrode of the OS (NM54. The NMOS (NM56) and the NMOS (NM5)
8), NMOS (NM59), and NMOS (NM6)
The control signal (Cres) is applied to the gate electrode of 1), and the control signal (Cen) is applied to the gate electrodes of the NMOS (NM55), the NMOS (NM57), and the NMOS (NM60). Here, the control signal (Cre
s) is a clock (CL1) and a control signal (Ce)
n) is an inverted clock of the clock (CL1),
These control signals (Cen, Cpc) are based on the clock (C
L1). Further, the capacitance value obtained by adding the capacitance value of the capacitor (CA2) and the capacitance value of the capacitor (CA3) is substantially equal to the capacitance value of the capacitor (CA1). Further, the decoder circuit A (361) outputs a first halftone voltage (Va), and the decoder circuit B (362) outputs a second halftone voltage (Vb).

Hereinafter, the operation of the output circuit 157 of this embodiment will be described. In the output circuit 157 of this embodiment, when the control signal (Cres) is at the H level (that is, the control signal (Cen) is at the L level) (during a reset operation),
MOS (NM56), NMOS (NM58), NMOS
(NM59) and NMOS (NM61) are on.
MOS (NM55), NMOS (NM57), and N
The MOS (NM60) turns off. In this state, the capacitor (CA1) is reset, the operational amplifier (OP21) forms a voltage follower circuit, and the output terminal and the inverting input terminal (-) of the operational amplifier (OP21).
Is the voltage of (VA). The other of the capacitors (CA2, CA3) is connected to the decoder circuit B (36).
2), each capacitor (CA2, CA2
3) is charged to a voltage of ΔV (= Vb−Va). Also, the NMOS (NM61) is turned on and the NMOS (NM6)
0) is turned off, so that the first intermediate gradation voltage (Va) output from the decoder circuit A (361) is supplied to the drain signal line (D).

When the control signal (Cres) is at the L level (ie,
When the control signal (Cen) is at H level (during normal operation)
NMOS (NM56), NMOS (NM58), N
The MOS (NM59) and the NMOS (NM61) are turned off, and the NMOS (NM55), the NMOS (NM57), and the NMOS (NM60) are turned on. In this state, the NMOSs (NM51 to NM54) are turned on or off depending on the value of the lower two bits of the display data. As a result, the output terminal of the operational amplifier (OP21)
a, Va- ／ ΔV, Va- ／ ΔV, Va-3 /
A gradation voltage of 4ΔV is output. As described above, the switched driver circuit is used for the output circuit 157, and the drain driver 130 that serves as the amplifier circuit for the switched capacitor circuit and the output amplifier circuit with one amplifier circuit is used.
In this case, it is necessary to discharge (reset) the capacitor (CA1) at the time of the reset operation, so that the precharge voltage cannot be supplied to the video signal line (D). However, in the present embodiment, the sub-amplifier circuit 363 is provided,
At the time of the reset operation, a precharge voltage can be supplied from the subamplifier 363 to the drain signal line (D).

<Modification of Liquid Crystal Display Module of the Present Embodiment> FIG. 20 shows a circuit configuration of another example of the output circuit 157 of the drain driver 130 in the TFT type liquid crystal display module of the fourth embodiment of the present invention. FIG. Note that FIG. 20 shows the configuration per drain signal (D), and the output pad 220 shown in FIG. 6 is omitted. The circuit shown in FIG. 20 includes a PMOS (PM71) and a PMOS (P
M72), the voltage level of the first intermediate gradation voltage (Va) output from the decoder circuit A (361) is increased by the threshold voltage (Vth) of the PMOS (PM12). Up, and PMOS
The signal is supplied to the drain signal line (D) via a source follower circuit composed of (PM73) and PMOS (PM74).

FIG. 21 is a circuit diagram showing an example of the decoder circuit A (361) and the decoder circuit B (362) shown in FIGS. 19 and 20, and a circuit configuration of the positive polarity gradation voltage generation circuit 151a. FIG. 21 is a circuit diagram showing a configuration of a decoder circuit on the positive polarity side. In FIG. 21, ○ indicates a switch element (for example, P
MOS switch), and ● represents a switch element (for example, NMO) that turns on when the data bit is at the H level.
S transistor). Note that FIG. 21 illustrates an example of a circuit configuration in the case of generating a gradation voltage of 64 gradations. As shown in the figure, the positive polarity gradation voltage generation circuit 151a
As in the first embodiment, the gray scale voltage of 64 gray scales is not generated, and the positive polarity 5 input from the positive voltage generation circuit 121 is not generated.
A first gradation voltage of 17 gradations of positive polarity is generated based on the gradation reference voltage (V "0 to V" 4) of the value.

The decoder circuit A (361) selects the upper 6 bits of the 8-bit display data from the odd-numbered intermediate gradation voltages.
A first halftone voltage corresponding to the bits (D2 to D5) is selected. The decoder circuit B (362) selects the second intermediate gray scale voltage corresponding to the upper 3 bits (D3 to D5) of the 6-bit display data from the even gray scale voltages. The decoder circuit A (361) uses the upper 4 bits (D2 to D5) of the 6-bit display data to generate a first intermediate gray scale voltage (V1) and a 17th intermediate gray scale voltage (V1).
7) is selected once, and the third to fifteenth intermediate gray scale voltages (V15) are selected twice successively. Decoder circuit B
(362) is the second intermediate gradation voltage (V) based on the upper 3 bits (D3 to D5) of the 6-bit display data.
2) to the sixteenth halftone voltage (V16)
It is configured to select times.

Here, V "0 <V" 1 <V "2 <V" 3
Since <V ″ 4, when the 3-bit (D2) bit value of the display data is at the L level, a gray-scale voltage lower than the gray-scale voltage of VOUTB is output as the gray-scale voltage VOUTA. When the 3-bit (D2) bit value of the display data is at the H level, the grayscale voltage VOUTA is set to VO
A grayscale voltage higher than the grayscale voltage of the UTB is output. Therefore, the multiplexer 302 is switched according to the H level and the L level of the bit value of the third bit (D2) of the display data, and the three bits (D
2) VO is connected to terminal (P1) when the bit value of the
The gradation voltage of UTA is output to the terminal (P2) as the gradation voltage of VOUTB, and the VOUTB is output to the terminal (P1) when the third bit (D2) of the display data is at the H level.
And outputs the gradation voltage of VOUTA to the terminal (P2). As a result, the gradation voltage of the terminal (P1) is changed to (V
a) When the gradation voltage of the terminal (P2) is (Vb),
It is always possible to set Va <Vb. Note that the decoder circuit on the negative polarity side can be configured similarly to the decoder circuit on the positive polarity side.

[Fifth Embodiment] FIG. 22 shows a basic structure of a liquid crystal display panel 10 of a TFT type liquid crystal display module according to a fifth embodiment of the present invention. 8 to 1
As is clear from FIG. 1, the time required for the pixel electrode to reach the final potential within one horizontal scanning period is longer at a far end farther from the drain driver 130. Therefore, in the present embodiment, a switch section 170 is provided at an end of the drain signal line (D) opposite to the end connected to the drain driver 130 (hereinafter simply referred to as the other end), and the precharge is performed. During the charge period, a predetermined precharge voltage (VPRE) is supplied to the other end of the drain signal line (D). Here, the switch unit 170 includes a switch element 151 that connects the other end of the drain signal line (D) and a power supply line to which a precharge voltage (VPRE) is supplied. This switch element 151 is turned on during the precharge period. The switch element 151 may be configured by a semiconductor integrated circuit device (IC) provided on a TFT substrate (SUB1) outside the liquid crystal display panel 10 as shown in FIG. 23, or as shown in FIG. , Liquid crystal display panel 1
In 0, a thin film transistor element (TFT) may be used.

<Modification of Liquid Crystal Display Module of the Present Embodiment> As shown in FIG. 25, in the present embodiment, the switch section 170 is provided with a positive gradation voltage applied during one horizontal scanning period, or The other end of the drain signal line (D) and a power supply line to which a positive precharge voltage (VPREa) is supplied or a negative precharge voltage (VPREb) in accordance with the negative gradation voltage. May be connected to a power supply line to which is supplied. As shown in FIG. 26, the other end of the adjacent drain signal line (D) may be connected by a switch element 171. Further, as shown in FIG. 27, the other ends of two or more drain signal lines (D) may be connected by a switch element 171. In FIGS. 22 to 27, AR indicates a display area. Further, in the present embodiment, the drain driver 130 may not apply the precharge voltage or the constant precharge voltage as described in each of the above embodiments.
In particular, when the resolution of the liquid crystal display panel 10 is large,
The drain driver 130 may be a precharge voltage as described in each of the above embodiments or a constant precharge voltage.
A configuration that can apply a di-voltage is preferable.

Further, in the above embodiment, the embodiment in which the present invention is applied to the liquid crystal display module adopting the dot inversion method has been mainly described. However, the present invention is not limited to this.
The present invention is also applicable to a common inversion method in which a drive voltage applied to the pixel electrode (ITO1) and the common electrode (ITO2) is inverted every line or every frame. As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention.
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist thereof.

[0050]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, in a semiconductor integrated circuit device used for a liquid crystal display device, high-speed operation can be performed, and a large screen of a liquid crystal display element can be realized. (2) According to the liquid crystal display device of the present invention, high-speed operation is enabled, the screen size of the liquid crystal display element can be increased, and the display quality of the display screen displayed on the liquid crystal display element can be improved. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a TFT type liquid crystal display module to which the present invention is applied.

FIG. 2 is a diagram showing an equivalent circuit of an example of the liquid crystal display panel shown in FIG.

FIG. 3 is a diagram showing an equivalent circuit of another example of the liquid crystal display panel shown in FIG.

FIG. 4 is a block diagram illustrating a schematic configuration of an example of a drain driver illustrated in FIG. 1;

FIG. 5 is a diagram for explaining the polarity of a liquid crystal driving voltage output from a drain driver to a drain signal line (D) when a dot inversion method is used as a driving method of a liquid crystal display module.

FIG. 6 is a diagram illustrating a basic configuration of an output circuit of a drain driver of the liquid crystal display module according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a basic configuration of an output circuit of a drain driver of a conventional liquid crystal display module.

FIG. 8 shows a pixel electrode (IT) of a pixel during one horizontal scanning period.
It is a figure which shows the voltage change of O1).

FIG. 9 illustrates a pixel electrode (IT) of a pixel during one horizontal scanning period.
It is a figure which shows the voltage change of O1).

FIG. 10 illustrates a pixel electrode (I) of a pixel during one horizontal scanning period.
It is a figure which shows the voltage change of TO1).

FIG. 11 illustrates a pixel electrode (I) of a pixel during one horizontal scanning period.
It is a figure which shows the voltage change of TO1).

FIG. 12 is a circuit diagram showing a specific circuit configuration of a precharge circuit according to the first embodiment of the present invention.

FIG. 13 is a diagram illustrating a basic configuration of an output circuit of a drain driver in a TFT-type liquid crystal display module according to a second embodiment of the present invention.

FIG. 14 is a circuit diagram illustrating a specific circuit configuration of an example of an output circuit of the drain driver according to the second embodiment of the present invention;

FIG. 15 is a diagram showing a counter circuit of a drain driver in a TFT liquid crystal display module according to Embodiment 3 of the present invention.

FIG. 16 is a circuit diagram showing a specific circuit configuration of an output circuit of a drain driver in a TFT type liquid crystal display module according to Embodiment 3 of the present invention.

FIG. 17 is a diagram illustrating a precharge voltage supplied to each pixel according to the third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a specific circuit configuration of another example of the output circuit of the drain driver in the TFT liquid crystal display module according to the third embodiment of the present invention.

FIG. 19 is a circuit diagram showing a basic configuration of an output circuit of a drain driver in a TFT type liquid crystal display module according to Embodiment 4 of the present invention.

FIG. 20 is a circuit diagram showing a circuit configuration of another example of the output circuit of the drain driver in the TFT liquid crystal display module according to the fourth embodiment of the present invention.

21 is a circuit diagram showing an example of the decoder circuits A and B shown in FIGS. 19 and 20, and a circuit configuration of a positive polarity gray scale voltage generation circuit.

FIG. 22 is a diagram showing a basic configuration of a liquid crystal display panel of a TFT type liquid crystal display module according to Embodiment 5 of the present invention.

FIG. 23 is a diagram showing an example of the switch element according to the fifth embodiment of the present invention.

FIG. 24 is a diagram showing another example of the switch element according to the fifth embodiment of the present invention.

FIG. 25 is a diagram showing a basic configuration of another example of the liquid crystal display panel of the TFT type liquid crystal display module according to the fifth embodiment of the present invention.

FIG. 26 is a diagram showing a basic configuration of another example of the liquid crystal display panel of the TFT type liquid crystal display module according to the fifth embodiment of the present invention.

FIG. 27 is a diagram showing a basic configuration of another example of the liquid crystal display panel of the TFT type liquid crystal display module according to the fifth embodiment of the present invention.

[Explanation of symbols]

10. Liquid crystal display panel (TFT-LCD), 30, 23
0, 330... Precharge control circuit, 31,
61, 278, 279, 361, 362: decoder circuit, 32: amplifier circuit, 33, 220: output pad, 1
00: interface unit, 110: display control device, 12
0: power supply circuit, 121, 122: voltage generation circuit, 123
... common electrode voltage generation circuit, 124 ... gate electrode voltage generation circuit, 130 ... drain driver, 131, 132,
134, 135, 141, 142 ... signal lines, 133 ... bus lines for display data, 140 ... gate drivers, 15
1a, 151b: gradation voltage generation circuit, 152: control circuit, 153: shift register circuit, 154: input register circuit, 155: storage register circuit, 156: level shift circuit, 157: output circuit, 158a, 158
b: voltage bus line, 160: counter circuit, 170:
Switch part, 171, switch element, 231, level shift circuit, 232, 233, 332 to 336, switch circuit, 263, output amplifier circuit, 302, multiplexer, 331, comparison circuit, 363, sub-amplifier circuit, G ...
Gate signal line (scanning signal line or horizontal signal line), ITO
1: pixel electrode, ITO2: common electrode, CL: counter electrode signal line, TFT: thin film transistor, CLC: liquid crystal capacitance,
CSTG: holding capacity, CADD: additional capacity, PM: PMO
S transistor, NM ... NMOS transistor, TG ...
Transfer gate circuit, SUB1 ... TFT substrate, NO
R: NOR circuit, IV: Inverter, OP: Operational amplifier,
CA: condenser, AR: display area.

Continuing from the front page (72) Inventor Shinya Suzuki 3681 Hayano, Mobara-shi, Chiba Prefecture Within Hitachi Device Engineering Co., Ltd. (72) Koichi Kodera 5-2-12-1 Kamisumihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd.・ S.I.Systems Co., Ltd. (72) Inventor Makoto Kimura 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Masahiko Arakawa 3681 Hayano, Mobara-shi, Chiba Within Hitachi Device Engineering Co., Ltd. (72) Inventor Kenji Kawada 3681 Hayano, Mobara-shi, Chiba F-term within Hitachi Device Engineering Co., Ltd. (reference) 2H093 NA16 NA33 NA53 NC04 NC13 NC15 NC22 NC25 NC34 ND33 ND43 5C006 AA01 AA16 AA22 AC28 AF42 AF44 BB16 BC12 BF03 BF04 BF14 BF16 BF22 BF25 BF26 BF27 BF28 BF34 BF43 BF46 FA14 FA56 5C080 AA10 BB05 CC03 DD08 EE29 EE30 FF11 JJ02 JJ03 JJ05

Claims (5)

[Claims] 1. A semiconductor integrated circuit device for supplying a gradation voltage corresponding to display data to each video signal line of a liquid crystal display element, wherein said semiconductor integrated circuit device is electrically connected to each of said video signal lines. A plurality of grayscale voltage output means provided for each output terminal to output grayscale voltages corresponding to display data, and generating a precharge voltage corresponding to the grayscale voltages output from the respective grayscale voltage output means A plurality of precharge voltage generating means for outputting a precharge voltage generated by each of the precharge voltage generating means from each of the output terminals within a predetermined period at the beginning of one horizontal scanning period; And a switching means for outputting a gradation voltage output from each of the gradation voltage output means from each of the output terminals. 2. The gray-scale voltage output unit includes: a gray-scale voltage generation unit configured to generate a plurality of gray-scale voltages; and a plurality of gray-scale voltage output units corresponding to display data from the plurality of gray-scale voltages generated by the gray-scale voltage generation unit. Gradation voltage selection means for selecting and outputting a gradation voltage to be applied, and the gradation voltage selected by each of the gradation voltage selection means,
Or it has a plurality of amplifier circuits for amplifying the precharge voltage generated by each of the precharge voltage generation means and outputting to each output terminal, the switching means, within a predetermined period at the beginning of one horizontal scanning period, The precharge voltage generated by each of the precharge voltage generation means is input to each of the amplifier circuits, and the grayscale voltage selected by each of the grayscale voltage selection means is input to each of the amplifier circuits within the other period. The semiconductor integrated circuit device according to claim 1, wherein: 3. A semiconductor integrated circuit device for supplying a gradation voltage corresponding to display data to each video signal line of a liquid crystal display element, wherein said semiconductor integrated circuit device is electrically connected to each of said video signal lines. A plurality of grayscale voltage output means provided for each output terminal to be output and outputting a grayscale voltage corresponding to display data; and within one horizontal scanning period of a region near the liquid crystal display element on the semiconductor integrated circuit device side. Outputting a gray scale voltage output from each of the gray scale voltage output means from each of the output terminals, and a predetermined voltage supplied from a power supply line within a first predetermined period in one horizontal scanning period of an area other than the adjacent area. A precharge voltage is output from each of the output terminals, and a grayscale voltage output from each of the grayscale voltage output means is output from each of the grayscale voltage output units during a period other than the predetermined period in one horizontal scanning period of a region other than the neighboring region. The semiconductor integrated circuit device characterized by having a switching means for outputting the terminal. 4. The gray-scale voltage output unit generates a plurality of gray-scale voltages, and corresponds to display data from the plurality of gray-scale voltages generated by the gray-scale voltage generation unit. And a gradation voltage selection means for selecting and outputting a gradation voltage to be selected, and amplifying the gradation voltage selected by each gradation voltage selection means or a predetermined precharge voltage and outputting to each output terminal A plurality of amplifier circuits, wherein the switching means changes a gray scale voltage selected by each of the gray scale voltage selecting means within one horizontal scanning period of a region near the semiconductor integrated circuit device of the liquid crystal display element. A predetermined precharge voltage supplied from a power supply line is input to each of the amplifier circuits within a first predetermined period of one horizontal scanning period of a region other than the vicinity region, and the predetermined precharge voltage is input to each of the amplifier circuits. Area other than 4. The semiconductor integrated circuit according to claim 3, wherein a gray scale voltage selected by said gray scale voltage selecting means is input to each of said amplifier circuits during a period other than said predetermined period in one horizontal scanning period. apparatus. 5. A liquid crystal display element comprising: a plurality of pixels; and a plurality of video signal lines for applying a gray scale voltage corresponding to display data to the plurality of pixels, and provided at one end of the liquid crystal display element. As well as
A liquid crystal display device comprising: at least one semiconductor integrated circuit device; and a video signal line driving unit configured to supply a gradation voltage corresponding to display data to each of the video signal lines. 5. A liquid crystal display device comprising: a semiconductor integrated circuit device according to claim 1;