JPH06250606A - Tft type liquid crystal display device - Google Patents

Abstract

PURPOSE:To set a power source voltage to be an optimal value and to suppress the malfunction of the shift register of a driver and the generation of a noise while keeping the writing and holding characteristics in a TFT type liquid crystal display device. CONSTITUTION:The positive power source voltage Vddy and the negative power source voltage Vssy of a scanning line driving circuit are set as the following equation: Vddy>=Vidd2+DELTAVy2, where, Vid2: the maximum value of a picture signal, DELTAVy2: a voltage between a gate and a source in which the ON resistance Ron of an N-type pixel TFT satisfies the following equation specifying a writing ratio larger than k%: Vssy<=Vid1-DELTAVy1, where, Vid1: the minimum value of a picture signal, DELTAVy1: the maximum value of a shifted voltage between the gate and the drain of the pixel TFT at the time of non-selection represented by the following equation. On these conditions, the writing characteristic having the writing ratio larger than k% and the excellent holding characteristic are obtained regardless of a value such as the parasitic capacitance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TFT (thin film transistor) type liquid crystal display device, and more particularly to a scan driver or a data driver set under a predetermined power supply voltage condition.

[0002]

2. Description of the Related Art In general, a circuit structure of a TFT type liquid crystal display device in which a driving circuit is integrally formed on one insulating substrate is shown in FIG. X driver section (data driver section or signal line drive circuit section) 20, Y driver section (scan line drive circuit section)
Three parts of 30 are formed by thin film technology. The pixel matrix section 10 includes signal lines X arranged in a grid pattern.
1, X2, has X3~ and the scanning lines Y1, Y2, ~ and the pixels arranged TFT their intersection (T ₁₁ ~). The source electrode S of each pixel TFT is connected to the signal line X, the gate electrode G is connected to the scanning line Y, and the drain electrode D is connected to the pixel electrode a. The pixel electrode a and the counter electrode b are several μ
They are opposed to each other through a gap of m, and a liquid crystal is filled in this gap. The capacitance C _lc of the liquid crystal works as a storage capacitance for storing an image signal. Since the electric charge accumulated in the liquid crystal capacitance C _lc is discharged by the leak current of the liquid crystal, some of the voltage written in the liquid crystal will be lost. In many cases, a storage capacitor is added in parallel with the liquid crystal capacitance C _lc (not shown).

On the other hand, the X driver section 20 includes signal lines X1 and X.
2 and X3 are data drivers for writing image data. The X driver unit 20 has an analog system and a digital system depending on the system of the data signal. In addition, a dot-sequential driving method in which a data signal is sequentially written to each signal line,
There is a line-sequential drive system in which data signals are written to all signal lines at once. The circuit of FIG. 13 shows an example of an analog dot sequential drive system, and the X driver unit 20 includes a sampling circuit 24 using a shift register 22 and analog switches.
It consists of and. The sampling circuit 24 selects the selection pulses Q ₁ , Q ₂ , sent from the shift register 22,
Video lines 26a, 26 depending on the timing of Q ₃ ~
b, 26c image signals (three primary color signals Vid (R), Vi
d (G), Vid (B)) to signal lines X1, X2, X3 ...
Write in. On the other hand, the Y driver unit 30 uses the scanning lines Y1, Y
It is a circuit for selecting 2 to, and has a shift register 32 and a buffer circuit 34. CLX is a transfer clock input terminal that determines the transfer speed of the timing pulse of the shift register 22, CLX (bar) is an inverted clock input terminal thereof, V _ddx is a positive power supply terminal of the X driver unit 20, and V _ssx is X. Negative power supply terminal of driver unit 20, DXIN
Is the start pulse input terminal of the shift register 22, DY
IN is a start pulse input terminal of the shift register 32,
V _ddy is a positive power supply terminal of the Y driver unit 30, V _ssy is a negative power supply terminal of the Y driver unit 30, and CLY is the shift register 3.
2, a transfer clock input terminal that determines the transfer speed of the timing pulse, CLY (bar) is an inverted clock input terminal, and V _com is a common power supply terminal that applies a voltage to the counter electrode b.

A TFT liquid crystal display device with a built-in driver is
Since a driving IC is not necessary and a mounting process of the IC is not necessary, a low cost liquid crystal display device can be realized by shortening the manufacturing process. Further, since the TFT drive circuit can sufficiently cope with a fine pixel pitch where an IC cannot be mounted, it is suitable for high definition, and the area thereof can be minimized, so that the size and weight of the device can be reduced. Further, by integrally forming the drive circuit, a strong display device module can be realized and high reliability can be obtained.

[0005]

As described above, although there are many advantages in integrally forming the peripheral drive circuit by the TFT, the TFT circuit has a problem which is not found in an ordinary IC.
That is, since a TFT usually uses an amorphous or polycrystalline semiconductor film, the field effect mobility is low and the characteristics vary greatly. In order to eliminate this, it is necessary to drive at a high voltage, and it is necessary to secure a large operation margin even for variations in characteristics. Further, since the display panel uses the insulating substrate, it is difficult to shield the TFT circuit and it is easily affected by noise. Therefore, the TFT circuit cannot exhibit sufficient performance unless the driving conditions are optimized.

On the other hand, in any type of drive circuit, timing pulses are transferred by the shift registers 22 and 32 to operate the sampling circuit 24 of the X driver section 20 and the buffer 34 of the Y driver section 30. The operation speed of these shift registers 22 and 32 depends on the number of pixels,
As the number of pixels increases, the operating speed must also increase. In recent years, the number of pixels (100,000 pixels or more) has increased due to the higher definition of the TFT display panel, and further speedup of the X driver section 20 and the Y driver section 30 is required. Therefore, attempts have been made to improve the mobility by improving the manufacturing process of the TFT (solid phase growth method, improvement of crystallinity by laser annealing, elimination of dangling bond by hydrogenation, etc.). However, it has been found that when the mobility of the TFT is improved and the operation speed of the drive circuit is increased in this way, the above-mentioned problems are promoted and, for example, the following problems become apparent.

Malfunction of Shift Register The malfunction of the shift register is caused by a timing shift (clock shift) between the clock CL and the inverted clock CL (bar) having a 180 ° phase shift as shown in FIG. Although it is caused by the rounding of the falling waveform, generally, when the mobility of the TFT is improved, the operation of the TFT becomes very sensitive. Therefore, the TFT easily malfunctions due to the subtle shift or the rounding of the clock waveform. Further, the malfunction occurs even when the threshold voltages of the P-channel FFT and the N-channel TFT are asymmetrical, but the higher the mobility, the greater the influence of the asymmetry of the thresholds of both channels, and the easier the malfunction occurs.

Noise is generated in a display image In a built-in driving circuit of a TFT liquid crystal display device, a long wiring is laid out on an insulating substrate, and therefore, unlike a semiconductor substrate in which the substrate acts as a shield layer, the influence of noise due to wiring capacitance or the like is generated. It is easy to receive, noise is generated in the display image, and display quality is deteriorated. For example, the X driver unit 2 shown in FIG.
At 0, wiring capacitance is parasitic between all clock lines and video lines. Since the wiring capacities of the video lines are different from each other, fixed pattern noise and jitter are likely to occur in the display image.

As described above, in a TFT liquid crystal display device with a built-in driver, the higher the definition, the more the display quality becomes a problem due to, for example, a malfunction of the shift register or noise. The malfunction of the shift register is caused by the input clock waveform, but the wiring capacity of the clock line also affects it. Therefore, it can be said that in a TFT liquid crystal display device with a built-in driver, malfunction of the shift register and generation of noise inevitably occur. In addition to such a problem, as will be described later, insufficiency of writing to the pixel TFT or the like and deterioration of the holding characteristic become apparent as the definition becomes higher (higher speed driving). In view of such a situation, the present inventor has researched liquid crystal display devices for many years, and these malfunctions, noise generation, and the like are sensitively affected by voltages such as the value of the power supply voltage and the signal strength. It was found that there is a tendency to increase with increasing.

Therefore, an object of the present invention is to realize a TFT liquid crystal display device capable of coping with higher definition by focusing on the required power supply voltage of the TFT liquid crystal display device and optimizing it. .

[0011]

The present invention is characterized in that the power supply bias of the scanning line drive circuit and the power supply bias of the signal line drive circuit in the TFT liquid crystal display device are set as follows.

First, a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion having an N-channel pixel TFT and a signal line driving circuit for supplying an image signal to a signal line are provided, and an analog point is provided. TF adopting sequential drive method
In the T-type liquid crystal display device, the bias condition of the power supply voltage of the scanning line driving circuit is set so as to satisfy the following expression.

V _ddy ≧ Vid2 + V _com ^* + ΔVy2 (1-1) V _ssy ≦ Vid1-V _com ^* -ΔVy1 (1-2) V _ddy : Positive power supply voltage of the scanning line driving circuit V _ssy : Scan line driving circuit Negative power supply voltage Vid1: minimum voltage of image signal Vid2: maximum voltage of image signal _Vcom ^* : drive voltage amplitude of counter electrode ΔVy1: shift voltage between gate and drain of pixel TFT represented by the following formula when not selected Maximum value of ΔV _gd (or average shift voltage) ΔV _gd = ΔV _g × C _gd / (C _gd + C _lc + C _stg ) (1-3) where ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ) and C _gd are the gate-drain parasitic capacitance of the pixel TFT.

[0014] DerutaVy2: gate-source voltage 1-exp pixel TFT, such as on-resistance R _on of the pixel TFT when selected to satisfy the write rate k% or more of the following formula _{{- (T 1 / R on} (C _lc + C _stg )} ≧ k / 100 (1-4) where T ₁ is the pixel TFT writing period, C _lc is the liquid crystal capacitance, and C _stg is the storage capacitance.

Secondly, it has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion having a P-channel pixel TFT and a signal line driving circuit for supplying an image signal to a signal line, and has an analog point. TF adopting sequential drive method
In the T-type liquid crystal display device, the bias condition of the power supply voltage of the scanning line driving circuit is set so as to satisfy the following expression.

V _ddy ≧ Vid2 + V _com ^* + ΔVy2 (2-1) V _ssy ≦ Vid1-V _com ^* -ΔVy1 (2-2) V _ddy : Positive power supply voltage of the scanning line driving circuit V _ssy : Scanning line driving circuit Negative power supply voltage Vid1: minimum voltage of image signal Vid2: maximum voltage of image signal V _com ^* : drive voltage amplitude of counter electrode ΔVy1: ON resistance R _on of pixel TFT at the time of selection is expressed by the following equation: Satisfactory pixel-gate gate-source voltage 1-exp {-(T ₁ / R _on (C _lc + C _stg )} ≧ k / 100 (2-4) where T ₁ is the writing period of the pixel TFT Is.

ΔVy2: shift voltage ΔV _gd between the gate and the drain of the pixel TFT when not selected
Maximum value of ΔV _gd = ΔV _g × C _gd / (C _gd + C _lc + C _stg ) ... (2-3) where ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ) and C _gd are the gate-drain parasitic capacitance of the pixel TFT, C _lc is the liquid crystal capacitance, and C _stg is the storage capacitance.

Thirdly, it has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion having a pixel TFT and a signal line driving circuit for supplying an image signal to a signal line, and analog point sequential driving is performed. In a TFT type liquid crystal display device adopting the method, when the sampling circuit of the signal line drive circuit is composed of sampling N-type channel TFTs, the bias condition of the power supply voltage of the signal line drive circuit satisfies the following equation. Set to do.

V _ddx ≧ Vid 2 + ΔVx 2 (3-1) V _ssx ≦ Vid 1-ΔVx 1 (3-2) V _ddx : Positive power supply voltage of the signal line drive circuit V _ssx : Negative power supply voltage of the signal line drive circuit Vid 1: Image Minimum voltage of signal Vid2: Maximum voltage of image signal ΔVx1: Maximum value of shift voltage ΔV _gd between gate and drain of sampling N-type channel TFT when not selected ΔV _gd = ΔV _g × C _gd / (C _gd + C _s ) (3-3) where ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ) and C _gd are gate-drain parasitic capacitances of the N-channel TFT for sampling, and C _s is a sample-hold capacitance (including wiring capacitance).

ΔVx2: N-type channel T for sampling
Gate-source voltage 1-exp {-(T _s / R _on C _s )} ≧ k / 100 (3-4) such that the on-resistance R _{on of the} FT satisfies the following expression when the writing rate is k% or more. However, T _s is a selection period of the sampling N-type channel TFT.

Fourthly, it has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion having pixel TFTs and a signal line driving circuit for supplying an image signal to a signal line, and analog point sequential driving is performed. In the TFT type liquid crystal display device adopting the method, when the sampling circuit of the signal line drive circuit is composed of sampling P-type channel TFTs, the bias condition of the power supply voltage of the signal line drive circuit satisfies the following equation. To do.

V _ddx ≧ Vid 2 + ΔVx 2 (4-1) V _ssx ≦ Vid 1-ΔVx 1 (4-2) V _ddx : Positive power supply voltage of the signal line drive circuit V _ssx : Negative power supply voltage of the signal line drive circuit Vid 1: Image Minimum voltage of signal Vid2: Maximum voltage of image signal ΔVx1: Gate-source voltage 1-exp {-(T where the on-resistance R _{on of the} sampling P-type channel TFT satisfies the following expression with a writing rate of k% or more 1-exp {-(T _s / R _on C _s )} ≧ k / 100 (4-4) where T _s is the sampling period of the sampling P-type channel TFT, and C _s is the sample-hold capacitance (including the wiring capacitance).
Is.

ΔVx2: Maximum value of the shift voltage ΔV _gd between the gate and drain of the P-type channel TFT for sampling when not selected ΔV _gd = ΔV _g × C _gd / (C _gd + C _s ) ... (4-3) where ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ), C _gd are gate-drain parasitic capacitances of the P-channel TFT for sampling.

Fifthly, it has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion having a pixel TFT and a signal line driving circuit for supplying an image signal to a signal line, and analog point sequential driving is performed. In a TFT type liquid crystal display device adopting the method, when the sampling circuit of the signal line drive circuit is composed of a sampling CMOS type TFT, the bias condition of the power supply voltage of the signal line drive circuit satisfies the following equation. To set.

V _ddx ≧ (Vid2-Vid1) / 2 + V _gsn (5-1) V _ssx ≦ (Vid2-Vid1) / 2-V _gsp (5-2) V _ddx ≧ Vid2 + ΔVx2 (5-3) V _ssx ≤ Vid1-ΔVx1 (5-4) V _ddx : Positive power supply voltage of signal line drive circuit V _ssx : Negative power supply voltage of signal line drive circuit Vid 1: Minimum voltage of image signal Vid 2: Maximum voltage of image signal V _gsn : The on-resistance R _onn of the N-channel TFT of the sampling CMOS TFT is a gate-source voltage that satisfies the following equation of the writing rate k%. 2 {1-exp (-T _s / R _onn C _s )} = k / 100 (5-5) V _gsp : The on-resistance R _onp of the P-channel TFT of the sampling CMOS TFT is next to the writing rate k%. The gate-source voltage satisfies the formula. _{2 {1-exp (-T s} / R onp C s)} = k / 100 ... (5-6) ΔVx1: ( maximum value of [Delta] V _gdn) - (minimum value of ΔV _gdp) ΔVx2: (maximum [Delta] V _gdp Value) − (minimum value of ΔV _gdn ) Here, ΔV _gdn and ΔV _gdn are respectively given by the following equations.

ΔV _gdp = (V _ddx −V _ssx ) × C _gdp / (C _gdp + C _s ) ... (5-7) ΔV _gdn = (V _ddx −V _ssx ) × C _gdn / (C _gdn + C _s ) ... (5-8) where C _gdp is the gate-rain capacitance of the P-channel TFT of the sampling CMOS TFT, and C _gdn is its N
The gate-drain capacitance of the channel TFT, C _s, is a sample hold capacitance (including wiring capacitance).

Sixthly, a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion having pixel TFTs and a signal line driving circuit for supplying an image signal to a signal line are provided, and analog line sequential driving is performed. A TFT type liquid crystal display device adopting a system, in which a signal line driving circuit includes a first-stage latch circuit in which the image signal is written by a selection pulse sent from a shift register and the image by the latch pulse. In the configuration including the second-stage latch circuit to which a signal is written and the analog buffer circuit which outputs the output voltage to the signal line by using the output of the second-stage latch circuit as an input voltage, the power supply of the signal line drive circuit is provided. The voltage bias conditions are set so as to satisfy the following formula.

V _ddx ≧ Vid 2 + ΔVx 2 (6-1) V _ssx ≦ Vid 1-ΔVx 1 (6-2) V _ddx : Positive power supply voltage of the signal line drive circuit V _ssx : Negative power supply voltage of the signal line drive circuit Vid 1: Image Minimum voltage of signal Vid2: Maximum voltage of image signal Here, Vid1 and Vid2 are defined as follows.

ΔVx1: The voltage ΔVx2 required to satisfy the equation (6-3) of the writing rate k% or more even when the linearity of the input / output signal of the analog buffer is maintained and the minimum value Vid1 of the image signal is input. The voltage required to satisfy the equation (6-3) of the writing rate of not less than k% even when the maximum value Vid2 of the image signal is input while keeping the linearity of the input / output signal of the analog buffer 1-exp (-T ₁ / Τ) ≧ k / 100 (6-3)

[0030]

According to the first means, the power source voltages V _ddy and V _ss of the scanning line driving circuit in the TFT type liquid crystal display device using the N-channel pixel TFT in the analog dot sequential driving system.
Optimize _y . That is, when the power supply voltage V _ddy is set so as to satisfy the equation (1-1), the pixel TFT having the writing rate of k% or more is irrespective of the writing time, the on-resistance of the pixel TFT, the liquid crystal capacitance and the holding capacitance. The writing by can be realized. When the power supply voltage V _ssy is set so as to satisfy the expression (1-2), the so-called _punch- through voltage generated when the pixel TFT is turned off regardless of the values of the coupling capacitance of the pixel TFT, the liquid crystal capacitance, and the storage capacitance. It is possible to eliminate the influence due to and prevent deterioration of the holding characteristics. Regardless of the writing time, the on-resistance of the pixel TFT, the liquid crystal capacitance, and the holding capacitance, writing by the pixel TFT with a writing rate of k% or more can be realized.

According to the second means, the power supply voltages V _ddy and V _{ss y} of the scanning line driving circuit can be optimized in the TFT type liquid crystal display device using the P channel pixel TFT in the analog dot sequential driving system. That is, when the power supply voltage V _ddy is set so as to satisfy the equation (2-1), the so-called _punch- through that occurs when the pixel TFT is turned off regardless of the values of the coupling capacitance of the pixel TFT, the liquid crystal capacitance, and the storage capacitance. It is possible to eliminate the influence of the voltage and prevent the retention characteristic from deteriorating. Further, if the power supply voltage V _ssy is set so as to satisfy the expression (2-2), the pixel TFT having the writing rate of k% or more can be used regardless of the writing time, the on-resistance of the pixel TFT, the liquid crystal capacitance and the holding capacitance. Writing can be realized. Under such a power supply bias condition, high-speed driving due to an increase in the number of pixels becomes possible, and a liquid crystal display device with higher definition can be realized.

Further, according to the third means, in the TFT type liquid crystal display device in which the sampling circuit of the signal line drive circuit is composed of sampling N-type channel TFTs in the analog dot sequential drive system, the power supply voltage of the signal line drive circuit is used. V _ddx
And V _ssx can be optimized. That is, equation (3-1)
When V _ddx is set to satisfy the above _condition , writing can be performed on the signal line with a writing rate of k% or more regardless of the selection time of the sampling N-type channel TFT, the on-resistance, and the value of the sample hold capacitance. In addition, the formula (3-
When the power supply voltage V _ssx is set so as to satisfy 2), regardless of the values of the coupling capacitance and the sample-hold capacitance, the so-called punch-through voltage generated when the sampling N-type channel TFT is turned off is eliminated,
It is possible to prevent the retention characteristics from deteriorating.

Furthermore, according to the fourth means, the sampling circuit of the signal line driving circuit is constituted by a sampling P-type channel TFT by the analog dot sequential driving method.
Also in the T-type liquid crystal display device, the power supply voltages V _ddx and V _ssx of the signal line drive circuit can be optimized. That is, contrary to the case of the N-channel TFT, setting the power supply voltage V _ddx so as to satisfy the equation (4-1) eliminates the influence of so-called _punch- through voltage that occurs when the sampling P-channel TFT is turned off. It is possible to prevent deterioration of the holding characteristics. Further, when the power supply voltage V _ssx is set so as to satisfy the expression (4-2), the so-called _punch- through voltage generated when the sampling P-type channel TFT is turned off is affected regardless of the value of the sample-hold capacitance or the like. It is possible to prevent the deterioration of the retention characteristics.

Further, according to the fifth means, in the TFT type liquid crystal display device in which the sunring circuit of the signal line drive circuit is composed of the sampling CMOS type TFT in the analog dot sequential drive system, the power supply voltage of the signal line drive circuit is used. Optimization of V _ddx and V _ssx can be achieved. That is, equation (5-1),
When the power supply voltage V _ddx is set so as to satisfy (5-2), the write rate k is set regardless of the sample and hold capacity.
It is possible to realize writing to the signal line of not less than%. In addition, the formula (5-
By setting the power supply voltage V _ssx so as to satisfy 3) and (5-4), it is possible to eliminate the influence of so-called _punch- through voltage that occurs when the CMOS type TFT is turned off, and prevent deterioration of the holding characteristic.

Further, according to the sixth means, in the analog line sequential drive system, the signal line drive circuit includes a first stage latch circuit in which the image signal is written by a selection pulse sent from the shift register, and a latch circuit. Even in a configuration having a second-stage latch circuit in which the image signals are written all at once by a pulse and an analog buffer circuit that outputs the output voltage to a signal line by using the output of the second-stage latch circuit as an input voltage The power supply voltages V _ddx and V _ssx of the line drive circuit can be optimized. That is, the power supply voltages V _ddx and V _ddx satisfy the equations (6-1) and (6-2).
_By setting _ssx , it is possible to obtain the write characteristic to the signal line with the write rate of k% or more and improve the retention characteristic regardless of the value of the wiring resistance of the signal line.

[0036]

Embodiments of the present invention will now be described with reference to the accompanying drawings. First, a description will be given power bias conditions of the scan driver unit, as shown in FIG. 13, the scan driver 30 is supplied with the positive power source V _ddy and the negative power supply V _ssy, counter electrode b of the pixel matrix portion 10 To the counter electrode potential V _com .

(First Embodiment) FIG. 1 shows a pixel TF when an N-channel TFT is used as a pixel TFT in the present invention.
It is an equivalent circuit diagram of T. The source electrode S of the pixel TFT is on the signal line X, the gate electrode G is on the scanning line Y, and the drain electrode D.
Is connected to the pixel electrode a and the storage capacitor C _stg . Liquid crystal is filled in the gap between the pixel electrode a and the counter electrode b, and this liquid crystal capacitance is C _lc . As for the circuit configuration of the storage capacitor C _stg , as shown in FIG. 2A, an additional capacitance method in which the scanning line and the pixel electrode in the preceding stage are overlapped with an insulating film interposed therebetween, and FIG.
As shown in (b), there is a storage capacitance method in which a capacitance line independent of the scanning line is provided and the capacitance line is superposed on the capacitance line via an insulating film. On the other hand, parasitic capacitances (coupling capacitances) C _ds , C _gd , and C _gs as shown in FIG. 1 exist between the source electrode S, the drain electrode D, and the gate electrode G of the pixel TFT. FIG. 3 shows drive waveforms of a typical TFT liquid crystal display device.

Since the liquid crystal needs to be driven by an alternating current, the image signal Vid applied to the signal line X is the video center Vid _c.
Use the one in which AC is inverted. Here, the AC inversion period is set to one field, but it may be inverted every horizontal scanning period T ₁ . The selection pulse (gate signal) V _G applied to the scanning line Y becomes a high level in one horizontal scanning period T ₁ , and the N-channel pixel T
Turn on FT. When the pixel TFT becomes conductive, the potential V _{p at the} pixel electrode P point becomes the same as the image signal Vid.
Here, a condition for writing the image signal Vid in the liquid crystal capacitance and the storage capacitance by at least k% through the pixel TFT in the horizontal scanning period (writing period) T ₁ is given by the following equation.

1-exp (-T ₁ / τ) ≧ k / 100 (1) However, τ is a time constant when the pixel TFT is conductive.
Here, when the on-resistance of the pixel TFT is R _on , τ = R _on (C _lc + C _stg ) ... (2) Since the writing rate k% is generally 95%,
Incidentally, if k = 95, the equation (1) is expressed as the following equation.

3R _on (C _lc + C _stg ) ≦ T ₁ (3) If this expression is not satisfied, insufficient pixel writing occurs and a sufficient contrast ratio cannot be obtained. As is well known, the on-resistance R _on of the pixel TFT largely depends _on the gate-source voltage V _gs . Therefore, from the formula (3), the potential V _{g of the} selection pulse required for sufficient writing can be limited as follows through the on-resistance R _on . By the way, in the case of a TFT liquid crystal display device with a built-in drive circuit, the positive power supply V _ddy of the scanning driver section (Y driver section) corresponds to the high level of the selection pulse, and the negative power supply V _{ssy thereof} has the low selection pulse. Corresponds to the level. Here, if the maximum potential of the image signal Vid is Vid2 and the minimum potential thereof is Vid1, V _gs
Satisfies the following equation: V _ddy −Vid 2 ≦ V _gs ≦ V _ddy −Vid 1 (4) _Vddy −Vid 2 in the _previous stage is the minimum gate-source potential, and V _ddy −Vid 1 in the _subsequent stage is It is the maximum gate-source potential. Generally, as V _gs increases, the on-resistance R _{on of the} TFT decreases, so that it is sufficient if the formula (3) is satisfied at the minimum potential of the formula (4). Conversely, if the value of V _gs is ΔVy2 via the on-resistance R _on such that the left side and the right side in equation (3) are equal, then V _gs
It is sufficient that ≧ ΔVy2 is satisfied. That is, the condition for preventing insufficient writing is given by the following equation.

V _ddy ≧ Vid2 + ΔVy2 (5) Here, ΔVy2 is the potential between the gate and the source where the ON resistance R _on of the pixel TFT satisfies the following equation.

R _on = T ₁ / {3 × (C _lc + C _stg )} (6) The formula (6) shows an example in which the writing rate is 95%, but generally, a sufficient writing rate is k. %, ΔVy2 is the pixel T
The on resistance R _{on of the} FT is a gate-source potential that satisfies the following equation.

1-exp {-(T ₁ / R _on (C _lc + C _stg )} = k / 100 (7) Here, T ₁ is a writing period of the pixel TFT, and one horizontal scanning is performed in the line-sequential driving method. This coincides with the period, but in the case of the dot-sequential driving method, it coincides with the bright line erasing (blanking) period.
This is because in dot-sequential driving, original data is written to the rightmost pixel immediately before the blanking period.

As described above, the condition for preventing insufficient writing is expressed by the equation (5). Not only the writing characteristic but also the holding characteristic (the written signal leaks during the non-selection period) is applied to the pixel TFT. Conditions for not doing) are also required. Since a CMOS type TFT is used for the drive circuit in the TFT liquid crystal display device with a built-in drive circuit, the pixel TFT is inevitably an enhancement type. Therefore, if the gate-source voltage is negative during the non-selection period, the off resistance of the pixel TFT is kept high, so that sufficient retention characteristics can be obtained, but the problem of punch-through voltage (shift voltage) due to parasitic capacitance Must be considered. This penetration voltage is Δ in FIG.
Although indicated as V _gd , it occurs at the moment when the pixel TFT is turned off due to capacitive coupling between the gate-drain parasitic capacitance C _{gd of the} pixel TFT, the liquid crystal capacitance C _lc, and the storage capacitance C _stg . The magnitude of this punch-through voltage is expressed by the following equation.

ΔV _gd = ΔV _g × C _gd / (C _gd + C _lc + C _stg ) (8) Here, the _punch- through voltage ΔV _gd is the magnitude of the selection pulse V _g applied to the scanning line Y (V _ddy − V _ssy ). In the formula (8), the liquid crystal capacitance C _lc changes according to the image signal Vid due to the dielectric anisotropy of the liquid crystal, and the storage capacitance C
_{Since stg} also changes the channel capacitance of the pixel TFT according to the gate-drain voltage, the punch-through voltage ΔV _gd also changes. Generally, as the amplitude of the image signal Vid is smaller and the gate-drain voltage is larger, the penetration voltage ΔV _gd
The value of becomes large. Since this penetration voltage ΔV _g always lowers the pixel electrode potential Vp, this voltage ΔV _gd
It suffices that the non-selection level of the scanning line Y (the negative power supply potential of the scan driver unit 30 in the drive circuit built-in type) is set to a low value only in advance. That is, the negative power supply potential V _ssy of the scan driver unit 30 must satisfy the following expression.

V _ssy ≤ Vid1-ΔVy1 (9) Here, Vid1 is the minimum potential of the image signal Vid,
ΔVy1 is the maximum value of the shift voltage represented by the equation (8). If this equation (8) is not satisfied, the data of the signal line X leaks to the image electrode a due to the off-leakage current of the pixel TFT in the non-selected state, causing vertical crosstalk and uneven brightness in the vertical direction of the screen. Since it is difficult to actually measure the parasitic capacitance C _gd of the pixel TFT and the liquid crystal capacitance C _lc for one pixel,
An average value of the shift voltage may be used as ΔVy1. Specifically, it is expressed as _{ΔVy1 = Vid c -V com ... (} 10). Here Vid _c is a video center with an average value of the image signal. In order to achieve high image quality and high reliability, the counter electrode (common electrode) potential must be set to the average value of the pixel electrode potential, so the right side of this equation indicates the average value of the shift voltage. As described above, the pixel TF
The power supply bias condition of the scan driver unit 30 that satisfies the write characteristic and the retention characteristic of T can be expressed by equations (5) and (9).

However, both equations are established only when the counter electrode potential is constant. Therefore, in the following, similar bias conditions will be derived when the counter electrode potential (and the storage capacitor electrode potential) is also AC-driven.

FIG. 5 shows the counter electrode potential (and the storage capacitor electrode potential) in the case where the storage capacitor circuit configuration is the storage capacitor system.
6 is a timing chart showing a driving method (hereinafter, abbreviated as common swing driving) in which AC is inverted by 180 ° out of phase with an image signal. According to such a common swing drive, the image signal Vid written by the data driver unit 20.
Since the voltage range can be narrowed, the drive voltage (positive power supply V _ddx ) of the data driver unit 20 can be lowered. The operation speed of the data driver 20 is the scanning driver unit 3
It is as high as several hundred times higher than that of 0, and if the driving voltage is lowered, there is an advantage that the TFT circuit and the external circuit are easily configured as described above, malfunction does not easily occur, and power consumption is reduced. By the way, in the common swing drive, if the maximum voltage of the counter electrode potential is V _com2 , the driving minimum voltage is V _com1 , and the driving dynamic voltage range is V _com ^* = V _com2 −V _com1 , the amount of the counter electrode potential is V _com. ^Since only ^* , the image electrode potential spreads vertically from the image signal voltage range (Vid2-Vid1), equation (5) can be rewritten as equation (11) and equation (9) can be rewritten as equation (12). .

V _ddy ≧ Vid 2 + V _com ^* + ΔVy 2 (11) V _ssy ≤ Vid1-V _com ^* -ΔVy1 (12) Here, when the counter electrode potential is constant, V _com ^* = 0. Therefore, equation (11) becomes equation (5), Expression (12) corresponds to expression (9), respectively. Therefore, equations (11) and (1
2) is a general formula that can be applied even when the common swing drive is not used.

The above-mentioned common swing drive is the case of the storage capacity method, and as shown in FIG. 2B, since the storage capacity is connected to the capacity line independent of the scanning line, this capacity line is used as the counter electrode. If the potentials are the same, common swing drive can be realized. However, in the case of the additional capacitance method as shown in FIG. 2A, since the storage capacitor is connected to the preceding scanning line, the scanning line cannot be set to the same potential as the counter electrode. Therefore, as shown in FIG. 6, two levels (V _ssy1 and V _ssy2 ) of the negative power source of the scan driver unit are provided, and the negative power source is AC-driven in a rectangular wave state in synchronization with the counter electrode potential. In such a case, if V _ssy2 −V _ssy1 = V _com ^* ,
Expression (11) is satisfied.

(Second Embodiment) In the first embodiment, the pixel TFT is an N-channel TFT, but in this embodiment, P
The power supply bias condition of the scan driver unit when the channel pixel TFT is used will be described. FIG. 7 is a drive timing chart when a P-channel pixel TFT is used when the potential of the counter electrode is constant. In this case, the scanning pulse waveform is upside down as compared with the case of the P channel. In addition,
As can be easily understood, the scanning pulse waveform in the case of the common swing drive may be upside down from the waveforms shown in FIG. 5 and FIG. However, in the case of the additional capacitance method shown in FIG. 6, the positive power source V _ddy1 of the scan driver unit is _set at two levels (V _ddy1 and V _ddy1).
ddy2 ), and its negative power supply is at one level (V _ssy ).

The bias conditions for the P-channel pixel TFT are also expressed by the equations (11), (1) for the N-channel pixel TFT.
It can be represented by 2). However, in this case, the formula (1
The contents of ΔVy1 and ΔVy2 in 1) and (12) are exchanged, and the expression (11) becomes the conditional expression of the retention characteristic, and the expression (12) becomes the conditional expression of the write shortage prevention. Where ΔVy1 and ΔV
y2 is opposite to the case of the N-channel pixel TFT and is as follows.

ΔVy1: Source-gate voltage where ON resistance R _{on of} pixel TFT satisfies equation (7) ΔVy2: Maximum shift voltage represented by equation (8) (or average shift voltage = image signal Average value Vid _c −
Counter electrode potential V _com ) As described above, the scan driver unit 30 for optimally driving the P-channel pixel TFT or the N-channel pixel TFT
The power supply bias condition of is given by equations (11) and (12) regardless of the format of the data driver unit 20. According to the liquid crystal display device that satisfies the power supply bias condition, insufficient writing can be suppressed and the holding characteristic can be improved. Due to such improvements, TF with the increase in the number of pixels
High-speed driving of T is possible, and high-quality display performance can be obtained.

Next, the power supply bias condition of the data driver section will be described. As shown in FIG. 13, the data driver unit 20 is supplied with a positive power supply V _ddx and a negative power supply V _ssx .

(Third Embodiment) As shown in FIG. 8, the sampling circuit 24 of the data driver unit 20 in this embodiment is N
The pixel TFT is driven by a dot-sequential driving method in a circuit configuration using a type channel analog switch (TFT) SW _i . That is, the selection pulse Q _i turns on the analog switch SW _i , and the image signal Vid is sent to the signal line.
It is written in the sample hold capacity C _s . In addition, C _gd
Is the parasitic capacitance between the gate and drain. Here, the problems of preventing insufficient writing to the sample-hold capacitance C _s and improving the retention characteristic can be discussed as an analogy in the case of the pixel TFT as described in the first and second embodiments. That is, the video line of FIG. 8 is used as the signal line X of FIG. 1, and the signal line of the selection pulse Q _i of FIG. 8 is used as the scanning line Y of FIG.
Further, if the sample hold capacitance C _s (including the wiring capacitance of the signal line) is replaced with the liquid crystal capacitance C _lc and the storage capacitance C _stg , the analog switch SW _i can be treated in the same manner as the pixel TFT. That is, the power supply voltage (the positive power supply V _ddx and the negative power supply V _ssx ) of the data driver unit 20 can be optimized in the same way as the power supply voltage of the scan driver unit is optimized.

First, _assuming that the selection period of the analog switch SW _i is T _s , the condition for writing the image signal of the video line on the signal line X _i at the writing rate k% (eg 95%) within this period is as follows. Similar to the equation (5), the following equation holds.

V _ddx ≧ Vid 2 + ΔVx 2 (13) where ΔVx 2 is the on resistance R of the analog switch SW _i
on is a gate-source voltage that satisfies the following expression of the writing rate k. 1-exp (-T _s / R _on C _s ) = k / 100 (14) If these expressions are not satisfied, writing of the image signal to the signal line X _i is insufficient, that is, horizontal resolution is lowered. .

On the other hand, there is a punch-through voltage (shift voltage) ΔV _gd when the analog switch SW _i is turned off.
The size is represented by ΔV _gd = (V _ddx −V _ssx ) × C _gd / (C _gd + C _s ) (15). When the maximum value of this shift voltage is ΔVx1, a condition for preventing the data once written to the signal line X _i from leaking (horizontal crosstalk does not occur) during the non-selection period (almost horizontal scanning period) of the analog switch SW _i. Becomes V _ssx ≤ Vid1-ΔVx1 (16). Even when the P-channel analog switch is used, as described in the second embodiment, equations (13),
(16) is the power supply bias condition, but only ΔVx1
Note that the contents of and ΔVx2 are interchanged.

(Fourth Embodiment) As shown in FIG. 9, the sampling circuit 24 of the data driver unit 20 in this embodiment is C
The pixel TFT is driven by a dot-sequential driving method with a circuit configuration using the MOS analog switch T _i . That is, the selection pulse Q _i is applied to the gate of the N-channel TFT of the CMOS analog switch T _i , and its inversion pulse Q _i (bar) is P.
It is supplied to the gate of the channel TFT and the two TFTs are turned on or off at the same time. In the case where the siping circuit has a CMOS structure, the on-resistance of the other TFT always becomes low even if the gate voltage is such that the on-resistance of one TFT becomes high. Therefore, compared with the case of the single-channel TFT in the third embodiment. The voltage range of the analog signal (image signal) that can be transmitted as a result becomes wider. However, the number of elements increases and the circuit configuration becomes complicated.

First, the CMOS analog switch T _i
Then, the conditions for preventing insufficient writing on the signal line X _i (the horizontal resolution does not decrease) will be examined. Wherein each R _onp the ON resistance of the P-channel TFT and an N-channel TFT, when the R _onn, parallel resistance of the two TFT R
_{onp · R onn / (R onp} + R onn) is, of both channels T
If the FT characteristics are symmetrical, the video center (Vid2-Vi
It becomes the highest around d1) / 2. At this time, the high on-resistance R _onp the P-channel TFT, it N-channel TFT in the on-resistance R _onn is sufficiently low, which under the condition that does not cause insufficient writing can easily be represented by the following formula from the above analogy Can understand.

V _ddx ≧ (Vid 2 −Vid 1) / 2 + V _gsn (17) Here, V _gsn is a gate-source voltage such that the on-resistance R _onn of the N-channel TFT satisfies the following expression of the writing rate k. .

2 {1-exp (-T _s / R _onn C _s )} = k / 100 (18) When k = 95, R _onn = 2T _s / 3C _s .

On the other hand, the on-resistance R _{onn of the} N-channel TFT
Is high, the ON resistance R _onp the P-channel TFT is sufficiently low, which under the condition that insufficient writing does not _{occur, V ssx ≦ (Vid2-Vid1} ) / 2-V gsp ... (19) where, V _gsp is The on-resistance R _onp of the P-channel TFT is a gate-source voltage that satisfies the following expression of the writing rate k. 2 {1-exp (-T _s / R _onp C _s )} = k / 100 (20) Incidentally, when = 95, R _onp = 2T _s / 3C _s . Therefore, if the expressions (17) and (19) are satisfied, writing at a writing rate of k% or more is possible.

Next, a condition for preventing the data once written in the signal line X _i from leaking (horizontal crosstalk does not occur) during the non-selection period of the CMOS analog switch T _i is determined. Even in the case of CMOS, a punch-through voltage (shift voltage) is generated at the moment when it is turned off. The shift voltage of the N-channel TFT [Delta] V _gdn, when the shift voltage of the P-channel TFT and [Delta] V _gdp, shift by N channel to the negative side,
Since the shift due to the P channel shifts to the positive side, the total shift amount is ΔV _gdp −ΔV _gdn . Therefore, the conditions under which the analog switch does not leak under all bias conditions are expressed by equations (13) and (16), where ΔV
x1 and ΔVx2 are expressed by the following equations.

[0065] ΔVx1 = (maximum value of ΔV _gdn) - (ΔV minimum of _{gdp) ... (21) ΔVx2 =} ( maximum value of [Delta] V _gdp) - (minimum value of ΔV _gdn) ... (22) where, [Delta] V _gdp And ΔV _gdn are given by the following equations.

ΔV _gdp = (V _ddx −V _ssx ) × C _gdp / (C _gdp + C _s ) ... (24) ΔV _gdn = (V _ddx −V _ssx ) × C _gdn / (C _gdn + C _s ) ... (25) ) However, C _gdp is P gate-drain capacitance of channel TFT, C _gdn also includes P gate-drain capacitance capacity channel TFT, C _s is the sample-and-hold capacitor (wiring capacitance).

(Fifth Embodiment) In the third and fourth embodiments, the power supply bias condition of the data driver section in the analog dot sequential drive system has been described, but this example shows the data driver section in the analog line sequential drive system. The power supply bias condition will be described. FIG. 10 is a block diagram of the data driver unit 40 based on the analog line sequential driving method. Select pulse Q sent from shift register 22
_The analog image signals Vid sequentially written in the first-stage latch A by _1, Q _{2 and} Q ₃ are simultaneously sent to the second-stage latch B by the latch pulse LP. The second-stage latch B is connected to the analog buffer C, and each image signal fetched in the latch B receives the signal line X during one horizontal scanning period.
Always drive _1, X _2, X ₃ ~. Analog buffer C
The simplest configuration is as shown in FIG. In this circuit configuration, the P-channel TFT ₂ functions as a current source, and the P-channel TFT ₁ outputs the image signal held in the latch B by the source follower to the input voltage V
and in _i as the output voltage Vout _i in response to this. Here, it should be noted that FIG.
As shown in, the input / output voltage difference V _sh and the rise / fall time are shown. In this example, since the output voltage Vout _i becomes higher than the input voltage Vin _i by V _sh , the positive power supply V _ddx of the data driver section must be made higher than the maximum value Vid2 of the image signal voltage by at least V _sh . Further, since the output voltage Vout _i rises slowly, it is necessary to set the power supply voltage and the channel width of the TFT ₂ that rise within one horizontal scanning period. As another circuit configuration of the analog buffer C, there is one using various operational amplifiers. Here, irrespective of the circuit configuration of the analog buffer, assuming that the output resistance of the analog buffer is R _out , the wiring resistance of the signal line is C _sl , and the horizontal scanning period is T _H , the condition of the writing rate k% or more is as follows. Given in.

1-exp {-(T _H / R _ou · C _st )} ≧ k / 100 (26) Incidentally, when the writing rate is 95% or more, it is given by the following equation.

[0069] _{R out × C sl × 3 <} T H ... (27) However, the output resistance R _out is related to the specific circuit configuration of the analog buffer supply voltage V _ddx, V _SSX an output resistor R _out Since the relationship between and depends on the circuit configuration, it is not possible to directly limit the power supply voltage from this equation. However, if ΔVx1 and ΔVx2 are defined as follows,
The bias conditions of the power supply voltages V _{ddx and} V _ssx of the data driver section for preventing write shortage and improving the retention characteristic must satisfy the expressions (13) and (16).

ΔVx1: voltage required to satisfy the equation (26) even if the minimum value Vid1 of the image signal is input while maintaining the linearity of the input / output signal of the analog buffer ΔVx2: the linearity of the input / output signal of the analog buffer Voltage required to satisfy the formula (26) even when the maximum value Vid2 of the image signal is input, although there is no liquid crystal display device that performs dot-sequential driving by a digital method, the digital line-sequential driving method does not is there. In this case, basically, only the power supply voltage given from the outside is selected, so that there is no write shortage or shift voltage which is a problem in the case of the analog method. Therefore, the formula (1
Both ΔVx1 and ΔVx2 in 3) and (16) may be 0.

[0071]

As described above, the TF according to the present invention
T-type liquid crystal display device, regardless of the sequential driving method or an analog line sequential type analog point, the power supply voltage V of the power source voltage V _{dd y} and V _ssy or the signal line driving circuit of the scan line driver circuit
_Since it is characterized in that _ddx and V _ssx are set to the optimum values as described above, the following effects are obtained.

That is, regardless of the writing time, the on-resistance of the pixel TFT and the sampling TFT, the liquid crystal capacitance and the storage capacitance, a sufficient writing characteristic of a writing rate of k% or more can be realized. Further, regardless of the values of the coupling capacitance, the liquid crystal capacitance, and the storage capacitance of the pixel TFT or the sampling TFT, the influence of a so-called punch-through voltage generated when the pixel TFT or the sampling TFT is turned off is eliminated, and the retention characteristic is deteriorated. Can be prevented. Under such a power supply bias condition, high-speed driving due to an increase in the number of pixels becomes possible, and a liquid crystal display device with higher definition can be realized. Especially TF with built-in driver
In the T-type liquid crystal display device, the value of the power supply voltage sensitively affects the malfunction of the shift register and the generation of noise. Therefore, when the scanning line drive circuit or the signal line drive circuit set to the above power supply bias is used, malfunction or noise is generated. Occurrence can be suppressed.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a pixel TFT when an N-channel TFT is used as the pixel TFT in the first embodiment of the present invention.

FIG. 2A is an equivalent circuit diagram in a case where a pixel holding capacitance is of an additional capacitance type, and FIG. 2B is an equivalent circuit diagram in which a pixel holding capacitance is of a storage capacitance type.

FIG. 3 is a waveform diagram showing a typical drive waveform of a TFT liquid crystal display device.

FIG. 4 is a timing chart showing a power supply voltage bias of a scanning line driving circuit when an N-channel TFT is used as a pixel TFT in the first embodiment of the present invention.

FIG. 5 is a timing chart showing the power supply voltage bias of the scanning line drive circuit in the case where the N-channel TFT is used as the pixel TFT and the storage capacitor circuit configuration is the storage capacitance system in the first embodiment of the present invention.

FIG. 6 is a timing chart showing the power supply voltage bias of the scanning line driving circuit in the case where the N-channel TFT is used as the pixel TFT and the storage capacitor circuit configuration is the additional capacitance system in the first embodiment of the present invention.

FIG. 7 is a timing chart showing a power supply voltage bias of a scanning line driving circuit when a P-channel TFT is used as a pixel TFT in the second embodiment of the present invention.

FIG. 8 is a timing chart showing the power supply voltage bias of the data driver when an N-channel TFT analog switch is used as the sampling circuit of the data driver in the third embodiment of the present invention.

FIG. 9 is a timing chart showing a power supply voltage bias of a data driver when a CMOS / TFT analog switch is used as a sampling circuit of the data driver in the fourth embodiment of the present invention.

FIG. 10 is a block diagram showing the configuration of a data driver of an analog dot sequential drive system in a fifth embodiment of the present invention.

11 is a circuit diagram showing a detailed configuration of the analog buffer shown in FIG.

FIG. 12 is a waveform diagram showing rising and falling states of an input voltage and an output voltage of the analog buffer shown in FIG.

FIG. 13 is a block diagram showing a circuit configuration of a TFT liquid crystal display device with a built-in driver.

14 is a waveform chart showing the mutual relationship between the clock and the inverted clock of the shift register shown in FIG.

15 is a block diagram showing a configuration of a data driver shown in FIG.

[Explanation of symbols]

1 ... Insulating substrate 10 ... Pixel matrix part 20, 40 ... X driver part 30 ... Y driver part X ... Scan line Y ... Signal line TFT ... Thin film transistor SW _i ... TFT analog switch T _i ... TFT CMOS analog switch

Claims (6)

[Claims] 1. An analog dot-sequential driving system having a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion including an N-channel pixel TFT and a signal line driving circuit for supplying an image signal to a signal line. In the TFT type liquid crystal display device, the bias condition of the power supply voltage of the scanning line drive circuit is set so as to satisfy the following expression. V _ddy ≥ Vid2 + V _com ^* + ΔVy2 (1-1) V _ssy ≤ Vid1-V _com ^* -ΔVy1 (1-2) V _ddy : Positive power supply voltage of the scanning line driving circuit V _ssy : Negative power supply of the scanning line driving circuit Voltage Vid1: Minimum voltage of image signal Vid2: Maximum voltage of image signal _Vcom ^* : Drive voltage amplitude of counter electrode ΔVy1: Shift voltage ΔV _gd between the gate and drain of the pixel TFT represented by the following equation when not selected Maximum value (or average shift voltage) ΔV _gd = ΔV _g × C _gd / (C _gd + C _lc + C _stg ) ... (1-3) where ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ) and C _gd are the gate-drain parasitic capacitance of the pixel TFT. DerutaVy2: gate-source voltage 1-exp pixel TFT, such as on-resistance R _on of the pixel TFT when selected to satisfy the write rate k% or more of the following formula _{{- (T 1 / R on} (C lc + C stg )} ≧ k / 100 (1-4) where T ₁ is the writing period of the pixel TFT, C _lc is the liquid crystal capacitance, and C _stg is the storage capacitance. 2. An analog dot-sequential driving system having a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion including a P-channel pixel TFT and a signal line driving circuit for supplying an image signal to a signal line. In the TFT type liquid crystal display device, the bias condition of the power supply voltage of the scanning line drive circuit is set so as to satisfy the following expression. V _ddy ≥ Vid2 + V _com ^* + ΔVy2 (2-1) V _ssy ≤ Vid1-V _com ^* -ΔVy1 (2-2) V _ddy : Positive power supply voltage of the scanning line driving circuit V _ssy : Negative power supply of the scanning line driving circuit Voltage Vid1: Minimum voltage of image signal Vid2: Maximum voltage of image signal V _com ^* : Drive voltage amplitude of counter electrode ΔVy1: On resistance R _on of the pixel TFT at the time of selection satisfies the following expression of writing rate k% or more Gate-source voltage of pixel TFT 1-exp {-(T ₁ / R _on (C _lc + C _stg )} ≧ k / 100 (2-3) where T ₁ is the writing period of the pixel TFT. ΔVy2: Maximum value of the shift voltage ΔV _gd between the gate and drain of the pixel TFT when not selected, ΔV _gd = ΔV _g × C _gd / (C _gd + C _lc + C _stg ) ... (2-4) However, ΔV _g is the size of the selection pulse V _ddy -
V _ssy ) and C _gd are the gate-drain parasitic capacitance of the pixel TFT, C _lc is the liquid crystal capacitance, and C _stg is the storage capacitance. 3. An analog dot-sequential driving system is adopted, which has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion including a pixel TFT and a signal line driving circuit for supplying an image signal to a signal line. In the TFT liquid crystal display device according to the present invention, the sampling circuit of the signal line driving circuit is composed of sampling N-type channel TFTs, and the bias condition of the power supply voltage of the signal line driving circuit is set to satisfy the following equation. A TFT type liquid crystal display device characterized by the following. V _ddx ≧ Vid 2 + ΔVx 2 (3-1) V _ssx ≦ Vid 1-ΔVx 1 (3-2) V _ddx : Positive power supply voltage of the signal line drive circuit V _ssx : Negative power supply voltage of the signal line drive circuit Vid 1: Minimum image signal Voltage Vid2: Maximum voltage of image signal ΔVx1: Maximum value of shift voltage ΔV _gd between the gate and drain of the sampling N-type channel TFT when not selected ΔV _gd = ΔV _g × C _gd / (C _gd + C _s ) (3-3) where ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ) and C _gd are gate-drain parasitic capacitances of the N-channel TFT for sampling, and C _s is a sample-hold capacitance (including wiring capacitance). ΔVx2: Gate-source voltage 1-exp {− (T _s / R _on C _s )} ≧ k / such that the on-resistance R _{on of the} sampling N-type channel TFT satisfies the following expression with a writing rate of k% or more. 100 (3-4) where T _s is the selection period of the sampling N-type channel TFT. 4. An analog dot-sequential driving system is adopted, which has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion including a pixel TFT and a signal line driving circuit for supplying an image signal to a signal line. In the TFT liquid crystal display device according to the present invention, the sampling circuit of the signal line driving circuit is composed of sampling P-type channel TFTs, and the bias condition of the power supply voltage of the signal line driving circuit is set so as to satisfy the following expression. A TFT type liquid crystal display device characterized by the following. V _ddx ≧ Vid 2 + ΔVx 2 (4-1) V _ssx ≦ Vid 1-ΔVx 1 (4-2) V _ddx : Positive power supply voltage of the signal line drive circuit V _ssx : Negative power supply voltage of the signal line drive circuit Vid 1: Minimum image signal Voltage Vid2: Maximum voltage of image signal ΔVx1: Gate-source voltage 1-exp {-(T _s / R) such that the on-resistance R _{on of the} sampling P-type channel TFT satisfies the following expression with a writing rate of k% or more. _on C _s )} ≧ k / 100 (4-4) where T _s is the sampling P-type channel TFT selection period and C _s is the sample-hold capacitance (including the wiring capacitance).
Is. ΔVx2: Maximum value of the shift voltage ΔV _gd between the gate and drain of the sampling P-type channel TFT when not selected ΔV _gd = ΔV _g × C _gd / (C _gd + C _s ) ... (4- 3) However, ΔV _g is the magnitude of the selection pulse (V _ddy −
V _ssy ), C _gd are gate-drain parasitic capacitances of the P-channel TFT for sampling. 5. An analog dot-sequential driving system is adopted, which has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion including a pixel TFT and a signal line driving circuit for supplying an image signal to a signal line. In this TFT type liquid crystal display device, the sampling circuit of the signal line drive circuit is composed of a sampling CMOS type TFT, and the bias condition of the power supply voltage of the signal line drive circuit is set so as to satisfy the following expression. A TFT type liquid crystal display device characterized by the above. V _ddx ≧ (Vid2-Vid1) / 2 + V _gsn (5-1) V _ssx ≦ (Vid2-Vid1) / 2-V _gsp (5-2) V _ddx ≧ Vid2 + ΔVx2 (5-3) V _ssx ≦ Vid1 -ΔVx1 (5-4) V _ddx : Positive power supply voltage of signal line drive circuit V _ssx : Negative power supply voltage of signal line drive circuit Vid 1: Minimum voltage of image signal Vid 2: Maximum voltage of image signal V _gsn : Sampling CMOS The gate-source voltage is such that the on-resistance R _onn of the N-channel TFT of the type TFT satisfies the following expression of the writing rate k%. 2 {1-exp (-T _s / R _onn C _s )} = k / 100 (5-5) V _gsp : The on-resistance R _onp of the P-channel TFT of the sampling CMOS TFT is next to the writing rate k%. The gate-source voltage satisfies the formula. _{2 {1-exp (-T s} / R onp C s)} = k / 100 ... (5-6) ΔVx1: ( maximum value of [Delta] V _gdn) - (minimum value of ΔV _gdp) ΔVx2: (maximum [Delta] V _gdp Value) − (minimum value of ΔV _gdn ) Here, ΔV _gdn and ΔV _gdn are respectively given by the following equations. ΔV _gdp = (V _ddx −V _ssx ) × C _gdp / (C _gdp + C _s ) ... (5-7) ΔV _gdn = (V _ddx −V _ssx ) × C _gdn / (C _gdn + C _s ) ... (5- 8) where C _gdp is the gate-rain capacitance of the P-channel TFT of the sampling CMOS type TFT, and C _gdn is its N
The gate-drain capacitance of the channel TFT, C _s, is a sample hold capacitance (including wiring capacitance). 6. An analog line sequential driving system is adopted, which has a scanning line driving circuit for supplying a selection pulse to a scanning line of a pixel matrix portion including a pixel TFT and a signal line driving circuit for supplying an image signal to a signal line. In the TFT type liquid crystal display device, the signal line driving circuit writes the image signal in response to a selection pulse sent from a shift register, and the latch circuit in the first stage writes the image signal in batches 2 It has a latch circuit of the second stage and an analog buffer circuit which outputs the output voltage to the signal line by using the output of the latch circuit of the second stage as an input voltage, and the bias condition of the power supply voltage of the signal line drive circuit. Is set so as to satisfy the following formula: A TFT type liquid crystal display device. V _ddx ≧ Vid2 + ΔVx2 (6-1) V _ssx ≦ Vid1-ΔVx1 (6-2) V _ddx : Positive power supply voltage of the signal line drive circuit V _ssx : Negative power supply voltage of the signal line drive circuit Vid 1: Minimum of image signal Voltage Vid2: Maximum voltage of image signal Here, Vid1 and Vid2 are defined as follows. ΔVx1: voltage required to satisfy the equation (6-3) of the writing rate k% or more even when the linearity of the input / output signal of the analog buffer is maintained and the minimum value Vid1 of the image signal is input ΔVx2: of the analog buffer maintaining the linearity of the input and output signals, the image signal of the maximum value if positioned also write rate k% or more equation Vid2 (6-3) needed to meet the voltage _{1-exp (-T 1 / τ} ) ≧ k / 100 (6-3)