JPH08137443A - Image display device - Google Patents

Abstract

PURPOSE: To suppress a charge/discharge current of a data signal line, to lower an operational voltage of a data signal line driving circuit, to reduce power consumption in an image display device, to lower breakdown strength of components and to reduce the manufacturing cost and operational cost. CONSTITUTION: The data signal line drive circuits 3, 4 are provided respectively, on both side sides placed opposite to each other of a pixel array 1. Source voltages of individually different levels are applied to the data signal line drive circuits 3, 4 so that every circuit outputs one side video signal. Two adjacent data signal lines SLi , SLi+1 are connected to the data signal line driving circuits 3, 4 by analog switches 8, 9. In a certain display period, the analog switch 8 selects the data signal line SLi , and the analog switch 9 selects the data signal line SLi+1 . In the next period, opposite selection are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device which enables low voltage driving of a data signal line driving circuit in an active matrix driven liquid crystal display device or the like.

[0002]

2. Description of the Related Art Image display devices employ a drive system according to the purpose of use and the like. Among them, the active matrix drive system suitable for graphics display is well known. As shown in FIG. 22, this type of image display device includes a pixel array 121 and a scanning signal line drive circuit 1.
22, a data signal line drive circuit 123, and a timing signal generation circuit 124. In the image display device having such a configuration, the scanning signal line drive circuit 122 uses the timing signal generated by the timing signal generation circuit 124 based on the synchronization signal, and each scanning signal line GL _j in the pixel array 121, which will be described later. _, GL _{j + 1} ... And outputs a scanning signal. In addition, the data signal line drive circuit 123
Transfers (or amplifies and transfers) the sampled video signal to the data signal lines SL _i, SL _{i + 1} ...

As shown in FIG. 23A, in the pixel array 121, a large number of scanning signal lines GL _j, GL _{j + 1} ...
And a large number of data signal lines SL _i, SL _{i + 1} ... Are arranged so as to intersect with each other, and two adjacent scanning signal lines GL · G.
A pixel 125 is provided in a portion surrounded by L and two data signal lines SL and SL adjacent to each other. in this way,
The pixels 125 are arranged in a matrix in the pixel array 121, and one data signal line SL is provided for each column.
, And one scanning signal line GL is allocated per row.

In the case of a liquid crystal display device, each pixel 125 includes a transistor 126 as a switching element, a liquid crystal capacitance C _L, and an auxiliary capacitance C _S added as needed, as shown in FIG. And the pixel capacitance 127. Generally, in an active matrix type liquid crystal display device, an auxiliary capacitance C _S is added to the pixel 125 in parallel with the liquid crystal capacitance C _{L in} order to stabilize the display. The auxiliary capacitances are the liquid crystal capacitance C _L , the leakage current of the transistor 126, the gate of the transistor 126,
This is for minimizing the influence of the fluctuation of the pixel potential due to the parasitic capacitance such as the capacitance between sources and the influence of the display data dependency of the liquid crystal capacitance C _L.

The gate of the transistor 126 is connected to the scanning signal line GL _j . Further, one electrode of the liquid crystal capacitance C _L and the auxiliary capacitance C _S is connected to the data signal line SL _i via the drain and the source of the transistor 126, and the other electrode of the liquid crystal capacitance C _L sandwiches the liquid crystal cell. It is connected to the counter electrode. Further, the other electrode of the auxiliary capacitance C _S is a common electrode line (Cs not shown) common to all pixels.
on common structure) or adjacent scanning signal line G
It is connected to L (in the case of Cs on Gate structure). In the latter case, since the parasitic capacitance of the scanning signal line GL _j increases, there is a problem that the signal delay increases and the signal waveform becomes blunt. On the other hand, in the former case, although the parasitic capacitance of the scanning signal line does not increase, it is necessary to newly lay an auxiliary capacitance line in parallel with the scanning signal line GL _j, which causes a problem that the aperture ratio decreases. .

A large number of scanning signal lines GL _j, GL _{j + 1,} ... Are connected to the scanning signal line drive circuit 122, and a large number of data signal lines SL _i, SL _{i + 1,} ... Are connected to the data signal line drive circuit 123. It is connected. Further, although not shown, the scanning signal line drive circuit 122 and the data signal line drive circuit 123 are driven by different power supply voltages V _DD and V _SS and power supply voltages V _CC and V _EE , respectively.

In the above image display device, the data signal line drive circuit 123 outputs the display data signal for each pixel.
Alternatively, it outputs to the data signal lines SL _i, SL _{i + 1,} ... For each horizontal scanning period (1H line). In addition, the scanning signal line GL
_{When j,} GL _{j + 1} ... becomes active, transistor 1
26 becomes conductive, whereby the data signal line S
The display data signal sent to L _i, SL _{i + 1} ... Is written in the pixel capacitor 127. Then, the display is maintained by the charges written in the pixel capacitor 127.

At this time, it is necessary to perform AC driving in order to prevent the deterioration of the liquid crystal capacitance C _L. When this AC drive (reverse drive) is performed in a frame cycle, flicker of, for example, 30 Hz or 25 Hz is conspicuous although it varies depending on the frame frequency of the signal. Therefore, in addition to the frame inversion,
4 (a) and (b), the polarity is inverted every horizontal scanning period, so-called “frame + gate line inversion” drive, or as shown in FIG. It is customary to perform either so-called "frame + source line inversion" driving, in which the polarity of the data signal is inverted and the polarity is inverted every vertical scanning period.

[0009]

However, in an image display device that needs to be driven by an alternating current such as a liquid crystal display device, even if the displayed contents (information) do not change,
A video signal is periodically supplied from the data signal line drive circuit 123 to the data signal lines SL _i, SL _{i + 1} , ...
It is necessary to write data to. Therefore,
A large amount of current is required for display.

In the case of the above-mentioned "frame + gate line inversion" drive, as shown in FIG. 24 (a), the polarities of the data signals output to the data signal lines SL _i, SL _{i + 1} . Is inverted every time the scanning signal lines GL _j, GL _{j + 1,} ... Are selected, the data signal lines SL _i, SL _{i + 1} accompanying the inversion of the polarities.
Power consumption increases due to the charge / discharge current of. In addition, as shown in FIG. 24B, the data signal line drive circuit 12
Since AC driving of the counter electrode is performed in order to suppress the output voltage range of No. 3, the power consumption also increases. As described above, when the "frame + gate line inversion" driving is adopted, there is a problem that the power consumption of the image display device increases.

On the other hand, in the case of the "frame + source line inversion" drive described above, since signals of the same polarity are written in one vertical scanning period as shown in FIG. 25, the data signal lines SL _i, SL _{i +.} The charge / discharge amount of ₁ ... decreases as shown by the shaded area in the figure. Moreover, in general, since the image data of the adjacent pixels are relatively similar to each other, the data signal line SL _i,
It is expected that the charge / discharge amount of SL _{i + 1} ... Will be considerably reduced. Therefore, the power consumption due to the charge / discharge current of the data signal lines SL _i, SL _{i + 1} ... Can be reduced.

However, in the "frame + source line inversion" driving, the AC drive of the counter electrode, which is performed in the "frame + gate line inversion" driving, cannot be performed, so that the output voltage range of the data signal line becomes large. As a result, power consumption increases and it becomes necessary to increase the withstand voltage of the drive circuit.

24 and 25, the thick solid line shows the voltage waveform applied to the data signal lines SL _i, SL _{i + 1} ..., The broken line shows the voltage waveform applied to the counter electrode, and the shaded area shows the data. The consumption current associated with charging / discharging of the signal lines SL _i, SL _{i + 1} ...

In the image display device, particularly the liquid crystal display device, the fact that the power is proportional to the square of the voltage is used to narrow the range of the voltage applied to the data signal lines SL _i, SL _{i + 1} ... By driving the data signal line drive circuit 123 with a voltage, it is desirable to suppress the power consumption of the data signal lines SL _i, SL _{i + 1} . However, in the liquid crystal display device, since it is necessary to perform the inversion drive, the data signal line drive circuit 123 may be twice the liquid crystal drive voltage (the sum of the positive electrode signal and the negative electrode signal) depending on the conventional driving method described above. It is necessary to apply a voltage in the range of to the data signal lines SL _i, SL _{i + 1} ..., This increases power consumption.

By the way, in recent years, this type of image display device is often used as a display device of a portable information terminal device, and some of them are premised for outdoor use. Therefore, driving with a small power source such as a battery is required, and low power consumption is a major issue.
Therefore, the increase in power consumption as described above is extremely disadvantageous for making an image display device portable.

In order to solve the above problems, in the active matrix type liquid crystal display device using the amorphous silicon (a-Si) TFT, in addition to the "frame + source line inversion" driving, the output range of the data line driving circuit A method has been proposed to reduce the power consumption by driving the data line drive circuit at a low voltage by changing the power supply voltage AC while maintaining the above (Society for Informa
tion Display 1993 Proceedings 4.3). However, although the liquid crystal display device proposed here is effective in reducing power consumption to some extent and is also effective in lowering the withstand voltage of the data line driving circuit, it changes the power supply voltage in an alternating manner, Not only the load of the power supply circuit becomes heavy, but also noise or the like may occur when switching the power supply, which may cause malfunction or display disorder.

The present invention has been made in view of the above circumstances, and further reduces the power consumption while ensuring the operation margin, and the breakdown voltage required for the elements constituting the drive system and the pixel array. An object is to provide an image display device that can be lowered.

[0018]

The image display device of the present invention is characterized in that the following means are provided to solve the above-mentioned problems.

According to another aspect of the image display device of the present invention, a plurality of pixels arranged in a matrix to perform display by active matrix driving, scanning signal lines connected to the pixels in one row, and one column of the above. A data signal line connected to the pixel and a scanning signal line drive circuit for supplying a scanning signal to the scanning signal line are provided in two systems, each driven by a power source having a different voltage level, and the even number column of the data signal line is provided. And odd-numbered columns are supplied with video signals having different polarities, and a data signal line drive circuit for inverting the polarities of the video signals given to the even-numbered columns and the odd-numbered columns of the data signal lines for each predetermined data display period, and an even number A video signal from one of the data signal line drive circuits is applied to the data signal lines in the columns, and a video signal from the other data signal line drive circuit is applied to the data signal lines in the odd columns. Together they give, and a replacement means replaces the data signal line driving circuits corresponding to the even columns and odd columns of the data signal lines for each predetermined data display period.

An image display device according to a second aspect is the image display device according to the first aspect, wherein the replacement means is commonly connected to one output stage of the data signal line drive circuit, and It has two lines of switching elements that are connected to the two data signal lines of the odd-numbered column and the even-numbered column that are paired and take in the video signal, and both switching elements are alternately turned on every predetermined data display period. Thus, the data signal line drive circuit and the data signal line are connected.

An image display device according to a third aspect is the image display device according to the first aspect, wherein the replacing means is connected to one output stage of the data signal line drive circuit and a video signal is transmitted. A first switching element to be taken in,
And a second switching element of two systems that supplies the video signal taken in by the first switching element to the two data signal lines, and the second switching element is alternately turned on every predetermined data display period. Thus, the data signal line drive circuit and the data signal line are connected.

An image display device according to a fourth aspect is the image display device according to any one of the first to third aspects,
Part or all of the data signal line drive circuit, the replacement means, and the active elements included in the pixels are formed on a single crystal silicon thin film or a polycrystalline silicon thin film formed on an insulating substrate.

An image display device according to a fifth aspect is the image display device according to the second or third aspect, in which the switching element or the first and second switching elements is an n-channel transistor connected in parallel. It is a gate having a CMOS structure including a p-channel transistor.

According to another aspect of the image display device of the present invention, a plurality of pixels arranged in a matrix to perform display by active matrix driving, scanning signal lines connected to the pixels in one row, and one column of the above. A data signal line connected to a pixel, a scanning signal line drive circuit for supplying a scanning signal to the scanning signal line, and two systems, each of which has a different polarity in even and odd columns of the data signal line. A data signal line drive circuit for applying a signal and inverting the polarity of a video signal applied to the even and odd columns of the data signal line for each predetermined data display period, and two systems of power supplies of different voltage levels are used for the data. Each of the signal line drive circuits is provided with a connection unit that switches and connects every predetermined data display period, and the active element included in the data signal line drive circuit and the pixel is provided. Some or all of, are formed on the single crystal silicon thin film or polycrystalline silicon thin film formed on an insulating substrate.

An image display apparatus according to a seventh aspect is the image display apparatus according to the sixth aspect, wherein the connecting means is formed on the insulating substrate.

An image display device according to an eighth aspect is the image display device according to the first or sixth aspect, in which the two systems of the data signal line drive circuits respectively output only the video signal of one polarity to the data signal line. It is designed to be driven by a power supply voltage which is given to the.

An image display device according to a ninth aspect is the image display device according to the first or sixth aspect, in which the data signal line drive circuit samples a video signal and transfers it to the data signal line. Is equipped with.

An image display device according to a tenth aspect is the image display device according to the first or sixth aspect, wherein the data signal line driving circuit is sampled by a sampling means for sampling a video signal and the sampling means. Holding means for temporarily holding the video signal, and amplifying means for amplifying the video signal held by the holding means and transferring it to the data signal line.

An image display device according to an eleventh aspect is the image display device according to the first or sixth aspect, wherein the data signal line drive circuit includes sampling means for sampling a digital signal representing video information, and the sampling means. Selecting means for selecting one of a plurality of discrete voltages based on the digital signal sampled by the means and transferring it to the data signal line.

According to a twelfth aspect of the present invention, in the image display apparatus according to the first or sixth aspect, the two systems of the data signal line drive circuits are both arranged on the same side of the pixel matrix. .

An image display device according to a thirteenth aspect is the image display device according to the first or sixth aspect, wherein each of the pixels has a liquid crystal element.

[0032]

According to another aspect of the image display device of the present invention, by the replacing means, video signals are given to the even and odd columns of the data signal line from different data signal line drive circuits during a certain data display period, In the next data display period, a video signal is supplied from the data signal line driver circuit which is different from the previous data display period. Further, by two systems of data signal line driving circuits driven by different power supply systems, for example, in a certain data display period, a positive video signal is given to even-numbered columns of the data signal lines and odd-numbered columns of the data signal lines. Is supplied with a negative video signal. Then, in the next data display period, a negative video signal is applied to the even-numbered columns of the data signal lines, and a positive video signal is applied to the odd-numbered columns of the data signal lines.

That is, as described above, by combining the operation by the replacing means and the "frame + source line inversion" drive of the data signal line drive circuit, each data signal line drive circuit has a video signal of one polarity. You only have to deal with it. Therefore, the drive voltage of the data signal line drive circuit can be reduced.

In the image display device according to the second aspect, since one of the switching elements is made conductive when the data signal line drive circuit and the data signal line are connected, the power supply line and the data signal line in the video signal line or the digital driver system are connected. There is only one switching element in between.
As a result, the impedance of the switching element when conducting is reduced, and the video signal can be easily applied to the data signal line.

According to another aspect of the image display device of the present invention, after the video signal is once taken in by the first switching element,
It is given to either one of the data signal lines via the second switching element of the system. With this configuration, it is only necessary to add the second switching element after the first switching element. As a result, the increase in the area of the drive circuit including the replacement unit can be suppressed to be relatively small, and the increase in the area of the image display device can be suppressed as much as possible.

According to another aspect of the image display device of the present invention, a part or all of the data signal line drive circuit, the replacement means and the active elements constituting the pixel are formed on the single crystal or polycrystalline silicon thin film formed on the insulating substrate. Since it is formed, the breakdown voltage tends to be lower than that of an active element formed on a conventional semiconductor substrate, but as described above, it is possible to reduce the drive voltage of the data signal line drive circuit. It is possible to secure a sufficient operation margin.

According to another aspect of the image display device of the present invention, the n-channel transistor and the p-channel transistor in the gate of the CMOS structure are turned on at the same time by applying gate voltages of opposite polarities. At this time, the video signal on the low potential side passes through the n-channel transistor, and the video signal on the high potential side passes through the p-channel transistor. Therefore, the video signal can be reproduced in a wider range from the low potential side to the high potential side.

According to another aspect of the image display device of the present invention, the connection means connects the power signal of different voltage levels to the data signal line drive circuits of the two systems and connects the data signal lines of the even columns and the signal lines of the odd columns to each other. The connection is switched every data display period. The respective data line driving circuits are driven by different power supply systems, and the power supply systems are switched for each display period. 2 driven by different power supply systems
The data signal line driving circuit of the system supplies a positive video signal to even-numbered columns of the data signal lines and a negative video signal to odd-numbered columns of the data signal lines in a certain data display period, for example. Then, in the next data display period, a negative video signal is applied to the even-numbered columns of the data signal lines, and a positive video signal is applied to the odd-numbered columns of the data signal lines.

That is, as described above, by combining the switching operation of the power supply by the connecting means and the "frame + source line inversion" drive of the data signal line drive circuit, each data signal line drive circuit has one polarity. It is sufficient to handle only the video signal of. Therefore, the drive voltage of the data signal line drive circuit can be reduced.

Further, since the data signal line drive circuit and a part or all of the active elements included in the pixel are formed on the single crystal silicon thin film or the polycrystalline silicon thin film formed on the insulating substrate, The load on the power supply circuit is reduced, and the power supply can be switched quickly and easily.

In the image display device according to the seventh aspect, since the connecting means is formed on the insulating substrate, the connecting line between the connecting means and the data signal line drive circuit and the like are incorporated on the insulating substrate. External wiring between the connection means and external circuits (controller, power supply, etc.) can be eliminated. Therefore, it is not necessary to use a dedicated wiring for connecting the connecting means and the external circuit, and the external circuit which has been conventionally used can be diverted as it is.

According to another aspect of the image display device of the present invention, since both data signal line drive circuits are driven by the power supply voltage which gives only the video signal of one polarity to the data signal line,
The drive voltage becomes the minimum necessary, and the drive voltage of the data signal line drive circuit can be reduced similarly to the image display device according to claim 1.

In the image display device of the ninth aspect, the video signal is sampled by the sampling means and directly transferred to the data signal line. This is a so-called panel sample and hold method, and one data signal line is
It is only necessary to provide a sampling means for the system. Therefore, the number of circuits for controlling the transfer gate and the sampling means in the subsequent stage is reduced.

In the image display device of the tenth aspect, the video signal is sampled by the sampling means, temporarily held in the holding means, and then transferred to the data signal line by the amplifying means. This is a so-called driver sample hold, and the writing time of the video signal to the data signal line is sufficiently long (approximately one horizontal scanning period). Therefore, the driving force of the switching element forming the sampling means can be small, and the size of the switching element can be reduced.

According to the eleventh aspect of the image display device, the digital signal is sampled by the sampling means.
Then, one of the plurality of discrete voltages is selected by the selection means based on the sampled digital signal and transferred to the data signal line. This is a so-called digital driver method, and when performing multi-gradation display that requires a large number of power sources, only the video signal of one polarity needs to be handled as described above, so the number of power sources is halved.

In the image display device according to the twelfth aspect, since the two systems of the data signal line drive circuits are arranged on the same side of the pixel matrix, the signal input to the image display device is concentrated at one place. By doing so, it is possible to shorten the routing of signal lines and the like, and it is possible to apply this configuration also when it is necessary to input the same video signal from both sides of the data signal line as the screen becomes larger.

The image display device according to a thirteenth aspect is an active matrix type liquid crystal display device in which each pixel has a liquid crystal element, and the low power consumption of the liquid crystal display device is reduced in order to reduce the power consumption due to the driving voltage drop of the data signal line drive circuit. The advantage of power is added.

[0048]

【Example】

[Embodiment 1] The following description will discuss Embodiment 1 of the present invention with reference to FIGS. 1 to 12.

The image display device according to the present embodiment is an active matrix drive type liquid crystal display device, and as shown in FIG. 1, a pixel array 1, a scanning signal line drive circuit 2,
The data signal line drive circuits 3 and 4 are provided. In the pixel array 1, a large number of scanning signal lines GL _j, GL _{j + 1,} ... And a large number of data signal lines SL _i, SL _{i + 1,} ... Further, in the area surrounded by the adjacent scanning signal lines GL and GL and the adjacent data signal lines SL and SL,
The pixels 5 are provided one by one, and the pixels 5 ... Are arranged in a matrix as a whole.

The pixel 5 has a switching element 6 and a pixel capacitor 7. The switching element 6 is, for example, M
It is composed of an OS type FET, and its gate is connected to the scanning signal line GL (GL _j, GL _{j + 1} ...). Although not shown, the pixel capacitor 7 is composed of a liquid crystal capacitor as a liquid crystal element and an auxiliary capacitor, like the liquid crystal capacitor described in the section of the related art (see FIG. 23B). That is,
The pixel 5 is configured and operates in the same manner as the pixel of the conventional image display device described above.

The data signal line drive circuits 3 and 4 are arranged on both sides with the pixel array 1 in between, and one end and the other end of each data signal line SL _i, SL _{i + 1} ... , 9 ... are connected. The data signal line drive circuit 3 is supplied with V _CC1 as a positive voltage and V _EE1 as a negative voltage, while the data signal line drive circuit 4 is supplied with V V as a positive voltage.
_CC2 is given and V _EE2 is given as a negative voltage.

The power supply voltage V _CC1 · V _EE1 · V _CC2 ·
V _EE2 is set to have a magnitude relationship such that V _EE2 <V _CC2 <V _EE1 <V _CC1 . In addition, the power supply voltage V _CC1 · V _EE1
V _CC2 · V _EE2 is expressed by the following equation, where V _T is the threshold voltage of the liquid crystal, V _S is the saturation voltage of the liquid crystal, and V _th is the threshold voltage of the switching element 6 described above. V _CC1 = V _S + V _th + V _ON V _EE1 = V _T + V _th −V _OFF V _CC2 = −V _T + V _th + V _ON V _EE2 = −V _S + V _th −V _OFF However, in the above formula, V _ON , V _OFF Are the on margin and the off margin of the analog switches 8 and 9, respectively.

The data signal line drive circuits 3 and 4 are designed to operate by the "frame + source line inversion" drive method. Specifically, in the data signal line drive circuit 3, the applied voltage (power supply voltage) to the gate circuits used in the sampling circuits 13 to 15 and 17 described later is the power supply voltage V.
_Since it is _CC1 · V _EE1 , a positive video signal is output. On the other hand, the data signal line drive circuit 4
Similarly, the voltage applied to the gate circuit is the power supply voltage V _CC2
Since it is V _EE2 , the negative video signal is output. That is, the data signal line drive circuits 3 and 4
The video signals of different ranges are taken in by making the operating voltage ranges of the gate circuits different and are applied to the data signal lines SL _i, SL _{i + 1} .

The data signal line drive circuits 3 and 4 described above are also provided.
The above is not limited to the panel sample hold method, but may be the driver sample hold method or the digital driver method. The panel sample and hold method uses the sampled video signal as the data signal line SL.
_i, SL _{i + 1,} ..., In the driver sample and hold method, the sampled video signal is once transferred to the data storage section, then amplified by the amplifier and written in the data signal line. Further, in the digital driver system, one of the power supplies that outputs a plurality of discrete voltages according to the digital video signal is selectively connected to the data signal line to write the video signal.

As shown in FIG. 2, the panel sample hold type data signal line drive circuit includes a shift register 11
, A latch circuit 12, ... And a sampling circuit 13 ,. The shift register 11 shifts a start pulse (not shown) in synchronization with the rising or falling of the timing signal and outputs the shift pulse. The sampling circuit 13 as a sampling means is a switch circuit that opens and closes in synchronization with the shift pulse that has passed through the latch circuit 12. When closed by the shift pulse, the video signal is applied to the data signal lines SL _i, SL _{i + 1} . Has become.

As shown in FIG. 3, the driver sample-hold type data signal line drive circuit includes a shift register 1
1, a latch circuit 12, ..., A sampling circuit 14 ,.
15 ... Sampling capacity C _samp ... and hold capacity C
_hold ... and amplifier 16 ...

Sampling circuits 14 and 15 as sampling means composed of analog switches are connected in series. The sampling circuit 14 opens and closes in synchronization with the shift pulse passed through the latch circuit 12, and the sampling circuit 15 transfers data. It opens and closes in synchronization with the signal TRF.

Sampling capacitance C _samp as holding means
Is provided at the output stage of the sampling circuit 14,
The data (video signal) sampled by the sampling circuit 14 is stored. Further, the hold capacitor C _{ho ld} as the holding means, the sampling circuit 1
5, the sampling circuit 15 stores the data (video signal) transferred from the sampling capacitor C _samp . The amplifier 16 as an amplifying means is provided at a stage _{subsequent to} the hold capacitance C _hold .

As shown in FIG. 4, the amplifier 16 includes transistors TR _{1 to} TR ₇ and a capacitor C, and the gates of the transistors TR ₁ and TR _{6 have} constant voltages V _b1 for biasing respectively. -V _b2 is given. This amplifier 16 has, in the preceding stage, transistors TR ₂ · TR ₃ which are p-channel MOS transistors and transistors TR ₄ · T which are n-channel MOS transistors.
It has a symmetrical circuit consisting of R ₅ and has n
Transistor TR ₇ which is a channel MOS transistor
Is a buffer amplifier having a source follower.

As shown in FIG. 5, the data signal line drive circuit of the digital driver system includes shift registers 11 ...
, The latch circuit 12, ..., The sampling circuit 17 ,.
And a digital buffer 18 ... A sampling circuit 17 as a sampling means opens and closes a digital video signal in synchronization with a shift pulse passed through the latch circuit 12.

As shown in FIG. 6, the digital buffer 18 has a decoder 19 and analog switches 20 ... The decoder 19 is provided for each bit S of the digital video signal sampled by the sampling circuit 17.
It is adapted to generate eight select signals by the combination of ₁ to S _3. The analog switches 20 ... As a selection means each have a discrete voltage V ₁ to V ₁ output from a voltage source (not shown) in response to a selection signal from the decoder 19.
One of V ₈ is selected and applied to the data signal line SL. The above voltages V _{1 to} V ₈ are set to values corresponding to the respective levels so that the transmittance of the liquid crystal (see FIG. 12) takes eight levels at even intervals.

The analog switches 8 and 9 are connected to the outputs of the data signal line driving circuits 3 and 4 based on an external signal from one of two adjacent data signal lines SL (odd column) and SL (even column). It is adapted to select and connect by switching conduction / non-conduction for each field. These analog switches 8 and 9 always select different data signal lines SL.

Further, the analog switches 8 and 9 are specifically the selection circuits 26.4 as shown in FIG. 7 or 10.
It is a part of 2. These analog switches 8
9 is applicable to the data signal line drive circuits 3 and 4 of the panel sample hold system, the driver sample hold system, and the digital driver system described above.

As shown in FIG. 7, the selection circuit 26 as the replacement means is composed of the analog switch 8 (9), the shift register 11 and the inverters 24 and 25.

The analog switch 8 (9) is composed of n-channel transistors 21-23. The n-channel transistor 21 as the first switching element is adapted to take in a video signal by being conductive.
The n-channel transistors 22 and 23 functioning as the second switching elements have their states inverted for each field, and the field switching signals FR ₁ and FR _{2 which} are always different from each other are applied to their gates so that conduction and non-conduction are alternately repeated. Has become. As a result, the n-channel transistor 22.2
3 is based on the field switching signals FR ₁ and FR ₂
The video signal from the n-channel transistor 21 is supplied to the data signal lines SL _i, SL _{i + 2} ... (Odd column) or the data signal line S.
L _{i + 1,} SL _{i + 3} ... (Even-numbered columns) are alternately given to one of them.

The inverters 24 and 25 are connected in series and are provided in the data signal line drive circuits 3 and 4 together with the shift register 11. These inverters 2
Reference numerals 4 and 25 increase the fan-out capacity of the output of the shift register 11 and apply the shift pulse from the shift register 11 to the gate of the n-channel transistor 21 as a control signal.

The selection circuit 26 is a panel sample hold type circuit having the above-mentioned configuration. However, when it is applied to the driver sample hold type, as shown in FIG. 8A or FIG. The n-channel transistors 21, 22, and 23 are provided at the subsequent stage of the amplifier 16. In addition,
WE (Write Enable) in FIG. 8B is a writing period setting signal. Further, when the selection circuit 26 is adopted in the digital driver system, as shown in FIG. 9, n-channel transistors 22 and 23 are provided after the analog switches 20 ...

On the other hand, as shown in FIG. 10, the selection circuit 42 as a replacement means forms a panel sample and hold system circuit, and is composed of an analog switch 8 (9), a shift register 11 and inverters 34 to 41. There is.

The analog switch 8 (9) includes CMOS transistors 31 to 31 called a transmission gate.
It consists of 33. C as the first switching element
The MOS transistor 31 is the n-channel transistor 3
1a and the p-channel transistor 31b are connected in parallel, and the captured video signal is supplied to the CMOS transistors 32 and 33 as the second switching elements.

The CMOS transistor 32 has a field switching signal FR at the gate of the n-channel transistor 32a.
₁ is input, and the field switching signal FR ₂ is input to the gate of the p-channel transistor 33b. CMO
The S transistor 33 is an n-channel transistor 33a.
And the field switching signals FR ₁ and FR ₂ input to the respective gates of the p-channel transistor 33b and the p-channel transistor 33b are C
It is the reverse of the MOS transistor 32. As a result, the CMOS transistors 32 and 33 are turned on and off at different timings.

The inverters 34 to 36 are connected in series, and together with the shift register 11, the data signal line drive circuit 3 is provided.
・ It is provided in 4. The inverters 37 to 39 and the inverters 40 and 41 are respectively provided on the paths branched from the output terminal of the inverter 36. The output terminal of the inverter 39 is connected to the gate of the n-channel transistor 31a, and the output terminal of the inverter 41 is connected to the gate of the p-channel transistor 31b. That is, even-numbered inverters 34 to 39 are provided in the signal path to the n-channel transistor 31a, while p
The signal path to the channel transistor 31b is provided with odd-numbered inverters 34 to 36, 40, and 41.

The circuit composed of the above-mentioned inverters 34 to 41 has the same function as that of the above-mentioned inverters 24 and 25, but further the gates of the n-channel transistor 31a and the p-channel transistor 31b are respectively inverted. A polarity control signal (gate voltage) is applied. As a result, the CMOS transistor 31 simultaneously becomes conductive and non-conductive, and the video signal is captured by the conduction. Then, the video signal is alternately applied to the data signal lines SL _i and SL _{i + 1} by the CMOS transistors 32 and 33 which conduct at different timings based on the field switching signals FR ₁ and FR ₂ .

In the selection circuit 42, by using the CMOS transistors 31 to 33, the low-potential-side video signal passes through the n-channel transistors 31a to 33a, while the high-potential-side video signal is transferred to the p-channel transistor 31.
Since it passes through b to 33b, the video signal can be captured in a wide range from the low potential side to the high potential side. As a result, it becomes possible to display high-quality images.

In the selection circuit 26, the video signal is once taken in by the n-channel transistor 21 and then divided into two systems by the n-channel transistors 22 and 23. Therefore, the data signal line drive circuits 3 and 4 side The analog switches 8 and 9 are basically controlled by simply controlling the n-channel transistor 21. Since the video signal is taken in using the switching element such as the n-channel transistor 21 even in the conventional configuration, it is only necessary to newly add the n-channel transistors 22 and 23 to such a configuration. The configuration of the selection circuit 26 can be realized. This also applies to the selection circuit 42.

The switching of the signal polarity for each field by the selection circuits 26 and 42 and the data signal line drive circuits 3 and 4 is performed as follows. For example, in a certain display field (data display period), the data signal line S
L _i is connected to the data signal line drive circuit 3 to write positive polarity data, and the adjacent data signal line SL _{i + 1} is connected to the data signal line drive circuit 4 to write negative polarity data. Then, in the next display field, the data signal line SL _i is connected to the data signal line drive circuit 4 to write the negative polarity data, and the data signal line SL _{i + 1} is connected to the data signal line drive circuit 3. Positive polarity data is written.

However, in the above structure, some display position adjusting circuit (not shown) is required to adjust the display position for each field. For example, the first output of the data signal line drive circuit 3 is output to the data signal line SL ₁ or the data signal line SL ₂ depending on the display frame. Therefore, the timing of the first output of the data signal line drive circuit 3 and the timing of the first output of the data signal line drive circuit 4 come and go for each frame, and it is necessary to adjust the display position accordingly. is there.

As the display position adjusting circuit, for example, a delay circuit for one pixel provided in each of the data signal line driving circuits 3 and 4 and an external device for delaying a video signal input to the data signal line driving circuits 3 and 4 are used. A delay circuit or the like can be used. Also,
It is also possible to deal with this by changing the clock signal or start pulse given to the shift register 11.

By the way, a silicon thin film transistor as shown in FIG. 11 is used for various switch elements and the like in this image display device. This silicon thin film transistor is a polycrystalline silicon thin film transistor (hereinafter referred to as p-Si thin film transistor), and a polycrystalline silicon thin film (hereinafter referred to as p-Si thin film) 52 formed on a glass substrate 51 as an insulating substrate 52. MIS (Metal I
nsulator Semiconductor) A field effect transistor is formed.

A gate electrode 54 is formed on the p-Si thin film 52 via a silicon oxide film 53 as a gate insulating film, and impurity ions are formed in a region of the p-Si thin film 52 other than the region covered with the gate electrode 54. Is injected into the source electrode 55.
And a drain electrode 56 is formed. Then, a silicon nitride film 57 as an interlayer insulating film is formed so as to cover the silicon oxide film 53 and the gate electrode 54, and metal wirings 58, 58 reaching the source electrode 55 and the drain electrode 56 from the gap of the silicon nitride film 57, respectively. Are formed.

As the silicon thin film, the above-mentioned polycrystalline silicon thin film 52 is suitable in that a driving circuit can be integrally formed and an inexpensive glass substrate 51 can be used as an insulating substrate due to a low process temperature. However, not limited to this, the same effect can be expected with a single crystal silicon thin film or an amorphous silicon thin film. The material of the thin film is not limited to silicon, but germanium, an alloy of silicon and germanium, or another compound semiconductor (ZnS).
Etc.) may be used.

In this embodiment, the "frame + source line inversion" driving method is basically adopted. Thus, the data signal line SL _i, the SL i + ₂ ... positive polarity data is written, so that the data signal line _{SL i + 1, SL i +} 3 ...... negative polarity data is written, data Are alternately written. Therefore, data of the same polarity is written to one data signal line SL _i within each field period, and each data signal line SL _i is written.
Data of respective polarities are supplied to _i, SL _{i + 1} ... By two data signal line drive circuits 3 and 4 having different power supply voltage levels.

As described above, in the present embodiment, since the display is performed by writing only the signal of one polarity, the liquid crystal drive voltage or less (more accurately, the liquid crystal saturation voltage-the liquid crystal threshold voltage).
It suffices to supply the voltage in the above range, and the output voltage range of the data signal line drive circuits 3 and 4 can be reduced.
In this regard, the conventional example and the present example will be compared below.

In the driving method of the conventional example, the power supply voltage of the data signal line drive circuits 3 and 4 required when the analog switches 8 and 9 are ON and OFF, respectively, is represented by the following equation. The OFF time of -V _S + V _th -V _OFF time _{ON + V S + V th +} V ON above 2 equations, the maximum amplitude of the supply voltage becomes _{2V S + (V OFF + V} ON) ... (1). However, in the above equation, V _T: the liquid crystal threshold voltage V _S: saturation voltage of the liquid crystal V _th: threshold voltage V _OFF of the switching element 6: Off margin V _ON of the switching element 6: On the margin of the switching element 6.

On the other hand, the power supply voltage in the driving method of this embodiment is expressed by the following equation. When OFF V _T + V _th −V _OFF (= V _EE1 ) When ON V _S + V _th + V _ON (= V _CC1 ) From the above two equations, the maximum amplitude of the power supply voltage is V _S −V _T + (V _OFF + V _ON ) ... (2).

For example, in equations (1) and (2), assuming that the threshold voltage of the liquid crystal is 2V and the saturation voltage is 7V, the conventional driving method is 14V (16V if both V _OFF and V _ON are 1 V). ) Was required, but according to the configuration of this embodiment, the range is 5 V (7 V if V _OFF and V _ON are both 1 V).

That is, as shown in FIG. 12, in the conventional example, since it was necessary to apply a voltage to the liquid crystal in the range from -V _S to + V _S , the amplitude of the voltage had to be large. On the other hand, in this embodiment, it is only necessary to apply a voltage to the liquid crystal in the range of + V _T to + V _S on the positive electrode side and in the range of −V _T to −V _S on the negative electrode side. It becomes smaller than the conventional example.

Here, a 5.6 type VGA (480 × 640
XRGB) liquid crystal display device, the worst data (image data that consumes the most power) and the stairs at the gate line inversion and the source line inversion assuming that the threshold voltage of the liquid crystal is 2V and the saturation voltage is 7V. The following table shows the result of calculating the calculated value (charge and discharge charge amount in the two-field period) for the data. As a result, comparing the worst values, the source line inversion is about 36% of the gate line inversion (about 56% compared to the gate line inversion + common inversion).

[0088]

[Table 1]

Therefore, the drive voltage of the data signal line drive circuits 3 and 4 can be lowered. As a result, it is possible to reduce the power consumption of the image display device,
The breakdown voltage of the constituent element can be reduced. In particular, in an image display device (particularly a transmissive display device) of a driver monolithic structure (a pixel switch and a drive circuit are formed on the same substrate) which has been developed in recent years, an element forming the drive circuit is also included. Since it is a thin film transistor, its withstand voltage is lower than that of an element on a single crystal substrate, and a circuit that can be driven at a low voltage as described above can be easily applied.

In this embodiment, one data signal line SL is provided for one output of the shift register 11.
However, when RGB signals are simultaneously sampled as in the case of handling a color computer image, one output of the shift register 11 corresponds to one output (three in the case of RGB). The data signal lines may correspond.

[Second Embodiment] The second embodiment of the present invention will be described below with reference to FIGS. 1 and 13 to 18. In addition, in the components in this embodiment,
Components having the same functions as those of the components in the first embodiment described above are designated by the same reference numerals and the description thereof will be omitted.

The image display apparatus according to the present embodiment is the same as the analog switches 8 and 9 shown in FIG.
The configuration shown in is adopted. Although these analog switches are applied to the panel sample hold type data signal line drive circuit, they are also applicable to the driver sample hold type and the digital driver type.

As shown in FIG. 13, the selection circuit 67 as a replacement means is composed of an analog switch 8 (9), a shift register 11, NAND gates 63 and 64, and inverters 65 and 66.

The analog switch 8 (9) is composed of n-channel transistors 61 and 62 as switching elements. The NAND gates 63 and 64 and the inverters 65 and 66 are provided in the data signal line drive circuits 3 and 4 and control the operation of the analog switch 8 (9) based on the shift pulse output from the shift register 11. It is supposed to do.

The shift pulse from the shift register 11 is input to one of the input terminals of the NAND gates 63 and 64. The field switching signal FR ₁ is input to the other input terminal of the NAND gate 63,
The field switching signal FR ₂ is input to the other input terminal of the AND gate 64. The input terminals of the inverters 65 and 66 are the NAND gate 63, respectively.
-Connected to 64 output terminals. On the other hand, in the n-channel transistors 61 and 62, the output terminals of the inverters 65 and 66 are connected to the respective gates, and the video signal is input to the sources.

In the above structure, the gate circuit calculates the logical product (the logical sum depending on the number of inverters) of the shift pulse from the shift register 11 and the field switching signals FR ₁ and FR ₂ to obtain two n values. Only one of the channel transistors 61 and 62 becomes conductive. By alternately conducting such conduction, the video signal is taken in from the n-channel transistors 61 and 62 and is alternately applied to the data signal lines SL _i and SL _{i + 1} .

The above-mentioned configuration of the selection circuit 67 is a panel sample and hold system circuit. However, when it is applied to the driver sample and hold system, as shown in FIG. N-channel transistors 22 and 23 are provided. These n-channel transistors 22 and 23 have a negative logic write period setting signal / W.
E and field switching signal of negative logic / FR ₁ // FR ₂
ON / O by NOR gates 68 and 69 that inputs and
The FF is controlled. In addition, the selection circuit 6
When 7 is adopted in the digital driver system, as shown in FIG.
As shown in FIG. 5, one output of the decoder 19 is divided into two, which are respectively input to the NAND gates 63 and 64. The n-channel transistors 61 and 62 are connected to the respective power supply lines that supply the power supplies V _{1 to} V _{8 so as} to also serve as the analog switch 20.

As shown in FIG. 16, the selection circuit 83 as a replacement means forms a panel sample and hold circuit, and includes an analog switch 8 (9) and a shift register 1.
1, inverters 73 to 78, NOR gates 79 and 80, and NAND gates 81 and 82.
The inverters 73 to 78, the NOR gates 79 and 80, and the NAND gates 81 and 82 are connected to the data signal line drive circuit 3
・ It is provided in 4.

The CMOS transistor 71 as a switching element has an n-channel transistor 71a and a p-channel transistor 71b connected in parallel. CMOS transistor 7 as a switching element
2, n-channel transistor 72a and p-channel transistor 72b are connected in parallel.

The inverters 73 to 75 are connected in series, and the inverters 76 and 77 and the inverter 78 are provided on the paths branched from the output terminal of the inverter 75, respectively. The output terminal of the inverter 77 is NOR
It is connected to one input terminal of the gates 79 and 80, and the output terminal of the inverter 78 is connected to one input terminal of the NAND gates 81 and 82. In addition, NOR gate 8
The field switching signal FR ₁ is input to the other input terminal of 0 and the NAND gate 81, and the field switching signal FR ₂ is input to the other input terminal of the NOR gate 79 and the NAND gate 82.

In the CMOS transistor 71, the output terminal of the NOR gate 79 is connected to the gate of the n-channel transistor 71a, and the output terminal of the NAND gate 81 is connected to the gate of the p-channel transistor 71b.
On the other hand, in the CMOS transistor 72, the output terminal of the NOR gate 80 is connected to the gate of the n-channel transistor 72a and the gate of the p-channel transistor 72b is N-type.
The output terminal of the AND gate 82 is connected.

With this configuration, the NOR gate 79
80 and NAND gates 81 and 82 alternately turn on the CMOS transistors 71 and 72 based on the output signals of the inverter 77 and the inverter 78 having opposite polarities and the field switching signals FR ₁ and FR ₂ . . The video signals captured by the CMOS transistors 71 and 72 are alternately applied to the data signal lines SL _i and SL _{i + 1} for each field at different timings.

Also in this embodiment, the analog switch 8 is used.
By the operation of 9, the adjacent data signal lines SL _i · SL
_{i + 1} is the data signal line drive circuit 3 as in the first embodiment.
・ 4 is switched for each field and connected.

In the selection circuit 67, since the video signal is directly fetched by the n-channel transistors 61 and 62, it is necessary to control both transistors 61 and 62 individually, and it is necessary to configure a dedicated control circuit. The following advantages are obtained by minimizing the number of switching elements. That is, since the switching elements that pass before the video signal is written to the data signal lines SL _i and SL _{i +} 1 are the n-channel transistors 61 and 62, respectively, the selection circuits 26 and 42 in the first embodiment have the same switching elements. In comparison, the impedance when both transistors 61 and 62 are conductive can be reduced. This also applies to the selection circuit 83.

In this embodiment, the "frame + source line inversion" drive is basically adopted, and therefore, like the first embodiment, two data signal line drive circuits 3 having different power supply voltage levels are used. .. at 4 to the data signal lines SL _i, SL _{i + 1} ...
Data of each polarity can be supplied. As a result, the output voltage range of the data signal line drive circuits 3 and 4 becomes smaller, so that the drive voltage can be lowered, and it is possible to reduce the power consumption and the breakdown voltage of the element.

The selection circuit 83 shown in FIG. 16 has a NOR gate 79.8 immediately before the analog switch 8 (9).
0 and NAND gates 81 and 82 are arranged, but as another replacement means, a NAN is provided immediately after the shift register 11 as in the selection circuit 101 shown in FIG.
A configuration in which the D gates 91 and 92 are arranged is also conceivable.

In this structure, the NAND gates 91 and 92 are
The shift pulse from the shift register 11 is input to one of the input terminals, and the field switching signals FR ₁ and FR ₂ are input to the other input terminals of the NAND gates 91 and 92, respectively. Then, in the subsequent stage of the NAND gates 91 and 92, the CMOS transistors 100 and 10 are provided by the inverters 93 to 99 that branch in the middle.
It is designed to control 0.

In addition, like the selection circuit 103 (replacement means) shown in FIG. 18, the shift register 11'.1 of another system is used.
1'may be provided. In this configuration, NA
Inverter 102.1 instead of ND gate 91.92
02 is provided so that the timing signal or the start pulse is not input to the shift register 11 'on the side of the data signal line SL which is separated by the analog switch 8 (9), the field switching signals FR ₁ and FR ₂ are unnecessary. become.

The image display device of this embodiment also requires a display position adjusting circuit to adjust the display position for each field.

[Third Embodiment] The third embodiment of the present invention will be described below with reference to FIG. The constituent elements of this embodiment that have the same functions as those of the constituent elements of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 19, the image display device according to the present embodiment has a pixel array 1 and a scanning signal line drive circuit 2.
, Data signal line drive circuits 3 and 4, and power supply switching circuit 11
1 and.

The data signal line drive circuits 3 and 4 are supplied with power supply voltages V _CC1 and V _EE1 via the power supply switching circuit 111.
And the power supply voltage V _CC2 · V _EE2 . Further, the data signal line drive circuits 3 and 4 are composed of thin film transistors (see FIG. 11) formed on an insulating substrate (glass substrate). The data signal line drive circuits 3 and 4 may be of the panel sample hold method, the driver sample hold method, or the digital driver method described above.

The power supply switching circuit 111 receives a power supply voltage V _{CC1 according} to an external signal (not shown) that switches for each field.
-V _EE1 and power supply voltages V _CC2 and V _EE2 are alternately switched and output. In addition, the power supply switching circuit 11
1 is incorporated in an image display module in which the pixel array 1 and a drive circuit are integrally formed on the same substrate. As a result, the number of signal lines and power lines input to the module is reduced, so that the interface can be simplified and the system can be downsized. Of course, the power supply switching circuit 11
Even if 1 is provided outside the above module, the original function of the image display device is not impaired.

When displaying with the above configuration, for example,
In a display field, a data signal line SL _i
Is connected to the data signal line drive circuit 3 to write positive polarity data, and the adjacent data signal line SL _{i + 1} is connected to the data signal line drive circuit 4 to write negative polarity data. Then, in the next display field, when the power supply voltage of the data signal line drive circuits 3 and 4 is switched by the power supply switching circuit 111, the levels of the timing signal and the video signal are also switched accordingly. This allows
Data having a polarity opposite to that of the previous field is written in each of the data signal lines SL _i and SL _{i + 1} .

In this embodiment, the "frame + source line inversion" drive is basically adopted, and therefore, as in the first embodiment, two data signal line drive circuits 3 having different power supply voltage levels. 4, it is possible to supply data of respective polarities to the data signal lines SL _i, SL _{i + 1} .... As a result, the output voltage range of the data signal line drive circuits 3 and 4 is reduced, and it is possible to reduce the power consumption and the breakdown voltage of the element.

Further, since the data signal line drive circuits 3 and 4 in this embodiment are constituted by the thin film transistors formed on the insulating substrate, there is no capacitance to the substrate and the load is small. In a general IC, a parasitic capacitance is present between the substrate and the wiring electrode, and when the ground potential is changed when the power supply voltage is switched, a large current flows instantaneously due to the parasitic capacitance,
It is a heavy burden on the switching operation. Therefore, since there is no capacitance to substrate as described above, not only can the power supply voltage be switched at high speed, but also noise accompanying the power supply voltage switching can be reduced.

In this embodiment, since the connection of the data signal line SL is fixed, the display position adjusting circuit which is necessary in the first and second embodiments is unnecessary.

[Embodiment 4] The following description will discuss Embodiment 4 of the present invention with reference to FIGS. 20 and 21. The constituent elements of this embodiment that have the same functions as those of the constituent elements of the first and third embodiments are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 20, the image display device according to this embodiment includes a pixel array 1 and a scanning signal line drive circuit 2.
And the data signal line driving circuits 3 and 4 are basically the same as the configuration of the image display device in the first embodiment. However, the present image display device is different from the configuration of the first embodiment in that the data signal line drive circuit 4 is provided on the same side as the data signal line drive circuit 3 with respect to the pixel array 1. The analog switch 9 is also arranged on the data signal line drive circuit 3 side accordingly.

On the other hand, as shown in FIG. 21, the other image display apparatus according to this embodiment has a pixel array 1, a scanning signal line drive circuit 2, data signal line drive circuits 3 and 4, and a power supply switching circuit. 111, and is basically the same as the configuration of the image display device in the third embodiment. However, this image display device also differs from the configuration of the third embodiment in that the data signal line drive circuit 4 is provided on the same side as the data signal line drive circuit 3 with respect to the pixel array 1.

In both of the image display devices described above, the data signal line drive circuits 3 and 4 operating at different power supply voltages are arranged adjacent to each other, or in some cases intricately arranged. On the other hand, since the data signal line drive circuits 3 and 4 are composed of thin film transistors having no substrate or well, the above arrangement can be easily realized.

As described above, by arranging the two data signal line driving circuits 3 and 4 on the same side of the pixel array 1, the data signal line driving circuit 3 from the circuit (not shown) serving as a signal supply source. The wiring of the signal lines up to 4 can be made substantially equal, and the inconvenience that the transmission of signals to both drive circuits 3 and 4 is deviated can be eliminated. Further, in order to compensate for a signal delay when the pixel display device has a large screen and a lack of driving force of the data signal line drive circuits 3 and 4, data signals are input from both sides of the data signal lines SL _i and SL _{i + 1.} Although it is necessary, if the two data signal line drive circuits 3 and 4 are provided on the other side of the pixel array 1 in the same manner as described above, even in this case, the data signal line drive circuits 3 and 4 can be driven.

As described above, the technique for reducing the power consumption,
The technique for lowering the drive voltage has been described by way of example, but the configuration is basic, and any modification or combination of the first to fourth embodiments may be used as necessary. Absent. Further, in each of the above-mentioned embodiments, the active matrix type liquid crystal display device has been described, but the present invention is not limited to this, and can be applied to other display devices as long as it is an active matrix drive system. Other display devices include, for example, plasma displays and LEDs.
Examples include a display and an EL display.

[0124]

As described above, the image display device according to the first aspect of the invention has a plurality of pixels arranged in a matrix and displaying by active matrix driving, and a scanning signal connected to one row of the pixels. A line, a data signal line connected to the pixels in one column, a scanning signal line drive circuit for applying a scanning signal to the scanning signal line, and two systems are provided, each driven by a power supply of a different voltage level, Data for applying video signals of different polarities to the even and odd columns of the data signal line, and for inverting the polarities of the video signals applied to the even and odd columns of the data signal line every predetermined data display period A video signal from one of the data signal line drive circuits is applied to the signal line drive circuit and the data signal lines in the even columns, and the other data signal line drive is applied to the data signal lines in the odd columns. With providing the video signal from the road, and a replacement means replaces the data signal line driving circuits corresponding to the even columns and odd columns of the data signal lines for each predetermined data display period.

As a result, the potentials of the data signal lines can be maintained at the same polarity during one field period, and the image can be displayed by suppressing the charge / discharge current of the data signal lines. Further, since the data signal line drive circuit is divided and each is driven by a separate power supply, it is possible to lower the power supply voltage of each and relax the conditions for the breakdown voltage of the constituent elements. Therefore, there is an effect that the power consumption of the drive circuit can be reduced.

An image display device according to a second aspect is the image display device according to the first aspect, wherein the replacement means is commonly connected to one output stage of the data signal line drive circuit, and It has two lines of switching elements that are connected to the two data signal lines of the odd-numbered column and the even-numbered column that are paired and take in the video signal, and both switching elements are alternately turned on every predetermined data display period. Thus, the data signal line drive circuit and the data signal line are connected.

As a result, only one switching element exists between the video signal line or power supply line and the data signal line, and the impedance when the switching element is conducting becomes small. Therefore, it is possible to easily write the video signal to the data signal line.

According to a third aspect of the present invention, in the image display apparatus according to the first aspect, the replacing means is connected to one output stage of the data signal line drive circuit, and a video signal is displayed. A first switching element to be captured,
And a second switching element of two systems that supplies the video signal taken in by the first switching element to the two data signal lines, and the second switching element is alternately turned on every predetermined data display period. Thus, the data signal line drive circuit and the data signal line are connected.

As a result, after the first switching element used in the conventional configuration for capturing the video signal,
Furthermore, the function as the replacement unit can be realized only by adding the second switching element, and the increase in the area of each pixel can be suppressed to a relatively small value. Therefore, it is possible to suppress the increase in the area of the image display device as much as possible.

An image display device according to a fourth aspect is the image display device according to any one of the first to third aspects,
A part or all of the data signal line drive circuit, the replacement means, and the active elements included in the pixels are formed on a single crystal silicon thin film or a polycrystalline silicon thin film formed on an insulating substrate. .

As a result, the breakdown voltage of the active element tends to be lower than the breakdown voltage of the active element formed on the conventional semiconductor substrate, but as described above, the data signal line drive circuit can be operated at a low voltage. Since it can be driven, there is an effect that a sufficient operation margin can be secured.

An image display device according to a fifth aspect is the image display device according to the second or third aspect, in which the switching element or the first and second switching elements is an n-channel transistor connected in parallel. Since the gate has a CMOS structure including a p-channel transistor, a low-potential-side video signal passes through the n-channel transistor and a high-potential-side video signal passes through the p-channel transistor. Therefore, it is possible to reproduce the video signal in a wider range from the low potential side to the high potential side, and it is possible to reproduce a high quality image.

According to a sixth aspect of the present invention, there is provided an image display device, wherein a plurality of pixels arranged in a matrix and performing display by active matrix driving, scanning signal lines connected to the pixels in one row, and one column of the above-mentioned pixels. A data signal line connected to a pixel, a scanning signal line drive circuit for supplying a scanning signal to the scanning signal line, and two systems, each of which has a different polarity in even and odd columns of the data signal line. A data signal line drive circuit for applying a signal and inverting the polarity of a video signal applied to the even and odd columns of the data signal line for each predetermined data display period, and two systems of power supplies of different voltage levels are used for the data. Each of the signal line drive circuits is provided with a connection unit that switches and connects every predetermined data display period, and the active element included in the data signal line drive circuit and the pixel is provided. Some or all of a structure which is formed on the single crystal silicon thin film or polycrystalline silicon thin film formed on an insulating substrate.

As a result, the respective data line drive circuits are driven by different power supply systems, the power supply systems are switched for each display period, and "frame + source line inversion" drive is performed in combination. So
Each data signal line drive circuit needs to handle only the video signal of one polarity, and the drive voltage of the data signal line drive circuit can be lowered. In addition, part or all of the data signal line driver circuit and the active elements included in the pixel are formed on the single crystal silicon thin film or the polycrystalline silicon thin film formed on the insulating substrate, so that the power supply circuit The load is reduced, and the power supply can be switched quickly and easily. Therefore, there is an effect that the power consumption of the drive circuit can be reduced.

An image display device according to a seventh aspect is the image display device according to the sixth aspect, wherein the connecting means is formed on the insulating substrate, so that the connecting means and the data signal line driving circuit are connected. Since the connecting wires will be incorporated on the insulating substrate, external wiring between the connecting means and external circuits (controller, power supply, etc.) can be eliminated, and it is necessary to use dedicated wiring for connecting the connecting means and the external circuit. Disappears. Therefore, the external circuit that has been used conventionally can be diverted as it is, and it is possible to avoid complication of the manufacturing process.

The image display device described in claim 8 is the image display device according to claim 1 or 6, which is driven by a power supply voltage that gives only a video signal of one polarity to the data signal line. The drive voltage becomes the minimum necessary, and the drive voltage of the data signal line drive circuit can be reduced as in the image display device according to claim 1. Therefore, it is possible to achieve low power consumption and low breakdown voltage of the drive circuit of the image display device with a simple configuration.

An image display device according to a ninth aspect is the image display device according to the first or sixth aspect, which is provided with sampling means for sampling a video signal and transferring it to the data signal line. The video signal is sampled and directly transferred to the data signal line. As a result, it suffices to provide one system of sampling means for each data signal line, and the number of circuits for controlling the transfer gate in the subsequent stage and the sampling means can be reduced. Therefore, there is an effect that the number of parts can be reduced.

An image display device according to a tenth aspect of the present invention is the image display device according to the first or sixth aspect, wherein the data signal line drive circuit is sampled by the sampling means and the sampling means. The video signal to the data signal line is constituted by the holding means for temporarily holding the video signal and the amplifying means for amplifying the video signal held by the holding means and transferring it to the data signal line. It is possible to secure a sufficiently long writing time (approximately one horizontal scanning period). Therefore, it is possible to reduce the size of the switching element that constitutes the sampling means and to reduce the scale of the data signal line drive circuit.

The image display device according to claim 11 is the image display device according to claim 1 or 6, wherein the data signal line drive circuit includes sampling means for sampling a digital signal representing video information, and the sampling means. And a selecting means for selecting one of a plurality of discrete voltages based on the digital signal sampled by the means and transferring the selected discrete voltage to the data signal line. Therefore, many power sources are required. When performing gradation display,
As described above, since only the video signal of one polarity needs to be handled, the number of power supplies is reduced by half. Therefore, there is an effect that the scale of the power source can be reduced.

According to a twelfth aspect of the present invention, in the image display apparatus according to the first or sixth aspect, the two systems of the data signal line drive circuits are both arranged on the same side of the pixel matrix. Therefore, the signal input to the image display device can be concentrated in one place. As a result, it is possible to shorten the routing of signal lines and the like, and even when it is necessary to input the same video signal from both sides of the data signal line as the screen becomes larger, the number of pixels on the other side of the pixel matrix is 2
By providing the system data signal line drive circuit, the drive can be performed by the two system data signal line drive circuits. Therefore, there is an effect that it is possible to easily cope with a large screen.

An image display device according to a thirteenth aspect is the image display device according to the first or sixth aspect, wherein each of the pixels has a liquid crystal element. That is, this image display device is an active matrix liquid crystal display device,
The advantage of low power consumption of the liquid crystal display device can be further exerted. Therefore, it is possible to further reduce the power consumption of the liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an image display device according to first and second embodiments of the present invention.

FIG. 2 is a block diagram showing a configuration of a panel sample hold system data signal line drive circuit in the image display device of FIG.

FIG. 3 is a block diagram showing a configuration of a driver sample hold system data signal line drive circuit in the image display device of FIG. 1.

4 is a circuit diagram showing a configuration of an amplifier in the data signal line drive circuit of FIG.

5 is a block diagram showing a configuration of a digital driver type data signal line drive circuit in the image display device of FIG. 1. FIG.

6 is a block diagram showing a configuration of a digital buffer in the data signal line drive circuit of FIG.

FIG. 7 is a circuit diagram showing a configuration of a selection circuit applied to a panel sample hold method in the image display device according to the first embodiment of the present invention.

8 is a circuit diagram showing two configuration examples applied to the driver sample hold system, which are selection circuits of the same format as the selection circuit of FIG. 7. FIG.

9 is a circuit diagram showing a selection circuit of the same format as the selection circuit of FIG. 7, and showing a configuration applied to a digital driver system.

FIG. 10 is a diagram showing the configuration of another selection circuit in the image display device according to the first example of the present invention.

11 is a vertical cross-sectional view showing a structure of a thin film transistor which constitutes a switching element and a drive circuit in the image display device of FIG.

FIG. 12 is a graph showing a relationship between liquid crystal applied voltage and liquid crystal transmittance.

FIG. 13 is a circuit diagram showing a first selection circuit in the image display device according to the second embodiment of the present invention, which is a configuration example applied to the panel sample hold system.

FIG. 14 is a circuit diagram showing a configuration example of the first selection circuit applied to the driver sample hold method.

FIG. 15 is a circuit diagram showing a configuration example of the first selection circuit, which is applied to a digital driver system.

FIG. 16 is a circuit diagram showing a configuration of a second selection circuit in the image display device according to the second embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration of a third selection circuit in the image display device according to the second embodiment of the present invention.

FIG. 18 is a circuit diagram showing a configuration of a fourth selection circuit in the image display device according to the second embodiment of the present invention.

FIG. 19 is a block diagram showing a configuration of a main part of an image display device according to a third embodiment of the present invention.

FIG. 20 is a block diagram showing a configuration of a main part of an image display device according to a fourth example of the present invention.

FIG. 21 is a block diagram showing a configuration of a main part of another image display device according to a fourth embodiment of the present invention.

FIG. 22 is a block diagram showing a schematic configuration of a conventional liquid crystal display device.

23 is a block diagram showing a configuration of a pixel array and a circuit diagram showing a configuration of pixels in the liquid crystal display device of FIG.

FIG. 24 is a waveform diagram showing an applied voltage and the like of a data signal line of “frame + gate line inversion” driving in a conventional liquid crystal display device and a data signal when an opposing electrode is AC-driven by “frame + gate line inversion” driving. It is a wave form diagram which shows the applied voltage etc. of a line signal.

FIG. 25 is a waveform diagram showing applied voltages and the like of data signal lines for “frame + source line inversion” driving in a conventional liquid crystal display device.

[Explanation of Codes] 1 Pixel array 2 Scan signal line drive circuit 3.4 Data signal line drive circuit 5 Pixel 8.9 Analog switch 13 Sampling circuit (sampling means) 14/15 Sampling circuit (sampling means) 16 Amplifier (amplifying means) ) 17 sampling circuit (sampling means) 20 analog switch (selection means) 21 n-channel transistor (first switching element) 22 · 23 n-channel transistor (second switching element) 26 selection circuit (replacement means) 31 CMOS transistor (first) Switching element) 32.33 CMOS transistor (second switching element) 42 Selection circuit (replacement means) 51 Glass substrate (insulating substrate) 52 Polycrystalline silicon thin film 61.62 n-channel transistor (switching element) 67 Selection circuit (replacement means) 71/72 CMOS transistor (switching element) 83 Selection circuit (replacement means) 100 CMOS transistor (switching element) 101 Selection circuit (replacement means) 103 Selection circuit (replacement means) 111 Power supply switching circuit (connection means) ) SL _i ... data signal line GL _j ... scanning signal line C _L crystal capacitance (liquid crystal element) C _samp sampling capacitance (holding means) C _hold hold capacitor (holding _{means) V CC1 · V CC2 · V} EE1 · V EE2 supply voltage

Claims (13)

[Claims] 1. A plurality of pixels arranged in a matrix to perform display by active matrix driving, a scanning signal line connected to the pixels in one row, and a data signal line connected to the pixels in one column. A scanning signal line driving circuit for supplying a scanning signal to the scanning signal line, and two systems, each of which is driven by a power source of a different voltage level, has different polarities for even and odd columns of the data signal line. A data signal line drive circuit that applies a video signal and inverts the polarity of the video signal applied to the even and odd columns of the data signal line for each predetermined data display period, and one of the data signal lines for the even column The video signal from the data signal line drive circuit is applied, the video signal from the other data signal line drive circuit is applied to the odd numbered data signal lines, and a predetermined data signal is applied. The image display apparatus characterized by and a replacement means replaces the data signal line driving circuit corresponding to each data display period into even columns and odd columns of the data signal lines. 2. The exchanging means is commonly connected to one output stage of the data signal line driving circuit, and is also connected to two data signal lines of an odd number column and an even number column which form a pair. It has two lines of switching elements for taking in a video signal, and by connecting both switching elements alternately for every predetermined data display period, the data signal line drive circuit and the data signal line are connected. The image display device according to claim 1, wherein the image display device is a display device. 3. The exchanging means is connected to one output stage of the data signal line drive circuit, and has a first switching element for taking in a video signal and two video signals for taking in the first switching element. And a second switching element of two systems which are applied to the data signal line, and by alternately conducting the second switching element for each predetermined data display period, the data signal line drive circuit and the data signal line. The image display device according to claim 1, wherein the image display device is connected to the image display device. 4. A part or all of the data signal line drive circuit, the replacing means and the active elements included in the pixels are formed on a single crystal silicon thin film or a polycrystalline silicon thin film formed on an insulating substrate. The image display device according to any one of claims 1 to 3, characterized in that: 5. The switching element or the first and second switching elements are composed of an n-channel transistor and a p-channel transistor which are connected in parallel.
The image display device according to claim 2, wherein the image display device is a gate having a MOS structure. 6. A plurality of pixels arranged in a matrix to perform display by active matrix driving, a scanning signal line connected to the pixels in one row, and a data signal line connected to the pixels in one column. A scanning signal line driving circuit for giving a scanning signal to the scanning signal line, and two systems are provided, each of which applies a video signal of a different polarity to the even and odd columns of the data signal line and displays predetermined data. A data signal line drive circuit that inverts the polarity of the video signal applied to the even and odd columns of the data signal line for each period, and two power supplies of different voltage levels are provided to each of the data signal line drive circuits. A connection means for switching and connecting for each data display period, wherein a part or all of the active elements included in the data signal line drive circuit and the pixel are insulated from each other. The image display apparatus characterized by being formed in the single crystal silicon thin film or polycrystalline on silicon thin film formed thereon. 7. The image display device according to claim 6, wherein the connecting means is formed on the insulating substrate. 8. The data signal line drive circuit of two systems is driven by a power supply voltage which gives only a video signal of one polarity to the data signal line, respectively. Image display device. 9. The image display device according to claim 1, wherein the data signal line drive circuit includes sampling means for sampling a video signal and transferring it to the data signal line. 10. The data signal line drive circuit includes a sampling means for sampling a video signal, a holding means for temporarily holding the video signal sampled by the sampling means, and an amplification of the video signal held by the holding means. 7. The image display device according to claim 1, further comprising an amplifying unit that transfers the data to the data signal line. 11. The data signal line drive circuit selects sampling means for sampling a digital signal representing video information, and selects one of a plurality of discrete voltages based on the digital signal sampled by the sampling means. 7. The image display device according to claim 1, further comprising: a selection unit that transfers the data to the data signal line. 12. The data signal line drive circuit of two systems,
The image display device according to claim 1, wherein both are arranged on the same side of the pixel matrix. 13. The image display device according to claim 1, wherein each pixel has a liquid crystal element.