JP2001174784A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device wherein a potential fluctuation is not caused when the voltage applied to each scanning signal line is changed over from a selected scanning voltage to a non-selected scanning voltage. SOLUTION: This is a liquid crystal display device comprising plural pixels with pixel electrodes, plural scanning signal lines for applying selected scanning voltages or non-selected scanning voltages to the plural pixels, a liquid crystal display element having plural capacitance signal lines connected with the pixel electrode of each pixel via capacitance elements, and a scanning signal line driving means for sequentially supplying the selected scanning voltages to respective scanning signal lines, supplying the non-selected voltages to respective scanning signal lines when the selected scanning voltages are not supplied, and also supplying driving voltages to respective capacitance signal lines, and the scanning signal line driving means supplies a voltage to compensate for variation in potential caused on the pixel electrode of each pixel when the voltage applied to each scanning signal line is changed over to the non-selected scanning voltage from the selected scanning voltage in each capacitance signal line corresponding to each scanning signal line supplied with the non-selected voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique which is effective when applied to a scanning signal line driving means (gate driver) of a liquid crystal display device capable of displaying multiple gradations.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device having an active element (for example, a thin film transistor) for each pixel and switchingly driving the active element is widely used as a display device of a notebook type personal computer or the like. This active matrix type liquid crystal display device applies a video signal voltage (a gray scale voltage corresponding to display data; hereinafter, referred to as a gray scale voltage) to a pixel electrode via an active element. There is no need to use a special driving method for preventing crosstalk unlike a simple matrix type liquid crystal display device, and multi-tone display is possible. TF is one of the active matrix type liquid crystal display devices.
T (T hin F ilm T ransister ) mode liquid crystal display panel of (T
2. Description of the Related Art A TFT-type liquid crystal display module including an FT-LCD, a drain driver and a gate driver arranged in a peripheral portion of a liquid crystal display panel, and an interface unit for driving the drain driver and the gate driver is known. I have. Incidentally, such a technique is disclosed in, for example, Japanese Patent Application No. Hei.
No.-86668.

[0003]

Generally, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, and as a result, an afterimage phenomenon is caused and the life of the liquid crystal layer is reduced. Will be reduced. In order to prevent this, in the liquid crystal display module, the voltage applied to the liquid crystal layer is converted into an alternating voltage every certain time, that is, based on the voltage applied to the common electrode, the voltage applied to the pixel electrode is The voltage is changed to the positive voltage side / negative voltage side at regular intervals. On the other hand, in a TFT type liquid crystal display panel,
Due to the parasitic capacitance between the pixel electrode and the gate signal line, the potential of the pixel electrode fluctuates when an active element (for example, a thin film transistor) provided for each pixel is turned off (hereinafter, simply referred to as jump-in). .). When the potential of the pixel electrode is biased to either the positive polarity or the negative polarity due to the jump, the voltage applied to the liquid crystal layer when the polarity is positive and the voltage applied to the liquid crystal layer when the polarity is negative. Unlike the above, there is a problem that a color shift of a displayed image occurs and, as a result, a DC voltage is applied to the liquid crystal layer. In the worst case, the liquid crystal layer is burned. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a liquid crystal display device in which a voltage applied to each scanning signal line is different from a selected scanning voltage. It is an object of the present invention to provide a technique capable of preventing a potential change from occurring in a pixel electrode of each pixel when the voltage changes to a selective scanning voltage. Another object of the present invention is to
It is an object of the present invention to provide a liquid crystal display device capable of supplying a grayscale voltage having a small maximum amplitude level and a low voltage level to a pixel electrode of each pixel. The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention provides a method for connecting a plurality of pixels having pixel electrodes, a plurality of scanning signal lines for applying a selection scanning voltage or a non-selection voltage to the plurality of pixels, and a pixel electrode of each pixel via a capacitor. In a liquid crystal display device having a liquid crystal display element having a plurality of capacitance signal lines, a non-selection scanning voltage is applied to each capacitance signal line corresponding to each scanning signal line to which each scanning signal line is supplied. A drive voltage that compensates for potential fluctuations that occur at the pixel electrode of each pixel when the voltage changes from the selected scan voltage to the non-selective scan voltage, or a voltage applied to the pixel electrode of each pixel and a drive voltage applied to the counter electrode And a driving voltage for increasing a potential difference between the driving voltage and the driving voltage. According to the means,
When the voltage applied to each scanning signal line changes from the selection scanning voltage to the non-selection scanning voltage, the parasitic capacitance between the pixel electrode of each pixel and the scanning signal line causes the potential fluctuation occurring at the pixel electrode of each pixel. It is possible to offset. According to the above means, the potential difference between the voltage applied to the pixel electrode of each pixel and the drive voltage applied to the counter electrode can be increased, so that the grayscale voltage supplied to the pixel electrode of each pixel can be increased. The voltage level can be reduced.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. First Embodiment <Basic Configuration of Liquid Crystal Display Module of First Embodiment of the Present Invention> FIG. 1 is a block diagram showing a basic configuration of a TFT type liquid crystal display module of the present embodiment. As shown in FIG. 1, the liquid crystal display module according to the present embodiment includes a liquid crystal display panel 10, a display control device 110, a power supply circuit 12
0, a drain driver section 130, and a gate driver section 140. The liquid crystal display panel 10 includes a TFT substrate on which a pixel electrode, a thin film transistor, and the like are formed;
A filter substrate on which a counter electrode, a color filter, and the like are formed is overlapped with a predetermined gap therebetween, and the two substrates are bonded together with a sealing material provided in a frame shape near a peripheral portion between the two substrates. Liquid crystal is sealed and sealed inside a seal material between the two substrates from a liquid crystal sealing opening provided in a part of the material, and further, a polarizing plate is stuck outside the two substrates.
The drain driver section 130 is composed of a plurality of drain drivers each composed of a semiconductor integrated circuit device (IC). Similarly, the gate driver section 140 is composed of a plurality of gates each composed of a semiconductor integrated circuit device (IC). Consists of a driver. The plurality of drain drivers and gate drivers are mounted on a glass substrate of a TFT substrate.

<Structure of Liquid Crystal Display Panel and Gate Driver of the Present Embodiment> FIG. 2 is a diagram showing an equivalent circuit of the liquid crystal display panel 10 of the present embodiment. FIG. 3 also shows the configuration of the capacitance signal line drive circuit section of the gate driver 40 according to the present embodiment. As shown in FIG. 2, the liquid crystal display panel 10 according to the embodiment of the present application has a plurality of pixels formed in a matrix. Although FIG. 2 shows only three pixels, they are actually arranged in a matrix as described above. Each pixel includes two adjacent signal lines (a drain signal line (D) or a gate signal line (G)) and two adjacent signal lines (a gate signal line (G) or a drain signal line (D)). And is arranged in the intersection area with. Each pixel has a thin film transistor (TFT), and a source electrode of the thin film transistor (TFT) of each pixel is connected to the pixel electrode (ITO1). Since a liquid crystal layer is provided between the pixel electrode (ITO1) and the common electrode (ITO2), a liquid crystal capacitance (CLC) is equivalently provided between the pixel electrode (ITO1) and the common electrode (ITO2). Connected. Further, a source electrode of a thin film transistor (TFT), a capacitance signal line (STG) and a source electrode (I
TO1), a storage capacitor (CSTG) is formed.
Note that FIG. 2 shows an equivalent circuit of a vertical electric field type liquid crystal display panel. In FIG. 2, AR is a display area.

In the liquid crystal display panel 10 of the present embodiment, the thin film transistor (T) of each pixel arranged in the column direction
FT) are connected to drain signal lines (D), respectively, and each drain signal line (D) is connected to a corresponding drain of the drain driver unit 130 that applies a gradation voltage to the liquid crystal layer of each pixel in the column direction. Connected to driver.
The gate electrodes of the thin film transistors (TFTs) in the pixels arranged in the row direction are connected to gate signal lines (G), respectively. Each gate signal line (G) is connected to each pixel in the row direction for one horizontal scanning time. Thin film transistor (TFT)
The scanning drive voltage (High level (hereinafter, referred to as “high level”)
Simply referred to as H level. ) Selection scan voltage and Lo
It is connected to a gate driver 40 that supplies a w-level (hereinafter, simply referred to as L level) non-selective scanning voltage. In the present embodiment, the capacitance signal line (STG) is also connected to the gate driver 40.

<Outline of Operation of Liquid Crystal Display Module of Present Embodiment> The display control device 110 is composed of one semiconductor integrated circuit (LSI), and receives a clock signal, a display timing signal, and a horizontal signal transmitted from the computer body. The drain driver and the gate driver of the drain driver unit 130 and the gate driver unit 140 are controlled based on the display control signals of the synchronization signal and the vertical synchronization signal and the display data (RGB). Drive. The gate driver 40 sequentially supplies the gate signal lines (G) of the liquid crystal display panel 10 for each horizontal scanning time based on the frame start instruction signal (FLM) and the shift clock (CL3) sent from the display control device 110. An H level selective scanning voltage is supplied. Thereby, a plurality of thin film transistors (TFTs) connected to each gate signal line (G) of the liquid crystal display panel 10 conduct for one horizontal scanning time. The drain driver includes a start pulse (display data capture start signal) transmitted from the display control device 110,
The display data sent from the display control device 110 is sequentially latched based on the display data latch clock (CL2). Further, the drain driver supplies a gray scale voltage corresponding to the latched display data to each drain signal line (D) based on the output timing control clock (CL1) sent from the display control device 110. By the above operation, an image is displayed on the liquid crystal display panel 10. The power supply circuit 120 shown in FIG. 1 supplies a gray scale reference voltage of positive polarity and a gray scale reference voltage of negative polarity to each drain driver, and applies the same to a gate driver 40 to a gate electrode of a thin film transistor (TFT). Scan driving voltage to be supplied.

<Method of AC Drive of Liquid Crystal Display Module shown in FIG. 1> Generally, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed.
As a result, an afterimage phenomenon is caused, and the life of the liquid crystal layer is shortened. In order to prevent this, in the liquid crystal display module, the voltage applied to the liquid crystal layer is converted into an alternating voltage at certain time intervals, that is, the pixel electrode (ITO1) is turned on based on the voltage applied to the common electrode (ITO2). Is changed to the positive voltage side / negative voltage side at regular time intervals. As a driving method for applying an AC voltage to the liquid crystal layer, two methods, a common symmetry method and a common inversion method, are known. The common symmetry method is a method in which the voltage applied to the common electrode is fixed, and the voltage applied to the pixel electrode (ITO1) is alternately positive (hereinafter, referred to as the voltage) applied to the common electrode (ITO2). This is a method of inverting the case to a positive polarity and negative (hereinafter, this case is referred to as a negative polarity). In this common symmetric method, a dot inversion method or an N-line inversion method, which is excellent in terms of low power consumption and display quality, can be used.

In the N-line inversion method, the voltage applied to the pixel electrode (ITO1) is alternately positive or negative for every N lines (for example, one line). Therefore, in the N-line inversion method, the voltage of the pixel electrode (ITO1) in one line is all positive or negative. In the dot inversion method, an odd-numbered drain signal line (D) (ie, an odd-numbered drain signal line (D))
A negative gradation voltage is supplied to the odd-numbered pixel electrode (ITO1), and a positive gradation voltage is supplied to the even-numbered drain signal line (D) (that is, the even-numbered pixel electrode (ITO1)). Further, in the even line of the odd frame,
A positive gradation voltage is supplied to the odd-numbered drain signal lines (D), and a negative gradation voltage is supplied to the even-numbered drain signal lines (D). The polarity of each line is inverted for each frame. That is, in the odd lines of the even frames, the gray scale voltage of the positive polarity is applied to the odd drain signal lines (D), and the even drain signal lines ( D) is supplied with a negative gradation voltage. Further, in the even-numbered lines of the even-numbered frame, a negative gradation voltage is applied to the odd-numbered drain signal lines (D), and the even-numbered drain signal lines (D)
Is supplied with a positive gradation voltage. The present invention is applicable to both the dot inversion method and the N-line inversion method.

<Equivalent circuit for one pixel of the liquid crystal display panel shown in FIG. 1> FIG. 3 shows a liquid crystal display panel 10 of the present embodiment.
3 is a diagram showing an equivalent circuit for one pixel of FIG. In fact,
Although the capacitance signal line (STG) is provided in parallel with the gate signal line (G), for convenience of explanation, FIG. 3 shows that the capacitance signal line (STG) is orthogonal to the gate signal line (G). Is shown. FIG. 4 is a time chart for explaining a potential change of the pixel electrode (ITO1) in the conventional liquid crystal display module and the liquid crystal display module of each embodiment of the present invention. Hereinafter, a conventional liquid crystal will be described as an example of a case where a one-frame inversion method in which a voltage applied to a pixel electrode (ITO1) is changed to a positive polarity and a negative polarity for each frame is applied as an alternating drive method. The pixel electrode (I) in the display module and the liquid crystal display module of the present embodiment.
The potential fluctuation of TO1) will be described. In a conventional liquid crystal display module, a common electrode (IT) is connected to a capacitance signal line (STG).
The voltage of the fixed potential Vcom applied to O2) is applied. In the conventional liquid crystal display module at the time of writing the positive gradation voltage, when the scanning signal voltage supplied to the gate signal line (G) becomes the H level selective scanning voltage, the thin film transistor (TFT) is turned on, and the pixel electrode is turned on. (I
The voltage of TO1) is the gradation voltage (VDh in FIG. 4) supplied from the drain signal line (D). Further, when the scanning signal voltage supplied to the gate signal line (G) becomes a non-selective scanning voltage of L level, the thin film transistor (TFT) is turned off, and the pixel electrode (ITO1) enters a floating state. However, at this time, the parasitic capacitance (Cgl) between the pixel electrode (ITO1) and the gate signal line (G) causes the scanning signal voltage H supplied to the gate signal line (G) to be high.
Following the change from the level to the L level, the pixel electrode (I
The voltage of the pixel electrode (ITO1) is lower than the gradation voltage (VDh in FIG. 4) supplied from the drain signal line (D). Becomes

Similarly, at the time of writing the negative gradation voltage, the scanning signal voltage supplied to the gate signal line (G) becomes H level.
When the level is selected, the pixel electrode (ITO1)
Becomes the gradation voltage (VDl in FIG. 4) supplied from the drain signal line (D), but when the scanning signal voltage supplied to the gate signal line (G) becomes the L-level non-selective scanning voltage. Due to the jump, the voltage of the pixel electrode (ITO1) becomes lower than the gradation voltage (VD1 in FIG. 4) supplied from the drain signal line (D). In FIG. 4, the voltage of the pixel electrode (ITO1) when the selection scanning voltage is supplied to the gate signal line (G) and the pixel electrode when the non-selection scanning voltage is supplied to the gate signal line (G). The potential difference from the voltage of (ITO1) is represented by VG. When displaying the same image on the liquid crystal display panel 10 within at least two frame periods,
The potential difference between the positive gradation voltage and the voltage of Vcom applied to the common electrode (ITO2), the negative gradation voltage and Vco applied to the common electrode (ITO2)
The potential difference from the voltage of m must be the same.

However, as shown in FIG. 4, when the selection scanning voltage is supplied to the gate signal line (G), the voltage of the pixel electrode (ITO1) and the non-selection scanning voltage are supplied to the gate signal line (G). When a potential difference of VG occurs between the voltage of the pixel electrode (ITO1) and the voltage of Vcom applied to the common electrode (ITO2), a potential difference of VG is generated between the pixel voltage and the voltage of the pixel electrode (ITO1). The potential difference between the negative gradation voltage and the voltage of Vcom applied to the common electrode (ITO2) is not the same. Therefore, the pixel electrode (IT
The potential of O1) is biased toward either the positive polarity or the negative polarity. As a result, a DC voltage is applied to the liquid crystal layer, and the color displayed on the liquid crystal display panel 10 is changed as described above. In the worst case, there is a problem that the liquid crystal layer is burned.

Also in this embodiment, as shown in FIG. 2, an H level selective scanning voltage is sequentially supplied from the shift register circuit (S / R) in the gate driver 40 to the gate signal line (G). However, in the present embodiment, when the H-level selection scanning voltage is supplied to the gate signal line (G), the NMOS transistor (hereinafter simply referred to as NMOS) (NM11) is turned on, and the capacitance signal is output. Line (S
When a voltage of Vsl is supplied to TG) and a non-selective scanning voltage of L level is supplied to the gate signal line (G), a PMOS transistor (hereinafter simply referred to as PMOS) (PM11). Is turned on, and the capacitance signal line (S
TG) is supplied with the voltage Vsh. Here, the voltage of Vsl is Vcom applied to the common electrode (ITO2).
And the potential difference between the voltage Vsh and the voltage Vsl is the same as the voltage VG. In this embodiment mode, the capacitance signal line (ST) is controlled by the storage capacitor (CSTG).
The potential of the pixel electrode (ITO1) can be increased following the change from the voltage Vsl supplied to G) to the voltage Vsh. Therefore, in the present embodiment, FIG.
As shown in Example 1, the voltage of the pixel electrode (ITO1) when the selection scanning voltage is supplied to the gate signal line (G) and the case where the non-selection scanning voltage is supplied to the gate signal line (G) Can be made equal to the voltage of the pixel electrode (ITO1), and a color shift occurs in the display image of the liquid crystal display panel 10 as in a conventional liquid crystal display module. Can be prevented from occurring. In the above description, the case where the one-frame inversion method is applied has been described. However, it is needless to say that the one-frame inversion method is also applicable. Also, Vs is applied from the gate driver 140 to the capacitance signal line (STG).
Although the voltages of 1 and Vsh are supplied, the present invention is not limited to this, and a dedicated circuit for supplying the voltages of Vsl and Vsh to the capacitance signal line (STG) may be provided.

Embodiment 2 <Characteristic Configuration of Liquid Crystal Display Module of Embodiment of the Present Invention> A liquid crystal display module of the present embodiment has a positive polarity floor as shown in Embodiment 2 of FIG. When writing the adjustment voltage,
When an L-level selection scanning voltage is supplied to the gate signal line (G), Vshh (Vshh> Vsh) higher than the voltage of Vsh is supplied to the capacitance signal line (STG), and a negative polarity is supplied. At the time of writing the gradation voltage, when an L-level selection scanning voltage is supplied to the gate signal line (G),
A lower potential V is applied to the capacitance signal line (STG) than the voltage Vsl.
sll (Vsll <Vsl). This allows
In this embodiment, the storage capacitor (CSTG) changes the voltage of Vsll supplied to the capacitance signal line (STG) to Vs
Following the change to the voltage of hh, the pixel electrode (ITO1)
Can be shifted to a higher potential side than in the case of the first embodiment. Similarly, the capacitance signal line (S
The potential of the pixel electrode (ITO1) can be further shifted to a lower potential side following the change from the voltage Vshh supplied to the TG) to the voltage Vsll.

Therefore, in the present embodiment, the positive VDh gradation voltage supplied to the drain signal line (D) and the negative VDl supplied to the drain signal line (D)
Is applied to the pixel electrode (ITO).
1) and the pixel electrode (ITO)
1) and the potential difference (VD
It can be smaller than D). As described above, in the present embodiment, since the voltage level of each grayscale voltage supplied to the drain signal line (D) can be reduced, a low-voltage transistor element using a low-voltage transistor element is used as a drive circuit in the drain driver. Withstand voltage drive circuit can be used,
It becomes possible to use a thin film transistor (TFT) having a low withstand voltage. Thus, power consumption can be reduced. Further, the VG voltage described in the first embodiment can be reduced.

FIG. 5 shows the gate driver 4 of the present embodiment.
FIG. 3 is a circuit diagram illustrating a capacitance signal drive circuit of 0. FIG. 6 shows each gate signal line (G) by the capacitance line driving circuit shown in FIG.
FIG. 4 is a waveform diagram showing a voltage waveform supplied to a capacitor signal line (STG). Hereinafter, the gate driver 40 shown in FIG.
The operation of the capacitance signal drive circuit of FIG. As shown in the figure, odd-numbered capacitance signal lines (STG1, STG
3) NMO via inverters (IV1, IV2)
S (NM23), so before starting display,
The reset signal (RST) becomes H level and the NMOS
When (NM23) is turned on, a drive voltage of Vsll is supplied to the odd-numbered capacitance signal lines (STG1, STG3). Therefore, the PMOS (PM21) is turned on,
The NMOS (NM21) turns off. In this case, since the gate signal line (G1) is supplied with the L-level non-selective scanning voltage, the PMOS (PM22) connected in series with the PMOS (PM21) and the NMOS (NM)
The NMOS (NM22) connected in series with 21) is off.

Now, when the selection scanning voltage at the H level is supplied to the gate signal line (G1), both the PMOS (PM22) and the NMOS (NM22) are turned on, whereby the node (N1) is connected to the Vshhh. Voltage. When the L-level non-selection scanning voltage is supplied to the gate signal line (G1) again, the PMOS (PM22) and the NM
Since both the OS (NM22) is turned off and the transfer gate circuit (TG) is turned on, the voltage of the node (N1) Vshh is applied to the inverter (IV1), so that the capacitance signal line (STG1) Has Vsh
h drive voltage is supplied. Thereby, the PMOS (P
M21) is turned off, and the NMOS (NM21) is turned on.
When one frame is completed, the next frame is started. When the H level selective scanning voltage is supplied to the gate signal line (G1) again, the node (N1) is set to the voltage of Vsll. Then, the capacitance signal line (STG1)
A driving voltage of Vsll is supplied. Thus, the odd-numbered capacitance signal lines (STG1, STG3) are alternately
Drive voltages of Vshh and Vsll are applied.

The even-numbered capacitance signal line (STG2) is connected to the NMOS (NM23) via the inverter (IV2), so that the reset signal (RS
T) goes high and the NMOS (NM23) turns on, the even-numbered capacitance signal line (STG2)
Shh drive voltage is supplied. Therefore, the PMOS
(PM21) is turned off, and the NMOS (NM21) is turned on. Now, when an H level selection scanning voltage is supplied to the gate signal line (G2), the PMOS (PM22) and the NMOS (PM22)
(NM22) are both turned on, so that the voltage of the node (N1) becomes Vsll. When the L-level non-selection scanning voltage is supplied to the gate signal line (G2) again, the PMOS (PM22) and the NMOS (NM2)
2) are both turned off and the transfer gate circuit (TG) is turned on, so that the inverter (IV1)
Is applied with the voltage of Vsll at the node (N1), so that the driving signal of Vsll is supplied to the capacitance signal line (STG2). Thereby, the PMOS (PM21) is turned on and the NMOS (NM21) is turned off. When one frame is completed, the next frame is started, and when the H level selective scanning voltage is supplied to the gate signal line (G1) again,
Since the node (N1) is set at the voltage of Vshh, the drive signal of Vshh is supplied to the capacitance signal line (STG2) in the next frame. As described above, the drive voltages of Vsll and Vshh are alternately applied to the even-numbered capacitance signal lines (STG2).

FIG. 7 is a circuit diagram showing an equivalent circuit of the liquid crystal display panel when the one-line inversion method is employed as the AC driving method in the liquid crystal display module of the present embodiment. FIG. 8 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel in a case where a dot inversion method is employed as an AC driving method in the liquid crystal display module of the present embodiment. As shown in FIG. 8, when the dot inversion method is adopted as the AC driving method, the odd-numbered storage capacitors (C
STG1, CSTG3, and CSTG5) are connected to the next-stage capacitance signal line (STG), and the even-numbered storage capacitors (CSTG) are connected.
2, CSTG4, CSTG6) to the capacitance signal line (S
TG). As described above, the drive voltage supplied to the adjacent capacitance signal line (STG) is Vsh
h or Vsll, it can be driven by the dot inversion method. However, unlike the timing chart shown in FIG. 4, the storage capacitors (CSTG1, CSTG3, CTG
STG5) shifts the potential of the pixel electrode (ITO1) connected to the next-stage capacitance signal line to the high potential side or the low potential side at the timing when the next-stage gate signal line (G)
This is when the H-level selected scanning voltage changes to the L-level non-selected scanning voltage.

As described above, in this embodiment, since the voltage level of each gray scale voltage supplied to the drain signal line (D) can be reduced, a low breakdown voltage transistor element is used as a drive circuit in the drain driver. Can be used, and a thin film transistor (TFT) having a low withstand voltage can be used. Accordingly, the present invention is not limited to a polysilicon type liquid crystal display module in which a thin film transistor (TFT) is formed by a polysilicon element, or a horizontal scanning circuit 230 and a vertical scanning circuit as shown in FIG. 240 is effective for a polysilicon type liquid crystal display module with a built-in peripheral circuit manufactured by a low-temperature polysilicon element on a TFT substrate.

Further, the present invention is also effective for an IPS type liquid crystal display module (a horizontal electric field type liquid crystal display module). FIG. 12 is a graph showing a voltage level of a gray scale voltage supplied from a drain driver to a drain signal line (D) in a conventional IPS mode liquid crystal display module, and FIG. 13 is a conventional IPS mode liquid crystal display module. 6 is a graph showing a voltage level of a gradation voltage of a pixel electrode (PX) in a module. As shown in FIG.
In the PS type liquid crystal display module, the pixel electrode (PX)
The difference between the maximum voltage level of the positive-polarity gray scale voltage and the maximum voltage level of the negative-polarity gray scale voltage (hereinafter, simply referred to as the maximum amplitude level) is as large as 15 V, as shown in FIG. The grayscale voltage having the maximum amplitude level is supplied from the drain driver to the drain signal line (D). As described above, in the case of the IPS mode liquid crystal display module, since the liquid crystal driving voltage is high, it is necessary to use a high voltage driving circuit and a high withstand voltage thin film transistor (TFT).

FIG. 10 is a graph showing the voltage level of the gray scale voltage supplied from the drain driver to the drain signal line (D) when the present invention is applied to the IPS mode liquid crystal display module. 4 is a graph showing a voltage level of a gradation voltage of a pixel electrode (PX) in an IPS type liquid crystal display module to which the present invention is applied.
In the present embodiment, the storage capacitor (Cstg) reduces the voltage of Vsll supplied to the capacitance signal line (STG) to Vs
The potential of the pixel electrode (PX) can be shifted to the higher potential side following the change to the voltage of hh, and similarly, the voltage of Vshh supplied to the capacitance signal line (STG) is changed to Vs
The potential of the pixel electrode (PX) can be shifted to a lower potential side following the change to the voltage of ll. Therefore, when the present invention is applied to the IPS mode liquid crystal display module, as shown in FIG. 10, the drain driver is connected to the drain signal line (D) as compared with the conventional IPS mode liquid crystal display module. A grayscale voltage having a small maximum amplitude level and a low voltage level is supplied, and the potential of the pixel electrode (PX) is changed according to a change in the drive voltage supplied to the capacitance signal line (STG). As in a conventional IPS type liquid crystal display module, it is possible to shift to a gradation voltage having a large maximum amplitude level. As described above, when the present invention is applied to the IPS mode liquid crystal display module, it is not necessary to use a high-voltage driving circuit and a high-breakdown-voltage thin film transistor (TFT) unlike the related art, and the low-voltage driving is not required. A circuit and a thin-film transistor (TFT) having a low withstand voltage can be used.

FIG. 14 is a diagram showing an equivalent circuit of a liquid crystal display panel of an IPS type liquid crystal display module to which the present invention is applied. As shown in FIG.
In the liquid crystal display panel of the PS type liquid crystal display module,
In addition to a counter electrode signal line (CL) for applying a drive voltage (Vcom) to the counter electrode (CT), a capacitance signal line (S
TG) is provided. FIG. 15 is a diagram showing the configuration of each electrode of the liquid crystal display panel shown in FIG. 14, and FIG.
FIG. 3 is a cross-sectional view showing a cross-sectional structure along the line AB shown in FIG.
In the liquid crystal display panel shown in FIGS. 15 and 16, a counter electrode (CT) and a counter electrode (C) are provided on the TFT substrate (SUB1) side.
A counter electrode signal line (CL) for applying a drive voltage (Vcom) to T) is provided. Also, the counter electrode (CT)
A pixel electrode (PX) for applying an electric field substantially parallel to the TFT substrate (SUB1) to the liquid crystal layer (LC) between the TFT substrate (SUB1) and the thin film transistor (TFT) formed in the lowermost layer through the through hole (SH1). Connected to source area (SD1). The drain region of the thin film transistor (TFT) is connected to a drain signal line (D) via a through hole (SH2). Therefore, a liquid crystal capacitance (Cpix) is equivalently connected between the pixel electrode (PX) and the counter electrode (CT). In FIG. 16, SUB2 is a filter substrate, and GRAS is a glass substrate of a TFT substrate (SUB1).

Here, the drain signal line (D) is connected to the counter electrode (CT) (or
The counter electrode signal line (CL) or the pixel electrode (P
X)) is formed in a layer below the layer in which is formed. Also,
Drain signal line (D) via interlayer insulating film (SZ2)
The capacitance signal line (S
TG) has a protrusion (STGa) extending below the pixel electrode (PX), and further has a thin film transistor (TF).
The source region (SD1) of T) also has a protruding portion (SD1a) extending below the pixel electrode (PX). here,
The protrusion (STGa) of the pixel electrode (PX) and the protrusion (S1) of the source region (SD1) of the thin film transistor (TFT).
D1a), an interlayer insulating film (SZ3) is provided. Thereby, the projection (STG) of the pixel electrode (PX)
a) and the pixel electrode (PX), and a storage capacitor (Cstg) formed between the protrusion (STGa) of the pixel electrode (PX) and the protrusion (SD1a) of the source region (SD1) of the thin film transistor (TFT). Is done. As described above, the invention made by the inventor has been specifically described based on the embodiment of the present invention. However, the present invention is not limited to the embodiment of the invention, and does not depart from the gist of the invention. It goes without saying that various changes can be made in.

[0027]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the liquid crystal display device of the present invention, when the voltage applied to each scanning signal line changes from the selected scanning voltage to the non-selected scanning voltage, it is possible to prevent a potential change from occurring in the pixel electrode of each pixel. Becomes possible. (2) According to the liquid crystal display device of the present invention, a grayscale voltage having a small maximum amplitude level and a low voltage level is
It can be supplied to the pixel electrode of each pixel.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a TFT-type liquid crystal display module according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the liquid crystal display panel according to Embodiment 1 of the present invention.

FIG. 3 is a diagram illustrating an equivalent circuit for one pixel of the liquid crystal display panel according to Embodiment 1 of the present invention.

FIG. 4 shows a pixel electrode (ITO) in a conventional liquid crystal display module and the liquid crystal display module of each embodiment of the present invention.
5 is a time chart for explaining the potential fluctuation of 1).

FIG. 5 is a circuit diagram showing a capacitance signal drive circuit of a gate driver according to a second embodiment of the present invention.

6 is a waveform diagram showing a voltage waveform supplied to each gate signal line (G) and capacitance signal line (STG) by the capacitance line drive circuit shown in FIG.

FIG. 7 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel in a case where a one-line inversion method is employed as an AC driving method in the liquid crystal display module according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram showing an equivalent circuit of a liquid crystal display panel in a case where a dot inversion method is employed as an AC driving method in the liquid crystal display module according to the second embodiment of the present invention.

FIG. 9 is a diagram showing an equivalent circuit of a liquid crystal display panel when the present invention is applied to a polysilicon type liquid crystal display module with a built-in peripheral circuit.

FIG. 10 is a graph showing a voltage level of a gray scale voltage supplied from a drain driver to a drain signal line (D) when the present invention is applied to an IPS type liquid crystal display module.

FIG. 11 is a graph showing a voltage level of a gradation voltage of a pixel electrode (PX) in a case where the present invention is applied to an IPS mode liquid crystal display module.

FIG. 12 is a graph showing a voltage level of a gray scale voltage supplied to a drain signal line (D) from a drain driver in a conventional IPS mode liquid crystal display module.

FIG. 13 is a graph showing a voltage level of a gradation voltage of a pixel electrode (PX) in a conventional IPS mode liquid crystal display module.

FIG. 14 is a diagram showing an equivalent circuit of a liquid crystal display panel of an IPS type liquid crystal display module to which the present invention is applied.

15 is a diagram showing the configuration of each electrode of the liquid crystal display panel shown in FIG.

16 is a cross-sectional view showing a cross-sectional structure taken along line AB shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display panel (TFT-LCD), 40 ... Gate driver, 110 ... Display control device, 120 ... Power supply circuit, 130 ... Drain driver part, 140 ... Gate driver part, 230 ... Horizontal scanning circuit, 240 ... Vertical scanning circuit , D: drain signal line (video signal line or vertical signal line), G: gate signal line (scanning signal line or horizontal signal line), ITO1, PX: pixel electrode, ITO2: common electrode, CT: counter electrode, CL: Counter electrode signal line, STG ...
Capacitance signal line, STGa: Projection formed on capacitance signal line (STG), LC: Liquid crystal layer, TFT: Thin film transistor, CLC, Cpix: Liquid crystal capacitance, CSTG: Storage capacitance,
Cstg: storage capacitance, PM: PMOS transistor, N
M: NMOS transistor, TG: transfer gate circuit, IV: inverter, SUB1: TFT substrate, SU
B2: Filter substrate, GRAS: Glass substrate, SD1 ...
Source region, SD1a: Projection formed in source region (SD1), AR: Display region, SH: Through hole, S
Z: interlayer insulating film; Cgl: parasitic capacitance.

Continued on the front page F term (reference) 2H093 NA16 NA79 NC13 NC16 NC18 NC23 NC26 NC34 NC67 ND07 ND33 ND58 NE03 NF05 5C006 AA16 AA22 AC27 AC28 AF42 AF44 AF50 BB16 BC03 BC06 BC12 BF03 BF04 BF15 BF42 FA26 FA34 FA37 FA05 DDC EE29 EE30 FF03 FF11 JJ02 JJ04 JJ05 JJ06 5C094 AA03 AA05 AA55 BA03 BA43 CA19 CA25 EA03 EA04 EA07 EA10 GA10

Claims (5)

[Claims] 1. A liquid crystal display element comprising: two substrates disposed to face each other; and a liquid crystal layer sandwiched between the two substrates; a plurality of pixels having pixel electrodes; A plurality of scanning signal lines for applying a selection scanning voltage or a non-selection signal voltage to a pixel; and a liquid crystal display element having a plurality of capacitance signal lines connected to a pixel electrode of each pixel via a capacitance element; A scanning signal line driving unit that sequentially supplies a selection scanning voltage to each scanning signal line, and supplies a non-selection signal voltage to each scanning signal line when the selection scanning voltage is not supplied, to each of the capacitance signal lines. A capacitance signal line driving unit that supplies a driving voltage, wherein the capacitance signal line driving unit is configured to control each of the capacitance signal lines corresponding to each of the scanning signal lines to which the non-selection scanning voltage is supplied. In addition, each of the scanning signals A liquid crystal display device for supplying a drive voltage for compensating for a potential change occurring in a pixel electrode of each pixel when a voltage applied to a signal line changes from the selected scanning voltage to a non-selected scanning voltage. 2. A liquid crystal display element comprising: two substrates disposed to face each other; and a liquid crystal layer sandwiched between the two substrates; a plurality of pixels having pixel electrodes; A plurality of scanning signal lines for applying a selection scanning voltage or a non-selection signal voltage to a pixel; and a liquid crystal display element having a plurality of capacitance signal lines connected to a pixel electrode of each pixel via a capacitance element; While sequentially supplying a selection scanning voltage to each scanning signal line, supplying a non-selection signal voltage to each scanning signal line when the selection scanning voltage is not supplied, and supplying a driving voltage to each of the capacitance signal lines A scanning signal line driving unit, wherein the scanning signal line driving unit is configured to provide the capacitance signal lines corresponding to the scanning signal lines to which the non-selective scanning voltage is supplied, Applied to the scanning signal line The liquid crystal display device and supplying the voltage to compensate for the potential variation occurring in the pixel electrode of each pixel when the pressure is changed to a non-selected scanning voltage from the selected scanning voltage. 3. A liquid crystal display device comprising: two substrates disposed to face each other; and a liquid crystal layer sandwiched between the two substrates; a plurality of pixels having pixel electrodes; A liquid crystal display having a plurality of scanning signal lines for applying a selection scanning voltage or a non-selection voltage to a pixel, a plurality of capacitance signal lines connected to a pixel electrode of each pixel via a capacitance element, and a counter electrode. A scanning signal line driving unit that sequentially supplies a selection scanning voltage to each of the scanning signal lines, and supplies a non-selection signal voltage to each of the scanning signal lines when the selection scanning voltage is not supplied; A capacitance signal line driving unit for supplying a driving voltage to the capacitance signal line, wherein the capacitance signal line driving unit corresponds to each scanning signal line to which the non-selective scanning voltage is supplied. For each capacitance signal line The liquid crystal display device and supplying the potential difference increasing driving voltage between the drive voltage applied to the counter electrode and the voltage applied to the pixel electrode of each pixel. 4. A liquid crystal display device comprising: two substrates disposed to face each other; and a liquid crystal layer sandwiched between the two substrates; a plurality of pixels having pixel electrodes; A plurality of scanning signal lines for applying a selection scanning voltage or a non-selection voltage to a pixel; a plurality of capacitance signals provided for each of the scanning signal lines and connected to a pixel electrode of each of the pixels via a capacitance element And a liquid crystal display element having a counter electrode, and sequentially supplying a selection scanning voltage to each of the scanning signal lines, and supplying a non-selection signal voltage to each of the scanning signal lines when the selection scanning voltage is not supplied. And a scanning signal line driving unit for supplying a driving voltage to each of the capacitance signal lines, wherein the scanning signal line driving unit is configured to perform each of the scans to which the unselected scanning voltage is supplied. Each of the above corresponding to the signal line A liquid crystal display device, wherein a driving voltage for increasing a potential difference between a voltage applied to a pixel electrode of each pixel and a driving voltage applied to the counter electrode is supplied to a capacitance signal line. 5. The pixel according to claim 3, wherein a plurality of the counter electrodes are provided in one pixel.
3. The liquid crystal display device according to 1.