JPH07306660A - Gradation driving circuit for liquid crystal display device and gradation driving method therefor - Google Patents

Abstract

PURPOSE:To provide a gradation driving circuit for a liquid crystal display device and a gradation driving method enabling multiple gradation display of 2<n> levels and allowing the number of external power input lines and analog switches to be reduced so as to be of low cost. CONSTITUTION:A gradation driving circuit for a liquid crystal display device performing the 2<n> level gradation display (n is an integer of 2 or more) of each display picture element has a shift register circuit 21 for transferring n-bit gradation data in regular succession, a latching circuit 22 for storing the contents of the shift register circuit 21, and a detecting circuit for detecting the coincidence between the gradation data D0-D6 stored in the latching circuit 22 and the gradation control clock number CPG. The gradation driving circuit is further provided with a pulse width modulating circuit 23 for converting pulse width into the width corresponding to the output of the detecting circuit, an analog switch 25 into which the output of the pulse width modulating circuit 23 is inputted as an on-off control switching signal so as to be controlled by this switching signal, with gradation reference voltage inputted to one side and with capacitive load connected to the other side, and a gradation control clock changeover switch 26 having gradation control clocks CPG disposed in two systems and selecting between two system gradation control clocks CPG.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grayscale driving circuit and a grayscale driving method thereof capable of displaying halftone in a liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 11 is well known as a circuit of a liquid crystal display device which is a kind of flat display. In FIG. 11, a plurality of X electrode lines (X ₁ , X ₂ , ...) 1 and Y electrode lines (Y ₁ , Y ₂ , ...)
2 intersect each other, and an active element 3 such as a TFT (thin film transistor) is formed at the intersection of each X electrode line and Y electrode line.
And the liquid crystal display elements 4 are arranged in a matrix.

The Y electrode line 2 is also called a data signal line, and is connected to a display signal circuit 5 which outputs a display data signal of each liquid crystal display element 4. The X electrode line 1 is also called a scanning signal line, and is connected to a scanning signal circuit 6 that sequentially outputs scanning signals. The active element 3 is driven by a line-sequential driving method in which the X electrode line 1 is sequentially scanned and driven, and the active element 3 on the X electrode line 1 is turned on in synchronization with the scanning of the X electrode line 1. At this time, a display data signal is output from the display signal circuit 5, and the data signal is written to the corresponding liquid crystal display element 4 via the active element 3 in the ON state.

Attempts have also been made to improve the charge retention characteristics of the liquid crystal display element 4 by providing the liquid crystal display element 4 with a storage capacitor 7 if necessary. Here, by varying the amplitude value of the data signal voltage written in the liquid crystal display element 4, the write voltage or the amount of charge to the liquid crystal display element 4 can be variably controlled, and the light transmittance of the liquid crystal can be variably controlled. it can. This method is called a voltage modulation driving method and is a typical driving method for displaying halftone in a liquid crystal display device.

As a liquid crystal drive circuit which enables gradation display by this voltage modulation drive method, for example, a liquid crystal drive driver, HD66310T (manufactured by Hitachi Ltd.) shown in FIG. 12 is known. . The liquid crystal drive circuit of FIG. 12 enables display of 8 gradations, and the 3-bit display data D0j, D1j, D2j corresponding to the liquid crystal pixels is synchronized with the clock signal CL2 in the first latch circuit 11 Entered in. The display data signal input to the first latch circuit 11 is then input to the second latch circuit 12 in synchronization with the clock signal CL1. Then, the output of the second latch circuit 12 is input to the voltage selector circuit 13.

The voltage selector circuit 13 is composed of a decoder circuit and the like. For example, one of 2 ³ = 8 output lines is selected based on a 3-bit input signal.
Data is output on the output line of the book. In this circuit configuration, the output of the voltage selector circuit 13 selects any one of the analog switches 14 _{1 to} 14 ₈ having P-MOS, N-MOS, FET and the like in the next stage to turn it on and outputs the analog signal. Any one of the eight power supply input lines V0 to V7 connected to the switches 14 _{1 to} 14 ₈
It operates so as to output to the driver output Yn. Reference numeral 15 is an inverter, which logically inverts the output of the voltage selector circuit 13 to convert the analog switches 14 ₁ to
The signal is output to the 14 ₈ N-MOS.

The liquid crystal drive circuit of the HD66310T (manufactured by Hitachi, Ltd.) is the same as the drive circuit of FIG.
Equipped with 160 dots. Further, the liquid crystal display device includes a number of liquid crystal driver circuits corresponding to the number of pixels of one horizontal scanning line. The transfer from the first latch circuit 11 to the second latch circuit 12 is performed after the display data for one horizontal scanning is input to the first latch circuit 11.

[0008]

However, in the drive circuit of the above-mentioned conventional liquid crystal display device, (1) when multi-gradation is attempted, it is necessary to input an external power source of a number corresponding to gradation reproduction, and Integrated drive circuit (IC)
By doing so, the area occupied by the wiring system of the power supply input line inside the IC increases, which is not economical.

(2) The number of analog switches composed of P-MOS, N-MOS, FET, etc. is also required to correspond to the number of gradation reproductions, and it is economical when integrated (IC) is considered. Absent. There were problems such as. The present invention eliminates the above-mentioned problems, can perform multi-gradation display of 2 ⁿ level, and can reduce the number of external power supply input lines and the number of analog switches, and is a low-cost liquid crystal display device. An object of the present invention is to provide a gradation driving circuit and a gradation driving method thereof.

[0010]

In order to achieve the above object, the present invention provides: (A) a floor of a liquid crystal display device for displaying each display pixel in 2 ⁿ level gradation (n is an integer of 2 or more); In the adjustment drive circuit,
(1) A shift register circuit that sequentially transfers n-bit grayscale data, a latch circuit that stores the contents of the shift register circuit, the grayscale data stored in the latch circuit, and the number of grayscale control clocks. A detection circuit that detects a match, a pulse width modulation circuit that converts a pulse having a width according to the output of this detection circuit, and the output of this pulse width modulation circuit
An analog switch circuit, which is inputted as a switching signal for controlling on / off, is controlled by this switching signal, and is inputted with a gradation reference voltage at one side and a capacitive load is connected to the other side, and the gradation control clock. 2
The system is arranged, and a gradation control clock changeover switch for selecting these two systems of gradation control clocks is provided.

(2) A shift register circuit for sequentially transferring n-bit gradation data, a latch circuit for storing the contents of the shift register circuit, gradation data stored in the latch circuit, and a gradation control clock. A detection circuit that detects a match with the number, a pulse width modulation circuit that converts the pulse to a pulse width according to the output of this detection circuit, and the output of this pulse width modulation circuit is input as a switching signal that controls on / off. In addition to being controlled by this switching signal, a gray scale reference voltage is input to one side and an analog switch circuit to which a capacitive load is connected to the other side, and the gray scale reference voltage are arranged in two systems. A gradation reference voltage changeover switch for selecting the gradation reference voltage is provided.

(B) In a grayscale driving method of a liquid crystal display device for performing grayscale display of 2 ⁿ levels (n is an integer of 2 or more) on each display pixel, (1) n-bit grayscale data is shifted register circuit. Sequentially, the contents of the shift register circuit are stored in a latch circuit, the detection circuit detects a match between the gradation data stored in the latch circuit and the number of gradation control clocks, and the pulse width modulation circuit An analog switch circuit is provided, which is converted into a pulse having a width according to the output of the detection circuit, and the output of the pulse width modulation circuit is input as a switching signal for controlling on / off, and which is controlled by this switching signal. A gray scale control clock switching switch in which a gray scale reference voltage is input to one of the analog switch circuits and a capacitive load is connected to the other, and the gray scale control clocks are connected in two systems. Switch is provided, and a grayscale control clock selection signal is input to this changeover switch to alternately select each scanning line, and each scanning line generates a grayscale control clock different from the previous frame. It is the one that is selected.

(2) The n-bit gradation data is sequentially transferred by the shift register circuit, the contents of the shift register circuit are stored in the latch circuit, and the gradation data stored in the latch circuit and the gradation control clock are stored. The detection circuit detects the coincidence with the number, the pulse width modulation circuit converts it into a pulse having a width according to the output of the detection circuit, and the output of this pulse width modulation circuit is input as a switching signal for controlling on / off. An analog switch circuit controlled by this switching signal is provided, a gray scale reference voltage is input to one of the analog switch circuits, a capacitive load is connected to the other, and the gray scale reference voltages are connected in two systems. A gradation reference voltage changeover switch is arranged, and a gradation reference voltage selection signal is input to the changeover switch so that the externally input gradation reference voltage is set to 1 for each frame. In which it was to be modulated within regulated voltage.

[0014]

According to the present invention, as described above, by providing two systems of gradation control clocks and selecting two kinds of gradation voltages with the same gradation data, display is performed with two kinds of gradation voltages. Since it is possible to obtain the average brightness of the displayed brightness, it is possible to generate more display colors than the gradation data. As the selection condition of the gradation control clock, it is possible to alternately select each scanning line, drive for each frame under a condition different from the previous frame, suppress flicker, and increase the display color by pseudo gradation. it can.

Further, by providing two systems of gradation reference voltages, selecting two kinds of gradation voltages with the same gradation data, and modulating within one gradation voltage for each frame, more than the gradation data can be obtained. It is possible to generate the display color of, and it is possible to increase the display color.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a gradation driving circuit of a liquid crystal display device showing a first embodiment of the present invention, and FIG. 2 is a gradation reference input to a gradation driving circuit of a liquid crystal display device showing the first embodiment of the present invention. 2A and 2B are diagrams showing a voltage waveform and a pulse width control clock, FIG. 2A is a diagram showing a gradation reference voltage with respect to a scanning time, FIG. 2B is a diagram showing display data, and FIG. 2C is a LOAD signal. 2 (d) is a diagram showing a pulse width modulation signal a (PWMa), FIG. 2 (e) is a diagram showing a pulse width control clock signal a (CPGa), and FIG. 2 (f) is a pulse width modulation. 3 shows a signal b (PWMb), FIG. 2 (g) shows a pulse width control clock signal b (CPGb), and FIG.
FIG. 4 is a diagram showing gradation data and a gradation reference voltage of a gradation drive circuit of the liquid crystal display device showing the first embodiment of the present invention, and FIG. 4 is a gradation of the liquid crystal display device showing the first embodiment of the present invention. 4A and 4B are operation timing charts of the drive circuit, FIG. 4A illustrates a vertical signal, FIG. 4B illustrates a frame selection signal, and FIG.
4C shows a horizontal signal (ST), FIG. 4D shows a horizontal selection signal, FIG. 4E shows data of a shift register circuit, and FIG. 4F shows a LOAD signal. Figure showing,
FIG. 4 (g) is a diagram showing data of the latch circuit, FIG. 4 (h).
Shows a CPGa signal, FIG. 4 (i) shows a CPGb signal, FIG. 4 (j) shows a CPG selection signal, FIG.
(K) is a diagram showing a PWM signal, and FIG. 4 (l) is a diagram showing a data line voltage.

As shown in these figures, for example, 21 is a shift register circuit, and this shift register circuit 2
1 is 7-bit gradation data D0 to D6, a start signal ST which is a horizontal synchronizing signal, and a data shift clock C
For example, it is a shift register circuit of 7 bits × 192 to which P and P are input. Reference numeral 22 is a latch circuit. The latch circuit 22 is, for example, a 7-bit × 192 latch circuit to which the output of the shift register circuit 21 is input.
The outputs D0 to D6 of the shift register circuit 21 are stored in the latch circuit 22 by the AD signal.

The output of the latch circuit 22 is input to the pulse width modulation circuit 23. In this pulse width modulation circuit 23,
The LOAD signal is input as the set signal, and the pulse width control clock CPG output from the CPG changeover switch 26 is input as the reset signal. That is, as the pulse width control clock CPG, two types of clocks CPGa and CPGb are selected by the CPG changeover switch 26 and input to the pulse width modulation circuit 23.

The output signal of the pulse width modulation circuit 23 is supplied as an ON / OFF control signal for the analog switch 25 via the level shifter circuit 24. The gradation reference voltage Vref set to the stepwise voltage is supplied to one of the analog switches 25, and the output V _0m (m = 1 to 1) is supplied from the other.
92) is obtained. The operation of the nth frame and the (n + 1) th frame of the vertical synchronizing signal will be described with reference to FIGS. 1 and 4.
Each frame is divided into an odd number frame and an even number frame to generate a frame selection signal. Each frame is divided into odd and even lines to generate a horizontal selection signal. The number of lines corresponds to the number of Y electrodes.

First, when the horizontal synchronizing signal on the (n-1) th line is input to the shift register circuit 21 as the start signal ST, the grayscale data D0 to D6 on the Hn-1th line.
Are sequentially transferred in the shift register circuit 21 by the data shift clock CP. When the data transfer for 192 pixels is completed, the shift end pulse H0 is
It is output from the shift register circuit 21 and input as a start pulse to a gradation drive circuit (not shown) in the next stage. Grayscale driving circuits are similarly cascade-connected according to the number of data to be transferred.

When the data transfer of the (n-1) th line is completed as described above, the data of the (n-1) th line is stored in the latch circuit 22 by the LOAD signal. Next, as the start signal ST, the horizontal synchronizing signal of the nth line is
When input to the shift register circuit 21, the gradation drive data signal of the nth line is sequentially transferred in the shift register circuit 21, and the same operation is repeated thereafter.

In the pulse width modulation circuit 23, as shown in FIG. 5, when the gradation data D0 to D6 are stored in the latch circuit 22 by the LOAD signal, the stored data are output Q0 to Q6. Is input to the coincidence circuit 23-2. At the same time, the LOAD signal is sent to the pulse width modulation circuit 23.
The flip-flop circuit 23-3 constituting the above is set.

The clock number counter 23-1 counts the number of pulse width control clocks CPG and outputs the data output g0.
~ G6 is obtained. Input to the EXNOR circuit so that the data of the outputs Q0 to Q6 of the latch circuit 22, the data of the outputs g0 to g6 of the clock number counter 23-1, and the data of Qm and gm (m = 0 to 6) are paired. And the signal obtained by
The pulse width control clock CPG is input to the AND circuit to obtain the output of the coincidence circuit 23-2. Matching circuit 23-2
The output obtained in step 7 resets the output of the flip-flop circuit 23-3.

The output is set by the LOAD signal and reset by the output signal indicating the coincidence of the number of gradation data and the number of gradation control clocks CPG. As described above, the pulse width modulation circuit output PWM-m having the pulse width corresponding to the gradation data is output.
To get As shown in FIG. 1, the output PWM-m is level-converted via a level shifter circuit 24 and then supplied to an analog switch 25 to control ON / OFF of the analog switch 25. The gradation reference voltage Vref is supplied to one of the analog switches 25. The gradation reference voltage Vref is a signal having a horizontal synchronizing signal cycle, for example, a ramp-shaped voltage waveform.

Then, the output V _{0m of the} analog switch 25
Is the same voltage as the gradation reference voltage Vref only while the output PWM-m of the pulse width modulation circuit 23 is "H", and is high while the output PWM-m of the pulse width modulation circuit 23 is "L". Impedance state. As described above, the analog switch 25 is the pulse width modulation circuit 2
ON / OFF control is performed by the output PWM-m of 3 to generate an output voltage corresponding to the ON time of the pulse width.

Grayscale control clocks CPGa, CP of the present invention
The operation of Gb will be described with reference to FIGS. 2 and 4. The gradation reference voltage Vref in FIG. 2 is a stepwise voltage of 256 steps, and the time of one step is represented by TS time. The time distribution of the stepwise voltage within one scanning time is as follows: a sampling period for selecting the V0 voltage to V255 voltage by pulse modulation, a hold period for holding a high gradation level (V255 voltage), and a low gradation level (V0). It consists of a holding reset period.
For example, the operation timing of the gradation drive circuit is n frames,
The gradation data “7FH” is stored in the latch circuit 22 for the Hn−1th line.

Pulse width control clocks CPGa, CPGb
Is the EX of the frame selection signal and the horizontal selection signal shown in FIG.
Determined by OR logic condition, CPGb is selected for the nth frame and Hn-1 line. Further, the CPG conditions of the odd and even lines are different for each frame, and CPGa is selected in the (n + 1) th frame and the (Hn-1) th line. Clock cycle T of the pulse width control clocks CPGa and CPGb
CPG _n is set to 2 × TS and the number of clocks is 128. The time relationship (TD) between CPGa and CPGb is CPGb
Is delayed (TD = TS) with respect to CPGa for one step Ts of the gradation reference voltage.

Further, the output PWM of the pulse width modulation circuit 23
-B is set by the LOAD signal, and the gradation data "7F
H ”and gradation control clock CPGb match condition (7FH
Is the decimal number, which corresponds to the 128th clock). While PWM-b is "H", the output of the analog switch 25 follows the gradation reference voltage Vref, and after reaching the voltage V255 at the time of reset, it becomes a high impedance state.

On the other hand, the gradation control clock CPGa is selected for the (n + 1) th frame and the (Hn-1) th line. Assuming that the gradation data is "7FH" similar to that in the nth frame, the output PWM-a of the pulse width modulation circuit 23 is earlier than PWM-b by one step time (TS) of the gradation reference voltage Vref. Since it is reset, the output of the analog switch 25 is
After reaching the voltage V254 at the time of reset, the high impedance state is set.

FIG. 3 shows gradation data and gradation reference voltage at the time of selection. In both CPGa and CPGb, the gradation reference voltage is selected every two steps as the gradation data increases. CPG
Since a and CPGb are selected alternately for each scanning line and for each frame, in the case of the same grayscale data for both odd and even frames, for example, "7F", the V254 voltage and the V255 voltage are alternated for each frame. Applied to liquid crystal. In addition, if the voltage is continuously applied to the liquid crystal, the intermediate brightness (V254) of the brightness obtained with the V254 voltage and the V255 voltage is obtained.
+ V255) / 2 is obtained.

In this way, the gradation control clock CPGa,
CPG changeover switch 2 to which two systems of CPGb are connected
6 are arranged, a grayscale control clock selection signal is input to the CPG changeover switch 26 to alternately select each scan line, and each scan line has a grayscale control clock different from that of the previous frame. Can be selected.

Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram of a grayscale driving circuit of a liquid crystal display device showing a second embodiment of the present invention, and FIG. 7 is a grayscale reference input to a grayscale driving circuit of a liquid crystal display device showing the second embodiment of the present invention. FIG. 8 is a voltage waveform diagram, FIG. 8 is a diagram showing grayscale data and a grayscale reference voltage of a grayscale drive circuit of a liquid crystal display device according to a second embodiment of the present invention, and FIG. 9 is a second embodiment of the present invention. 9 is an operation timing chart of the gradation drive circuit of the liquid crystal display device, and FIG.
9A shows a vertical signal, FIG. 9B shows a frame selection signal, FIG. 9C shows a horizontal signal (ST), and FIG. 9D shows data of a shift register circuit. 9 (e) shows a LOAD signal, FIG. 9 (f) shows data of a latch circuit, FIG. 9 (g) shows a CPG signal, and FIG. 9 (h) shows a PMW signal. Fig. 9
(I) is a diagram showing a data bus voltage.

As shown in these figures, 31 is a shift register circuit, and this shift register circuit 31 is
It is a shift register of, for example, 7 bits × 192 to which the bit gradation data D0 to D6, a start signal ST which is a horizontal synchronizing signal, and a data shift clock CP are input. 32 is a latch circuit, and this latch circuit 32
Is a latch circuit of, for example, 7 bits × 192 to which the output of the shift register circuit 31 is input, and the outputs D0 to D6 of the shift register circuit 31 are stored in the latch circuit 32 by a LOAD signal.

The output of the latch circuit 32 is input to the pulse width modulation circuit 33. The LOAD signal as a set signal and the pulse width control clock CPG for generating a reset signal are input to the pulse width modulation circuit 33. The output signal of the pulse width modulation circuit 33 is the level shifter circuit 34.
Is supplied as an ON / OFF control signal for the analog switch 35. On one side of the analog switch 35,
Two kinds of stepwise voltages Vref1 and Vref2 are selected by the gradation reference voltage changeover switch 36 and input, and an output V _0m (m = 1 to 192) is obtained from the other.

The operation of the nth frame and the (n + 1) th frame of the vertical synchronizing signal will be described with reference to FIG. Each frame is divided into an odd number frame and an even number frame to generate a frame selection signal. First, the start signal ST is sent to the shift register circuit 31.
When the horizontal synchronization signal (TS) of the n-1th line is input, the grayscale data D0 to D6 of the Hn-1th line
Are sequentially transferred in the shift register circuit 31 by the data shift clock CP. When the data transfer for 192 pixels is completed, the shift end pulse H0 is output from the shift register circuit 31 and input to the next stage gradation drive circuit (not shown) as a start pulse. Grayscale driving circuits are similarly cascade-connected according to the number of data to be transferred.

When the data transfer of the (n-1) th line is completed as described above, the data of the (n-1) th line is stored in the latch circuit 32 by the LOAD signal. Next, as a start signal ST, a horizontal synchronization signal (S
When (T) is input to the shift register circuit 31, the grayscale drive data signal of the nth line is sequentially transferred in the shift register circuit 31, and the same operation is repeated thereafter.

The pulse width modulation circuit 33 is the same as the circuit shown in FIG. 5 described above, and a description thereof will be omitted here. In this way, the pulse width modulation circuit 33 outputs the pulse width modulation circuit output PWM-n having the pulse width corresponding to the grayscale data.
To get As shown in FIG. 6, the output PWM-n is level-converted via the level shifter circuit 34 and then supplied to the analog switch 35, and the analog switch 3
Controls 5 on / off. The gradation reference voltage Vref is supplied to one of the analog switches 35. The gradation reference voltage Vref is a signal having a horizontal synchronizing signal cycle, for example, a ramp-shaped voltage waveform.

Then, the output V _{0m of the} analog switch 35
Becomes the same voltage as the gradation reference voltage Vref only during the period when the output PWM-n is "H", and is in the high impedance state during the period when the output PWM-n is "L". As described above, the analog switch 35 is ON / OFF controlled by the output PWM-n of the pulse width modulation circuit 33, and generates the output voltage corresponding to the ON time of the pulse width.

The gradation operation of the liquid crystal display device according to the second embodiment of the present invention will be described with reference to FIGS. 7, 8 and 9. As shown in FIG. 7, the gradation reference voltage Vref is composed of a stepwise voltage of 128 steps using a D / A converter. The amplitude corresponding to one gradation of each voltage is Va1, and one step time is represented by Ts. The gradation reference voltage is variable in stepwise voltage level within one gradation voltage according to each gradation data for each scanning frame. In FIG. 7, for example, V0, V2 to V252, and V254 are set as the voltage levels of odd frames, and V1 and V3 to V3 are set as the voltage levels of even frames.
V253 and V255 are set.

The relationship between the gradation data and the gradation reference voltage is shown in FIG. When the grayscale data is 00H in hexadecimal, the stepwise voltage V0 is selected in the odd-numbered frame and the stepwise voltage V1 is selected in the even-numbered frame. Similarly, in each gradation data, the difference voltage Voffset is provided at the staircase voltage level in the odd frame and the even frame. As the gradation reference voltage, as shown in FIG. 7, a frame selection signal is input to the gradation reference voltage changeover switch 36, and an odd gradation reference voltage (Vref1) and an even gradation reference voltage (Vre
Select f2).

In FIG. 9, for example, n frames, Hn-
The output PWM of the pulse width modulation circuit 33 is reset at the first clock of the gradation control clock by the gradation data “00H” of the first line, and the analog switch 35 is turned on / off. As the input voltage of the analog switch 35, the gradation reference voltage Vref1 of the odd frame is selected, and the output of the analog switch 35 follows the gradation reference voltage Vref1 while the PWM is “H”, and reaches the voltage V0 at the time of reset. is doing.

Further, as the input voltage of the analog switch 35 of the (n + 1) th frame and the Hn−1th frame, the grayscale reference voltage Vref2 of the even frame is selected, and its output reaches the voltage V1 at the time of reset. The same grayscale data is used in both the odd-numbered frame and the even-numbered frame, but the V0 voltage and the V1 voltage are alternately applied to the liquid crystal for each frame. Further, if applied continuously to the liquid crystal, an intermediate brightness (V0 + V1) / 2 of the brightness obtained by the V0 voltage and the V1 voltage can be obtained.

In this way, the gradation reference voltage changeover switch 36 to which the gradation reference voltage Vref is connected in two systems is arranged, and the gradation reference voltage selection signal is inputted to this changeover switch to input the gradation reference voltage of the external input. The voltage is modulated within one gradation voltage for each frame. By the way, the active matrix type liquid crystal display device has a circuit configuration shown in FIG. That is, reference numeral 51 is a data signal circuit of the present invention, which is composed of the gradation driving circuit described above. 52 is a scanning signal circuit, 41 is a data bus line connected to the output of the data signal circuit 51, 42 is a scanning bus line connected to the output of the scanning signal circuit 52, 43 is a data bus line 41 and a scanning bus line 42. Provided at the intersection of,
For example, an a-Si thin film transistor (hereinafter referred to as a TFT) 44 is a liquid crystal cell whose one side is connected to the TFT 43, and the other side of the liquid crystal cell 44 is connected to a counter electrode 46 and electrically, for example, 0.1 PF. It is about a capacitor.

Reference numeral 45 denotes a storage capacitor provided in parallel with the liquid crystal cell 44 (capacitor), which is, for example, a 0.5 PF capacitor. Further, the data bus line 41 and the scanning bus line 42 are arranged so as to face the counter electrode 46 with the liquid crystal interposed therebetween, and a parasitic capacitance 47 is formed between the data bus line 41 and the counter electrode 46. A parasitic capacitance 48 is formed at the intersection of the scan bus lines 42.

The capacitance C of the data bus line 41 is determined by the parasitic capacitances 47, 48, etc., and becomes the load capacitance of the grayscale drive circuit, and the grayscale reference voltage Vref is the analog switch 35.
The load capacitance of the data bus line 41 is charged via (see FIG. 6). The potential of the data bus line 41 is the capacitance C of the data bus line 41 and the analog switch 35.
Is determined by the time constant (τ = CR) formed by the ON resistance R of, and the gradation reference voltage Vref is followed during the time when the output of the analog switch 35 is fixed. When the output of the analog switch 35 is in a high impedance state, it has a potential determined by the charged load capacitance. That is, it is held at the potential immediately before the high impedance state.

The charges charged in the load capacitance of the data bus line 41 are finally passed through the TFT 43 and finally the liquid crystal cell 4
4. It is applied to the storage capacitor 45 and has the same potential as the load capacitor. Further, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0047]

As described in detail above, according to the present invention, the following effects can be achieved. (1) Since two systems of gradation control clocks are provided and two kinds of gradation voltages are selected with the same gradation data, the average brightness of the brightness displayed by two kinds of gradation voltages can be obtained. It is possible to generate more display colors than gradation data. As the selection condition of the gradation control clock, it is possible to alternately select each scanning line, drive for each frame under a condition different from the previous frame, suppress flicker, and increase the display color by pseudo gradation. it can.

(2) Two gradation reference voltages are provided, two kinds of gradation voltages are selected with the same gradation data, and modulation is performed within one gradation voltage for each frame. Many display colors can be generated, and the display colors can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a gradation drive circuit of a liquid crystal display device showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a gradation reference voltage waveform and a pulse width control clock input to a gradation drive circuit of the liquid crystal display device showing the first embodiment of the present invention.

FIG. 3 is a diagram showing grayscale data and a grayscale reference voltage of a grayscale drive circuit of the liquid crystal display device showing the first embodiment of the present invention.

FIG. 4 is an operation timing chart of the gradation drive circuit of the liquid crystal display device showing the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a pulse width modulation circuit of the gradation drive circuit of the liquid crystal display device showing the first embodiment of the present invention.

FIG. 6 is a block diagram of a gradation drive circuit of a liquid crystal display device showing a second embodiment of the present invention.

FIG. 7 is a waveform diagram of a gradation reference voltage input to a gradation drive circuit of a liquid crystal display device showing a second embodiment of the present invention.

FIG. 8 is a diagram showing grayscale data and a grayscale reference voltage of a grayscale drive circuit of a liquid crystal display device showing a second embodiment of the present invention.

FIG. 9 is an operation timing chart of the gradation drive circuit of the liquid crystal display device showing the second embodiment of the present invention.

FIG. 10 is a circuit diagram of a liquid crystal display panel showing an embodiment of the present invention.

FIG. 11 is a circuit diagram of a conventional liquid crystal display panel.

FIG. 12 is a gradation drive circuit diagram of a conventional liquid crystal display device.

[Explanation of symbols]

 21, 31 Shift register circuit 22, 32 Latch circuit 23, 33 Pulse width modulation circuit 23-1 Clock number counter 23-2 Matching circuit 23-3 Flip-flop circuit 24, 34 Level shifter circuit 25, 35 Analog switch 26 CPG change switch 36 Grayscale reference voltage changeover switch 41 Data bus line 42 Scanning bus line 43 a-Si thin film transistor (TFT) 44 Liquid crystal cell 45 Storage capacitor 46 Counter electrode 47, 48 Parasitic capacitance 51 Data signal circuit 52 Scanning signal circuit

Claims (4)

[Claims] 1. A shift for sequentially transferring (a) n-bit grayscale data in a grayscale drive circuit of a liquid crystal display device for performing grayscale display of 2 ⁿ levels (n is an integer of 2 or more) on each display pixel. A register circuit; (b) a latch circuit for storing the contents of the shift register circuit; and (c) a detection circuit for detecting a match between the gradation data stored in the latch circuit and the gradation control clock number. (D) A pulse width modulation circuit for converting into a pulse having a width according to the output of the detection circuit, and (e) an output of the pulse width modulation circuit is inputted as a switching signal for controlling on / off, and the switching signal (F) an analog switch circuit that is controlled by, and has a gray scale reference voltage input to one side and a capacitive load connected to the other side;
2. A gradation drive circuit for a liquid crystal display device, comprising: two gradation control clocks arranged; and a gradation control clock changeover switch for selecting the two gradation control clocks. 2. A shift for sequentially transferring (a) n-bit grayscale data in a grayscale drive circuit of a liquid crystal display device for performing grayscale display of 2 ⁿ levels (n is an integer of 2 or more) on each display pixel. A register circuit; (b) a latch circuit for storing the contents of the shift register circuit; and (c) a detection circuit for detecting a match between the gradation data stored in the latch circuit and the gradation control clock number. (D) A pulse width modulation circuit for converting into a pulse having a width according to the output of the detection circuit, and (e) an output of the pulse width modulation circuit is inputted as a switching signal for controlling on / off, and the switching signal (F) an analog switch circuit that is controlled by, and has a gray scale reference voltage input to one side and a capacitive load connected to the other side;
A gradation drive circuit for a liquid crystal display device, comprising: two gradation reference voltages arranged; and a gradation reference voltage changeover switch for selecting the two gradation reference voltages. 3. A grayscale driving method for a liquid crystal display device for performing grayscale display of 2 ⁿ levels (n is an integer of 2 or more) on each display pixel, wherein (a) n-bit grayscale data is converted by a shift register circuit. Sequentially, (b) the contents of the shift register circuit are stored in a latch circuit, and (c) the detection circuit detects a match between the gradation data stored in the latch circuit and the number of gradation control clocks, (D) The pulse width modulation circuit converts the pulse into a pulse having a width according to the output of the detection circuit, and (e) the output of the pulse width modulation circuit is input as a switching signal for controlling on / off, and the switching signal An analog switch circuit controlled by, a grayscale reference voltage is input to one of the analog switch circuits, and a capacitive load is connected to the other, and (f) the grayscale control clock is connected to two systems. Control Tsu Place the click change-over switch,
A gradation control clock selection signal is input to the changeover switch to alternately select each scanning line, and each scanning line selects a gradation control clock different from that of the previous frame. Driving method for liquid crystal display device. 4. A grayscale driving method for a liquid crystal display device, wherein each display pixel performs grayscale display of 2 ⁿ levels (n is an integer of 2 or more), wherein (a) n-bit grayscale data is converted by a shift register circuit. Sequentially, (b) the contents of the shift register circuit are stored in a latch circuit, and (c) the detection circuit detects a match between the gradation data stored in the latch circuit and the number of gradation control clocks, (D) The pulse width modulation circuit converts the pulse into a pulse having a width according to the output of the detection circuit, and (e) the output of the pulse width modulation circuit is input as a switching signal for controlling on / off, and the switching signal A gray scale reference voltage is input to one side of the analog switch circuit and a capacitive load is connected to the other side of the analog switch circuit. Reference voltage off A liquid crystal display device characterized in that a changeover switch is arranged, and a gradation reference voltage selection signal is inputted to the changeover switch to modulate the externally inputted gradation reference voltage within one gradation voltage for each frame. Gradation driving method.