JP3097612B2 - Liquid crystal drive semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a semiconductor device for driving a liquid crystal device for transmitting pixel signals to a TFT active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art As a matrix type liquid crystal display device, a TFT (thin film transistor) for addressing is provided in a liquid crystal panel.
Get the representation by embedding T on the matrix
FT active matrix type liquid crystal display devices are currently the mainstream.

FIG. 10 is a diagram showing a configuration of a TFT active matrix type liquid crystal display device. Also, in FIG.
2 shows an internal configuration of a liquid crystal display panel. For driving the TFT active matrix type liquid crystal display device, a source driver 14 for transmitting a pixel signal and a gate driver 13 for transmitting a scanning signal for performing line-sequential scanning are used.

A gate driver 13 applies a voltage to a gate electrode of a TFT according to a timing signal for scanning a row electrode generated from an image signal through a signal conversion circuit 12. The operation is as follows. Assuming that one horizontal period (scanning period) is H, a scanning signal having a pulse value of H is applied to the scanning electrodes line by line, and the TFTs on the panel are turned on sequentially for each line. is there. However, one horizontal period (scanning period) H
One frame (full scanning period) of a row electrode is T, and the number of row electrodes is N
Then, it is given by H = T / N.

The image signal is converted into an AC drive signal according to the voltage-transmittance characteristic of the liquid crystal by a signal conversion circuit 12 and a γ correction circuit 11, and a source driver 14 applies a voltage corresponding to the converted signal to a gate driver. The liquid crystal is applied to the liquid crystal through the TFT (see FIG. 11) turned on by 13.
By repeating this operation for all the row electrodes, an appropriate voltage can be applied to the liquid crystal of all the pixels.
The time when the above operation is repeated for the row electrodes is one frame. However, one frame period T must be a time during which a person cannot recognize line-sequential scanning, and one horizontal period H is longer than the time during which the voltage applied to the capacitance C1c of the liquid crystal layer becomes the voltage applied by the source driver. There is a need.

In a TFT active matrix type liquid crystal display device, gradation display is realized by changing a voltage applied to liquid crystal. Due to the electrical and optical properties of the liquid crystal sandwiched between the upper and lower polarizers, the light transmittance varies according to the voltage applied to the liquid crystal.

For this reason, the light = darkness of light passing through the liquid crystal panel from the backlight behind the liquid crystal panel is determined by the voltage applied to the liquid crystal. Multi-color display is realized by passing light transmitted through the liquid crystal panel through RGB (red, green, blue) color filters. For example, if the gradation is 64
In the case of gradation, R × G × B = 64 × 64 × 64 = 260,000 colors can be displayed, and in the case of 256 gradations, 16.78 million colors (full color) can be displayed.

At present, multi-color (multi-gray scale) and high-definition TFT active matrix type liquid crystal display devices are being developed.

According to the voltage-transmittance characteristic of the liquid crystal, when the transmittance is at an intermediate level, the transmittance greatly changes with a slight change in voltage. In order to realize multiple gradations, it is necessary to apply a highly accurate voltage to the liquid crystal layer such that the liquid crystal has an expected transmittance.

For example, at the 64 gradation level, the accuracy of the applied voltage requires ± 10 mV, and at 256 gradations, which is equivalent to a television, a precision of ± 5 mV is required.

Incidentally, the offset voltage of the operational amplifier used for the output of the source driver varies by several mV even in the same chip. For example, when the same gradation is displayed on the panel, the same voltage should be applied to each pixel from the source driver according to the voltage-transmittance characteristic of the liquid crystal. However, when the offset voltage of each operational amplifier in the source driver that applies a voltage to each pixel is different, a different voltage corresponding to the offset voltage is applied between the pixels, resulting in a difference in the transmittance of the liquid crystal.

When the number of gradations is large, a slight difference in the transmittance of the liquid crystal appears as a difference in gradation in the display device, deteriorating the quality of the display device. Therefore, in order to increase the number of gradations, it is necessary to have an offset cancel function that can ignore the offset voltage.

By the way, high definition is to enable fine display by increasing the number of pixels. At that time, since the number of row electrodes increases, one horizontal period must be shortened. For example, XGA (extended graphics arr)
ay) In the case of display (1024 × 768 pixels), one horizontal period must be about 18 μs or less. In the case of S-XGA display (1280 × 1024 pixels), one horizontal period must be about 13 μs or less. Must.

Therefore, in order to simultaneously realize multicolor and high definition, the source driver must be able to apply a highly accurate voltage to the liquid crystal device in a short time.

Next, a source driver generally used at present will be described.

Currently used source drivers are mainly digital input / analog output. Figure 1 shows a block diagram of a digital input / analog output type source driver.
It is shown in FIG. Digital signals corresponding to gradations are input from outside (6 bits for 64 gradations, 8 bit digital data for 256 gradations), and digital data for all outputs are sequentially stored in registers in synchronization with the clock I do. Thereafter, all the data is latched by the latch 3, and the voltage of the liquid crystal is reduced.
An analog voltage corresponding to the digital input is output through a digital-analog conversion circuit (D / A converter) 4 having a level power supply voltage input compatible with the transmittance characteristics. An output timing signal and a level power supply / reference power supply are input to the D / A converter 4.

FIG. 13 shows an example of a circuit of a D / A converter using a capacitor having an offset canceling function.
This type of D / A converter is called a “switched capacitor type D / A converter” (referred to as “SC-DAC”). At present, SC-DAC is
The D / A converter can have an offset cancel function in a simple (simple) form, and is the most balanced in terms of chip size. Referring to FIG. 13, the configuration of this circuit includes a level power supply V1 as an analog input,
It has V2 and a reference power supply voltage Vr, and has input capacitors C0 to Cn having a ratio corresponding to the number of bits of input digital data and an output capacitor Cos connected to the output. Further, an operational amplifier 15 in which a wiring in which the input capacitance and the output capacitance are connected in parallel is used as an inverting input and the reference power supply voltage Vr is used as a non-inverting input, and a switch that changes the connection between the level power supplies V1, V2 and the input capacitance according to the input digital data. S1-Sn, SC-DAC
SW1 to SW5 for switching the operation state of the switch.

The circuit operation of the SC-DAC shown in FIG. 13 will be described below.

In the first operation state, after the switch SW2 connected to the external load via the output terminal OUT is turned off, the other end of the switch SW1 connected to the output capacitance Cos is connected to the operational amplifier 15. The switch SW3 is turned on by connecting to the reference power supply voltage Vr which is a non-inverting input. Further, the switch SW4 is turned off, and the switch SW5 is turned off.
Is turned on, and the switches C1 to Sn are switched to the capacitors C0 weighted according to the number of bits of the digital input signal.
.. Cn are connected to the reference power supply voltage Vr through the switch SW5. FIG. 14 shows the D / A converter in this state.

At this time, the operational amplifier 15 functions as a voltage follower, and the voltage Vα at the point α, which is the inverting input terminal node, ideally becomes the reference power supply voltage Vr connected to the non-inverting input of the operational amplifier 15. Actually, since the operational amplifier 15 has an offset voltage, the voltage at the point α is obtained by adding the offset voltage ΔV of the operational amplifier 15 to the reference power supply voltage Vr.

That is, in this operating state, the output capacitance Co
In s, C0 to Cn, charges corresponding to the offset voltage of the operational amplifier 15 are accumulated. The waveform at point α at this time is shown in FIG.

As shown in FIG. 15, in this operating state, the operational amplifier 15 (see FIG. 14) has an output capacitance Cos,
A voltage follower having input capacitances C0 to Cn and the like as a load is configured. Here, Cos, C0 to Cn are considerably smaller than the load of the liquid crystal panel due to the limitation of the chip size, and are about 1/20. Operational amplifier 15
Since the driving capability is determined in accordance with the load of the liquid crystal panel, the ringing easily occurs with a light load in the circuit. Therefore, it takes several μs to stabilize the voltage Vα at the point α.

Referring to FIG. 15, the voltage V at point α
After α is stabilized, switch SW1 is connected to the output of operational amplifier 15, and switch SW3 is turned off. Further, after the switch SW5 is turned off and the switch SW4 is turned on, the switches S1 to Sn are connected to the level power input V1 or V2 in accordance with the digital input data. Subsequently, the switch SW2 is turned on to apply a voltage to the liquid crystal panel load. FIG. 16 shows a circuit of the D / A converter in this state. At this time, the voltage at the point α is the capacitance C
Since the voltage follower is established through os,
It is the sum of the reference voltage Vr and the offset voltage ΔV of the operational amplifier 15.

Assuming that the first operation state is the left side and the second operation state is the right side, the total charge conservation equation at the point α is given by the following equation (1).

{(Vr + ΔV) −Vr｝ nC + ｛(Vr + ΔV) −Vr｝ (a−n) C + ｛(Vr + ΔV) −Vr｝ xC = {Vα-V1｝ nC + ｛Vα-V2｝ (a-n) C + (Vα−Vout) × C (1)

Here, Coc = xC, n = 1 to N−1,
Let a = N (C is the unit capacitance value) and let the output voltage be Vout.

By substituting Vα = Vr + ΔV and solving for Vout, the following equation (2) is obtained.

[0028]

As described above, the D / A converter stores the offset voltage of the operational amplifier 15 in each capacitor in the first operation state within one horizontal period, and stores the stored offset voltage in the second operation state. By redistributing the charge corresponding to the voltage according to the digital input, the input voltage is amplified according to the above equation (2) to output an analog voltage.

FIG. 17 shows a timing chart of the operation of the above-described SC-DAC. The output timing signal shown in FIG. 17A is a switch S for connection to a liquid crystal panel load.
This corresponds to switching of W2. SC-DA of FIG.
The C state changeover switch signal includes the switches SW1 and SW
3 shows the timing of a signal relating to switching and on / off of connection of SW4 and SW5, and the first operating state and the second operating state are switched according to this timing.

As described above in connection with the first operation state, the SC-DAC is configured as a voltage follower, and it takes 3 to 5 μs to store charges corresponding to the offset voltage in the light load Coc and C0 to Cn. Time is needed.

On the other hand, it takes about 10 μs to apply a voltage to the load on the liquid crystal panel with high accuracy. Therefore, one horizontal period of 18 μs in the case of XGA display
In this case, the voltage can be sufficiently applied to the load on the liquid crystal panel. However, in the case of the S-XGA display, since one horizontal period needs to be 13 μs or less, it cannot be driven using the SC-DAC having the above operation.

[0033]

As described above,
As the definition of a TFT active matrix type liquid crystal display device is advanced, it is necessary to shorten one horizontal period. S
In the XGA display, one horizontal period must be 13 μs or less.

On the other hand, in order to realize multiple colors (multiple gradations), the offset voltage of the operational amplifier in the source driver poses a problem in terms of accuracy. However, the use of an offset cancel circuit increases the definition. Becomes possible.

In the case of the SC-DAC, the operational amplifier is used as a voltage follower, and the offset voltage is stored in the capacitor to realize offset cancellation. However, it takes 3 to 5 μs to store the offset voltage in the capacitor. Further, since it takes about 10 μs to apply a voltage to the load on the liquid crystal panel, one horizontal period for applying a high-precision voltage that enables multicoloring to the liquid crystal is, in the case of the SC-DAC,
It needs to be about 18 μs.

In order to promote multicolor and high definition, the above two conditions must be satisfied. However, the present conditions for multicolor and high definition are inconsistent. Therefore, the current method cannot realize multi-gradation in S-XGA display.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide an active matrix type liquid crystal display for realizing a multi-color and high definition TFT active matrix type liquid crystal display device. It is to provide a source driver for driving a display device.

[0038]

In order to achieve the above object, a source driver for driving a TFT active matrix type liquid crystal display device according to the present invention is compatible with multi-color and high definition TFT active matrix type liquid crystal display devices. hand,
A highly accurate voltage can be applied to the liquid crystal in a short horizontal period. More specifically, an SC-D having an offset cancel function in a source driver is provided.
In the AC circuit, the first operation state for storing the offset voltage of the operational amplifier in the SC-DAC is realized once per frame or only once in several horizontal periods, and thereafter, the second output state is output according to the digital data input. Means for realizing only the second operation state in each of the other horizontal periods.

Further, the switching of the operation state of the SC-DAC is realized by a means for obtaining a signal from the outside or a means for internally counting the number of horizontal periods.

[Summary of the Invention] An SC-DAC having an offset canceling function in a source driver obtains a signal every frame or every several horizontal periods, and switches between a first operation state and a second operation state.

In the first operating state, the SC-DAC
-Acts as a voltage follower for driving the capacitance in the DAC;
The charge corresponding to the offset voltage of the operational amplifier in the C-DAC is stored. After the first operation state is completed, in the second operation state, an analog voltage is applied to the liquid crystal according to the input digital data.

In another horizontal period, only the second operation state is realized.

The horizontal period in which the first operation state and the second operation state are both executed and the horizontal period in which only the second operation state is executed are distinguished by counting the horizontal period internally or externally. I do.

As a result of the above operation, when only the second operation state is performed, a highly accurate voltage can be applied to the liquid crystal even when one horizontal period is 13 μs or less. On the other hand, in a horizontal period in which the first operation state and the second operation state are performed for each frame, time is allowed between frames, so that a highly accurate voltage can be applied to the liquid crystal. Further, in the horizontal period in which the first operation state and the second operation state are performed every several horizontal periods, the horizontal period in which the first operation state and the second operation state are shifted for each frame is shifted on the panel. It can be displayed with high accuracy.

[0045]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] A first embodiment of the present invention will be described. In the first embodiment of the present invention, a switched capacitor type digital-to-analog converter (“SC-DA
C ") has the configuration shown in FIG.
It has level power supplies V1 and V2 and a reference power supply voltage Vr as analog inputs, and has input capacitors C0 to Cn having a ratio corresponding to the number of bits of input digital data, and an output capacitor Cos connected to an output. Further, an operational amplifier 15 in which the wiring in which the input capacitance and the output capacitance are connected in parallel is an inverting input and the reference power supply voltage Vr is a non-inverting input, and the connection between the level power supplies V1, 2 and the input capacitance is changed according to the input digital data Switches S1 to Sn and SW1 to SW5 for switching the operation state of the SC-DAC are provided.

The timing chart of the operation of the conventional SC-DAC shown in FIG. 13 is shown in FIG. 17 as described above. The output timing signal of FIG. 17 indicates the timing of switching SW2 related to the connection with the liquid crystal panel load. The SC-DAC state switch signal is S
The timing of a signal related to the switching and on / off of W1, SW3, SW4, and SW5 is shown, and the first operating state and the second operating state are switched according to this timing. As described above, the first operating state uses the operational amplifier 15 as a voltage follower and operates with a light load C0.
To drive Cn and Cos, it takes several μs for the output of the operational amplifier 15 to stabilize. Therefore, if one horizontal period is set to 13 μs in accordance with the S-XGA panel, the second operation state becomes 10 μs or less.
An accurate voltage cannot be applied to the liquid crystal.

FIG. 1 shows a timing chart of Example 1 according to the first embodiment of the present invention. Example 1
Takes advantage of the fact that it takes much longer than the normal interval of one horizontal period at the boundary between frames, and executes the first operation state only once in one frame. Without the first operating state,
The switch connection is changed according to the digital data in the second operation state. At this time, the second operation state can be set in most of one horizontal period, and sufficient time can be taken for applying a highly accurate voltage to the liquid crystal.

Conventionally, the contents of the above operation are as follows. In each horizontal period, the charge corresponding to the offset voltage of the operational amplifier 15 is accumulated in each capacitor of the SC-DAC in the first operation state, and the digital charge is accumulated in the second operation state. Although the analog voltage is output by distributing according to the data, in the first embodiment of the present invention, S
An electric charge corresponding to the offset voltage of the operational amplifier 15 is accumulated in each capacitance of the C-DAC, and during one frame, an analog voltage is output by distributing the accumulated charge between the frames to each capacitance. I have.

According to the first embodiment of the present invention, S-
If one horizontal period is set to 13 μs in accordance with the XGA panel, the first operation state is not required in each horizontal period, and the output timing signal is used for switching digital data.
Since only a time width of about μs is required, 12 μs is applied to apply a voltage to the liquid crystal within 13 μs in one horizontal period, so that a highly accurate voltage can be applied to the liquid crystal. Also, when realizing the first operation state between frames, utilizing the fact that sufficient time can be taken between frames, if the horizontal period is extended only between frames, the output between frames will also be accurate. Voltage can be applied to the liquid crystal.

The source driver according to the first embodiment of the present invention has a block configuration as shown in FIG. 3, and in addition to the output timing signals used so far, the SC-DAC of the SC-DAC is externally provided for each frame. It can be realized by inputting a signal for switching the operation state (state switching signal) and using a circuit as shown in FIG.

The circuit shown in FIG. 4 is an example of a circuit configuration for realizing the operation of the first embodiment shown in FIG. It has a simple configuration in which an output timing signal and a signal for switching the operation state of the SC-DAC for each frame are input, and a NOR gate NOR1 and an inverter INV1 are used internally.

FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. An output timing signal IN1 having a short width and a signal IN2 for each frame having such a width as to stabilize the output of the voltage follower in the first operating state by the operational amplifier 15 (see FIG. 13) are input to the NOR gate NOR1. . SC for each frame
In the case of a horizontal period between frames in which a signal for switching the operation state of the DAC is H and an output timing signal is also H at the same time, the SC-DAC for each frame is used.
The output O1 having the value of the signal for switching the operation state is obtained. In the case of another horizontal period, SC-D for each frame
A signal whose AC operation state is switched is fixed at L and a signal whose output timing signal is H is input and an output O1 having the same short width as the output timing signal is obtained.

If the output O1 is used as a new output timing signal and the signal for switching the operation state of the SC-DAC for each frame is used as the signal for switching the operation state of the SC-DAC, the second embodiment of the present invention shown in FIG. The operation of the embodiment can be realized.

However, the offset voltage stored in each capacitor in the first operation state performed once per frame continues to be accurately stored until the offset voltage is stored again in the first operation state executed in the next frame. If not, SC-DA
This causes a decrease in the accuracy of the output voltage of C, and lowers the quality of the display panel. To do so, the stored voltage (charge)
Is not changed by a MOS transistor or metal capacitor with high impedance and low leakage,
A DAC needs to be configured.

FIG. 2 shows an operation timing chart of another example of the first embodiment of the present invention.

The example shown in FIG. 2 is similar to the example shown in FIG.
In addition to the conventional output timing signal, it can be realized by introducing a signal having a width such that the output of the voltage follower in the first operation state is stabilized every several horizontal periods. However, a signal having such a width as to stabilize the output of the voltage follower has an H period for each horizontal period in which the output accuracy of the SC-DAC having the offset cancel function does not decrease due to leakage.

Also in this case, a signal having a width in which the output of the voltage follower in the first operating state is stabilized is expressed as follows:
The first operation state and the second operation state are executed in the horizontal period having the H output, and only the second operation state is executed in the horizontal period having the L output. Furthermore, the horizontal period in which both the first and second operations are performed is not always the horizontal period in which the TFTs in the row on the same liquid crystal panel are turned on.
This is a horizontal period in which TFTs in different rows on the liquid crystal panel are turned on for each frame.

By performing the above operation, 6 seconds
In the case of a panel that operates with 0 frames, an arbitrary row on the liquid crystal panel performs (1) the first operation state and the second operation state only for a certain one frame in one second, and in the other 59 frames, Execute only the second operation state, or (2) 6
Execute only the second operation state in the case of all 0 frames,
Will be one of In the case of the above (2), since the time for applying the voltage to the liquid crystal is long, a highly accurate voltage can be applied to the liquid crystal.

In the case of the above (1), it is considered that the accuracy is somewhat reduced in the frames in which the first and second operating states are performed, but in the other frames, the application time is sufficiently long, so that the voltage with the high accuracy is required. Can be applied to the liquid crystal,
A decrease in display quality on the display panel can be avoided.

In the example shown in FIG. 2, since the signal for changing the operation state is fetched from the outside, the timing operation can be realized with the circuit configuration shown in FIG.

In the example shown in FIG. 1, the first operation of storing the offset cancellation of the differential amplifier in the SC-DAC is performed once per frame, but the leak of the circuit does not lower the output accuracy. Was a condition.
However, there is a possibility that some leaks actually exist, and it is considered that sufficient accuracy cannot be obtained for each frame. On the other hand, the example shown in FIG. 2 has an advantage that the problem of the leak can be avoided by performing the first operation only in a few horizontal periods within one frame in accordance with the leak.

[Second Embodiment] FIG. 6 shows a block configuration of a second embodiment of the present invention.

In the first embodiment, the first operation state is performed in accordance with an external signal. In this embodiment, however, the provision of the circuit 6 for counting the output timing signal in the device allows the external operation to be performed. The operation of Example 1 of the first embodiment is performed without receiving a signal for switching the state of the SC-DAC once per frame, and only the second operation state is performed in other horizontal periods. Thus, it is possible to apply an accurate voltage to the liquid crystal in a short horizontal period.

An example of the circuit configuration in this embodiment is shown in FIGS.

Referring to FIG. 7, a circuit 7 for modifying the waveform so that the short width of the output timing signal has a width in which the voltage follower output of the SC-DAC is stabilized (for details, see FIG. 8).
), A circuit 8 for counting the deformed waveforms (see FIG. 9 for details), a NAND signal of the outputs of the two circuits, an inverted signal, and an external output timing signal.
And a circuit 5 for generating a new output timing signal described in the first embodiment as an input (see FIG. 4).

FIG. 8 shows an example of the circuit 7 for modifying the waveform so that the short width of the output timing signal has a width in which the voltage follower output of the SC-DAC in the first embodiment has a stable width. Referring to FIG. 8, this circuit 7
Uses a delay circuit and a NOR gate. The advantages of this circuit configuration are that the configuration is simple and that the width of the waveform after deformation can be freely selected. If the NOR gate has two inputs, it can be deformed only up to about twice the width of the output timing signal.
By increasing the number of delay circuits as an input, the waveform can be deformed up to three times or four times the width of the timing signal.

The circuit 8 for counting the waveforms having different widths
It comprises a toggle flip-flop and a NOR gate.

FIG. 9 shows an example of a circuit configuration of the count circuit 8 for a signal in which the width of the output timing signal is changed in the case of the S-XGA panel, and an operation timing chart thereof.

The number of pixels in the case of the S-XGA panel is 102
Since it is 4 × 768, one frame is 768 horizontal periods. Therefore, in order to realize the first operation state once per frame, the counter needs 10 bits by a binary counter, and the output of the counter in the case where the signal whose width of the output timing signal is changed is counted 767 times is counted. Is detected. However, the width of the signal detected using the toggle flip-flop 9 is the width of one horizontal period.

As shown in FIG. 7, the output of a circuit 7 for generating a signal having a changed width of the output timing signal and the output of a circuit 8 for counting the signal having a changed width of the output timing signal are supplied to a NAND gate and an inverter. By inputting, an SC-DAC state switching signal is generated and SC-DAC is generated.
By inputting the DAC state switching signal and the output timing signal to the two-input NOR gate, the SC input from the outside once per frame in the second embodiment of the present invention.
A signal corresponding to the signal for bringing the DAC into the first operating state can be generated;

By inputting this signal together with the output timing signal to the same circuit as the circuit for generating a new output timing signal described in the first embodiment, the implementation of the first embodiment is achieved. The same operation as in Example 1 can be performed. Therefore, in the second embodiment of the present invention, a highly accurate voltage can be applied to the liquid crystal in a short horizontal period without introducing a special signal from the outside.

Another example of the second embodiment of the present invention will be described. In this example, the count number of the count circuit 8 is set to a value corresponding to several horizontal periods in which the leakage of the SC-DAC circuit does not lower the output accuracy, thereby providing the same state as the example 2 of the first embodiment in the first state. Can work. Therefore, in another example of the second embodiment of the present invention, a highly accurate voltage can be obtained in a short horizontal period similar to that of the second embodiment of the above embodiment without introducing a special signal from the outside. Can be applied to the liquid crystal.

[0074]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that in an SC-DAC circuit having an offset cancel function of a source driver for driving a TFT active matrix type liquid crystal display device, a horizontal period for outputting without reducing accuracy can be shortened. It is.

The reason is that, in the present invention, since the offset cancel operation is performed once in one frame or several horizontal periods, the time for applying the voltage to the liquid crystal can be extended in other horizontal periods.

A second effect of the present invention is that the first effect can be realized without using a new signal input in addition to the output timing signal conventionally taken in.

The reason is that in the present invention, a circuit for changing the width of the output timing signal, a circuit for counting the output timing signal, and a circuit for generating a new output timing signal are provided in the source driver.

[Brief description of the drawings]

FIG. 1 is a timing chart of Example 1 according to the first embodiment of the present invention.

FIG. 2 is a timing chart of Example 2 according to the first embodiment of the present invention.

FIG. 3 is a block diagram of the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an output signal generation circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart of the output signal generation circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a block diagram of a counter circuit according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a circuit that changes the width of an input signal according to a second embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of an input signal counting circuit according to a second embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a liquid crystal display device.

FIG. 11 is a diagram showing an internal configuration of a TFT type liquid crystal display panel.

FIG. 12 is a block diagram showing a configuration of a conventional source driver.

FIG. 13 shows a conventional SC- with an offset cancel function.
FIG. 3 is a diagram illustrating a DAC circuit.

FIG. 14 is a diagram showing a conventional output timing waveform.

FIG. 15 is a diagram illustrating a first operation state of the SC-DAC circuit.

FIG. 16 is a diagram showing a voltage waveform at a point α in the first operation state of the SC-DAC circuit.

FIG. 17 is a diagram illustrating a first operation state of the SC-DAC circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Shift register block in source driver 2 Data register block in source driver 3 Latch block in source driver 4 D / A converter block in source driver 5 Output signal generating circuit 6 used in Embodiment 1 of the present invention A counter block used in the second embodiment of the present invention A circuit for changing the width of an input signal constituting the counter block of 76 An input signal counting circuit constituting a counter block of 86 Toggle flip-flop constituting a count circuit of 8 10 Liquid crystal display panel 11 γ correction circuit 12 Signal conversion circuit 13 Gate driver 14 Source driver 15 Operational amplifier in SC-DAC

Claims (3)

(57) [Claims] 1. A switched capacitor type digital-analog converter (hereinafter referred to as "SC-DAC") having an offset canceling function for higher accuracy in a source driver for driving an active matrix type liquid crystal display device. The first operation state in which the offset voltage of the operational amplifier in the DAC is stored is performed only once in one frame or once in several horizontal periods, and then the second operation state in which an analog signal is output according to digital data input And a means for controlling so as to perform only the second operation state in each of the other horizontal periods.
A semiconductor device for driving an active matrix type liquid crystal display device. Wherein a circuit for counting the output timing signal from the outside, the timing generation circuit and a semiconductor device of a TFT active matrix liquid crystal display device for driving according to claim 1, further comprising a. 3. A horizontal period in which both the first operation state and the second operation state are executed, and a horizontal period in which only the second operation state is executed, are defined by an external signal or an internal horizontal period. 2. The semiconductor device for driving a TFT active matrix type liquid crystal display device according to claim 1 , wherein the semiconductor device is distinguished by counting.