JP2007003967A - Display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce or eliminate adverse effects, such as color shifts and blurrs caused by parasitic capacitance etc. between adjoining video signal lines in a simple device configuration, while adopting a time-sharing driving system of the video signal lines. <P>SOLUTION: A potential variation amount caused by the parasitic capacitance between video signal lines is set to a desired value, by setting the parasitic capacitance of three analog switches of one group in a liquid crystal panel to an appropriate value. Hence, the potential variations amounts caused by the parasitic capacitance of the video signal lines connected to pixel forming sections of red and green, are set to be equal. A voltage, corresponding to a correction voltage signal Vcb in which the potential variation amount is added, is applied to the video signal line, connected to the pixel forming section of blue from a voltage generation circuit 320 of a drive circuit 300 of the video signal line. Consequently, since the potential variational amounts for each video signal line are made approximately equal, as a result, display quality deterioration, such as the display color shift and blurrs over the whole screen, is reduced or eliminated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix display device, and more specifically, a plurality of video signal lines (for example, three) for transmitting a video signal to a plurality of pixel forming portions for forming an image to be displayed. ) Is grouped into a plurality of video signal line groups, and a video signal is output in a time division manner from a drive circuit for each grouped video signal line group.

  In recent years, the progress of high definition display images in display devices has been remarkable. For this reason, in a display device that requires a number of signal lines (column electrodes or row electrodes) corresponding to the resolution of an image to be displayed, such as an active matrix liquid crystal display device, the display image has become higher in definition. Therefore, the number of signal lines (number of electrodes) per unit length becomes enormous. As a result, in the mounting of the drive circuit that applies signals to these signal lines, the pitch of the connection portion between the output terminal of the drive circuit and the signal line of the display panel (hereinafter referred to as “connection pitch”) becomes extremely small. The tendency of the connection pitch to become narrower as the display image becomes higher in definition has a display unit of three adjacent pixels of R (red), G (green), and B (blue) as in a color liquid crystal display device. In the case of a color display device, particularly at the connection between a video signal line (column electrode) and its drive circuit (referred to as a “column electrode drive circuit”, “data line drive circuit” or “video signal line drive circuit”). Become prominent.

  In order to solve such a problem, two or more video signal lines (for example, three video signal lines corresponding to adjacent three pixels of R, G, B) are grouped into one set, and each video signal line is grouped. One output terminal of the video signal line driving circuit is assigned to a plurality of video signal lines constituting the group, and a video signal is applied to the video signal lines in each group in a time division manner within one horizontal scanning period in image display. Conventionally, a liquid crystal display device configured as described above has been proposed (see, for example, Japanese Patent Laid-Open No. 6-138851).

  FIG. 2A shows a video signal line and its driving circuit (hereinafter referred to as “video signal line driving circuit”) in an active matrix type liquid crystal display device of such a system (hereinafter referred to as “video signal line time division driving system”). The structure of the connection part is shown schematically. In the example shown in this figure, three video signal lines Ls are grouped as one set, and the output terminals TS1, TS2, and TS2 of the video signal line driving circuit 300 are associated with the video signal line group constituting each set. TS3,... Are associated one by one. A changeover switch is provided between the grouped three video signal lines corresponding to the output terminals TS1, TS2, TS3,... Of the video signal line driving circuit 300. Each selector switch is provided for each video signal line Ls, and one of the analog switches SW1, SW2, SW3,..., One end of which is connected to the video signal line Ls, is adjacent to three analog switches SW (3j-2), SW ( 3j-1) and SW3j (j = 1, 2, 3,...). The other ends of the three analog switches SW (3j-2), SW (3j-1), SW3j constituting each changeover switch are connected to each other, and the output terminal of the video signal line driving circuit 300 corresponding to the changeover switch. Connected to TSj. These change-over switches are realized by, for example, analog switches using thin film transistors (TFTs) formed on a liquid crystal panel substrate in the display device.

  4 shows scanning signals G1, G2, G3,..., Control signals (hereinafter referred to as “switching control signals”) GSa to GSC, and video signal lines in the video signal line time-division driving type liquid crystal display device. It is a timing chart which shows the video signal applied to SL1-SL6. Here, when the scanning signal Gk is at a high level (H level), the kth scanning signal line is selected, and when the scanning signal Gk is at a low level (L level), the kth scanning signal line is not selected. Assume that k = 1, 2, 3,... In addition, each change-over switch has three output terminals TSj of the video signal line driving circuit 300 corresponding to the three video signals when the switch control signal GSa is at the H level (and the switch control signals GSb and GSc are at the L level). When the switching control signal GSb is at the H level (and the switching control signals GSa and GSc are at the L level) when connected to the left video signal line Ls (in FIG. 4) of the signal lines, the video signal line driving circuit 300 Each output terminal TSj is connected to the central video signal line among the three corresponding video signal lines. When the switching control signal GSc is at the H level (and the switching control signals GSa and GSb are at the L level), the video is output. Each output terminal TSj of the signal line driving circuit 300 is connected to the right video signal line among the three video signal lines corresponding thereto.

  As described above, in this liquid crystal display device, the video signal lines to which the output terminals TSj are connected are switched within one horizontal scanning period, that is, a period in which one scanning signal line is selected, thereby constituting each set. Of the three video signal lines, in the first period when each horizontal scanning period is divided into three equal periods from the first to the third period, the left video signal line is connected to the second period of each horizontal scanning period. The video signal from the video signal line driving circuit is applied to the central video signal line and to the right video signal line in the third period of each horizontal scanning period. Thereby, each video signal line Ls is charged with the voltage of the video signal output from the output terminal TSj while the output terminal TSj of the video signal line driving circuit 300 is connected to the video signal line Ls. The voltage value is written as a pixel value in the pixel formation portion Px corresponding to the intersection of the video signal line and the selected scanning signal line.

In the video signal line time-division drive type liquid crystal display device as described above, the charging time to each video signal line is shortened according to the number of video signal lines constituting each set, that is, the number of time divisions by the changeover switch, If the number of time divisions is m, the charging time of each video signal line is 1 / m in the case of a normal liquid crystal display device that is not a video signal line time division drive system (in the example shown in FIG. 2, 1/3). Becomes). However, by forming the change-over switch with the time division number m on the liquid crystal panel substrate, the connection pitch between the output terminal of the video signal line driving circuit and the video signal line is m times that of a normal liquid crystal display device. can do. Further, with such a configuration, when a video signal line driving circuit composed of a plurality of integrated circuit chips (IC chips) is used for driving one liquid crystal panel, the number of chips can be reduced. The advantages of such a video signal line time-division drive method are widely known, and the video signal line grouping for this purpose is performed on three adjacent pixels of R (red), G (green), and B (blue). In many cases, three video signal lines for transmitting signals are grouped as a set.
Japanese Patent Laid-Open No. 6-138851 JP-A-6-250146 Japanese Patent Laid-Open No. 2000-2867 JP 2003-58119 A JP 2003-233086 A

  However, in such a video signal line time-division driving type liquid crystal display device, the voltage of the video signal to be written to the pixel formation portion Px varies due to the parasitic capacitance between the adjacent video signal lines. Hereinafter, this phenomenon will be described with reference to the drawings.

  FIG. 7 is a diagram showing in detail the potential change of the video signal applied to the video signal lines SL3 to SL5 of the conventional liquid crystal display device shown in FIG. For the sake of explanation, the figure shows the amount of voltage fluctuation caused by the parasitic capacitance or the like larger than the actual fluctuation amount. Here, paying attention to the potential change of the video signal line SL4, the video signal line SL4 is applied to the video signal line SL4 from the video signal line driving circuit at time t1, so that the potential of the video signal line SL4 becomes a desired potential. Ideally, when this potential is held, the voltage value must be written as a pixel value in the corresponding pixel formation portion Px.

  However, when a video signal is applied to the video signal line SL5 from the video signal line driver circuit at time t2, the potential of the video signal line SL4 to be held also changes according to the potential change of the video signal line SL5. This is because the video signal lines SL4 and SL5 are capacitively coupled. The parasitic capacitance between the adjacent video signal lines includes a direct capacitance between the signal lines and an indirect capacitance formed via the pixel formation portion.

  Since the video signal lines SL3 and SL4 are also capacitively coupled, when a video signal is applied to the video signal line SL3 from the video signal line driving circuit at time t3, the video signal lines SL3 and SL4 correspond to changes in the potential of the video signal line SL3. The potential of the video signal line SL4 changes. As a result, the potential difference ΔV4 is ideally generated between the potential to be held and the actual potential, thereby causing undesirable effects such as a shift in display color (here, red and green) and blurring.

  Here, since one horizontal scanning period is a period from the time t1 to the time t4, the voltage value changed after the video signal is applied to the video signal line SL3 from the video signal line driving circuit at the time t3 is a corresponding pixel. It is not written as a pixel value in the formation part Px. Therefore, no blue shift occurs.

  Note that the display color shift in this specification is the luminance balance (luminance ratio) of red (R), green (G), and blue (B) in the original ideal display color (given from the outside of the apparatus). The display color shift does not occur in the visual sense when the luminance increases or decreases while maintaining this balance.

  The potential difference ΔV4 as described above similarly occurs in the video signal line SL4 at time t7, and the potential of the video signal line SL5 is ideally the potential difference ΔV5 between the potential to be held and the actual potential for the same reason. As a result, undesired effects such as display color shift and blurring occur over the entire screen.

  In this regard, there is a conventional liquid crystal display device having a liquid crystal panel in which the parasitic capacitance between pixel electrodes of adjacent pixel formation portions is set to have different values in each display row (see, for example, Japanese Patent Application Laid-Open No. 2003-233086). ). With this configuration, unfavorable influences such as the display color shift and blurring are scattered over the entire screen, so that the unfavorable influences are reduced as a whole.

  However, in this conventional liquid crystal display device, it is necessary to use a special liquid crystal panel that is arranged so that the distances between the pixel electrodes in the adjacent pixel forming portions are different from each other. .

  Therefore, in the present invention, while adopting the video signal line time-division driving method as described above, display quality deterioration such as display color shift and blurring over the entire screen caused by parasitic capacitance between adjacent video signal lines can be easily performed. An object of the present invention is to provide a display device that can be reduced or eliminated with a simple device configuration.

A first invention provides a plurality of pixel forming portions for forming an image to be displayed and a plurality of video signal lines for transmitting a plurality of video signals indicating the image to be displayed to the plurality of pixel forming portions. And a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of pixel forming portions correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively, in a matrix form An active matrix type display device arranged in
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines;
Video having a plurality of output terminals respectively corresponding to a plurality of sets of video signal lines obtained by grouping the plurality of video signal lines with three or more video signal lines as one set, and a video corresponding to each output terminal A video signal output circuit that outputs a video signal to be transmitted by the signal line group from the output terminal in a time-sharing manner within a predetermined period; and
By connecting each output terminal of the video signal output circuit to any video signal line in the corresponding video signal line group, the connected video signal line and the scanning signal line selected by the scanning signal line driving circuit A connection switching circuit that provides the video signal to the pixel forming section connected to the video signal and switches the video signal line to which each output terminal is connected within the corresponding video signal line group according to the time division,
The connection switching circuit generates a potential change in accordance with a potential change of an adjacent video signal line within the predetermined period after being connected to the output terminal in the video signal line group of one set. It has a parasitic capacitance that has a predetermined value so that the amount of potential change of the video signal line is almost equal,
The video signal output circuit is a voltage of a video signal to be transmitted by a video signal line that does not cause a potential change according to a potential change of an adjacent video signal line within the predetermined period after being connected to the output terminal. Is corrected by an amount substantially equal to the amount of potential change.

According to a second invention, in the first invention,
The connection switching circuit includes a plurality of analog switches each connected to correspond to each of the video signal lines and including one or more transistors,
The plurality of analog switches include two or more types of transistors having different parasitic capacitances depending on video signal lines to be connected.

According to a third invention, in the second invention,
The transistor includes a drain region and a source region having a predetermined area, and a gate region provided between the drain region and the source region and having a predetermined width and length.
The plurality of analog switches include two or more types of transistors having different lengths of the drain region and the source region along the width direction of the gate region according to a video signal line to be connected. .

According to a fourth invention, in the first invention,
The video signal output circuit includes:
A shift register circuit for outputting a predetermined sampling pulse;
A data latch circuit that latches data indicating a pixel value to be given to the pixel forming unit included in a plurality of video signals indicating the image to be displayed by receiving a sampling pulse output from the shift register circuit;
A D / A conversion circuit that converts the digital data latched by the data latch circuit into an analog voltage signal and outputs the analog voltage signal;
An output buffer circuit for outputting the analog voltage signal output from the D / A conversion circuit to a video signal line connected to the output terminal;
Among the analog voltage signals output from the D / A conversion circuit, a video signal line that does not change in potential in response to a change in potential of an adjacent video signal line within the predetermined period after being connected to the output terminal. A voltage generation circuit that outputs a correction voltage signal that is a signal having a voltage obtained by adding a voltage change amount substantially equal to the voltage change amount to a voltage of an analog signal corresponding to the video signal to be transmitted by
The output buffer circuit outputs the correction voltage signal output from the voltage generation circuit from the output terminal.

According to a fifth invention, in any one of the first to fourth inventions,
The video signal output circuit includes a plurality of sets obtained by grouping the plurality of video signal lines with a group of three adjacent video signal lines respectively connected to three types of pixel forming portions that display predetermined three primary colors. A plurality of output terminals respectively corresponding to the video signal line groups, and video signals to be transmitted by the video signal line groups corresponding to the respective output terminals are output from the output terminals in a time division manner.

  According to the first invention, first, the parasitic capacitance of the connection switching circuit is set to an appropriate value in advance, so that the potential changes in accordance with the potential change of the adjacent video signal line within a predetermined period after being connected to the output terminal. The amount of change in potential of two or more video signal lines that cause the above is made substantially equal. Further, the video signal output circuit supplies the voltage of the video signal to be transmitted by the video signal line that does not cause a potential change according to the potential change of the adjacent video signal line within a predetermined period after being connected to the output terminal. Correction is made with an amount approximately equal to the potential change amount. As a result, almost the same amount of potential change occurs in all the video signal lines. As a result, display over the entire screen (for example, display color shift, blurring, vertical stripes, etc.) with a simple device configuration. Deterioration of quality can be reduced or eliminated.

  According to the second invention, the connection switching circuit includes a plurality of analog switches including one or more transistors, and the plurality of analog switches include two or more types of transistors having different parasitic capacitances according to the video signal lines to be connected. Therefore, by appropriately setting the parasitic capacitance of this transistor, for example, the parasitic capacitance between the gate and the drain or between the source and the drain, an image that easily changes its potential according to the potential change of the adjacent video signal line. The amount of change in potential of the signal line can be made substantially equal.

  According to the third invention, the plurality of analog switches include two or more types of transistors in which the lengths of the drain region and the source region along the width direction of the gate region differ according to the connected video signal line. By appropriately setting the length, it is possible to easily set an appropriate parasitic capacitance according to the video signal line to be connected.

  According to the fourth invention, a video to be transmitted by a video signal line that does not cause a potential change in accordance with a potential change of an adjacent video signal line within a predetermined period after being connected to the output terminal by the voltage generation circuit. The voltage of the analog signal corresponding to the signal is corrected. Thus, by using the voltage of the analog voltage signal output from the D / A conversion circuit as a reference, an accurate correction operation without error can be performed.

  According to the fifth aspect of the present invention, a set of three adjacent video signal lines respectively connected to the three types of pixel forming portions for displaying predetermined three primary colors is used as a set, so that adjacent video signals in a general color display device. It is possible to reduce or eliminate the deterioration of the color display quality such as a display color shift or blur due to a parasitic capacitance between lines.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
<1. Configuration and operation of liquid crystal display device>
<1.1 Overall configuration and operation>
FIG. 1A is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display device includes a display control circuit 200, a video signal line driving circuit (also referred to as “column electrode driving circuit”) 300, a scanning signal line driving circuit (also referred to as “row electrode driving circuit”) 400, an active matrix. Type liquid crystal panel 500.

  A liquid crystal panel 500 as a display unit in the liquid crystal display device includes a plurality of scanning signal lines (row electrodes) each corresponding to a horizontal scanning line in an image represented by image data Dv received from a CPU or the like in an external computer. A plurality of video signal lines (column electrodes) intersecting with each of the plurality of scanning signal lines, and a plurality of video signal lines provided corresponding to the intersections of the plurality of scanning signal lines and the plurality of video signal lines, respectively. A pixel formation portion. The configuration of each pixel formation portion is basically the same as that in a conventional active matrix liquid crystal panel (details will be described later).

  In the present embodiment, image data (in a narrow sense) representing an image to be displayed on the liquid crystal panel 500 and data for determining the timing of a display operation (for example, data indicating the frequency of a display clock) (hereinafter referred to as “display control data”). Are sent to the display control circuit 200 from a CPU or the like in an external computer (hereinafter, these data Dv sent from the outside are referred to as “broadly defined image data”). That is, an external CPU or the like supplies (in a narrow sense) image data and display control data constituting the image data Dv in a broad sense to the display control circuit 200 by supplying an address signal ADw, and the display described later in the display control circuit 200. Write to memory and register respectively.

  The display control circuit 200, based on the display control data written in the register, drives the source clock signal SCK and the source start pulse signal SSP given to the video signal line drive circuit 300 for display, and scan signal line drive for display. Various signals including a gate clock signal GCK and a gate start pulse signal GSP supplied to the circuit 400 are generated. Since these signals are publicly known, detailed description is omitted. Further, the display control circuit 200 reads out (narrowly defined) image data written in the display memory by an external CPU or the like from the display memory and outputs it as a digital image signal Da. Furthermore, the display control circuit 200 generates switching control signals GSa to GSc (hereinafter, these signals are also referred to as “switching control signals GS”) for time-division driving of the video signal lines, and outputs these.

  Thus, among the signals generated by the display control circuit 200, the digital image signal Da is in the video signal line driving circuit 300, and the switching control signals GSa to GSc are in the video signal line driving circuit 300 and the liquid crystal panel 500, which will be described later. To the connection switching circuit. Note that as the signal lines for supplying the digital image signal Da from the display control circuit 200 to the video signal line driving circuit 300, signal lines corresponding to the number of gradations of the display image are arranged.

  As described above, the video signal line driving circuit 300 is supplied with data representing an image to be displayed on the liquid crystal panel 500 serially as a digital image signal Da in units of pixels, and a source clock as a signal indicating timing. A signal SCK, a source start pulse signal SSP, and a switching control signal GS are supplied. The video signal line driving circuit 300 is based on the digital image signal Da, the source clock signal SCK, the source start pulse signal SSP, and the switching control signal GS, and the video signal (hereinafter referred to as “drive”). A video signal ”), which is applied to each video signal line of the liquid crystal panel 500.

  When generating this driving video signal, the video signal line driving circuit 300 reduces a specific video signal line in order to reduce or eliminate the influence of display color shift and blurring due to parasitic capacitance between adjacent video signal lines. An operation for correcting only the voltage applied to the signal is performed. This operation will be described later.

  Based on the gate clock signal GCK and the gate start pulse signal GSP, the scanning signal line drive circuit 400 should be applied to each scanning signal line in order to sequentially select the scanning signal lines in the liquid crystal panel 500 by one horizontal scanning period. Scan signals G1, G2, G3,... Are generated, and application of active scanning signals for sequentially selecting all the scanning signal lines to each scanning signal line is repeated with one vertical scanning period as a cycle.

  In the liquid crystal panel 500, the video signal lines S1, S2, S3,... Based on the digital image signal Da are applied to the video signal lines by the video signal line driving circuit 300 as described above, and the scanning signal lines are Scan signals G1, G2, G3,... Are applied by the scan signal line driving circuit 400. Thereby, the liquid crystal panel 500 displays an image represented by the image data Dv received from an external CPU or the like.

<1.2 Display control circuit>
FIG. 1B is a block diagram showing a configuration of the display control circuit 200 in the liquid crystal display device. The display control circuit 200 includes an input control circuit 20, a display memory 21, a register 22, a timing generation circuit 23, a memory control circuit 24, and a signal line switching control circuit 25.

  A signal indicating image data Dv in a broad sense received by the display control circuit 200 from an external CPU or the like (hereinafter, this signal is also denoted by “Dv”) and an address signal ADw are input to the input control circuit 20. . The input control circuit 20 distributes the image data Dv in a broad sense into the image data DA and the display control data Dc based on the address signal ADw. Then, the image data DA is supplied to the display memory 21 together with the address signal AD based on the address signal ADw by supplying a signal representing the image data DA (hereinafter, these signals are also represented by the symbol “DA”). And display control data Dc is written to the register 22. The display control data Dc includes timing information that specifies the frequency of the clock signal including the source clock signal SCK and the horizontal scanning period and the vertical scanning period for displaying the image represented by the image data Dv.

  A timing generation circuit (hereinafter abbreviated as “TG”) 23 generates a source clock signal SCK and a source start pulse signal SSP based on the display control data held in the register 22. The TG 23 generates a timing signal for operating the display memory 21 and the memory control circuit 24 in synchronization with the source clock signal SCK.

  The memory control circuit 24 reads an address signal ADr for reading out data representing an image to be displayed on the liquid crystal panel 500 from the image data DA input from the outside and stored in the display memory 21 via the input control circuit 20; A signal for controlling the operation of the display memory 21 is generated. These address signal ADr and control signal are supplied to the display memory 21, whereby data representing an image to be displayed on the liquid crystal panel 500 is read from the display memory 21 as the digital image signal Da and output from the display control circuit 200. Is done. The digital image signal Da is supplied to the video signal line driving circuit 300 as described above.

  The signal line switching control circuit 25 generates switching control signals GSa to GSc for time division driving of the video signal lines based on the timing signal from the TG 23. The switching control signals GSa to GSc are used for one video scanning line to which the video signal output from the video signal line driving circuit 300 is applied in one horizontal scanning period in order to drive the video signal line in a time-sharing manner as will be described later. It is a control signal for switching within. In this embodiment, as shown in FIG. 4, each horizontal scanning period (period in which the scanning signal is active) is H level in the first period when the first to third periods are equally divided into three levels. A signal that becomes L level in the period is generated as the switching control signal GSa, and a signal that becomes H level in the second period and becomes L level in the other periods is generated as the switching control signal GSb, and becomes H level in the third period. A signal that becomes L level in other periods is generated as the switching control signal GSc.

<1.3 LCD panel and its driving method>
<1.3.1 Configuration of liquid crystal panel>
FIG. 2A is a schematic diagram showing a configuration of the liquid crystal panel 500 in the present embodiment similar to the conventional configuration, and FIG. 2B is a part of this liquid crystal panel (a portion corresponding to 4 pixels). 510 is an equivalent circuit diagram, and FIG. 2C is an equivalent circuit diagram showing a changeover switch constituting a connection changeover circuit 501 described later in the liquid crystal panel.

  A liquid crystal panel similar to this conventional configuration includes a plurality of video signal lines Ls connected to the video signal line drive circuit 300 via a connection switching circuit 501 including analog switches SW1, SW2, SW3,. A plurality of scanning signal lines Lg connected to the circuit 400, and the video signal lines Ls and the scanning signal lines Lg intersect each other. Are arranged in a grid pattern. As described above, a plurality of pixel formation portions Px are provided corresponding to the intersections of the plurality of video signal lines Ls and the plurality of scanning signal lines Lg, respectively. As shown in FIG. 2B, each pixel forming portion Px includes a TFT 10 having a source terminal connected to the video signal line Ls passing through the corresponding intersection, and a pixel electrode Ep connected to the drain terminal of the TFT 10. A counter electrode Ec provided in common to the plurality of pixel formation portions Px; a liquid crystal layer provided in common to the plurality of pixel formation portions Px and sandwiched between the pixel electrode Ep and the counter electrode Ec; Consists of. A pixel capacitor Cp is formed by the pixel electrode Ep, the counter electrode Ec, and the liquid crystal layer sandwiched therebetween.

  The pixel forming portions Px as described above are arranged in a matrix to form a pixel forming matrix. By the way, the pixel electrode Ep, which is the main part of the pixel forming portion Px, can be viewed in one-to-one correspondence with the pixels of the image displayed on the liquid crystal panel. Therefore, in the following, for convenience of explanation, the pixel formation portion Px and the pixel are regarded as the same, and the “pixel formation matrix” is also referred to as “pixel matrix”.

  In FIG. 2A, “R”, “G”, or “B” attached to each pixel formation portion Px represents red, green, or blue as the color of the pixel formed by the pixel formation portion Px. Represents. These colors are typical three primary colors, but may be other three primary colors. In general, in a liquid crystal display device, AC driving is performed in order to suppress deterioration of the liquid crystal and maintain display quality. In this embodiment, as a typical AC driving method, a liquid crystal layer that forms a pixel is used. It is assumed that a so-called line inversion driving method is employed in which the positive / negative polarity of the applied voltage is inverted every scanning signal line and every frame. Further, instead of this line inversion driving method, a frame inversion driving method which is a driving method for inverting the positive / negative polarity of the voltage applied to the pixel liquid crystal only for each frame, or for each scanning signal line and for each video signal line. A so-called dot inversion driving method that inverts (and inverts every frame) may be employed.

  As described above, the liquid crystal panel includes analog switches SW1, SW2, and SW3 corresponding to the video signal lines Ls on the liquid crystal panel as parts for connecting the video signal lines Ls to the video signal line driving circuit 300, respectively. ,... Are formed (FIG. 2A), and these analog switches SW1, SW2, SW3,... Have a plurality of sets (one of the video signal lines Ls). 1/3 of the number of analog switches). One end of each analog switch SWi (i = 1, 2, 3,...) Is connected to the video signal line Ls corresponding to the analog switch SWi, and the other end is an analog belonging to the same set as the analog switch SWi. The other ends of the switches are connected to each other and to one output terminal TSj (j = 1, 2, 3,...) In the video signal line driving circuit 300. In this way, the video signal lines Ls in the liquid crystal panel are grouped into a plurality of video signal line groups, with three as one set, and each video signal line group (three video signal lines Ls in the same set). Are connected to one output terminal TSj in the video signal line driving circuit 300 through three analog switches in the same set. In this way, the output terminals TSj of the video signal line driving circuit 300 are associated with the video signal line group on a one-to-one basis, and the same set of video signals are passed through the three analog switches in the same set. Connected to a line group (three video signal lines Ls).

  Here, each analog switch SWi is realized by two thin film transistors (TFTs) and an inverter formed on the liquid crystal panel substrate, and as shown in FIG. 2C, three analog switches SW ( 3j-2), SW (3j-1), and SW3j are configured to be turned on / off in response to the switching control signals GSa to GSc (j = 1, 2, 3,...). Therefore, the three analog switches SW (3j-2), SW (3j-1), and SW3j in each set shown in FIG. 2C constitute a changeover switch, and each output terminal in the video signal line driving circuit 300 TSj is connected in time division to three video signal lines in the video signal line group corresponding to the output terminal. The structure of this analog switch will be further described.

<1.3.2 Configuration of each analog switch>
Each analog switch SWi includes an n-channel TFT, a p-channel TFT, and an inverter (logic inversion circuit). The gate terminal of the n-channel TFT is one of the corresponding switching control signals GSa to GSC. And the gate terminal of the p-channel TFT receives the logically inverted signal of any of the corresponding switching control signals GSa to GSC via the inverter. Accordingly, when the received switching control signals GSa to GSc are at the H level, the drain and source of each TFT are brought into conduction. Hereinafter, the structure of this analog switch and its parasitic capacitance will be described.

  FIG. 3 is a diagram showing a numerical example of the structure of this analog switch and its parasitic capacitance. More specifically, FIG. 3A is a schematic plan view showing a structural example when the n-channel TFT constituting the analog switch is viewed from the vertical direction with respect to the glass substrate, and FIG. ) Is a diagram showing a numerical example of parasitic capacitance in an analog switch according to the size of the TFT. Such an analog switch is formed on a liquid crystal panel substrate made of glass through a predetermined process, but since this process is well known, detailed description thereof is omitted.

  As shown in FIG. 3A, in the n-channel TFT, a source region 61 and a drain region 62 are formed in a silicon thin film, and a gate region 63 is interposed between them (with a gate insulating film in between). Formed. Here, the length of the entire n-channel TFT in the horizontal direction of the drawing is 38 [μm], and the length of the gate region 63 in the horizontal direction of the drawing (hereinafter referred to as “gate length”) L is 13 [μm]. The vertical length (hereinafter referred to as “gate width”) W of the source region 61 (and the drain region 62) in the figure is 20 [μm], and is formed around the source region 61 and the drain region 62. The peripheral width SE of the frame region is 2 [μm]. Of these values, the gate length L and the peripheral width SE are values that are difficult to change in design, but the gate width W is a value that can be changed relatively freely in design. The same applies to P-channel TFTs.

  It is known that changing the gate width W changes the parasitic capacitance of the analog switch. For example, as shown in FIG. 3B, the gates of the n-channel TFT and the p-channel TFT described above are used. Increasing the width W increases both the parasitic capacitance when the analog switch is turned on and the parasitic capacitance when the analog switch is turned off. The numerical example shown in FIG. 3B is an actual measurement value for a certain TFT driven at 16V, and these values for a TFT driven at 12V are approximately 4 / of the values for a TFT driven at 16V. The value is about 5. Therefore, in this case as well, when the gate width W is increased, the parasitic capacitance increases.

  Here, as will be described later, the three analog switches SW (3j-2), SW (3j-1), and SW3j in the same set are turned on one by one in accordance with the switching control signals GSa to Gsc, The remaining two are turned off. Therefore, as described above, it is caused by the parasitic capacitance between the adjacent video signal lines in the video signal line group corresponding to the output terminals of the three analog switches SW (3j-2), SW (3j-1), and SW3j in each group. The potential fluctuation amount can be set to a desired value by appropriately setting the parasitic capacitance (typically, the gate width W) of the analog switch.

  That is, the potential fluctuation amount is determined by the parasitic capacitance value between adjacent video signal lines, but is also determined by the parasitic capacitance value of the analog switch in addition to this. This is because the video signal line that causes this potential fluctuation is capacitively coupled to other wirings (for example, switching control signal line or common electrode) by the parasitic capacitance of the analog switch (for example, the parasitic capacitance between the gate and the drain or between the source and the drain). Because it is. Therefore, by appropriately setting the parasitic capacitance (typically, the gate width W) of the analog switch, the display color shift amount (luminance change amount of the display color) due to the parasitic capacitance between adjacent video signal lines is set. It can be set to a desired value.

Further, the parasitic capacitance value of this analog switch will be specifically examined. First, the parasitic capacitance value between the adjacent video signal lines is calculated by multiplying the direct parasitic capacitance value per pixel forming portion between the adjacent video signal lines by the number of scanning signal lines. A value obtained by adding an indirect parasitic capacitance value between the adjacent video signal lines via the pixel electrode to the value. The capacitance value and C _1.

Further, when the parasitic capacitance values (when OFF) of the analog switches corresponding to the video signal lines connected to the pixel forming portions that form red (R) and green (G) are set to Coff and Cgoff, the adjacent video signals The parasitic capacitance value between the video signal line and the common electrode that causes potential fluctuation due to the parasitic capacitance between the lines is precisely the parasitic capacitance value between the video signal line and the common electrode with the liquid crystal layer sandwiched between them. It is a value obtained by adding the capacitance value between the pixel electrode and the common electrode, the auxiliary capacitance value for the adjustment, and the above-mentioned Croff or Cgoff. This capacitance value is defined as (C ₂ + Coff) or (C ₂ + Cgoff).

Then, the amount of potential fluctuation of the video signal line caused by the addition of the video signal to the video signal line connected to the pixel forming portion for forming red (R), green (G), and blue (B) is VR and VG, respectively. , VB, and when the potential fluctuation amounts due to the parasitic capacitance generated in the video signal lines connected to the pixel forming portions forming red (R) and green (G) as a result of the potential fluctuation are ΔVr and ΔVg, respectively, ΔVr , ΔVg can be expressed by the following equations (1) and (2).
ΔVr = C ₁ / (C ₂ + Coff) · VG
+ C ₁ / (C ₂ + Cgoff) · VB (1)
ΔVg = C ₁ / (C ₂ + Cgoff) · VB (2)

  Note that the video signal line connected to the pixel forming portion that forms blue (B), which is the video signal line corresponding to the analog switch SW3j that is switched last in one horizontal scanning period, is a parasitic capacitance between adjacent video signal lines, etc. Does not cause potential fluctuations.

Here, when VG = VB, the above equation (1) can be expressed as the following equation (3).
ΔVr = C ₁ / (2 · C ₂ + Coff) · VB (3)

Therefore, from the above equations (2) and (3), it can be seen that a relationship such as the following equation (4) should be established in order to set ΔVr = ΔVg.
Coff = C ₂ + 2 · Cgoff (4)

  Actually, ΔVr = ΔVg is not necessarily set. For example, if ΔVr is about twice or less than ΔVg, the display color shift is not so noticeable. In this case, red (R) and green The difference between the parasitic capacitance values Coff and Cgoff (typically, the difference in the gate width W) of the analog switch corresponding to the video signal line connected to the pixel formation portion forming (G) is made relatively small. be able to.

  As described above, by appropriately setting the parasitic capacitance (typically, the gate width W) of the analog switch so as to substantially satisfy the above equation (4), the pixel forming portion that forms red (R) and the green The display color shift amount (luminance change amount) in the pixel formation portion that forms (G) can be set to substantially the same value.

  However, even if the shift amounts of the red and green display colors are set to the same value, the display color shift (specifically, for example, a normally black type, as long as there is no blue display color shift). In the liquid crystal panel, red and green brightness is higher than an ideal value) and undesired influences such as blurring occur over the entire screen.

  Therefore, the video signal line driving circuit 300 according to the present embodiment performs an operation of correcting the voltage of the video signal to be written in the pixel formation portion that forms blue (B), thereby shifting the shift amounts (luminances) of all display colors. Change amount) is set to be almost the same. As a result, the luminance changes over the entire screen (from the ideal display state), but undesirable effects such as display color shift and blurring are eliminated over the entire screen.

  In the following, the driving method of the present liquid crystal display device including the switching operation of the analog switch will be described with reference to FIG. 4, and then the correcting operation of the video signal line driving circuit 300 will be described.

<1.3.3 Driving method>
FIG. 4 is a timing chart for explaining a driving method in the present liquid crystal display device. As shown in FIG. 4, scanning signals G1, G2, G3,... That sequentially become H level are applied to the scanning signal lines Lg in the liquid crystal panel for each horizontal scanning period (one scanning line selection period). By such scanning signals G1, G2, G3,..., Each scanning signal line Lg is in a selected state (active) when an H level is applied, and is connected to the scanning signal line Lg in the selected state. On the other hand, when the L level is applied, the TFT 10 in Px is in a non-selected state (inactive), and the TFT 10 in the pixel formation portion Px connected to the scanning signal line Lg in the non-selected state is in an off state. . As shown in FIG. 4, the switching control signal GSa includes first to third horizontal scanning periods (periods in which each scanning signal Gk (k = 1, 2, 3,... Is H level) divided into three equal parts. It becomes H level in the first period among the periods until and becomes L level in the remaining second and third periods.

  Here, among the analog switches in the connection switching circuit 501, the analog switch SW (3j-2) connected to the (3j-2) th video signal line Ls is turned on when the switching control signal GSa is at the H level. It turns off when the switching control signal GSa is at L level. The analog switch SW (3j-1) connected to the (3j-1) th video signal line Ls is turned on when the switching control signal GSb is at the H level and turned off when the switching control signal GSb is at the L level. . Further, the analog switch SW3j connected to the 3j-th video signal line Ls is turned on when the switching control signal GSc is at the H level and turned off when the switching control signal GSc is at the L level.

  Accordingly, each output terminal TSj of the video signal line driving circuit 300 is connected to the (3j-2) th video signal line Ls in the first period of each horizontal scanning period, and in the second period of each horizontal scanning period. It is connected to the (3j-1) th video signal line Ls, and is connected to the (3j-2) th video signal line Ls in the third period of each horizontal scanning period.

  Therefore, for example, the video signal S1 to be output from the output terminal TS1 and the video signal S2 to be output from the output terminal TS2 in the video signal line driving circuit 300 are signals as shown in FIG. Here, the timing chart in FIG. 4 showing the video signals S1 and S2 is composed of two upper and lower stages, and the upper stage is the color (pixels to be displayed on the pixel forming portion Px by the video signals S1 and S2. The lower part shows video signal lines to which the video signals S1 and S2 are to be applied.

  In order to output such a video signal, the video signal line driving circuit 300 first forms a pixel in which the TFT 10 is turned on by the scanning signal Gk in the pixel formation portion Px of the (3j-2) th pixel column in the pixel matrix. Pixel values to be written in the part Px (here, pixel values for displaying R) are sequentially input from the display control circuit 200, and the video signal Sj corresponding to these pixel values in the first period of the horizontal scanning period. Output from the output terminal TSj.

  Next, a pixel value (here, a pixel for displaying G) to be written in the pixel formation portion Px in which the TFT 10 is turned on by the scanning signal Gk among the pixel formation portions Px of the (3j−1) th pixel column in the pixel matrix. Value) are sequentially input from the display control circuit 200, and the video signal Sj corresponding to these pixel values is output from the output terminal TSj in the second period of the horizontal scanning period.

  Subsequently, a pixel value (here, a pixel value for displaying B) to be written in the pixel formation portion Px in which the TFT 10 is turned on by the scanning signal Gk in the pixel formation portion Px of the 3j-th pixel column in the pixel matrix is displayed. Sequentially input from the control circuit 200, video signals Sj corresponding to these pixel values are output from the output terminal TSj in the third period of the horizontal scanning period.

  As described above, the video signal line driving circuit 300 repeats the operation of writing the pixel values corresponding to the respective colors to the respective pixel formation portions Px via the respective video signal lines Ls in the order of RGB every horizontal period. Such a video signal line time-division driving type liquid crystal display device has a pixel forming portion for forming red (R) and a green (G) due to parasitic capacitance between adjacent video signal lines as described above. The voltage of the video signal to be written to the pixel forming portion to be formed varies, and as a result, display quality such as display color shift and blurring may be deteriorated.

  Therefore, by appropriately setting the parasitic capacitance (typically, the gate width W) of the analog switch as described above, a pixel formation portion that forms red (R) and a pixel formation portion that forms green (G) The display color shift amount (luminance change amount) is set to be substantially the same, and the video signal line driving circuit 300 corrects the voltage of the video signal to be written in the pixel forming portion for forming blue (B). As a result, the shift amounts (luminance change amounts) of all display colors are set to substantially the same value. Hereinafter, the configuration and operation of the video signal line driving circuit 300 will be described in detail.

<1.4 Video signal line drive circuit>
<1.4.1 Configuration of Video Signal Line Driver Circuit>
FIG. 5 is a block diagram showing a configuration of the video signal line driving circuit 300. Hereinafter, each component will be described with reference to FIG. The video signal line driving circuit 300 includes a shift register circuit 301 that outputs a predetermined sampling pulse Smp by receiving the source clock signal SCK and the source start pulse signal SSP output from the display control circuit 200 shown in FIG. A data latch circuit 302 for latching data indicating pixel values included in the digital image signal Da by receiving the digital image signal Da, the switching control signal GS and the sampling pulse Smp output from the display control circuit 200; A level shifter circuit 303 for shifting the voltage of the data latched by the latch circuit 302, a D / A conversion circuit 304 for converting the digital data whose voltage has been shifted by the level shifter circuit 303 into an analog voltage signal, and this D / A conversion Circuit 30 And an output buffer circuit 305 to be applied to the video signal line Ls to a corresponding analog voltage signal from. These components are almost the same as those of the conventional video signal line driving circuit.

  Further, the video signal line driving circuit 300 should be generated in a video signal to be written in a pixel formation portion that forms red (R) and a pixel formation portion that forms green (G) due to parasitic capacitance between the video signal lines. A voltage generation circuit 320 that outputs a correction voltage signal Vcb for correcting the voltage fluctuation of the video signal to be written in the pixel forming portion that forms blue (B) by adding an amount corresponding to the voltage fluctuation amount. Prepare.

  FIG. 5 shows the operation of the constituent elements substantially the same as those of the conventional video signal line driving circuit among the above constituent elements (this operation is hereinafter referred to as “basic operation” of the video signal line driving circuit). The description will be given with reference.

<1.4.2 Basic operation of video signal line drive circuit>
The shift register circuit 301 has a configuration in which a plurality of stages of flip-flop circuits are connected in series, and the source start pulse signal SSP is sequentially transferred in each stage in synchronization with the source clock signal SCK. A predetermined sampling pulse Smp is sequentially output from the stage.

  The data latch circuit 302 includes a plurality of latch circuits each provided corresponding to each stage of the shift register circuit 301. The data latch circuit 302 samples data included in the digital image signal Da by the sampling pulse Smp, Thereafter, the sampled data is continuously output for a predetermined period. Here, the digital image signal Da includes digital display data DR, DG, DB (here, 6 bits each) indicating pixel values of RGB colors, and these digital display data DR, DG, DB is simultaneously supplied from the display control circuit 200 via three sets of signal lines (not shown) (here, a total of 18 lines of 6 colors). The data latch circuit 302 sequentially samples the digital display data DR, DG, and DB in time division in synchronization with the sampling pulse Smp from the shift register circuit 301.

  Specifically, in the first period obtained by dividing one horizontal scanning period into three equal parts, the digital display data DR applied to the R pixel formation portion Px in a certain row (for example, the first row) in the pixel matrix is a data latch. The data temporarily stored in a sampling memory circuit (not shown) included in the circuit 302 is supplied to a hold memory circuit (not shown) included in the data latch circuit 302. The hold memory circuit takes in an output signal from each stage of the corresponding sampling memory circuit at the rising edge of the switching control signal GS (here, the switching control signal GSa) corresponding to the latch signal, and outputs the output signal as an output signal Dh. This is applied to the circuit 303. The hold memory circuit maintains the output state of the output signal Dh until the next switching control signal GS (here, the switching control signal GSb) rises. Next, in the second period, the digital display data DR applied to the G pixel formation portion Px in a certain row in the pixel matrix is similarly sampled at the rising edge of the switching control signal GS (here, the switching control signal GSb). Is temporarily stored and provided to the hold memory circuit. Similarly, in the subsequent third period, the digital display data DG is temporarily stored in the sampling memory circuit at the rising edge of the switching control signal GS (here, the switching control signal GSc) and is supplied to the hold memory circuit.

  The level shifter circuit 303 receives the output signal Dh from the data latch circuit 302 and shifts (generally increases) the voltage level of the signal so that the D / A conversion circuit 304 has an appropriate input signal level. Output as level shift signal Ds.

  The D / A conversion circuit 304 receives the level shift signal Ds, which is a digital signal output from the level shifter circuit 303, and converts it into analog voltage signals Var, Vag, Vab corresponding to the digital display data DR, DG, DB. To do. Specifically, the D / A conversion circuit 304 selects an analog voltage corresponding to the received digital signal from a plurality of types of analog voltages for gradation display generated by a reference voltage generation circuit (not shown). Output as analog voltage signals Var, Vag, Vab.

  The output buffer circuit 305 is composed of, for example, a voltage follower circuit, and uses the corrected voltage signal Vcb, which is a signal obtained by correcting the analog voltage signal Vab, and the uncorrected analog signals Var and Vag as video signals Sj, and corresponding outputs. The signal is output from the terminal TSj to the video signal line Ls. Here, the correction voltage signal Vcb output from the output buffer circuit 305 is supplied from the voltage generation circuit 320. Hereinafter, an operation of generating the correction voltage signal Vcb by the voltage generation circuit 320 (hereinafter, this operation is referred to as “correction operation” of the video signal line driving circuit) will be described with reference to FIG.

<1.4.3 Correcting operation of video signal line driving circuit>
The voltage generation circuit 320 stores a correction voltage value Cb for compensating for the influence of the voltage fluctuation of the video signal due to a predetermined parasitic capacitance between adjacent video signal lines, and the like from the D / A conversion circuit 304. A correction voltage signal Vcb corresponding to a value obtained by adding the correction voltage value Cb to the voltage value of the video signal is output in accordance with the rising edge of the switching control signal GSc received from the display control circuit 200 based on the received analog voltage signal Vab. .

  That is, the voltage generation circuit 320 uses the absolute value of the voltage value of the video signal Sj output from the output buffer circuit 305 based on the analog voltage signal Vb output from the D / A conversion circuit 304 based on the correction voltage value Cb. A correction voltage signal Vcb whose value is larger by the correction voltage value Cb than the absolute value of the voltage value of the analog voltage signal Vb is output. With this correction voltage signal Vcb, the shift amount (luminance change) of the other display colors (R and G) in the blue (B) pixel formation portion that does not cause a display color shift due to parasitic capacitance between adjacent video signal lines. Shift of an amount substantially equal to (quantity) can be generated, and thus a display color shift over the entire screen can be reduced or eliminated.

  Note that the voltage generation circuit 320 performs an accurate correction operation without error by using the analog voltage signal Vb output from the D / A conversion circuit 304 as a reference, rather than using the digital display data DB as a reference. Can do.

  Here, the correction voltage value Cb is calculated and stored in advance based on a value obtained by measuring a capacitance in the liquid crystal panel, a parasitic capacitance between wirings, or performing a numerical simulation. The correction voltage value Cb may be set and stored individually for each corresponding video signal line.

<2. Effect>
As described above, in the present embodiment, the parasitic capacitances (typically in FIG. 3A) of the three analog switches SW (3j-2), SW (3j-1), and SW3j in the same set. By appropriately setting the gate width W) of the source region 61 (and the drain region 62) shown, a video signal line connected to the pixel formation portion that forms red (R) and the pixel formation portion that forms green (G) Since the amount of potential fluctuation caused by the parasitic capacitance between adjacent video signal lines can be easily set to a desired value, it depends on the parasitic capacitance between adjacent video signal lines that affect these pixel formation portions. The display color shift amount (luminance change amount) based on the voltage fluctuation can be set to be substantially the same value. In addition to this, the voltage generation circuit 320 shifts other display colors (R and G) in a blue (B) pixel formation portion that does not cause a shift in display color due to parasitic capacitance between adjacent video signal lines. A shift of an amount approximately equal to the amount (luminance change amount) can be easily generated. As a result, with a simple apparatus configuration, it is possible to reduce or eliminate deterioration in display quality such as display color shift and blurring over the entire screen as a result. Hereinafter, this will be described in detail with reference to FIG.

  FIG. 6 is a diagram showing in detail the potential change of the video signal applied to the video signal lines SL3 to SL5 of the liquid crystal display device shown in FIG. For the sake of explanation, in the figure, the voltage fluctuation amount caused by the parasitic capacitance is shown larger than the actual fluctuation amount. Here, the change in the potentials of the video signal lines SL4 and SL5 is the same as in the conventional case shown in FIG. 7, except that the voltage fluctuation amounts are both ΔV.

  As described above, the video signal line SL4 is affected by the potential change of the video signal lines SL3 and SL5 (twice in total) due to the parasitic capacitance, and the video signal line SL5 is affected by the potential change of the video signal line SL6 due to the parasitic capacitance. For example, if the parasitic capacitance between the video signal lines is the same (and the parasitic capacitance between each video signal line and other wirings, electrodes, etc.) is the same, it is adjacent. These voltage fluctuation amounts due to parasitic capacitance between the video signal lines to be performed are not the same. However, as described above, since the parasitic capacitance of the analog switch is set to an appropriate value, the potentials of the video signal lines SL3 and SL4 are both large in absolute value from the original potential by the voltage fluctuation amount ΔV. It has become.

  At time t3, the voltage of the video signal applied to the video signal line SL3 is shifted by an amount substantially equal to the shift amount (luminance change amount) of other display colors (R and G) by the voltage generation circuit 320. The voltage fluctuation amount ΔV that causes the above is added. As a result, the potentials of all the video signal lines are shifted from the ideal potential by almost the same amount, so that the luminance changes equally (eg, increases) over the entire screen, but the display color shifts and blurs over the entire screen. Etc. can be solved.

<3. Modification>
In the present embodiment, the video signal line is a time-division driving type liquid crystal display device in which three video signal lines for transmitting video signals to adjacent three pixels of each RGB color are grouped as a set and the number of time divisions is three. However, the number of time divisions may be 4 or more. Further, even in a configuration in which each pixel forming unit performs multi-grayscale black and white display, for example, vertical shifts are made over the entire screen due to variations in the display luminance (display gradation) shift amount for each display column over the entire screen. Deterioration of display quality such as streaking along the direction (column direction) can be eliminated.

  In the present embodiment, the video signal lines are driven in a time-sharing manner in the order of R, G, and B. However, the drive order is not limited, and for example, B, G, and R (reverse to the present embodiment) May be driven in a time-sharing manner in this order. In this case, the voltage generation circuit 320 may output the correction voltage signal Vcr for compensating for the fluctuation of the video signal line voltage to be applied to the video signal line connected to the R pixel formation portion Px here.

  In the present embodiment, the gate width W shown in FIG. 3A in the source region 61 (and the drain region 62) of the analog switches SW (3j-2), SW (3j-1), and SW3j is appropriately set. As a result, the potential fluctuation amount due to the parasitic capacitance between the video signal line connected to the pixel forming portion for forming red (R) and the pixel forming portion for forming green (G) and the adjacent video signal line is set to a desired value. At least one of the parameters that influence the parasitic capacitance of the analog switch, which is approximately a transistor, such as the size, shape, structure, or material of the source region 61, the drain region 62, and the gate region 63 to be set The amount of potential fluctuation due to the parasitic capacitance between the video signal lines may be set to a desired value by appropriately changing.

  Further, in the present embodiment, the parasitic capacitance of the analog switch that is a transistor is set as appropriate. However, even if the parasitic capacitance is set by including a capacitance element having an appropriate capacitance inside the analog switch, Alternatively, the capacitance of the connection switching circuit 501 for the connected video signal line may be set by connecting a capacitive element having an appropriate capacitance to the outside.

  In the present embodiment, the voltage generation circuit 320 is provided in the video signal line driving circuit 300, but the voltage generation circuit 320 may be provided outside the video signal line driving circuit 300. The voltage generation circuit 320 and the video signal line driving circuit 300 realize a video signal output function for outputting a video signal having the potential corrected as described above to each video signal line. The correction function corresponding to the voltage generation circuit 320 included in the video signal output function may be realized by the D / A conversion circuit 304. For example, a video signal having a voltage to which a predetermined amount of voltage fluctuation due to a parasitic capacitance between adjacent video signal lines is applied in advance is supplied to the D / A conversion circuit 304 included in the video signal line driving circuit 300. Alternatively, the D / A conversion circuit 304 may perform an operation for adding the voltage fluctuation amount.

  The voltage generation circuit 320 in this embodiment stores a predetermined correction voltage value Cb, but receives digital display data DR, DG or analog voltage signals Var, Vag, and is adjacent based on at least one of these values. A value obtained by calculating an expected fluctuation amount of the voltage of the video signal applied to the video signal line due to a parasitic capacitance between the video signal lines may be used as the correction voltage value Cb. The correction voltage value Cb may be calculated after being calculated outside the D / A conversion circuit 304, the display control circuit 200, or outside the apparatus, and then applied to the voltage generation circuit 320.

  In this embodiment, the scanning signal lines are sequentially selected for each row. However, even in a driving mode in which the scanning signal lines are sequentially selected by skipping every other row or every two rows or more, that is, driving by interlace scanning. The same effect as described above can be obtained.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on one Embodiment of this invention. FIG. 2 is a schematic diagram (a) and equivalent circuit diagrams (b) and (c) for explaining a basic configuration of the liquid crystal panel in the embodiment. It is a figure which shows the numerical example of the structure of the analog switch in the said embodiment, and its parasitic capacitance. It is a timing chart for demonstrating the drive method in a liquid crystal display device provided with the same liquid crystal panel as the conventional structure. It is a block diagram which shows the structure of the said video signal line drive circuit. It is a figure which shows in detail the electric potential change of the video signal applied to video signal line SL3-SL5 of this liquid crystal display device which concerns on the said embodiment. It is a figure which shows the electric potential change of the video signal applied to video signal line SL3-SL5 of the conventional liquid crystal display device in detail.

Explanation of symbols

10 ... TFT (Thin Film Transistor)
DESCRIPTION OF SYMBOLS 25 ... Signal line switching control circuit 200 ... Display control circuit 300 ... Video signal line drive circuit 301 ... Shift register circuit 302 ... Data latch circuit 303 ... Level shifter circuit 304 ... D / A conversion circuit 305 ... Output buffer circuit 320 ... Voltage generation circuit 400 ... Scanning signal line drive circuit 500 ... Liquid crystal panel 501 ... Connection switching circuit SCK ... Source clock signal SSP ... Source start pulse signal GCK ... Gate clock signal GSP ... Gate start pulse signal Da ... Digital image signal GSa to GSc ... Switch control signal TSj ... Output terminal Gk ... Scanning signal (k = 1, 2, 3, ...)
Sj: Video signal (j = 1, 2, 3,...)
SL: Video signal line Ls: Video signal line (column electrode)
Lg Scanning signal line (row electrode)
Px: Pixel formation part (pixel)
Cp ... Pixel capacitance Ep ... Pixel electrode Ec ... Counter electrode Cb ... Correction voltage value Vcb ... Correction voltage signal Var, Vag, Vab ... Analog voltage signal SWi ... Analog switch (i = 1, 2, 3, ...)
ΔV… Voltage variation L… Gate length W… Gate width

Claims (5)

A plurality of pixel forming portions for forming an image to be displayed, a plurality of video signal lines for transmitting a plurality of video signals indicating the images to be displayed to the plurality of pixel forming portions, and the plurality of images An active matrix comprising a plurality of scanning signal lines intersecting with the signal lines, wherein the plurality of pixel forming portions are arranged in a matrix corresponding to the intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively. Type display device,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines;
Video having a plurality of output terminals respectively corresponding to a plurality of sets of video signal lines obtained by grouping the plurality of video signal lines with three or more video signal lines as one set, and a video corresponding to each output terminal A video signal output circuit that outputs a video signal to be transmitted by the signal line group from the output terminal in a time-sharing manner within a predetermined period; and
By connecting each output terminal of the video signal output circuit to any video signal line in the corresponding video signal line group, the connected video signal line and the scanning signal line selected by the scanning signal line driving circuit A connection switching circuit that provides the video signal to the pixel forming section connected to the video signal and switches the video signal line to which each output terminal is connected within the corresponding video signal line group according to the time division,
The connection switching circuit generates a potential change in accordance with a potential change of an adjacent video signal line within the predetermined period after being connected to the output terminal in the video signal line group of one set. It has a parasitic capacitance that has a predetermined value so that the amount of potential change of the video signal line is almost equal,
The video signal output circuit is a voltage of a video signal to be transmitted by a video signal line that does not cause a potential change according to a potential change of an adjacent video signal line within the predetermined period after being connected to the output terminal. Is corrected by an amount substantially equal to the amount of potential change. The connection switching circuit includes a plurality of analog switches each connected to correspond to each of the video signal lines and including one or more transistors,
2. The display device according to claim 1, wherein the plurality of analog switches include two or more types of transistors having different parasitic capacitances according to video signal lines to be connected. The transistor includes a drain region and a source region having a predetermined area, and a gate region provided between the drain region and the source region and having a predetermined width and length.
The plurality of analog switches include two or more types of transistors having different lengths of the drain region and the source region along the width direction of the gate region according to a video signal line to be connected. The display device according to claim 2. The video signal output circuit includes:
A shift register circuit for outputting a predetermined sampling pulse;
A data latch circuit that latches data indicating a pixel value to be given to the pixel forming unit included in a plurality of video signals indicating the image to be displayed by receiving a sampling pulse output from the shift register circuit;
A D / A conversion circuit that converts the digital data latched by the data latch circuit into an analog voltage signal and outputs the analog voltage signal;
An output buffer circuit for outputting the analog voltage signal output from the D / A conversion circuit to a video signal line connected to the output terminal;
Among the analog voltage signals output from the D / A conversion circuit, a video signal line that does not change in potential in response to a change in potential of an adjacent video signal line within the predetermined period after being connected to the output terminal. A voltage generation circuit that outputs a correction voltage signal that is a signal having a voltage obtained by adding a voltage change amount substantially equal to the voltage change amount to a voltage of an analog signal corresponding to the video signal to be transmitted by
The display device according to claim 1, wherein the output buffer circuit outputs the correction voltage signal output from the voltage generation circuit from the output terminal.   The video signal output circuit includes a plurality of sets obtained by grouping the plurality of video signal lines with a group of three adjacent video signal lines respectively connected to three types of pixel forming portions that display predetermined three primary colors. A plurality of output terminals respectively corresponding to the video signal line groups, and outputting video signals to be transmitted by the video signal line groups corresponding to the respective output terminals from the output terminals in a time-sharing manner, The display device according to any one of claims 1 to 4.

Images