JPH05150737A - Driving circuit for display device - Google Patents

Abstract

PURPOSE:To provide the driving circuit for the display device which can supply a driving voltage for many gradations without increasing the number of external source voltages. CONSTITUTION:This driving circuit is equipped with a timing signal generating circuit 4 which generates timing signals TO, T1... T7 having different pulse widths in one horizontal period as many as the gradations. Further, the driving circuit is equipped with a voltage control circuit 5 which selects one of the timing signals T0, T1... T7 in each horizontal period according to the contents of video signals HnDO, HnD1, and HnD2 by receiving the video signals HnDO, HnD1, and HnD2 and the timing signals TO, T1...,T7, and outputs control signals CON1 and CON2 of specific level only for a period corresponding to the pulse width of the selected timing signal. An output voltage generating circuit 6 receives the external source voltage V and charges a capacitor with the external source voltage V only for the period wherein the control signals CON1 and CON2 are outputted in one horizontal period to generate the driving voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device, and more particularly to a drive circuit (digital source) which outputs a multi-grayscale drive voltage based on an input digital video signal of a predetermined number of bits.・ Driver)

[0002]

2. Description of the Related Art Conventionally, as a drive circuit of this type, FIG.
There is something like the one shown in 2. This drive circuit includes a shift register 101, a sampling memory 102, a hold memory 103, a decoder 104, and an output voltage selection circuit 105. This drive circuit has m signal systems corresponding to the number of picture elements, and is the nth (1≤n≤m)
The signal system of is configured as shown in FIG. The portion of the output selection circuit 105 belonging to the nth signal system is composed of eight analog switches ASW ₀ , ..., ASW ₇ . In operation, first, the shift register shown in FIG. 12 causes the sampling pulse Ts corresponding to the nth picture element
Output mpn. At the rising timing of this sampling pulse Tsmpn, the video signal D ₀ ,
D ₁ and D ₂ are taken into the sampling memory 102. Then, the sampling memory 102 shown in FIG.
It is held in the three D-flip-flops 121, 122, 123 belonging to the n-th signal system. When the sampling for one horizontal period is completed, the output pulse OE is input to the hold memory 103. As a result, the video signals D ₀ , D held in the sampling memory 102
₁ and D ₂ are transferred to the hold memory 103 (three D-flip-flops 131, 132, 133) and further sent to the decoder 104. The decoder 104 decodes the received video signals D ₀ , D ₁ , and D ₂ to obtain eight drive signals Y ₀ ,
…, Y ₇ (only one of these is high (H) level, the rest are low)
(L) level) is output. The analog signals ASW ₀ , ..., A are generated by the drive signals Y ₀ , ..., Y ₇ .
One of the SW ₇ 's becomes conductive, and one of the eight types of external power supply voltages V ₀ , ..., V ₇ applied to the conductive analog switch is output to the source line On. Therefore, the multi-gradation drive voltages V ₀ , ..., V ₇ can be supplied to a display device (not shown) according to the contents of the video signals D ₀ , D ₁ , D ₂ .

[0003]

However, the above-mentioned conventional drive circuit has a problem that a large number of external power supply voltages are required when increasing the number of bits of a video signal in order to promote multi-gradation display. .. For example, when the number of bits of the video signal increases to ³ , ⁴ , ⁶ , 8, ..., The required number of external power supply voltages is 2 ³ (= 8), 2 ⁴ (= 16), 2 ⁶ (= 64). , 2 ⁸ (= 2
56), ... and increasing. For this reason, the scale of the external power supply increases and the cost increases. The number of input terminals of the LSI (Large-scale integrated circuit) that incorporates the drive circuit increases, making it difficult to implement. Accuracy required for each external power supply voltage The problem is that it becomes stricter and the coordination management becomes difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a drive circuit for a display device which can supply a multi-gradation drive voltage without increasing the number of external power supply voltages.

[0005]

In order to achieve the above object, the device of the present invention is a drive circuit for a display device which outputs a multi-gradation drive voltage based on an input digital video signal of a predetermined number of bits. A timing signal generating circuit for generating timing signals having different pulse widths in one horizontal period according to the number of gradations, and the video signal and the timing signal are received, and the video signal is generated for each horizontal period. A voltage control circuit that selects one of the timing signals based on the content of the signal and outputs a control signal of a predetermined level for a period corresponding to the pulse width of the selected timing signal;
Output voltage generation that has a capacitor, receives the external power supply voltage, and charges the external power supply voltage to the capacitor only during a period in which the control signal of the voltage control circuit is output within one horizontal period to create a drive voltage It is characterized by having a circuit.

The output voltage generating circuit has two capacitors for each signal system, and the drive voltage is generated by alternately charging the external power source voltage to the two capacitors every horizontal period. desirable.

[0007]

The display device drive circuit of the present invention operates as follows. First, as illustrated in FIG. 7, the timing signal generation circuit generates the timing signals T ₀ , T ₁ , ..., T ₇ having different pulse widths within one horizontal period (a period corresponding to the cycle of the pulse signal OE). A number corresponding to the number of gradations (8 in this example) is created (however, the timing signal T ₀ maintains the H level). Next, the voltage control circuit receives the video signals D ₀ , D ₁ and D ₂ and the timing signals T ₀ , T ₁ , ..., T ₇ as illustrated in FIG. Signal D
₀ , D ₁ , D ₂ based on the contents of the timing signal T ₀ ,
Select one of T ₁ , ..., T ₇ . For example, when the levels of the video signals D ₀ , D ₁ and D ₂ are L, L and L, respectively, the timing signal T ₀ and when the levels of the video signals D ₀ , D ₁ and D ₂ are H, L and L, respectively. Selects the timing signal T ₁ . Further, the levels of the video signals D ₀ , D ₁ , D ₂ are H, H, H, respectively.
In the case of, the timing signal T ₇ is selected. Then, this voltage control circuit outputs a control signal of a predetermined level only for a period corresponding to the pulse width of the selected timing signal. The output voltage generation circuit receives the external power supply voltage and charges the capacitor with the external power supply voltage only during the period in which the control signal of the voltage control circuit is output within one horizontal period. As a result, a drive voltage is created for each horizontal period. As shown in FIG. 9, the driving voltage is the timing signals T ₀ , T
Increases or decreases according to the pulse width of ₁ , ..., T ₇ . When a normally white (mode in which light is transmitted when a voltage is applied) liquid crystal display device is driven by this drive voltage, a timing signal T ₀
The multi-gradation display is dark on the side and bright on the timing signal T ₇ side.

As described above, according to this display device drive circuit, a multi-grayscale drive voltage is generated by one external power supply voltage. Even when the number of bits of the video signal is increased to promote multi-gradation, the timing signal creation circuit creates the number of timing signals according to the number of gradations, and multi-gradation is performed based on this timing signal. Drive voltage is created. Therefore, it is not necessary to increase the types of external power supply voltage.

Further, the output voltage generating circuit has two capacitors for each signal system, and when the external power supply voltage is alternately charged in the two capacitors for each horizontal period to generate a drive voltage, The driving voltage is alternately output from the two capacitors for each horizontal period. That is, even when one of the capacitors is being charged, the drive voltage is output from the other capacitor, and the drive voltage is continuously output without interruption. The switching between the two capacitors is performed using, for example, signals OE1 and OE2 that are alternately inverted every horizontal period as shown in the lower part of FIG. 7 and using these signals OE1 and OE2 (described later).

[0010]

The drive circuit for a display device of the present invention will be described in detail below with reference to the embodiments.

FIG. 1 shows the overall configuration of a drive circuit of one embodiment, and FIG. 2 shows the n-th (1.ltoreq.n.ltoreq.n.ltoreq.m) signal system among m (3 bits for each) signal system corresponding to the number of picture elements of the drive circuit. The signal system of m) is shown. This drive circuit includes a shift register 1, a sampling memory 2, a hold memory 3, a timing signal generation circuit 4, a voltage control circuit 5, and an output voltage generation circuit 6. The shift register 1, sampling memory 2 and hold memory 3 are the shift register 101 and sampling memory 1 shown in FIG.
02, the same as the hold memory 103.

The timing signal generating circuit 4 is composed of two parts 4A and 4B as shown in FIG. Four
The portion A is composed of D-flip-flops 41, 42, 43, a logical product circuit 44, a negative logical sum circuit 45 and a negative logical sum circuit 47, and outputs a clock signal CLK and a pulse signal OE input every horizontal period. In response, as shown in FIG. 4, the signals OE1 and OE2 which are alternately inverted every horizontal period.
And a clear signal CLR obtained by substantially inverting the pulse signal OE
Create 1 and. The signals OEA and OEB in the figure represent the outputs of the D-flip-flops 42 and 43, respectively. On the other hand, the 4B portion shown in FIG. 3 is composed of a 6-bit counter 46, an inverter 48 and D-flip-flops 49, ..., 55. As shown in FIG. Signal (64C
LK), and using this signal 64CLK, eight timing signals T ₀ , T ₁ , ..., T ₇ having different pulse widths within one horizontal period are created (however, the timing is The signal T ₀ maintains the H level).

Further, the voltage control circuit shown in FIG. 2 (portion belonging to the n-th signal system) includes the video signals HnD ₀ , HnD ₁ and HnD ₂ from the hold memory 3 and the timing signals T ₀ and T. _1, ..., receiving the signal OE1, OE2 from T ₇ and timing signal generating circuit 4. Then, as shown in FIG. 6, control signals CON1 and CON2 of a predetermined level are output for each horizontal period based on the content of the received signal. That is, the signals OE1 and OE2 are logic "0" and logic "1", respectively.
, The control signal CON1 is the video signals HnD ₀ , HnD ₁ ,
The control signal CON2 is set to the H level only during the period corresponding to the pulse width of the timing signals T ₀ , T ₁ , ..., T ₇ according to the content of HnD ₂ , while the control signal CON2 corresponds to the content of the video signals HnD ₀ , HnD ₁ , HnD ₂ . Regardless, it remains L level. In addition, the signals OE1 and O
If E2 is logic "0" (corresponding to L level) or logic "1" (corresponding to H level), the control signal CON
1 becomes L level regardless of the contents of the video signals HnD ₀ , HnD ₁ and HnD ₂ , while the control signal CON2 is the video signal Hn.
D _0, HnD _1, the timing signal T ₀ according to the content of HND _2,
The level becomes H level only during the period corresponding to the pulse width of T ₁ , ..., T ₇ . When the signals OE1 and OE2 are both logic "0", the control signals CON1 and CON2 are the video signals HnD ₀ and Hn.
Both are at the L level regardless of the contents of nD ₁ and HnD ₂ . Further, as can be seen from FIG. 4, signals OE1 and OE
There is no case where 2 becomes logical "1".

Further, the output voltage generating circuit 6 shown in FIG.
The (portion belonging to the nth signal system) includes wirings L1 and L2 that connect the external power supply (voltage V) and the source line On,
Analog switches ASW1 and ASW and capacitors C1 and C2 connected between each wiring L1 and L2 and the ground
2, ASW3, ASW4. The analog switches ASW1 and ASW3 are provided on the side of the external power source and on the side of the source line On with respect to the capacitor C1 of the line L1, respectively, and control signals CON1 and
ON / OFF control is performed by the signal OE2 from the timing signal generation circuit 4 (ON when the control signal is at H level, L
Turn off at level. ). On the other hand, the analog switches ASW2 and ASW4 are respectively capacitors C of the wiring L2.
2 are provided on the external power supply side and the source line On side of the control signal CON1 from the voltage control circuit 5 and the signal OE2 from the timing signal generating circuit 4 (ON when the control signal is at H level, It turns off at L level.).

This drive circuit operates as follows as a whole. First, when the shift register 1 shown in FIG. 1 outputs the sampling pulse Tsmpn corresponding to the n-th picture _element , the video signals D ₀ , D ₁ , D input from the outside at the rising timing of the sampling pulse Tsmpn. ₂ is taken into the sampling memory 2. Then, the three D-flip-flops 21, 22, 23 of the sampling memory 2 (portion belonging to the n-th signal system) shown in FIG.
Are stored as video signals SnD ₀ , SnD ₁ and SnD ₂ . 1
When the sampling in the horizontal period is completed, the pulse signal OE is input to the hold memory 3. This allows
The video signals SnD ₀ , Sn held in the sampling memory 3 (three D-flip-flops 31, 32, 33)
D ₁ and SnD ₂ are transferred to the hold memory 3 and further transferred to the voltage control circuit 5 as video signals HnD ₀ , HnD ₁ and HnD ₂ . The voltage control circuit 5 uses the video signals HnD ₀ , HnD ₁ ,
Based on the content of HnD ₂ , as already described, the H-level control signal CON1 or CON2 is supplied only during the period corresponding to the pulse width of the timing signals T ₀ , T ₁ , ..., T ₇ selected for each horizontal period. Output. For example, assume that the signal OE1 is at the H level and the signal OE2 is at the L level during a specific horizontal period. In this case, the control signal CON1 becomes H level and the control signal CON2 becomes L level. As a result, the analog switches ASW1 and ASW4 of the output voltage generating circuit 6 are turned on and the analog switches ASW2 and ASW3 are turned off. Therefore, analog switch ASW1
Through the control signal CON1 through the voltage control circuit 5
The capacitor C1 is charged for a period corresponding to the pulse width of the timing signals T ₀ , T ₁ , ..., T ₇ selected by. As a result, the video signals D ₀ , D ₁ , D ₂ are applied between the electrodes of the capacitor C1.
A multi-tone driving voltage is created according to the contents of. on the other hand,
From the capacitor C2, the voltage (driving voltage) charged in the horizontal period immediately before this horizontal period is supplied to the analog switch A.
It is output to the source line On through SW4. In the next horizontal period subsequent to this horizontal period, the signal OE1 becomes L level and the signal OE2 becomes L level. In this case, the control signal CON1 becomes L level and the control signal CON2 becomes H level. As a result, the analog switches ASW1 and ASW4 of the output voltage generating circuit 6 are turned off and the analog switches ASW2 and ASW3 are turned on. Therefore,
Control signal CON is supplied through the analog switch ASW2.
2, the capacitor C2 is charged for a period corresponding to the pulse width of the timing signals T ₀ , T ₁ , ..., T ₇ selected by the voltage control circuit 5. As a result, a multi-grayscale driving voltage corresponding to the contents of the video signals D ₀ , D ₁ , and D ₂ is created between the electrodes of the capacitor C2. On the other hand, the voltage (driving voltage) previously charged from the capacitor C1 is the analog switch AS.
It is output to the source line On through W3. Therefore, even when one of the capacitors is being charged, the driving voltage can be output from the other capacitor, and the driving voltage can be continuously output. Note that there is a period in which the signals OE1 and OE2 are both at the L level and the control signals CON1 and CON2 are both at the L level for a moment at the transition of the horizontal period (the analog switch ASW1,
, ASW4 are all in the off state), and there is almost no effect on the operation in each horizontal period.

As described above, according to this display device drive circuit, it is possible to generate a multi-gradation drive voltage with one external power supply voltage. Even if the number of bits of the video signal is increased in order to promote multiple gray levels, the timing signal creation circuit 4 creates a number of timing signals according to the number of gray levels, and based on this timing signal, multi-level Key drive voltages can be created. Therefore, it is possible to supply multi-gradation drive signals without increasing the types of external power supply voltages.

When a normal white liquid crystal display panel is used as the display device, as shown in FIG. 10, the transmittance changes in the intermediate region of the applied voltage V and is saturated in the low and high regions. In the case of digital 1-bit display, since it is only on or off, sufficient contrast can be obtained by operating between the above low range and high range. However, in the case of multi-gradation display, since the change in the transmittance is non-linear in the low and high regions of the applied voltage V, the desired luminance cannot be obtained as it is, and the correct color cannot be displayed. Therefore,
As shown in FIG. 11, the waveform (V−t
Correct the characteristics). This allows each gradation to have a linear characteristic.

[0018]

As is apparent from the above, the drive circuit for a display device of the present invention includes a timing signal generating circuit for generating timing signals having different pulse widths in one horizontal period according to the number of gradations. Receiving the video signal and the timing signal, selecting one of the timing signals based on the content of the video signal for each horizontal period,
A voltage control circuit that outputs a control signal of a predetermined level only for a period corresponding to the pulse width of the selected timing signal, and a capacitor are received, and the control signal of the voltage control circuit is received within one horizontal period when receiving an external power supply voltage. Since the output voltage creation circuit that creates the drive voltage by charging the external power supply voltage to the capacitor only during the output period is provided, it is possible to create a multi-gradation drive voltage with one external power supply voltage. it can. Therefore, even when the number of bits of the video signal is increased in order to improve the image quality, it is possible to create a multi-gradation drive voltage without increasing the number of types of external power supply voltage. Along with this, the scale of the external power supply can be reduced, and the cost can be reduced. In addition, the number of input terminals of an LSI (Large Scale Integrated Circuit) incorporating the above drive circuit is reduced, which facilitates mounting. Further, the accuracy required for the external power supply voltage is relaxed, and the adjustment management becomes easy.

The output voltage generating circuit has two capacitors for each signal system, and when the external power supply voltage is alternately charged in the two capacitors for each horizontal period to generate the drive voltage, The drive voltage can be alternately output from the two capacitors for each horizontal period. That is, even when one capacitor is being charged, the other capacitor can output the drive voltage, and the drive voltage can be continuously output without interruption.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a display device drive circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of one signal system of the display device drive circuit.

FIG. 3 is a diagram showing a timing signal generation circuit which constitutes the display device drive circuit.

FIG. 4 is a diagram showing an output waveform of the timing signal generation circuit.

FIG. 5 is a diagram showing an output waveform of the timing signal generation circuit.

FIG. 6 is a diagram illustrating how a voltage control circuit included in the display device drive circuit creates a control signal.

FIG. 7 is a diagram exemplifying an output waveform of a timing signal generation circuit which constitutes the display device drive circuit of the present invention.

FIG. 8 is a diagram illustrating a manner in which a voltage control circuit included in the display device drive circuit of the present invention creates a control signal.

FIG. 9 is a diagram illustrating a relationship between a timing signal and a drive voltage.

FIG. 10 is a diagram showing a relationship between an applied voltage and a transmittance of normally white liquid crystal.

FIG. 11 is a diagram showing how to correct a drive voltage.

FIG. 12 is a diagram showing an overall configuration of a conventional display device drive circuit.

FIG. 13 is a diagram showing a configuration of one signal system of the conventional display device drive circuit.

[Explanation of symbols]

1 shift register 2 sampling memory 3 hold memory 4 timing signal creation circuit 5 voltage control circuit 6 output voltage creation circuit 21, 22, 23, 31, 32, 33, 41, 42, 43, 49,
50,51,52,53,54,55 D-flip-flop ASW1, ASW2, ASW3, ASW4 analog switches C1, C2 capacitor L1, L2 interconnection _{O 1, ..., On, ...} , Om source line

Claims (2)

[Claims] 1. A drive circuit for a display device which outputs a multi-grayscale drive voltage based on an input digital video signal of a predetermined number of bits, wherein a timing signal having a different pulse width within one horizontal period is output. A timing signal generating circuit for generating a number corresponding to the key number, receiving the video signal and the timing signal, and selecting one of the timing signals based on the content of the video signal for each horizontal period. , A voltage control circuit which outputs a control signal of a predetermined level only for a period corresponding to the pulse width of the selected timing signal, and a capacitor, which receives an external power supply voltage and receives the control signal of the voltage control circuit within one horizontal period. A drive circuit for a display device, comprising: an output voltage generation circuit that charges the external power supply voltage in the capacitor to generate a drive voltage only during a period in which is output. 2. The output voltage creating circuit has two capacitors for each signal system, and creates a drive voltage by alternately charging the external power supply voltage to the two capacitors every horizontal period. The display device drive circuit according to claim 1.