JP2520169B2 - Driving circuit for display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device, and more particularly to a drive circuit for a display device capable of performing gray scale display by an amplitude modulation drive method. The matrix type liquid crystal display device will be described below as an example of the display device.
The present invention is also applicable to drive circuits for other types of display devices, such as EL (electroluminescence) display devices and plasma displays.

(Prior Art) FIG. 5 schematically shows an example of a conventional matrix type liquid crystal display device. The matrix type liquid crystal display device of FIG. 5 has a TFT (T) as a switching element for driving the pixel electrodes.
hin Film Transistor). The TFT liquid crystal panel 100 has n lines (numbers 0 to n arranged in parallel with each other).
-1) scan electrodes 101 and m signal electrodes 102 (numbers 0 to m-1) arranged orthogonal to the scan electrodes 101 and parallel to each other.
It has and. A TFT 104 for driving the pixel electrode 103 is provided near each intersection of the scanning electrode 101 and the signal electrode 102. One horizontal scanning line is composed of m picture element electrodes 103 corresponding to one scanning electrode 101.

The TFT liquid crystal panel 100 is driven by a driving circuit including a source driver 200 and a gate driver 300. The source driver 200 and the gate driver 300 are connected to the signal electrode 102 and the scan electrode 101 of the TFT panel 100, respectively.
The source driver 200 samples and holds the input analog image signal or video signal, and supplies the sampled and held signal to the signal electrode 102. On the other hand, the gate driver 300 sequentially outputs scan pulses to the scan electrodes 101. A control signal such as a clock input to the gate driver 300 and the source driver 200 is given from the control circuit 400.

The source driver 200 will be described in detail with reference to FIG. The source driver 200 includes a shift register 210,
A sample hold circuit 220 and an output buffer 230 are provided. In the shift register 210, a shift pulse input from the control circuit 400 is shifted according to a shift clock, the line _{B 1, B 2, ...,} B i, ..., sequentially sampling pulses B _m is output. Along with this, the analog switches ASW1 (1), ..., ASW of the sample hold circuit 220
1 (i), ..., ASW1 (m) sequentially become conductive, and the sampling capacitor 221 is sequentially charged to the instantaneous amplitude v (i, j) of the input analog image signal. Where v
(I, j) is the instantaneous amplitude of the analog image signal to be written in the pixel electrode 103 corresponding to the intersection of the i-th signal electrode and the j-th scanning electrode of the TFT panel 100. In this way, after the image signal of one horizontal scanning period is sampled by the sample hold circuit 220, the output pulse OE
Is input and the image signal is transferred from the sampling capacitor 221 to the hold capacitor 222. The image signal held by the hold capacitor 222 is output to the output buffer 230.
Is output to the signal electrode 102 via.

FIG. 7 shows an outline of input / output signal waveforms in the source driver 200. In FIG. 7, v (C _SPL (i)),
v (C _H (i)) and v ₅ (i) are the voltage of the i-th sampling capacitor 221 and the i-th holding capacitor 222.
And the output voltage of the i-th output buffer 230 are shown.

(Problems to be Solved by the Invention) In the drive circuit of the so-called analog image signal sampling system as described above, in order to increase the capacity and the definition of the display panel such as the TFT liquid crystal panel 100, the following number is required. It has become clear that there is a problem.

(1) In the drive circuit that samples the amplitude of the analog image signal, the sampled image signal amplitude v (i, j)
Accuracy is determined by the time constant determined by the on-resistance R _ON when the analog switch ASW1 (i) is conducting and the capacitance C _SPL of the sampling capacitor 221, so that the sampling does not narrow the frequency band of the image signal. Therefore, it is necessary to select the above time constant. That is, if the frequency at which the signal level decreases by 3 dB in the frequency characteristics of the input analog image signal is f (-3 dB) Hz, the condition of the following equation must be satisfied.

By the way, as the display panel (TFT liquid crystal panel 100) has a larger capacity and higher definition, the frequency band of the input image signal is becoming wider, and therefore high-speed sampling is required.
Low R _ON and small C _SPL are required to satisfy the above equation.

However, due to the OE pulse, the sampling capacitor
By distributing the charge of 221 to the hold capacitor 222, the voltage of the hold capacitor 222 having the capacitance C _H becomes And when C _H (i) << C _SPL (i), v (C
_H (i)) + v (i, j). Therefore, in order to minimize the amplitude attenuation due to the charge distribution from the sampling capacitor 221 to the hold capacitor 222, there is a limit to the reduction of the capacitance C _SPL . In addition, on-resistance R _{ON and} capacitance C
_The capacitance C _SPL cannot be made too small in order to suppress the deterioration or unevenness of the input / output linearity due to the manufacturing variation of _SPL and C _H. As described above, there is a limit to reducing the capacity of the sampling capacitor 221, and it is difficult to significantly widen the frequency band of the input image signal. This has been an obstacle to increasing the capacity of the display panel.

(2) The analog image signal is supplied to the source driver 200 via the bus line as shown in FIG. 6, but the frequency band of the image signal becomes wider with the increase in the capacity and definition of the display panel. At the same time, the wiring capacity of the bus line increases. Therefore, a broadband power amplifier is required on the side of the circuit for supplying the image signal, which causes a cost increase.

(3) When a plurality of analog image signal supply bus lines are provided for color image display that requires R, G and B video signals, the display panel has a large capacity,
With the increase in definition, the broadband power amplifier described above is required to have an extremely high quality in which there is no phase difference between a plurality of image signals and there is no variation in amplitude characteristics and frequency characteristics.

(4) In the drive circuit of the matrix type display device, CR
Unlike the case of displaying on T, the analog image signal is sampled according to the clock and displayed on the picture elements arranged in a matrix, but the delay in the drive circuit including the delay in the bus line is avoided. Therefore, it is very difficult to ensure the accuracy of the sampling position for the analog image signal. In particular, when displaying computer graphics in which the relationship between the image signal and the address of the display pixel is clearly defined on a matrix type display device, in principle, a computer-generated image can be completely displayed. Although it should be possible to reproduce on the panel, the display position shift of the image, the image bleeding, etc. due to the delay and the deterioration of the frequency characteristic which occur in the drive system,
It cannot be avoided by the conventional driving circuit of the analog image signal sampling system.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a drive circuit for a display device capable of solving the above-described drawbacks of the analog image signal sampling type display system. To do.

(Means for Solving the Problems) A drive circuit for a display device according to the present invention has a display unit provided with a plurality of parallel signal electrodes, and outputs a digital image signal of a predetermined plurality of levels. A signal electrode driving means for converting the DC voltage signal into any one and sending the DC voltage signal to the signal electrode is provided. The signal electrode driving means includes a sampling generation circuit that generates a sampling pulse based on a clock signal,
A digital image signal storage circuit for directly storing a digital image signal corresponding to each input signal electrode based on the sampling pulse, and the digital image signal storage circuit corresponding to each signal electrode based on an output of the storage circuit. It is configured to convert a digital image signal into a DC voltage signal. Thereby, the above object is achieved.

According to the present invention, in the drive circuit for the display device, the signal electrode drive means is a data decoding circuit for decoding information of the digital image signal stored in the digital image signal storage circuit, and a plurality of data decoding circuits having different levels. A circuit configuration having a DC voltage signal output means for outputting a DC voltage signal and a selection means for selectively sending any one of the plurality of DC voltage signals to the signal electrode according to the output of the data decoder circuit is adopted. It is a thing.

According to the present invention, in the drive circuit for the display device, the digital image signal storage circuit has a circuit configuration for storing the input digital image signal for at least one horizontal scan.

(Operation) In the present invention, the digital image signal is converted into a digital image.
Since the obtained analog signal is applied to the signal electrodes by performing analog conversion and amplitude modulation, avoiding the deterioration of the frequency characteristics due to the sampling time constant when sampling the amplitude of the analog image signal. Therefore, it is possible to avoid the amplitude attenuation due to the charge distribution between the sampling capacitor and the hold capacitor.

Further, since the digital image signal storage circuit is controlled by the sampling pulse output from the sampling pulse generation circuit to store the digital image signal directly in the storage circuit, a circuit portion for storing data It is possible to achieve low power consumption.

(Examples) The present invention will be described below with reference to Examples.

FIG. 1 schematically shows an example of a matrix type liquid crystal display device using an embodiment of the present invention. The drive circuit for displaying on the TFT liquid crystal panel 100 includes a source driver 2, a gate driver 300, and a control circuit 4.
The gate driver 300 has a configuration substantially similar to the conventional one shown in the fifth). The source driver 2 obtains an amplitude-modulated analog signal by digital-analog converting the input digital image signal or video signal and sends the analog signal to the signal electrode 102 of the TFT liquid crystal panel 100. Up-down counter and decoder circuit 20, digital data memory 30, data decoder circuit
A level shifter circuit 60 and a D / A conversion output circuit 50 are provided. Various signals necessary for the operation of the source driver 2 are supplied from the control circuit 4.

The source driver 2 is shown in more detail in FIG. The example shown in FIG. 2 is for performing color display, and R, G
And B image signals are 4-bit data R _{0 to} R ₃ and G _{0, respectively.}
~G _3, and are represented by B ₀ ~B _3. The up / down counter and decoder circuit 20 includes an up / down counter 21 and a decoder 22. The up / down counter 21 is supplied with a U / D signal for designating a count in the increasing direction or a count in the decreasing direction and a clock CK for performing the counting operation. Up-down counter 21
The output of is decoded by the decoder 22. The up / down counter and decoder circuit 20 can also be configured with a shift register.

R signal (R ₀ ~ included in the input digital image signal
The R ₃ ), the G signal (G _{0 to} G ₃ ) and the B signal (B _{0 to} B ₃ ) are once latched by the latches 31, 32 and 33, respectively, and then according to the output of the decoder 22, the digital data memory 30 Are stored in the corresponding storage units in the R memory 34, the G memory 35, and the B memory 36, respectively. After the digital image signal for one horizontal scanning period is stored in the digital data memory 30, by inputting the latch strobe signal LS,
The data in the digital data memory 30 is given to the data decoder circuit 40 in parallel. The output of the data decoder circuit 40 is given to the D / A conversion output circuit 50 via the level shifter 60. To the D / A conversion output circuit 50, DC voltage signals V _{0 to} V ₁₅ having different levels (16 steps) are given from a DC voltage generating circuit (not shown). In this embodiment, the level of the voltage signal is set to increase from the signal V ₁₅ to the signal V ₀ .

A block diagram of a system for processing the R signal between the data decoder circuit 40 and the D / A conversion output circuit 50 is shown in FIG. The data decoder circuit 40 includes an R signal R ₀ (i) from the R memory 34.
A 4-bit latch circuit 41 to which R ₃ (i) is input and a decoder 42 are provided. R signal R ₀ (i) ~ R
₃ (i) is the latch circuit 4 in response to the latch strobe signal LS
Latched to 1 and decoded by decoder 42.
The output of each inverting output terminal 0 to 15 of the decoder 42 is the R signal R
Depending on the contents of ₀ (i) to R ₃ (i), one of them becomes L level and the other becomes H level (for example, output terminal 3
There the L level), is level converted respectively by the level shifter 61 _{0-61 15} in the level shifter circuit 60. In the case of this embodiment, the up / down counter circuit 20, the digital data memory 30, and the data decoder circuit 40 have V _CC = 5.
Although it is a logic circuit that operates with a power supply voltage of V, V _SS = 0V, TF
In order to drive a display panel such as the T liquid crystal panel 100, a voltage higher than the power supply voltage of the logic circuit is usually required, and thus the level conversion as described above is required.

In the D / A conversion output circuit 50, analog gates AG _{0 to} AG ₁₅ are provided between the applied DC voltage signals V _{0 to} V ₁₅ and the output ends, respectively. The analog gate AG ₀ ~AG _15, the inverted output of the level shifter 61 _{0-61 15} are applied respectively, the applied voltage is turned on at the H level. For example, when the output of the terminal 3 of the decoder 42 is L level, the output of the level shifter 61 ₃ becomes H level, the analog gate AG ₃ becomes conductive, and the DC voltage signal V ₃ having the fourth level is used as the R signal as the signal electrode. Sent to 102.
Each part of the decoder circuit 40, the level shifter circuit 60, and the D / A conversion output circuit 50 corresponding to each signal electrode 102 operates in parallel as described above.

FIG. 4 shows an outline of the above display drive timing. In the example shown in FIG. 4, as the R signal, G signal and B signal,
In the j-th horizontal scan, DC voltage signals V ₃ , V ₅ and V ₆
However, in the (j + 1) th horizontal scan, a DC voltage signal
V ₁₀ , V ₁₂ and V ₁₄ are selected respectively. In this embodiment, the time required for D / A conversion of the image signal is substantially only the time required for decoding by the decoder 42. Therefore, the time required for D / A conversion is extremely short. When the digital data memory 30 stores an image signal for one horizontal scan as in the present embodiment, the horizontal scan period next to the horizontal scan period in which the image signal is input is fully utilized to set D / A
Just convert it. Therefore, although it is necessary to store the input image signal in the digital data memory 30 at high speed, the D / A conversion can be performed at relatively low speed.

In addition, since the display panel such as the TFT liquid crystal panel 100 is deteriorated quickly when the applied voltage contains a DC component,
The voltage signals V _{0 to} V ₁₅ applied to the display panel may be prevented from deteriorating so that their polarities are alternately changed every time a predetermined horizontal scanning period elapses.

(Effect of the Invention) According to the present invention, there is provided a drive circuit for a display device capable of solving various problems of the conventional drive circuit of the analog image signal sampling system.

In the drive circuit of the present invention, the digitized image signal is stored and transferred. Therefore, it is possible to avoid the deterioration of the frequency characteristic of the image signal due to the sampling time constant, which has been a problem in the driving circuit of the analog image signal sampling system. Further, amplitude attenuation due to charge distribution between the sampling capacitor and the hold capacitor does not occur. Furthermore, variations in delay time and the like due to variations in circuit constants of constituent elements of the drive circuit do not occur.

The drive circuit of the present invention does most of the processing on digital signals. Therefore, the operation of each unit in the circuit can be surely synchronized. Therefore, it is possible to suppress the displacement of the display position of the image, the blurring of the image, etc. due to the delay or the like generated in the circuit, and the display accuracy and the display quality of the image are significantly improved. This is particularly effective in faithfully displaying high-definition image information, so that computer graphics can be displayed accurately.

The drive circuit of the present invention can basically cope with the increase in the capacity of the display panel by increasing the speed of a logic circuit which constitutes a memory circuit for storing an input digital image signal. Since the image signal storage circuit of the drive circuit of the present invention can store at least one horizontal scanning image signal,
D / A conversion of the stored digital image signal can be performed at a relatively low speed by using the next horizontal scanning period. This contributes to cost reduction of the drive circuit and also contributes to improvement of display accuracy and the like.

Further, since the digital image signal storage circuit is controlled by the sampling pulse output from the sampling pulse generation circuit to store the digital image signal directly in the storage circuit, a circuit portion for storing data There is an effect that power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a matrix type liquid crystal display device using an embodiment of the present invention, FIG. 2 is a block diagram of a source driver of the embodiment, and FIG. 3 is a data decoder circuit and a level shifter of the embodiment. And FIG. 4 is a timing chart showing the operation of the embodiment, and FIG. 5 is a schematic block diagram of an example of a matrix type liquid crystal display device using a conventional drive circuit. 6 and 6 are circuit diagrams of the source driver of the display device of FIG. 5, and FIG. 7 is a timing chart showing the operation of the source driver of FIG. 2 ... Source driver, 20 ... Up-down counter and decoder circuit, 21 ... Up-down counter, 22 ...
Decoder, 30 ... Digital data memory, 31 ... 33 ... Latch, 34 ... R memory, 35 ... G memory, 36 ... B memory, 341 ... storage unit, 40 ... D / A comparison conversion output circuit , 41 …… Latch circuit, 42 …… Decoder, 60 …… Level shifter circuit, 60 _{0 to} 61 ₁₅ …… Level shifter, 100 …… TFT
Liquid crystal panel, 101 ... Scan electrode, 102 ... Signal electrode, 103
…… Pixel electrode, 104 …… TFT, 300 …… Gate driver, A
G ₀ ~ AG ₁₅ …… Analog gate.

Claims (3)

(57) [Claims] 1. A drive circuit for a display device having a display unit provided with a plurality of parallel signal electrodes, wherein a digital image signal is converted into any of a plurality of predetermined levels of DC voltage signals, A signal electrode driving means for sending a DC voltage signal to the signal electrode is provided, wherein the signal electrode driving means is a sampling pulse generating circuit for generating a sampling pulse based on a clock signal, and an input based on the sampling pulse. A digital image signal storage circuit for directly storing a digital image signal corresponding to each signal electrode, and a DC voltage signal of the digital image signal corresponding to each signal electrode based on an output of the digital image signal storage circuit. Drive circuit for a display device configured to perform the conversion of. 2. The signal electrode driving means includes a data decoder circuit for decoding information of a digital image signal stored in the digital image signal storage circuit, and a DC voltage signal output for outputting a plurality of DC voltage signals having different levels. 2. The display device according to claim 1, further comprising: means, and selection means for selectively transmitting any one of the plurality of DC voltage signals to the signal electrode according to an output of the data decoder circuit. Drive circuit. 3. The drive circuit for a display device according to claim 2, wherein the digital image signal storage circuit stores the input digital image signal for at least one horizontal scan.