JPH06266314A - Driving circuit of display device - Google Patents

Abstract

PURPOSE:To provide the driving circuit of the display device which can obtain a sufficient sampling time with a simple constitution without performing parallel processing and is adaptive to high-precision driving as to the driving circuit of a display device, specially, a data driver which drives a high-definition LCD panel. CONSTITUTION:This circuit includes N (N<=2) input lines 42-1 and 42-2 which are set to R, G, and B of an analog video signal respectively and supplied with the same data DATA1 and DATA2 delayed in order, N analog switches SW1 and SW2 which are connected corresponding to the N input lines 42-1 and 42-2, a shift register which operates the N analog switches SW1 and SW2 with delay in order, and a sample holding capacitor C connected to the output sides of the N analog switches DATA1 and DATA2 and is charged in order with the N same data DATA1 and DATA2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a display device, and more particularly to a data driver for driving a high definition LCD panel.

With the recent increase in the definition of LCDs, it is required to increase the speed of peripheral circuits. In particular, it is necessary to make the video sampling circuit of the data driver that processes the video signal compatible with high-speed driving.

[0003]

2. Description of the Related Art In a liquid crystal display (LCD) used as an image display device, the quality of the display device is rapidly improving, and it is about to replace the CRT. Among flat panel displays, active matrix type LCDs are the mainstream of liquid crystal displays, which are characterized by being thin and lightweight and operating with low power consumption. This LCD is composed of a substrate in which electrodes run in a matrix and switching elements (TFTs, etc.) are connected to the intersections, a substrate in which electrodes are evenly distributed, and a liquid crystal sealed between both substrates. It is configured. Here, the former substrate is called a TFT substrate, and the latter substrate is called a common substrate.

FIG. 8 shows a TFT substrate of an LCD,
In the TFT substrate 8, the data bus line (signal electrode) 10
-10, gate bus lines (scan electrodes) 12 to 12 intersect in a matrix, and TFTs are provided at all the intersections.
14 to 14 are connected as switching elements.
When the TFTs 14 to 14 of the row selected by the gate bus lines 12 to 12 are turned on, the video signal voltage applied to the data bus lines 10 to 10 is applied to the TFTs 14 to 1.
4 is written to each pixel electrode 136 to 16, and the electrodes 16 to 16 retain electric charge until the next row is selected, thereby retaining information. Since the tilt of the liquid crystal is determined according to the held information, it is possible to control the amount of transmitted light and display gradation. Furthermore, color display is realized by mixing lights using RGB color filters.

There are two types of ICs that drive LCDs.
One is a data driver for applying to the data bus line, and the other is a gate driver for applying to the gate bus line. Here, the data driver related to the present invention will be described.

FIG. 9 shows a block circuit of a conventional LCD data driver, which is composed of a shift register 18, a sample hold circuit 20, and an output buffer circuit 22. Shift register 18
Is based on the start pulse SP and the clock signal CLK, the sample and hold 20 inputs the input data RDATA, G.
The timing for sampling DATA and BDATA as analog information is controlled, and the data RDATA, GDATA, and BDATA obtained by this control are set to 1
When held in the line sample and hold circuit 20, the analog information is transferred as it is to the output buffer circuit 22 in the next stage. The voltage output from the output buffer circuit 22 is applied to the data bus lines 10 to 10 (see FIG. 8) of the liquid crystal panel.

[0007]

A video signal of a device capable of high-definition display such as a workstation is 100M.
Since the data is sent at a frequency exceeding Hz, it is not possible to take a sufficient time for the sampling process in the sample hold circuit of the data driver. Therefore, at present, a video signal whose speed has been reduced by processing the video signal in parallel is input to the data driver. In the parallel processing of the high-speed video signals, when the input is an analog video signal, it is once A / D converted and then rearranged by a line memory. If the input is a digital video signal, the line memory is used for rearrangement. The video signal is D / A converted and then sent to the input side of the data driver.

This point will be described below with reference to FIGS. 10 and 11. FIG. 10 shows a circuit configuration of a conventional LCD driver (in the case of an analog video signal). The input data RDATA, GDATA, BDAT of the analog video signal are shown.
After A is A / D converted by the A / D converter 24, 1 line data is latched and rearranged in the line memory 26, and D / A converted by the D / A converters 28 and 28,
It is supplied to the data drivers 30 and 30. Note that reference numeral 3
Reference numerals 36, 38, and 34 denote analog lines.
38 indicates a digital line. The data driver 30,
30 is connected to the TFT substrate 8 via the data bus lines 10 to 10 and 10 to 10, while the gate driver 4 is connected.
0 and 40 are connected to the TFT substrate 8 through gate bus lines 12 to 12 and 12 to 12. The structure of the TFT substrate 8 is the same as that shown in FIG.

FIG. 11 shows a circuit configuration of a conventional LCD driver (in the case of a digital video signal), which is input data RDATA, GDATA, BDA of the digital video signal.
TA is latched and rearranged for one line data in the line memory 26 as it is, D / A converted in the D / A converters 28 and 28, and then supplied to the data drivers 30 and 30. In addition, reference numerals 34 and 34 represent analog lines,
Reference numerals 36, 38 and 38 denote digital lines. Further, the data drivers 30, 30, the gate drivers 40, 40, T
The description of the FT substrate 8 is the same as in the case of FIG.

As described above, the conventional LCD driver uses the line memory 26 to process the video signals in parallel, which causes an increase in peripheral circuits, which hinders cost reduction.

As described above, since the conventional LCD driver does not have the ability to process the high-speed video signal for the high-definition display device, it is necessary to perform the parallel processing of the video signal, and the peripheral circuit for this parallel processing is required. The problem was that the

Therefore, an object of the present invention is to provide a drive circuit of a display device which can obtain a sufficient sampling time with a simple structure without performing parallel processing and is compatible with high-definition drive.

[0013]

According to the present invention, in a drive circuit for driving a display device, N [N ≧ 2] pieces of the same data (DATA1, DATA2) of an analog video signal are sequentially delayed. Input line (42-1, 42-
2) and N analog switches (SW) respectively connected to the N input lines (42-1 and 42-2).
1, SW2) and the N analog switches (SW1,
A shift register (1) for sequentially delaying and operating SW2)
8) and the N analog switches (SW1, SW)
It is connected to the output side of 2), and N identical data (D
ATA1, DATA2) and a sample-and-hold capacitor (C) that is sequentially charged.

FIG. 1 shows a drive circuit of a display device according to the principle of the present invention, and (A) shows its circuit configuration.
(B) shows the timing chart. In FIG. 1A, analog video input lines 42-1 and 42-2 for the data DARA1 and DATA2 are provided, and the data DATA1 is the original analog video signal and the data D
ATA2 is a signal in which the phase of the data DATA1 is delayed by the time corresponding to one dot on the display screen. C is a sample and hold capacitor, and SW1 and SW2 store the data DATA1 and data DATA2 in the capacitor C, respectively.
SHP1 and SHP2 are sampling shift pulses for selecting the switch SW1 and the switch SW2, respectively. BF is a buffer that outputs the analog information stored in the capacitor C to the next-stage capacitor C.

Then, the sampling shift pulse SH
Analog switches SW1 and SW2 by P1 and SHP2
Are sequentially turned on, the data DATA1 and DATA2 of the input lines 42-1 and 42-2 are sequentially supplied to the capacitor C. Here, as described above, DATA2 is DATA
Since the signal has a phase delayed by a time corresponding to one dot on the display screen as compared with 1, the same data is charged twice in one capacitor C.

[0016]

The operation of the drive circuit shown in FIG. 1A will be described below.
This will be described with reference to the timing chart of (B).

In FIG. 1B, the data DATA2 is a signal delayed in phase from the data DATA1 by a time corresponding to one dot on the display screen (that is, a time corresponding to one data D1 in the data DATA1). First, at time T ₁ , the shift pulse SHP1 is selected and the switch S
The W1 is turned on, and the sample-and-hold capacitor C is precharged to a certain voltage VB 'by the analog voltage of one data D1 in the data DATA1. At the next time T ₂ , the shift pulse SHP2 is selected and the switch SW2 is turned on, and the analog voltage of one data D1 in the data DATA2 charges the sample hold capacitor C to the desired voltage VB corresponding to the data D1. To be done.

As described above, in the drive circuit according to the principle of the present invention, the data D1 in the data DATA1, DATA2 is
By sequentially supplying D2 to the capacitors, one sample-hold capacitor C can be charged twice with the same analog voltage of the data D1.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows an LC according to the first embodiment of the present invention.
The block circuit of the D driver is shown. The LCD driver is an analog driver having 120 outputs.

In FIG. 2, the LCD data driver comprises a shift register 18, a sample hold circuit 20, and an output buffer circuit 22. In the shift register 18, the sample hold 20 receives the input data RDATA based on the start pulse SP and the clock signal CLK.
1, RDATA2, GDATA1, GDATA2, BD
The timing for sampling ATA1 and BDATA2 as analog information is controlled. Here the data RDAT
A1, GDATA1, BDATA1 are original analog video signals, and RDATA2, GDATA2, BDA
TA2 is the data RDATA1, GDATA1, B
This signal has a phase delayed by a time corresponding to one dot on the display screen as compared with DATA1.

The sample hold circuit 20 transfers the sampled data to the output buffer circuit 22 in the next stage. Then, the voltage output from the output buffer circuit 22 corresponds to the data bus lines 10 to 10 (FIG. 8) of the liquid crystal panel.
Reference).

FIG. 3 shows the configuration of the shift register and sample hold circuit of the LCD driver of FIG. In FIG. 3, the circuit configuration focusing only on the data RDATA is shown, but the data GDATA and BDAT are not shown.
A has the same circuit configuration. The shift register 18 uses the data RDATA, GDATA, BDATA.
Commonly used for.

In FIG. 3, data RDATA1, RD
Analog video input lines 42-1 and 42-2 for ATA2 are provided, the data RDATA1 is the original analog video signal, and the data RDATA2 is the data RD.
This is a signal in which the phase of ATA1 is delayed by the time corresponding to one dot on the display screen. C1, C2, ~, C39, C4
0 is a sample hold capacitor, switch SW
Reference numerals 1-1 and SW1-2 are analog switches for charging the data RDATA1 and the data RDATA2 into the capacitor C1, respectively. The switches SW2-1 and SW2-
2, ..., SW39-1, SW39-2, SW40-1,
The same applies to SW40-2. Shift register 1
SHP1 and SHP2 from 8 are switches SW1 respectively.
-1, SW1-2 are sampling shift pulses for selecting the shift pulse SHP2 and the next SHP3.
Selects the switches SW2-1 and SW2-2, respectively, and the same applies to the following shift pulses. BF
1, BF2, ..., BF39, BF40 respectively output the analog information stored in the capacitors C1, C2, ..., C39, C40 to the capacitors C1 ', C2' ,.
It is a buffer for outputting to 9'and C40 '.

Next, referring to FIG. 4, the horizontal synchronizing signal HSYNC
Shifts to the “H” level, the shift register 18 shifts the sampling shift pulses SHP1, SHP2, SHP based on the start pulse SP and the clock signal CLK.
3 is sequentially set to "H" level. Also, the data RDATA
Reference numeral 1 is an original analog video signal, which is data RDAT.
A2 is a signal in which the phase of the data RDATA1 is delayed by the time corresponding to one dot on the display screen.

First, at time T ₁ , the shift pulse SHP1
Is selected and the switch SW1-1 is turned on, and the analog voltage of one data D1 in the data RDATA1 precharges the sample-hold capacitor C1 to a certain voltage VB ′.

The following are selected the time T ₂ the shift pulse SHP2 switch SW1-2 is activated ON, data R
The analog voltage of one data D1 in DATA2 charges the sample-hold capacitor C1 to the desired voltage VB corresponding to the data D1.

At this time T ₂ , the switch SW2-1 is also turned on by the shift pulse SHP2, and the data RDAT is output.
Due to the analog voltage of the data D2 in A1, the next sample and hold capacitor C2 is precharged to a certain voltage.

By sequentially performing the above operation, all the sample and hold capacitors C1 to C40 are charged twice with the same analog voltage of the data D1 to D40. That is, the sampling time is twice as long as the conventional one.

The analog information charged in the capacitors C1 to C40 is stored in the buffers BF1 to BF40, respectively.
Through the capacitors C1 ′ to C40 ′ of the next stage.

Next, FIG. 5 shows the circuit configuration of the LCD driver according to the second embodiment of the present invention (in the case of an analog video signal).
In the case of this analog video signal, an analog delay element such as a delay line is used to create delay data for input data.

More specifically, the input data RDATA, GD
ATA and BDATA are the original data RDAT as they are.
The data is supplied to the data drivers 30 and 30 as A1, GDATA1, and BDATA1, and after the phase is delayed by the analog delay element 44 for a time corresponding to one dot on the display screen, the delay data RDATA2 and GDATA are delayed.
2, BDATA2 is supplied to the data drivers 30, 30.

According to the above configuration, the data driver 3
0 and 30 can perform the operations described with reference to FIGS. 2, 3 and 4, and can realize a simpler structure than the conventional structure (see FIG. 10).

Reference numerals 46, 48 and 50 denote analog lines. The data drivers 30 and 30 are connected to the TFT substrate 8 via the data bus lines 10 to 10 and 10 to 10, while the gate drivers 40 to 40 are connected to the TFT substrate via the gate bus lines 12 to 12 and 12 to 12. 8
It is connected to the. The structure of the TFT substrate 8 is the same as that shown in FIG.

Next, FIG. 6 shows a circuit configuration of an LCD driver (in the case of a digital video signal) according to the third embodiment of the present invention.
Delay data is created for input data using a digital delay element such as a dot latch circuit.

More specifically, the input data RDATA, GD
ATA and BDATA are the original data RDAT as they are.
Data drivers 30, 30 after being D / A converted by the D / A converter 52 as A1, GDATA1, and BDATA1
To the delay data RDATA2, GDATA2, BDATA2 by delaying the phase by the time corresponding to one dot on the display screen by the digital delay element 54.
After that, the data is D / A converted by the D / A converter 56 and then supplied to the data drivers 30 and 30.

According to the above configuration, the data driver 3
0 and 30 can perform the operations described with reference to FIGS. 2, 3 and 4, and can realize a simpler configuration than the conventional configuration (see FIG. 11).

Reference numerals 58, 60 and 62 indicate digital lines, and reference numerals 64 and 66 indicate analog lines. Also,
Data drivers 30, 30, gate drivers 40, 4
0, the description of the TFT substrate 8 is the same as in the case of FIG.

As is apparent from the comparison of the second embodiment of FIG. 5 and the third embodiment of FIG. 6 with the conventional configuration of FIGS. 10 and 11, respectively, the conventional configuration provides high-definition driving. A large memory for one line is required. On the other hand, in the second and third embodiments of FIGS.
High-definition driving can be achieved with a simple configuration by simply replacing a large memory for one line with a memory for one dot or a delay element corresponding thereto.

Although the number of input lines for the analog video signal is two in the first, second and third examples, the number N of input lines is not limited to two. It is possible to further extend the sampling time by setting the number N of input lines to 3 or more and providing N analog switches corresponding to the number N. And FIG.
Shows an example in which the number N of input lines is set to 3.

FIG. 7 shows the configuration of the shift register and sample hold circuit of the LCD driver according to the fourth embodiment of the present invention. In FIG. 7, the data RD
Analog video input lines 42-1, 42-2, 42-3 for ATA1, RDATA2, RDATA3 are provided, the data RDATA1 is the original analog video signal, and the data RDATA2 is the data RDATA1 for one dot of the beat screen. Is a signal whose phase is delayed by a time corresponding to, and data RDATA3 is a time corresponding to one dot on the display screen (that is, data RDATA2).
This is a signal in which the phase of TA1 is delayed by a time corresponding to 2 dots on the display screen.

Then, the shift pulses SHP1 and SHP
2, SHP3 are sequentially switches SW1-1, SW1-2,
When SW1-3 is turned on, the data RDATA1,
The sample hold capacitor C1 is sequentially charged by RDATA2 and RDATA3. Therefore, the capacitor C1 is charged three times with the same data, and the sampling time is three times that of the conventional case. Since the charging operation for the sample and hold capacitor C2 and thereafter is the same as that for the capacitor C1, the description is omitted.

In each of the above embodiments, the LCD is taken as the display device, but the present invention is not limited to the drive circuit of the LCD, but can be applied to the drive circuit of the display device driven by the charging voltage. .

Further, although the color display device has been described in the above embodiments, the present invention can be applied to a monochrome display device. In this case, the configuration may be the same as that of any one of RGB.

[0044]

According to the present invention, a plurality of input lines are provided for an analog video signal, and the same data is supplied to the plurality of input lines in a sequentially delayed state, and the same data is supplied to the sample hold capacitor. It is configured to be charged multiple times. As a result, it is possible to eliminate the shortage of charging time in high-definition driving, and it is not necessary to carelessly set the capacitance of the sample hold capacitor to a small value. In addition, the peripheral circuit becomes simpler than the parallel processing performed by the conventional drive circuit.

As described above, the application of the present invention makes it possible to charge high-speed data with simple signal processing, which greatly contributes to the cost reduction of a high-definition display device.

[Brief description of drawings]

FIG. 1 shows a drive circuit of a display device according to the principle of the present invention, (A) is its circuit configuration diagram, and (B) is its timing chart diagram.

FIG. 2 is a block circuit diagram of an LCD driver according to a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a shift register and a sample hold circuit of the LCD driver of FIG.

FIG. 4 is a timing chart of the shift register and sample hold circuit of FIG.

FIG. 5 is a circuit configuration diagram (in the case of an analog video signal) of an LCD driver according to a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram (in the case of a digital video signal) of an LCD driver according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a shift register and a sample hold circuit of an LCD driver according to a fourth embodiment of the present invention.

FIG. 8 is a configuration diagram of a TFT substrate of an LCD.

FIG. 9 is a block circuit diagram of a conventional LCD driver.

FIG. 10 is a circuit configuration diagram of a conventional LCD driver (in the case of an analog video signal).

FIG. 11 is a circuit configuration diagram (in the case of a digital video signal) of a conventional LCD driver.

[Explanation of symbols]

 18 ... Shift register 20 ... Sample hold circuit 22 ... Output buffer circuit 42-1, 42-2 ... Input line DATA1, DATA2 ... Data SW1, SW2 ... Analog switch SHP1SHP2 ... Sample hall capacitor

Claims (3)

[Claims] 1. A drive circuit for driving a display device, wherein the same data (DATA1, DATA) of an analog video signal is used.
2) corresponds to N [N ≧ 2] input lines (42-1, 42-2) supplied in a sequentially delayed state and the N input lines (42-1, 42-2). N analog switches (SW1, SW
2), a shift register (18) that sequentially delays and operates the N analog switches (SW1, SW2), and is connected to the output side of the N analog switches (SW1, SW2). Individual identical data (DATA1,
A drive circuit for a display device, comprising: a sample hold capacitor (C) that is sequentially charged by DATA2). 2. A display device whose information source is an analog video signal, wherein an analog delay element (44) for delaying the analog video signal, the delayed analog video signal from the analog delay element (44) and the delay are received. The drive circuit according to claim 1, wherein the drive circuit receives an analog video signal which is not present on the N input lines (48, 50). 3. A display device in which an information source is a digital video signal, a digital delay element (54) for delaying the digital video signal, a delayed digital video signal from the digital delay element (54) and a delay. The non-digital video signal is received by the N input lines (60, 62).
A drive circuit for a display device, comprising: