JP2605699B2 - Display control circuit and color image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color image display device using a liquid crystal or the like, and more particularly, to a display control circuit for driving and controlling a column direction thereof.

[Conventional technology]

As an arrangement of color pixels in a color display device using a liquid crystal or the like as a display material, an arrangement as shown in FIGS. 3A and 3B was generally used. Here, R indicates red, G indicates green, and B indicates blue pixels. In FIG. 3A, pixels of the same color are arranged in the vertical direction, and R, G, B color pixels are alternately arranged in the horizontal direction. However, with this arrangement of color pixels, the resolution in the vertical direction is inferior. In FIG. 3B, the R, G, and B color pixels are alternately arranged in both the vertical and horizontal directions to solve the problem in FIG. 3A. However, in this arrangement of the color pixels, the resolution in the oblique direction (in FIG. 3B, the obliquely downward left) is inferior.

In order to compensate for the drawback in image display due to the conventional arrangement of color pixels as described above, a color image display device having an arrangement of color pixels as shown in FIG. 4 has been proposed. That is, the pixels are shifted in each row, and the R, G, B color pixels are alternately arranged in the horizontal direction so that the single color pixels do not continue in any of the vertical, horizontal, and diagonal directions. In FIG. 4, the shift between the j-th row and the j + 1-th row is 1/2 pixel.

[Problems to be solved by the invention]

A conventional column-direction drive of a color image display device of color pixels as shown in FIG. 4 will be described. In the column direction, video data is output from the drive circuit as a drive signal.
Is a video signal using a television as an example. Since the video signal of the jH-th (H: horizontal synchronizing signal period) and the video signal of the (j + 1) -th H are close to each other, generally they are almost the same video data. 502 is an enlargement of a portion of 501. Reference numeral 503 denotes a sampling clock signal for sampling video data, one cycle of which is the same as the time corresponding to one pixel. Sampling is performed at the falling edge of the sampling clock. In the j-th row, the video data of A of the jH-th video signal is stored in the pixel of a,
Similarly, C video data is written in the C pixel. Thus, in the (j + 1) th row, the (j + 1) Hth video data B and D should be written into each pixel of b and d.
Since the video data is always sampled at the falling edge of the sampling clock 503, the video data A and C are written to the pixels b and d. This will reduce the horizontal resolution of the image.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to increase the resolution in the horizontal direction in a color image display device in which color pixels are arranged as shown in FIG.

[Means for solving the problem]

In order to achieve the above object, first, a first pixel row in which each color pixel is sequentially arranged in a horizontal direction and each color pixel whose arrangement position is shifted with respect to the first pixel row are horizontally arranged. The second pixel row sequentially arranged is
In a display control circuit that supplies a drive signal to each pixel row of a color image display body that is alternately arranged in a vertical direction, a shift register that transfers shift data according to a clock signal, and a shift register that outputs shift data according to an output of the shift register A data capturing means for sequentially capturing image data for forming the drive signal to be supplied to a pixel row; and a phase inverting means for alternately inverting the phase of the clock signal supplied to the shift register in accordance with the generation of the shift data. Wherein the shift is performed when capturing the image data for forming a drive signal to be supplied to the first pixel row and when capturing the image data for forming a drive signal to be supplied to the second pixel row. The phase of the clock signal supplied to the register is inverted.

Second, a first pixel row in which each color pixel is sequentially arranged in the horizontal direction, and a second pixel in which each color pixel whose arrangement position is shifted with respect to the first pixel row are sequentially arranged in the horizontal direction Line and
In a color image display device having a color image display body alternately arranged in a vertical direction and a drive signal being supplied to each pixel row, a shift register for transferring shift data according to a clock signal; A data capturing unit for sequentially capturing image data for forming the drive signal to be supplied to a pixel row according to an output of a register; and a phase of the clock signal supplied to the shift register alternately according to generation of the shift data. Phase inverting means for inverting the image data when forming the drive signal to be supplied to the first pixel row, and when converting the image data to form the drive signal to be supplied to the second pixel row. When taking in, the phase of the clock signal is inverted.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a configuration block diagram of a first embodiment of the present invention. FIG. 6 is a time chart thereof. 101 is a red (R) image data sampling circuit. The circuit is A /
It comprises a D converter 104 and an encoder 107. The A / D converter 104 further includes a comparator 105 and a sampling switch 106. Comparator 105 has two inputs,
One side is connected to one tap terminal of a resistor r group connected in series so as to generate an R signal and the other side to generate a voltage of a desired number of gradations. The comparator 105 compares both inputs, determines the level of the R signal, and outputs a digital signal. Sampling switch 106
Samples the A / D-converted digital signal by the output signal of the 111 EX-NOR gate. The timing changes at the rising edge of the 111 signal as shown in FIG. The A / D converter 104 has a desired number of gradations. For example, in the case of 16 gradations, 16 outputs are input to the 107 encoders and encoded into 4-bit codes. 102 green (G) image data sampling circuit, 103 blue (B)
The image data sampling circuit also has the same configuration as 101.

R, G, B image data 108 digitized to 4 bits
Are input to the multiplexer 109. Multiplexer 1
At 09, the image data 108 is multiplexed according to the arrangement of the color pixels in the horizontal and vertical directions of the color image display, and 4-bit image data 117 is output to the first memory group 114.

Reference numeral 113 denotes a shift register which transfers shift data D by a shift clock φ. Reference numeral 114 denotes a first memory group. Each of the memories is configured by, for example, a 4-bit latch and configured to capture 4-bit image data 117. Importing image data
This is performed by the output 118 of each stage of the shift register 113. Each memory of the second memory group 115 is also configured by, for example, a 4-bit latch, and is configured to receive the 4-bit output 119 of the corresponding memory of the first memory group. The loading of 119 is performed by a LOAD signal generated after the loading of the image data 117 in the first memory group 114 is completed. The 4-bit image data 120 captured by the LOAD signal is output to the driver 116. The driver 116 uses the 4-bit image data 120 to output the ON potential V _ON and OF supplied from the outside.
The ratio in the selection period to the F potential V _OFF is determined, and is output as the column direction drive signal 121 to the color image display.

Reference numeral 110 denotes a toggle F / F (flip flop) to which a signal D is input as a toggle signal. D is also a shift data signal of the shift register 113. D is a short pulse of 1H cycle as shown in FIG. 6, for example, and is close to the start position of the image information in 1H. The LOAD signal is slightly ahead of D. Q output of toggle F / F110 is D
Is divided, and “1” and “0” are repeated every 1H. CL is a clock signal, one cycle of which corresponds to the time of one pixel. 111 is an EX-NOR gate, which outputs a CL signal and 1
10Q output signal is input. Therefore, the output of 111 repeats the same phase and the opposite phase with the CL signal every 1H as shown in FIG. In each sampling circuit of R, G, B, the signal 111
Multiplexer 109
The 4-bit image data 117 from
A, then C. Then, the image data 117 is loaded into the first memory group 114 at the output 118 of each stage of the shift register 113. In the (j + 1) H, the 4-bit image data 117 is in the order of B and D of the video signal, and the output 118 of each stage of the shift register 113 is output.
Then, it is taken into the first memory group 114.

As a result, pixels a and c in row j of FIG.
A and C are written in the pixels of b and d in the (j + 1) th order in the same manner as B and D, so that the resolution in the horizontal direction can be increased.

(Second Embodiment) FIG. 2 is a configuration block diagram of a second embodiment of the present invention. FIG. 7 is a time chart thereof. Reference numeral 203 denotes a multiplexer to which R, G, and B color signals are input. At 203, the image data is multiplexed according to the arrangement of the color pixels in the horizontal and vertical directions of the color image display. Reference numeral 204 denotes a shift register which transfers shift data D by a shift clock φ. 205 is a sampling hold circuit. One stage includes an analog switch 206, a capacitor 207, and a buffer amplifier 208. The analog switch 206 has a control signal 210 output from each stage of the shift register 204 as 210, one end connected to the image data line from the multiplexer 203, the other end connected to a capacitor 207 (one end of which is grounded). It is connected to the buffer amplifier 208. The output of 208 is the column drive signal 21
Is one. Explaining the operation, the analog switch 206 is turned on at the output 210 of each stage of the shift register 204, and the image data at that time is written to the capacitor 207. The buffer amplifier 208 forms a column direction drive signal 211 based on the image data written in the capacitor 207.

A toggle F / F 201 receives a signal D as a toggle signal. D is also a shift data signal of the shift register 204. D is a short pulse of 1H cycle as shown in FIG. 7, and is close to the start position of the image information in 1H. The Q output 209 of the toggle F / F 201 is a signal obtained by dividing D, and repeats “1” and “0” every 1H. CL is a clock signal whose cycle corresponds to the time of one pixel. 20
Reference numeral 2 denotes an EX-NOR gate, which is a CL signal and a Q output signal 209 of 201.
Is entered. The output of 202 is the shift clock φ of the shift register 204. Therefore, 204φ repeats the same phase and the opposite phase with respect to the CL signal every 1H as shown in FIG. In the shift register 204, the shift data D is transferred at the falling edge of the shift clock φ. Therefore, jH
Sample the image data in the order of A and C of the video signal, and j + 1H sample the image data in the order of B and D.

As a result, pixels a and c in row j of FIG.
A and C are written in the pixels of b and d in the (j + 1) th row in the same manner as B and D, so that the resolution in the horizontal direction can be increased.

〔The invention's effect〕

As described above, according to the present invention, in a column-direction drive circuit of a color image display having a pixel shift of one pixel or less for each row, the timing of sampling a video signal corresponding to each row is adjusted to a pixel shift. By shifting each line by the corresponding time, a color image display device without losing the horizontal resolution is provided. In addition, the configuration in which the sampling (acquisition) timing is shifted is realized by efficiently utilizing the shift data supplied to the shift register that generates the sampling timing signal and the generation of the clock signal, and changing the clock phase according to the generation of the shift data. This can be achieved only by providing a simple additional circuit for inversion. In the present invention, the pixel shift in each row is described as half a pixel. However, it is apparent that a color image display device according to the present invention can be realized with the same configuration even with other shifts of one pixel or less.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention. FIG. 2 is a block diagram of a second embodiment of the present invention. FIGS. 3A and 3B are color image display members. 4............. FIG. 5... Conventional video signal sampling time chart FIG. 6. Time chart of each part Fig. 7 ... Fig. 2 Time chart of each part

Claims (6)

(57) [Claims] 1. A first pixel row in which each color pixel is sequentially arranged in a horizontal direction, and a second pixel row in which each color pixel whose arrangement position is shifted with respect to the first pixel row is sequentially arranged in a horizontal direction. A display control circuit for supplying a drive signal to each pixel row of a color image display body in which pixel rows are alternately arranged in a vertical direction; a shift register for transferring shift data in response to a clock signal; A data capturing means for sequentially capturing image data for forming the drive signal to be supplied to a pixel row according to the output of the pixel row, and a phase of the clock signal supplied to the shift register alternately according to the generation of the shift data. And a phase inverting means for inverting the image signal, wherein the image data for forming the drive signal to be supplied to the first pixel row is captured and the drive signal supplied to the second pixel row is formed. In the case of capturing the image data to be display control circuit characterized by comprising by inverting the clock signal of the phase supplied to the shift register. 2. The display control circuit according to claim 1, wherein said data fetch means comprises a group of memories for fetching digital image data. 3. The display control circuit according to claim 1, wherein said data capturing means comprises a group of switches for sampling image data and a group of capacitors for holding the sampled image data. . 4. A first pixel row in which each color pixel is sequentially arranged in the horizontal direction, and a second pixel row in which each color pixel whose arrangement position is shifted with respect to the first pixel row is sequentially arranged in the horizontal direction. In a color image display device having a color image display in which pixel rows are alternately arranged in a vertical direction, and a drive signal is supplied to each pixel row, a shift for transferring shift data in response to a clock signal A register, data capturing means for sequentially capturing image data for forming the drive signal to be supplied to a pixel row in accordance with an output of the shift register, and the clock supplied to the shift register in response to generation of the shift data And a phase inverting means for alternately inverting the phase of the signal. The phase inverting means alternately inverts the phase of the signal. When capturing the image data for forming a drive signal for the color image display apparatus characterized by comprising by inverting the phase of the clock signal. 5. A color image display apparatus according to claim 4, wherein said data fetch means comprises a group of memories for fetching digital image data. 6. A color image display according to claim 4, wherein said data capturing means comprises a group of switches for sampling image data and a group of capacitors for holding sampled image data. apparatus.