JPS63287897A - Driving circuit for active matrix type display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION - [Field of Industrial Application] The present invention relates to a drive circuit for an active matrix display device having switching elements arranged in a matrix and pixels made of display elements such as liquid crystals.

[Conventional technology]

In an active matrix display device, when the speed of the switching elements arranged in each pixel is slow, it is necessary to perform so-called line-sequential driving, making the external drive circuit complicated. Conventional display devices that take this point into consideration are
As described in Publication No. 0-12584, each row scanning electrode that scans the switching element of each pixel is divided into two, and the scanning phase is shifted by approximately half the horizontal scanning period to perform so-called point sequential scanning. However, the operating speed of the switching element of each pixel was reduced to half the horizontal scanning period.

[Problem that the invention seeks to solve]

In the above conventional technology, since the row scanning electrodes to be driven are divided into left and right sides, the number of row scanning electrodes is doubled, and therefore, when the row scanning electrode scanning circuit is externally attached, there is a problem that the number of connection lines is doubled. there were. Further, even when a row-scanning electrode scanning circuit, which operates relatively slowly, is built into an active matrix substrate, the circuit scale is doubled, which causes a problem of lower yield.

An object of the present invention is to improve a drive circuit for an active matrix display device using switching elements with slow operation speed, and to provide a drive circuit with a small circuit scale.

[Means for solving problems]

For the above purpose, the screen is divided horizontally into P (P≧2), and the video signal of the TV, etc. is delayed by the time corresponding to each divided area, and each screen is simultaneously divided in a period of approximately 1/P of the horizontal scanning period. In a delay circuit that is part of a drive circuit that drives divided region column signal electrodes point-sequentially and lengthens the writing period to the display element by the switching element of each pixel, a low-pass filter is provided at the output part of the delay element, and a The video signal used as it is delayed is also passed through a low-pass filter with the same specifications.

[Effect]

The screen is divided into P (P≧2) in the horizontal direction, and the video signal of TV etc. is delayed by the time corresponding to each divided area, and the column signal of each divided area is simultaneously generated in a period of approximately 1/P of the horizontal scanning period. In the delay circuit, which is part of the drive circuit that drives the electrodes point-sequentially and lengthens the writing period to the display element by the switching element of each pixel, the video signal that has passed through the delay element is filtered into a low-pass filter to remove clock leakage. By inputting the signal, the delay time of the video signal becomes the sum of the delay time caused by the delay element and the group delay time of the low-pass filter. On the other hand, by passing the non-delayed video signal that is used without passing through the delay circuit through a low-pass filter with the same specifications, the relative time difference between the non-delayed video signal and the delayed video signal can be made constant. The relative time difference between the delayed video signal and the delayed video signal is no longer affected by the group delay time of the low-pass filter.

〔Example〕

3. Hereinafter, a first embodiment of the present invention is shown in FIG. 1, and will be explained using FIG. 2, which is an example of its operating waveforms.

In the following description, an example will be used in which a MOS transistor is used as a switching element and a liquid crystal is used as a display element, but the same applies to other combinations.

The shift registers 1 and 2 receive a clock pulse φH that is synchronized with the horizontal scanning frequency of the television video signal vI and corresponds to the number of pixels in the horizontal direction of the display panel 11. A signal sH for starting horizontal scanning writing is applied, and the output of each stage is supplied to a switching element (MOS) transistor 3 which forms a sample-and-hold circuit together with a capacitor 4.

On the other hand, the applied video signal V! After delaying by approximately half of the horizontal effective display period by a delay element 5 such as a CCD (charge coupled device), the clock removal low-pass filter 12 is applied.
-2 to obtain the delayed video signal VDL, and vI to the same specification low-pass filter 12-1 to obtain VIL. The above-mentioned sample-and-hold circuit samples these VDL and VIL in the latter half of the horizontal effective display period (the shaded area in FIG. 2). At this time, the low-pass filter 1 for removing the leakage of clock components
2-2, the number of display pixels in the horizontal direction of the display panel 11 is set to 640 by using a panel with a group delay time of approximately 100 rLy.
If a pixel is used and a COD is used as the delay element 5, for example,
In order to delay the video signal by half the horizontal effective display period, 320 stages of COD are required when the period of the sampling clock and the CCD shift clock are equal.
The lock cycle required for CD is 82.5 nJ. However, since the video signal is passed through the low-pass filter 12-2 for removing the clock component leakage, there is an additional delay of about one pixel. In addition, an appropriate number of CC
If D cannot be obtained and a 340-stage COD is used, the lock cycle required to delay the video signal by half of the horizontal effective display signal period is 78 ns. This C
Passing the delayed video signal obtained by the CD through the same low-pass filter as in the above example results in an additional delay of approximately one pixel. Therefore, in order to keep the reciprocal time difference between the video signals VDL and VIL constant, the applied video signal I is also passed through the low-pass filter 12-1 having the same specifications as the low-pass filter 12-2. Furthermore, the signals obtained by sampling the video signals VIL and VDL are held in the first half of the horizontal retrace period and the horizontal effective display signal period, and the column signal electrodes 7
to be applied. That is, the corresponding video signals are written to each column signal electrode 7 by point-sequential driving during the second half of the horizontal effective display signal period, and during the other periods (the horizontal retrace period and the first half of the horizontal effective display signal period). The written signal is held.

Next, to the shift register 6, a vertical scanning start signal Sv obtained by delaying a clock pulse φV of the horizontal scanning period (a pulse that is substantially the same as the horizontal scanning start signal, or whose phase is slightly advanced) and a vertical synchronization signal is added.

A MOS transistor 9 whose gate is connected to a row scanning electrode corresponding to a television scanning line is turned on, and a signal voltage held in a column signal electrode 7 is applied to a liquid crystal cell 10 to display a television image. be. In addition, the liquid crystal itself and MO
S) If the leakage when the transistor 9 is off cannot be ignored, it is preferable to add a signal holding capacitor to the liquid crystal drive electrode of each pixel. Also, one electrode of all liquid crystal cells is connected in common, and when driving the liquid crystal with AC, the midpoint potential of the signal electrode.

When driving with direct current, connect to ground or power supply potential.

In FIG. 2, looking at the waveform of the first row scanning electrode 8L from the top, it becomes H level that turns on the MOS transistor of the pixel in the middle of the horizontal effective display period, and the video signal VIL
In the latter half of the horizontal effective display signal period (the hatched period in the waveform 3i), the video signals corresponding to the column signal electrodes are connected to two column signal electrodes (and the capacitors connected to each column signal electrode). They are written simultaneously dot-sequentially. The video signal written to the column signal electrode is then transferred to the row scanning electrode 8t.
is written into each liquid crystal cell through the MOS) transistor of each pixel. Therefore, the MOS of each pixel)
Since it is sufficient for the transistor to complete the write operation at least during the latter half of the horizontal valid display signal period and the horizontal retrace period, it can be seen that the operating speed 7. can be quite slow. Specifically, in the case of a TV NTSC signal, the horizontal scanning period is 63.5uj, and the horizontal effective display signal period is 52.7tL&, which is half of 26.
．． 37.2 excluding the column signal electrode writing period of 41A&
t&,? It is sufficient if the writing of each pixel can be completed in this manner. Therefore, even if an α-8i substrate with low mobility is used as an active matrix substrate, it is possible to form a MOS (MOS) transistor in a sufficiently small area. It has a great effect on improving.

In addition, in the conventional method of dividing the row scanning electrodes approximately at the center and connecting lines from both sides of the liquid crystal panel substrate, the number of row scanning electrode scanning lines was required to be twice the number of row scanning electrodes. In this embodiment, the number of row scanning electrodes is the same as the number of row scanning electrodes, so if the vertical scanning circuit is externally connected, the number of connection wires can be halved, and even if the vertical scanning circuit is built in, the area occupied can be halved. It is effective in reducing

In the example of the operation waveforms in FIG. 2, the time for delaying the video signal is set to be half of the horizontal effective display period, but it does not have to be exactly half. For example, television (NTSC)
) in the display of the signal, the horizontal valid display signal period 52.7
When u and t are displayed by m pixels in the horizontal direction, and the number of stages of the horizontal shift registers 1 and 2 is 4 and (m - n ) stages, respectively, the delay time of the delay element 5 is 52.7uz x (m - n ), and the writing time allowed for the MOS) transistor of each pixel is 63.5uj-52,7ut x "52".

Therefore, the allowable writing time of the pixel's MOS transistor is the maximum at Luni m/20, which is 37.2 as described above.
fA,? For example, the optimum delay time is 26.4 tA due to the delay circuit? Even if it is not possible to set the delay circuit to
n, the operation speed can be reduced compared to the case where screen division is not performed.

In the above description, the shift registers 1 and 2 perform the same operation, and instead of being provided independently, the shift register with a larger number of stages can be used in common, and the shift register with a smaller number of stages can be omitted. This is shown in FIG. Furthermore, the capacitor 4 constituting the sample and hold circuit may be replaced by a wiring capacitance of a column signal electrode, etc., and does not need to be provided as a separate component.

FIG. 4 is a configuration diagram showing an embodiment in which the screen is divided horizontally. The delay element 5 delays the input video signal vI by 1/1 of the horizontal effective display signal period to obtain (k-1) outputs, VDI + VD2 +''·, VD&-1.Low-pass filter 12 -2.12-3.
. . , 12- are used to remove leakage of clock components caused by the delay element 5. Also, the low pass filter 12
-1 is for making the delay time difference between the video signals VIL, VDL-1+VDL-2°, . . . , VDL-A-1 constant, and has the effect of normally reproducing images. At this time, as is clear from the operation waveform example in FIG. 5, the column signal electrode writing period is l of the horizontal effective display signal period.
/A, for example, in the case of the previous TV signal, it is 52.7
Since uz/, the operating speed required for the MOS transistor of each pixel is 52.7 63.5-T(''), which has the effect of further lowering the required operating speed than the embodiment shown in FIG. be.

Another embodiment of the present invention is shown in FIG. In the embodiment shown in FIG. 1, the applied video signal and the delayed video signal that has passed through the delay element 5 are passed through low-pass filters with the same specifications.
In the embodiment shown in FIG. 6, the input video signal is limited to approximately 1/2 or less of the frequency of the clock used by the delay element 5 (according to the sampling theorem, signal components of 1/2 or more of the clock frequency cannot be reproduced, and thus generate false signals). ) is applied to the delay element 5 and the low-pass filter 12-2. In this case, the delay time from ■■ of the delayed video signal VDL is the delay time due to the delay element 5 plus the group delay due to the low pass filter 12-2, 1:HC. On the other hand, the video signal VIL is VI
It is delayed by the group delay caused by the low-pass filter 12-1.13. Therefore, since the low-pass filters 12-1 and 12-2 have the same specifications, the difference in delay time between the video signals VDL and VIL is determined only by the delay element.
It is not affected by the group delay of the low-pass filters 12-1°, 11, 12-2, and 13.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to make the delay time difference between the delayed video signal and the non-delayed video signal constant, so that the expected accurate delay time difference can be obtained, and therefore leakage into the delayed video signal can be achieved. This has the effect of allowing images to be reproduced normally without being affected by the group delay time of the low-pass filter for removing clock components.

[Brief explanation of drawings]

1, 3, 4 and 6 are schematic diagrams of a driving circuit of an active matrix display device according to an embodiment of the present invention, and FIGS. 5 is a waveform diagram showing an example of operation waveforms of the embodiment of FIG. 4. FIG. 2...Horizontal scanning shift register, 4...Capacitor, 5...Delay element, 7...
- Column signal electrode, 8... Row scanning electrode, 10...
Display elements: 11...Display panel.

Claims (1)

[Claims] 1. A circuit that synchronizes the video signal applied from the outside of the active matrix display device with a clock and delays it by a predetermined time, and a plurality of point sequential scanning circuits each having a multi-stage shift register and a plurality of switching elements are provided, so that the video signal is not delayed. The video signal and the delayed video signal are each input to a plurality of point sequential scanning circuits that operate simultaneously, and the video signal corresponding to the pixels connected to the scanning electrode in one row is converted to the signal in each column in a time less than half the horizontal scanning period. In the delay circuit that is part of the drive circuit that writes to the electrodes, the delayed video signal that has passed through the delay element is passed through a low-pass filter, and the video signal that is input to the dot sequential scanning circuit as a non-delayed video signal is also passed through a low-pass filter with the same specifications. 1. A drive circuit for an active matrix display device, characterized in that a drive circuit for an active matrix display device.