JPS5845034B2 - Matrix panel drive device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive device for a matrix panel, and an object of the present invention is to provide a drive device that is particularly compact and consumes less power.

The matrix panel 1 in FIG. 1 has odd-numbered row scanning electrodes
1. X3. X5. ...and even-numbered row scanning electrode X2
．． X4. X6. . . . , and terminals for applying scanning signals to the two types of scanning electrodes are provided at opposing positions.

Such a configuration is used particularly in matrix panels where the pixel pitch is small in order to facilitate coupling between the scanning circuit and the scanning electrodes.

Conventionally, means for driving a matrix panel of X rows and Y columns as described above transfers a serial signal applied from a terminal 3 to a shift register 2 using a clock signal applied from a terminal 4. The outputs of each stage were sequentially applied to the X electrode group.

FIG. 2 shows the waveform of the main part, and FIG. 2A shows the serial signal having a pulse width of one scanning period TH.

B in the same figure shows one cycle of the clock signal, which corresponds to one scanning period.

Further, C and D in the figure are the outputs of the shift register 2.

With recent advances in IC technology, the drive circuit and other peripheral circuits mentioned above have been integrated into ICs, and more and more configurations are being placed near the IJ rack panel. The wires are longer and most of them intersect, increasing the wiring space.

Furthermore, it is necessary to form a large number of through holes on the board, which poses problems in terms of reliability.

Therefore, a configuration can be considered in which, for example, the X electrode driving IC is placed on the left and right of the matrix panel, and the Y electrode driving IC is placed on the top and bottom of the matrix panel, but the shift register that drives the X electrode takes the power output from the even-numbered stage. On the other hand, since the output is taken out from the odd-numbered stages, the total number of stages, which is only 4, is actually used, which is wasteful.

This is a waste of space and power consumption when trying to downsize the entire device.

The present invention has achieved a simple configuration by thoroughly considering the circuit configuration.

An embodiment of the matrix panel drive device according to the present invention will be shown below.

FIG. 3 shows the main parts of the matrix panel 5 and its 1 driving section.

Reference numerals 6 and 7 indicate circuit sections that drive the X electrodes of the matrix panel 5, and 8 and 9 indicate circuit sections that drive the Y electrodes.

In addition, Fig. 4 shows the main parts of the Mal-IJ socknel 5.
FIG. 5 shows the main part of the circuit section that drives the Y electrode, and the sixth
The figure is a waveform diagram of main parts used for explaining FIG. 5.

Further, FIG. 7 is a circuit section for applying a control signal to the circuit section for driving the X electrode, and FIG. 8 is a waveform diagram for explaining its operation.

In the main part of the matrix panel 5 shown in FIG.
10 is a liquid crystal cell, 11 is a storage capacitor, 12 is an MO
This is an S transistor, and one picture element is composed of these three elements.

Next, one driving operation of the Y electrode will be explained using FIGS. 5 and 6.

The serial signal shown in Fig. 6 is applied to the shift register 4 from the terminal 13, and the sampling pulse signal (Fig.
).

Next, the video signal of FIG. 6A applied to the terminal 16 is sampled, and a charge corresponding to the video signal is stored in the first capacitor 7.

Next, a discharge pulse signal (FIG. 6B) located in the first half of the horizontal blanking period is applied to the terminal 18, and the MOS transistor 9 is turned on during that pulse period, discharging the charge stored in the second capacitor 20. Discharge and cancel.

Next, a transfer pulse signal located in the latter half of the horizontal blanking period shown in FIG.
The OS transistor 22 is turned on, and the charge stored in the first capacitor 7 is transferred to the second capacitor 20.

After passing through the amplifier 23, the sampled and held signal is applied to the Y electrode as shown in FIG.
The sampled and held signal shown in FIG. The display is performed by continuing to do so.

There are two problems here.

One is that, as is clear from the sample-and-hold signal shown in FIG. 6F, when selecting this signal with the X electrode signal, at least the discharge period must not be selected. Ransistor 12 goes from ON to OFF
Since the falling time when the signal changes to F is long, it is necessary to take this long falling time into consideration so that the level of the discharge period is not stored in the storage capacitor 1 using the sampled and held signal.

A method of driving the X electrode in consideration of these problems will be described next.

First, the circuit configuration is such that the output of each stage of the shift register 24, 25 is applied to one input terminal of the two-man power NAND corresponding to each stage, as shown in the drive circuit sections 6 and 7 in FIG.
The other input terminals are connected in common and each is connected to common terminal 2.
6.27 is connected.

A serial input signal is input to terminals 28 and 29, and a serial input signal is input to terminal 3.
A clock signal is applied to 0.31.

An example of the configuration of a circuit for obtaining signals to be applied to these terminals is shown in FIG.

In FIG. 7, the horizontal drive signal HD shown in FIG. 8A is applied to the terminal 32, and the outputs Q, Q of the flip-flop 33 are applied.
As a result, two signals shown in FIGS. 8B and 8C whose frequency is divided by 4 and whose phases are inverted from each other are obtained.

- The monostable multi 34 is triggered by the horizontal drive signal HD to obtain a pulse train signal H in FIG. 8 having a pulse width Ta.

The pulse width Ta is adjusted and determined by the variable resistor 35 in consideration of the fall time of the MOS transistor 2 shown in FIG.

A discharge pulse signal shown in FIG. 8G is applied to the terminal 36.

This signal is applied to terminal 18 of the drive circuit of FIG.
This is the same signal as shown in FIG. 6B.

Then, the Q output of the flip-flop 33 (FIG. 8B), the output of the monostable multi 34 (FIG. 8H) and the discharge pulse signal (
8G) to the three-man power AND circuit 37 to obtain the first common pulse train signal shown in FIG. 8J.

- Adding the Q output of the power flip-flop 33 (FIG. 8C), the output of the monostable multi 34 (FIG. 8H), and the discharge pulse signal (FIG. 8G) to the three-man power AND circuit 38, Figure K
A second common pulse train signal shown in FIG.

Next, a vertical drive signal VD (not shown) is applied to the terminal 39,
The D-type flip-flops 40, 41, and 42 are driven by the Q output of the flip-flop 33.
1 and the Q output of the D-type flip-flop 42 are expressed as A
In addition to the ND circuit 43, a serial input signal shown in Figure 8 is obtained.

Therefore, in FIG. 3, the serial input signals shown in FIG. 8 are applied to terminals 2B and 29, and the
Adding the clock signal shown in Figure B, the first one at the rising edge,
The second shift registers 24 and 25 are driven to obtain the output shown in FIG. 8E in the first stage of both shift registers, and the output shown in FIG. 8F in the second stage of both shift registers.

Thereafter, outputs are sequentially shifted in accordance with the clock signal.

A first common pulse train signal shown in FIG. 8J is applied to the common terminal 26, and a second common pulse train signal shown in FIG. 8K is applied to the common terminal 27.

The output of the first stage of the shift register 24 and the first common pulse train signal are added to the NAND circuit 44, as shown in Figure 8.
A scanning pulse signal is obtained and applied to the scanning electrode X.

Next, the second stage output of the shift register 24 and the first common pulse train signal are applied to the NAND circuit 45, and the scanning electrode
The scanning pulse signal shown in FIG. 8N is obtained to be added to.

Similarly, the first stage, second stage, etc. of the shift register 25, etc.
. . and the second common pulse train signal are connected to NAND circuits 46, 47 . . . . by adding scan electrode X2. Figure 8 M, 0 to be added to X4...
Obtain the scanning pulse signal shown in ....

In the above embodiment, the NAND circuits 44, 45 .・・・・・・
- inputs the output of the shift register 24 and the common pulse train signal, and leads the output of this NAND circuit to the X electrode, so the sampled and held signal (sixth The output pulse width of the shift register can be easily limited so as not to select the signal level at least during the discharge period in Figure F).

In other words, when driving a multi-IJ socknel in which each picture element is provided with a switch element, the output pulse width of the shift register is narrowed to compensate for the delay in response of the switch element, thereby making the image on the matrix panel clearer. It became possible to do so.

Further, in this embodiment, it was possible to employ a CMO8 configuration, which was not used in the past due to poor response when used as a switch element, and at this time, power consumption could be halved.

In addition, the matrix panel and drive circuit IC (peripheral circuit I)
Problems such as the arrangement of C and scanning circuit IC) were also solved, and industrial advantages such as less wiring space and ease of implementation were obtained.

As described above, the present invention provides an excellent driving device for a matrix panel that can realize miniaturization and power saving, and can also provide clear images.

[Brief explanation of drawings]

Fig. 1 is a configuration diagram of the main parts of a conventional Mar-IJ Luxnel and its drive device, Fig. 2 is a waveform diagram of the main parts of Fig. 1, and Fig. 3 is an implementation of the matrix panel drive device of the present invention. 4 is a configuration diagram of the main parts of the matrix panel, FIG. 5 is a configuration diagram of the circuit section that drives the Y electrode, FIG. 6 is a waveform diagram of the main parts of FIG. 5, and FIG. The figure is a configuration diagram of a circuit section that generates a control signal, and FIG. 8 is a waveform diagram of a main part of this embodiment. 5... Matrix panel, 6,7...
・・・・・・Circuit section for driving the X electrode, 8, 9...
......Circuit section for driving the Y electrode, 11...
・・・・Memory capacitor, 12・・・・・・・・・M
OS transistor, 24.25......Shift register, 44, 45, 46, 47...
・NAND circuit.

Claims (1)

[Claims] 1 A matrix panel is formed by arranging picture elements in X rows and Y columns, each consisting of a liquid crystal cell, a memory element that accumulates a signal to be applied to the liquid crystal cell, and a switching element that transfers the signal to be applied to the memory element. Then, the signal application terminal for the X electrodes in the odd rows and the signal application terminal for the X electrodes in the even rows of the multi-IJ Luxnel are placed in opposing positions, and a shift register and an AND circuit group having one terminal connected to each stage thereof; and a shift register for the even-numbered X electrodes and an AND circuit group having one end connected to each stage thereof, Applying the same serial signal with a width of 2 scanning periods to the two shift registers and driving them by the same clock signal with one period of 2 scanning periods,
A first pulse train signal shorter than one scanning period width is commonly applied to the other terminal of the logic circuit group for odd rows, and the first pulse train signal is commonly applied to the other terminal of the logic circuit group for even rows. 1
A matrix panel driving device characterized in that a second pulse train signal having a phase different from that of the pulse train signal by 1800 degrees is applied.