JPH0654416B2 - Liquid crystal driving device and liquid crystal display device using the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a liquid crystal driving device and a liquid crystal display device using the same, and for example, a device for forming a driving signal of a signal electrode of a liquid crystal display panel having a dot matrix structure, and The present invention relates to a technique effective for a liquid crystal display device using the same.

[Technical background]

Conventionally, the liquid crystal display device of the dot matrix configuration,
For example, “Electronic Materials” magazine, October 1980, page 21.
, Page 43, are known.

In a display device using a conventional liquid crystal display panel with a dot matrix structure, the pixel data is formed by a microprocessor or the like and written in a RAM (random access memory), and the data is read at a fixed cycle. To drive the signal electrode. In such a display operation, the serial image data read from the RAM is converted into a parallel signal by the shift register to form a drive signal for each signal line electrode.

In this case, it is considered that the same display panel has a two-tier structure in order to enlarge the display area. The signal electrodes of the display panel are, for example, 1
Allocated corresponding to pixel data of ~ n. When such fixed signal electrodes and pixel data are allocated, in the liquid crystal driving device that forms the display signal, the pin arrangement of the output terminals is different between the lower liquid crystal driving device and the upper liquid crystal driving device. Will be reversed. Therefore, for example, the liquid crystal driving device on the upper side is connected to the signal electrodes of the liquid crystal panel on the upper side by cross wiring, or when writing the display data thereof, the input / output terminals 0 to 49 of the liquid crystal driving device are connected to 49 to 0
It is conceivable to convert the data in advance and write the data.

However, in the former case, the wiring space for forming a large number of cross wirings is increased and the wiring of the printed wiring board has a complicated pattern, which increases the price of the printed wiring board. The latter has the drawback that a special address translation program is required when writing the display data.

[Object of the Invention]

An object of the present invention is to provide a liquid crystal display drive device which has a degree of freedom in mounting on a liquid crystal display panel.

Another object of the present invention is to provide a liquid crystal display device in which the mounting substrate is simplified.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in a liquid crystal display drive device that forms display signals to be supplied to signal electrodes in a liquid crystal display panel having a dot matrix configuration, a plurality of latch circuits are provided in parallel with serial image data, and the time-sequential fetching order is set. By making it variable, the degree of freedom in matching the signal electrodes of the liquid crystal display panel with the output terminals in mounting is increased.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of the present invention.

Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known method for manufacturing a semiconductor integrated circuit device.

A semiconductor integrated circuit device LSI (CDRV) shown in the figure drives the signal line electrodes of a liquid crystal display panel having a dot configuration composed of scanning line electrodes and signal line electrodes,
It is configured to generate drive signals for n signal line electrodes.

The following respective circuits are provided for the n signal line electrodes in order to form a drive signal according to a character or a figure to be displayed in synchronization with the selection timing of the scanning line electrodes.

The second latch circuit FF2 converts the character or graphic pixel data serially supplied from the input data terminal D in accordance with the above scanning timing into a parallel signal. That is, the data input terminals of the n latch circuits are commonly connected to receive the pixel data in parallel. And, the clock terminal of each latch circuit,
Timing signals S1 to Sn formed in time series by a decoder DCR described later are supplied.

The output signal of the second latch circuit FF2 is fetched in parallel by the first latch circuit FF1 in synchronization with the clock signal CL1. The drive circuit DV processes the pixel data taken into the first latch circuit FF1 in accordance with a timing signal (not shown) to form a drive signal by a multi-valued pulse for AC driving the liquid crystal. Voltage V1 to V4
Is a power supply voltage for forming the multi-valued pulse.
Since the method of alternating-current driving the liquid crystal is well known, its detailed description is omitted.

In this embodiment, in order to selectively switch the pixel data and its output terminal by serial / parallel conversion in the second latch circuit FF2, the fetch timing signals S1 to Sn are set as follows. It is formed.

The counter circuit CONT receives the clock signal CL2 supplied in synchronization with the pixel data and counts it. Although not particularly limited, this counter circuit CONT
Is for performing an up / down counting operation according to a control signal supplied from the external terminal U / D. For example, if the external terminal U / D is high level, it operates as an up counter, and if the external terminal U / D is low level, it operates as a down counter. The count output signal of the counter circuit CONT is converted into the timing signals S1 to Sn formed in time series by the decoder DCR.

The clock signal CL1 supplied from the external terminal is
It is also used as a clear signal for the counter circuit, and all its outputs are cleared to logic "0" at the time of up operation and all the outputs to logic "1" at the time of down operation.

In the liquid crystal display drive device CDRV of this embodiment, when the external terminal U / D is set to the high level, the counter circuit CO
NT increments the count value each time the clock signal CL2 arrives. Therefore, since the decoder DCR sequentially forms the timing signals from S1 to Sn in time series, the pixel data supplied in synchronization with the clock signal CL2 is sequentially shifted from the left end of the second latch circuit FF2 to the right direction. It is captured. As a result, display signals according to the order of the pixel data serially supplied are transmitted from the display output terminals O1 to On.

On the other hand, when the external terminal U / D is set to the low level, the counter circuit CONT decreases the count value each time the clock signal CL2 arrives. Therefore, the decoder DCR sequentially forms the timing signals from Sn to S1 in a time series, so that the pixel data supplied in synchronization with the clock signal CL2 is sequentially leftward from the right end of the second latch circuit FF2. It is captured. As a result, the display output terminal O
From n to O1, a display signal according to the order of serially supplied pixel data is transmitted. That is, the display output signal is transmitted in the opposite direction to the above case, in other words, under the pin arrangement opposite to the order of the pixel data serially supplied.

[Embodiment 2] FIG. 2 shows a block diagram of essential parts of another embodiment of the present invention.

In this embodiment, the following circuit is used in order to selectively switch the arrangement of the display output terminals in the forward and reverse directions for the serially supplied pixel data string. That is, in this embodiment, a match / mismatch circuit such as exclusive OR circuits EX1 to EX4 is provided for each output bit of the counter circuit CONT which only performs the count-up operation. The switching signal C is supplied from the external terminal C to the other input of these match / mismatch circuits.

Thereby, for example, the match / mismatch circuits EX1 to EX
4 forms a coincidence output of logic "0" and a non-coincidence signal of logic "1", if the control signal C is logic "0",
The output of the counter circuit CONT is the decoder D as it is.
Since it is transmitted to the CR, its output signal is sequentially formed from the timing signals S1 to Sn in time series. On the other hand, when the control signal C is logic "1", all the outputs of the counter circuit CONT are inverted, in other words,
The logic "0" is transmitted to the decoder DCR as the logic "1" and the logic "1" as the logic "0". As a result, when viewed from the input side of the decoder DCR, the counter signals in the reverse direction are supplied from the all logic "1" to the all logic "0", so that the timing signals Sn to S1 are reversed in the order opposite to the above case. It is formed in time series. With such a control signal C, it is possible to switch the substantial pin arrangement of the display output terminals, as in the above-described [Embodiment 1].

[Embodiment 3] FIG. 3 is a block diagram showing an embodiment of a display device using the liquid crystal display drive device according to the present invention.

In the figure, the liquid crystal display panel LCD is composed of two upper and lower tiers.
It consists of two display panels ULCD and DLCD,
The scanning electrodes run in the horizontal direction and the signal electrodes run in the vertical direction. Then, a display dot is formed at the intersection of the two, and a predetermined display is performed by the brightness and darkness.
Therefore, the input terminals of the signal electrodes of the upper display panel ULCD are arranged on the upper side, and the lower display panel DLCD is arranged.
The input terminal of the signal electrode of is arranged on the lower side.

A scan electrode drive circuit RDRV sequentially supplies selection drive signals to the scan electrodes of the liquid crystal display panel LCD. The scan electrode drive circuit RDRV is not particularly limited, but is a one-chip monolithic semiconductor integrated circuit device IC.
1 to form a multi-valued pulse drive signal for AC driving the liquid crystal. For example, as the scan electrode driving circuit RDRV, a semiconductor integrated circuit device such as a product name “HD44103C” sold by Hitachi, Ltd. can be used.

In this embodiment, the signal electrodes of the liquid crystal display panel LCD are provided with the liquid crystal display driving devices CDRV1 and CDRV for driving the signal electrodes shown in the embodiment of FIG. 1 or FIG.
2 is used.

As in this embodiment, liquid crystal display panels ULCD and DLC
When the arrangement of the output terminals of the signal electrodes is reversed as in D, the liquid crystal drive devices CDRV1 and CDRV2 make the pixel data serially supplied in the opposite directions by the external terminals U / D or C. It is something to capture. This allows the display output terminals to be aligned and arranged in order from the left. Although the output terminals of the upper liquid crystal display drive device CDRV2 are arranged as n to 1 from the left in the figure, the pixel data is fetched in the reverse direction, so that the lower liquid crystal display drive device is substantially driven. Device CDRV
The same as 1 can be set to 1 to n.

A timing generation circuit (not shown) forms a scan timing signal for the scan electrodes and a selection timing signal for the signal electrodes, which are associated with each other, on the basis of the reference frequency pulse formed, and the scan electrode drive circuit RDRV,
Liquid crystal driving devices CDRV1 and CDRV2 for the signal electrodes
To be sent to.

[Embodiment 4] FIG. 4 is a schematic view of a liquid crystal display panel for explaining another embodiment of the present invention. In the liquid crystal display panel LCD of this embodiment, with the miniaturization of its electrode lines,
The input terminals of the signal line electrodes are arranged and led out alternately up and down. For this reason, odd-numbered signal line electrodes such as 1, 3, 5 are arranged on the lower terminal, and even-numbered signal line electrodes are arranged on the upper terminal such as 2, 4, 6. A liquid crystal display driving device CDRV that forms a driving signal for such a liquid crystal panel
In order to improve the matching of the pin combination, the decoder makes the timing signal generation order as follows in the embodiment of FIG. 1 or FIG. For example, when the number of signal lines is 80, the left half of the second latch circuit FF2 (4
0) and the right half (40), the odd-numbered clock signal CL2 is formed in the left half in the order of timing signals S1, S2, ... From the left, and the even-numbered clock signal CL2 is right. Timing signals S80, S79, ... Are formed in order from the right in half. As a result, the left half output terminals 1 to 40 can correspond to the lower signal line electrodes 1, 3, 5 ... 79,
The right half output terminals 80 to 41 can be made to correspond to the upper signal line electrodes 2, 4, 6 ... 80 without passing through the lower side of the liquid crystal panel.

The order of the timing signals S1 to S80 may be reversed. Then, the above-mentioned FIG. 1 or 2
It may be configured in combination with switching of the pin arrangement as in the above embodiment. The circuit for forming the timing signal as described above can be easily realized by preparing a plurality of sets of decoder circuits and selectively performing an operation by a control signal from an external terminal.

[Effect]

(1) In one liquid crystal display drive device, by providing a latch circuit in parallel with the pixel data that is serially supplied, and changing the time-sequential order of the fetch timing signals from the display output terminal. The pixel data to be sent can be changed. As a result, the pin arrangement of the display output terminals can be arbitrarily switched, so that it is possible to improve the matching property with respect to the electrode arrangement direction of the liquid crystal display panel.

(2) By virtue of the above (1), it is possible to achieve the high-density mounting by ensuring the pin arrangement matching between the liquid crystal display panel constituting the liquid crystal display device and the driving device thereof.

(3) By virtue of the above (1), the applicable range of the liquid crystal display device is expanded, and therefore, it is possible to obtain the effect that the mass productivity can be improved.

(4) Due to the above (2), it is possible to obtain an effect that it is possible to obtain a liquid crystal display device in which the mounting substrate is simplified.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, a circuit that forms a fetch timing signal of a latch circuit in parallel with respect to serially supplied pixel data can employ various embodiments.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used as a liquid crystal display drive device that forms a drive signal for a signal electrode of a liquid crystal display panel.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of an essential portion of another embodiment of the present invention, and FIG. 3 is a liquid crystal display driving device according to the present invention. FIG. 4 is a block diagram showing an embodiment of the liquid crystal display device used, and FIG. 4 is a schematic view for explaining still another embodiment of the present invention. DV ... Drive circuit, FF1, FF2 ... Latch circuit, D
CR ... Decoder, CONT ... Counter circuit, EX1
~ EX4 ... Match / mismatch circuit, LCD (ULCD, D
LCD) ... Liquid crystal display panel, RDRV ... Scan electrode drive circuit, CDRV, CDRV1, CDRV2 ... Liquid crystal display drive device (signal line electrode drive device)

Claims (6)

[Claims] 1. A plurality of latch circuits provided in parallel with a signal line for transmitting serially supplied display data, and a counter circuit for counting a timing signal synchronized with the serially supplied display data. A decoder circuit for receiving a count output of the counter circuit and forming a selection signal for instructing a time-sequential fetching order of display data in the plurality of latch circuits; and display data fetched in the plurality of latch circuits. And a drive circuit for receiving in parallel to form a liquid crystal drive signal corresponding to a signal line electrode of a liquid crystal display panel having a dot matrix configuration, and the counting operation of the counter circuit or its output signal according to a control signal supplied from an external terminal. To switch the display data acquisition sequence in one direction in the latch circuit consisting of multiple switches. A liquid crystal driving apparatus, characterized in that which gave the same function of switching in the opposite direction. 2. The counter circuit is an up / down bidirectional counter circuit, and a control signal from the external terminal selectively switches up or down counting operation and performs initial setting. The liquid crystal drive device according to claim 1, wherein: 3. The counter circuit performs counting operation in one direction of up or down, and its counting output is
2. The decoder circuit according to claim 1, wherein one of the input terminals is switched through an exclusive OR circuit to which the control signal supplied from the external terminal is supplied and is input to the decoder circuit. LCD drive device. 4. A plurality of latch circuits provided in parallel with a signal line for transmitting serially supplied display data, and a counter circuit for counting timing signals synchronized with the serially supplied display data. A decoder circuit for receiving a count output of the counter circuit and forming a selection signal for instructing a time-sequential fetching order of display data in the plurality of latch circuits; and display data fetched in the plurality of latch circuits. And a drive circuit that receives a parallel signal to form a liquid crystal drive signal, and switches the counting operation of the counter circuit or its output signal in accordance with a control signal supplied from an external terminal to display time-series display data in a latch circuit composed of a plurality of A liquid crystal driving device including means for switching the taking-in order in one direction or the opposite direction; A liquid crystal display device comprising the liquid crystal driving signal outputted from the circuit is a liquid crystal display panel that is supplied to the signal line electrode of the dot matrix configuration. 5. The liquid crystal display panels are combined in a vertical stack so that the signal line electrodes of the two liquid crystal display panels are substantially extended, and the liquid crystal driving device is provided for the upper and lower liquid crystal display panels. Is provided, and the order of time-sequential display data fetching in the plurality of latch circuits of both liquid crystal drive devices is designated in the opposite directions by the corresponding external control signals. A liquid crystal display device according to item 4. 6. The liquid crystal display panel is such that signal input electrodes for odd-numbered and even-numbered signal line electrodes are vertically distributed, and the liquid crystal driving is performed corresponding to the vertically distributed signal input electrodes, respectively. A device is provided, and the order of time-sequential display data fetching in the plurality of latch circuits of both liquid crystal driving devices is designated in opposite directions by an external control signal corresponding to each device. The liquid crystal display device according to claim 4.