JP2000122616A - Liquid crystal display device having switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of part items, realize a high definition, and reduce the size, weight and a cost by arranging a switch circuit for switching liquid crystal impressing voltage and gate ON voltage output driven by being divided into blocks. SOLUTION: A liquid crystal controller 104 generates a dot clock in synchronism with display data, a CL 1 becoming effective with every single horizontal period and an FLM becoming effective with every single frame to be transferred to upper/lower data drivers 115, 119, a data switch control circuit 109, a scanning driver 123 and a scanning switch control circuit 112. The data switch circuit 109 generates control signals of the upper/lower data drivers 115, 119 becoming effective with every 1/2 horizontal period and control signals of upper/ lower data switches 117, 121 from the transferred dot clock and the CL1 to be respectively outputted through a signal conductor 110 and a signal path 111. The scanning switch control circuit 112 generates a control signal of the scanning driver 123 becoming effective with every 1/2 frame and a control signal of a scanning switch 125 from the CL1 and the FLM to be outputted through a signal conductor 113 and a signal path 114.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, particularly to a high resolution panel.

[0002]

2. Description of the Related Art As a conventional liquid crystal display device, a flat panel display 1991 "Multicolor technology for TFT color liquid crystal display, from 4096 colors to more than 260,000 colors" (November 1990)
26, Nikkei BP Publishing Co., Ltd., pp. 173 to 180).

FIG. 13 is a diagram showing a conventional liquid crystal display device.
This will be described using 15.

FIG. 13 is a configuration diagram of a conventional liquid crystal display device. 1301 is an information processing device such as a personal computer (hereinafter referred to as a PC). 1302 and 1303 are a signal bus and a data bus, which transfer control signals and display data, respectively. A liquid crystal controller 1304 and a data bus 1305 transfer display data. 1306, 1307 and 1308 are signal lines, each of which is a dot clock which is a display control signal;
Transfer CL1 and FLM. 1309-1 to 1309-6 are six upper data drivers, each having 160 output terminals. 1
310-1 to 1310-6 are 160 upper drain lines, respectively, for a total of 960 lines.

Reference numerals 1311-1 to 1311-6 denote six lower data drivers, each having 160 output terminals. 1312-1 to 1312-6 are 160 lower drain lines, respectively, for a total of 960 lines. Reference numerals 1313-1 to 1313-6 denote six scanning drivers, each having 80 output terminals. 1314-1 to 1314
-6 are 80 gate lines, respectively, for a total of 480 lines. 1315 is a liquid crystal panel, and the upper and lower drain lines 1315
Pixels composed of transparent electrodes and pixels composed of thin film transistors (hereinafter, referred to as TFTs), which are switching elements, are formed at intersections of the gate lines 1314 and 10, 1312, and have a resolution of 6 pixels.
40 pixels x 480 lines. Since one pixel is composed of three dots of R, B, and G, the number of dots in the horizontal direction is 640 × 3 dots, which is equal to the total number of output terminals of the upper and lower data drivers 1309 and 1311. Further, the total number of output terminals of the six scanning drivers 1313 is 480, which is equal to the total number of gate lines.

FIG. 14 is an operation timing chart of the conventional data drivers 1309 and 1311.

FIG. 15 is a timing chart of a display operation of a conventional liquid crystal display device.

Next, the configuration and operation of a conventional liquid crystal display device will be described with reference to FIGS.

Display data transferred from the information processing device 1301 via the data bus 1303 is converted by the liquid crystal controller 1304 into display data suitable for the configuration of the liquid crystal panel 1315.
Upper and lower data drivers 1309, 1311 via data bus 1305
Is forwarded to At the same time, the liquid crystal controller 1304 controls the display operation of the liquid crystal panel 1315 from the control signal transferred from the information processing device 1301 via the signal bus 1302, and controls the display operation of the liquid crystal panel 1315. CL1 and FLM that are enabled for each frame are generated, and upper and lower data drivers are sent via signal lines 1306, 1307, and 1308, respectively.
1309, 1311 and the scan driver 1312.

As shown in the timing chart of FIG. 14, the upper data driver 1309 operates according to the dot clock.
Of the display data, display data of odd-numbered dots is sequentially taken in one dot at a time. When the display data for one line is captured, CL1 is enabled, and the display data for odd dots for one line is converted into the corresponding liquid crystal applied voltage at one time.
Output to the upper drain line 1310. At the same time, the lower data driver 1311 captures display data of even-numbered dots of the display data one by one according to the dot clock. When the display data for one line is captured, CL1 becomes valid, and the display data for even-numbered dots for one line is converted into the corresponding liquid crystal applied voltage at one time, and the lower drain line 13
Output to 12.

As shown in the timing chart of FIG. 15, the scanning driver 1313 sequentially selects the first line to the 480th line of the liquid crystal panel 1315 every one horizontal period according to CL1, A gate-on voltage for turning on the dot switch element TFT of the liquid crystal panel 1315 is output to the selected gate line 1314. The dots connected to the gate line 1314 to which the gate-on voltage is applied include:
A liquid crystal application voltage is applied via the upper and lower drain lines 1310 and 1312, and display is performed. When the display for one frame is completed, the FLM becomes valid, the scanning driver 1313 again selects sequentially from the first gate line, and the next frame is displayed.

The upper and lower data drivers 1309-1 to 139-1
09-6, 1311-1 to 1311-6 each have 160 output terminals.
It takes in the display data for the dots, converts them to the liquid crystal applied voltage, and connects the upper and lower drain lines 1310-1 to 1310-
6. Output from 1312-1 to 1312-6. Similarly, the scan drivers 1312-1 to 1312-6 each have 80 output terminals, so the first
6th scan driver 1 to 6th scan driver 1312-1
312-6 selects the gate line 1314 in order of 80 lines from the first line to the 480th line in one frame period.

[0013]

The liquid crystal display device is required to have higher definition, and the demand as a display device for portable information equipment is increasing. Therefore, it is essential to increase the resolution of the liquid crystal panel and to reduce the size and weight of the liquid crystal display device. For this reason, it is necessary to reduce the number of components and narrow the pitch. However, in the conventional liquid crystal display device, when the resolution is increased, the number of drain lines and the number of gate lines of the liquid crystal panel are increased, and accordingly, the number of data drivers and scan drivers required for driving the liquid crystal panel is increased. For this reason, the number of parts increases, the weight and cost increase accordingly,
There is a problem that narrowing the pitch becomes difficult.

[0014]

A drive circuit of a liquid crystal display device and a liquid crystal panel are formed by using low-temperature single-crystal silicon (hereinafter referred to as low-temperature poly).
-Si), the driver circuit is integrated on the same substrate as the liquid crystal panel without deteriorating the performance of the circuit, and the liquid crystal panel is divided into multiple blocks and driven. Thus, a switch circuit for switching the voltage applied to the liquid crystal to each block of the liquid crystal panel and the gate-on voltage output is provided. With such a driving circuit configuration and driving method, the number of necessary data drivers and scanning drivers can be reduced. In addition, by incorporating a peripheral drive circuit, it is possible to cope with higher definition, lighter weight, smaller size, and narrower pitch.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the liquid crystal display device of the present invention will be described with reference to FIGS.

FIG. 1 is a configuration diagram of the liquid crystal display device of the first embodiment.

In FIG. 1, 101 is an information processing device such as a PC, and 102 and 103 are a signal bus and a data bus, respectively, for transferring a control signal and display data, respectively. 104 is a liquid crystal controller, 105 is a data bus, and transfers display data. 106, 107 and 108 are signal lines for transferring dot clocks, CL1 and FLM, which are display control signals, respectively. 109 is a data switch control circuit, 110 and 111 are signal lines and signal buses, respectively, and control signal CLm /
2. Transfer the switch control signals 1L, 2L, 1R, 2R. 112 is a scanning switch control circuit, 113 and 114 are signal lines, respectively.
A signal bus for transferring a control signal CLn / 2 and switch control signals U and D, respectively. Reference numeral 115 denotes an upper data driver, and reference numeral 116 denotes m / 4 output lines of the upper data driver 115. 117 is an upper data switch, and 118 is m / 2 upper drain lines. 119 is a lower data driver, and 120 is m / 4 output lines of the lower data driver 119. 121 is a lower data switch, and 122 is m / 2 lower drain lines.

Reference numeral 123 denotes a scanning driver, and reference numeral 124 denotes n / 2 output lines of the scanning driver 123. Reference numeral 125 denotes a scanning switch, and reference numeral 126 denotes n gate lines. A liquid crystal panel 127 has a resolution of m dots × n lines. LCD panel 12
In FIG. 7, at the intersection of the upper and lower drain lines 118 and 122 and the gate line 126, a pixel electrode composed of a transparent electrode and a dot composed of a TFT as a switch element are configured. The upper drain line 118 is connected to odd-numbered dots in the horizontal direction, and the lower drain line 122 is connected to even-numbered dots.
In the present embodiment, the number of output terminals of the data drivers 115 and 119 and the scanning driver 123 is set to m / 4 and n / 4, respectively.
The number of divisions when driving is 2 in both the horizontal and vertical directions.
The description will be made assuming that the whole is divided into four.

FIG. 2 is a configuration diagram of the data switch control circuit 117 shown in FIG.

In FIG. 2, 201 is a counter, 202 is a signal line, and transfers the counter value output from the counter 201. 203 is a signal generation circuit, and 204, 205, 206, and 207 are signal lines, which constitute the signal bus 111 shown in FIG. 1, and transfer data switch control signals 1L, 1R, 2L, and 2R, respectively.

FIG. 3 shows the scanning switch control circuit shown in FIG.
FIG. 125 is a configuration diagram of an example.

In FIG. 3, reference numeral 301 denotes a counter, and 302 denotes a counter 301.
Transfers the counter value output by. 303 is a signal generation circuit, 304 and 305 are signal lines, which constitute the signal bus 114 shown in FIG. 1, and transfer the scan switch control signals U and D, respectively.

FIG. 4 is a configuration diagram of the upper and lower data drivers 115 and 119. In FIG. 4, reference numeral 401 denotes a data latch, which stores display data for m / 4 dots. A data bus 402 transfers display data for m / 4 dots at a time. A shift register 403 stores display data for m / 4 dots at a time. A data bus 404 transfers display data for m / 4 dots at a time. A voltage generation circuit 405 converts the transferred display data into a corresponding liquid crystal drive voltage. Reference numeral 406 denotes m / 4 output lines, each of which transfers a corresponding liquid crystal drive voltage.

FIG. 5 shows the upper and lower data switches 1 shown in FIG.
It is a block diagram of 17,121. In FIG. 5, 501-1 to 501-m / 4 are the left first switches SWL1-1 to SWL1-m / 4, and 502-1 to 50-m / 4.
2-m / 4 is the right first switch SWR1-1 to SW1R-m / 4, 50
3-1 to 503-m / 4 is the left second switch SWL2-1 to SWL2-m / 4
And 504-1 to 504-m / 4 are right second switches SWR2-1 to SWR2-m / 4. 505-1 to 505-m / 4 are left capacitors
CL-1 to CL-m / 4, and 506-1 to 506-m / 4 are right capacitors CR-1 to CR-m / 4. Since the capacitors 505 and 506 have sufficiently large capacities, the voltage fluctuation due to the on / off switching of each switch affects the liquid crystal applied voltage applied to each dot of the liquid crystal panel 127, and the voltage value fluctuates.
Prevent display from being distorted.

FIG. 6 is a block diagram of the scanning switch 125 shown in FIG.

In FIG. 6, 601-1 to 601-n / 2 are upper switches S
WU-1 to SWU-n / 2, and 602-1 to 602-n / 2 are lower switches SWD-1 to SWD-n / 2.

FIG. 7 is an operation timing chart of the data switch control circuit 109 and the upper and lower data drivers 115 and 119.

FIG. 8 is an operation timing chart of the scan switch control circuit 112 and the scan driver 123.

First, the configuration and operation of the liquid crystal display device of this embodiment will be described with reference to FIG.

The display data transferred from the information processing device 101 is transferred to the liquid crystal controller 104 via the data bus 103. The liquid crystal controller 104 converts the transferred display data into display data corresponding to the configuration of the liquid crystal panel 127, and outputs the data to the upper and lower data drivers 11 via the data bus 105.
Transfer to 5,119. At the same time, the LCD controller 104
A control signal for controlling display of the liquid crystal panel 127 from a control signal transferred from the information processing device 101 via the signal bus 102. Dot clock synchronized with display data, CL1 enabled every horizontal period, FLM enabled every frame
Is generated and transferred to the upper and lower data drivers 115 and 119, the data switch control circuit 109, the scan driver 123, and the scan switch control circuit 112 via the signal lines 106, 107 and 108, respectively.

In the data switch control circuit 109, the control signal CLm / 2 of the upper and lower data drivers 115 and 119, which becomes effective every 1/2 horizontal period, and the control of the upper and lower data switches 117 and 121, from the transferred dot clock CL1. The signals 1L, 2L, 1R, and 2R are generated and output via a signal line 110 and a signal bus 111, respectively. In the scan switch control circuit 112, the transferred CL1, FL
From M, a control signal CLn / 2 of the scan driver 123 and control signals U and D of the scan switch 125, which are enabled every 1/2 frame, are generated and output via the signal line 113 and the signal bus 114, respectively. Here, the data switch control circuit 109 will be described with reference to FIGS.
Will be described.

Counter 201 of data switch control circuit 109
Counts the transferred dot clock, and transfers the count value to the signal generation circuit 203 via the signal line 202. As shown in the timing chart of FIG. 7, the signal generation circuit 203 converts the dot clock, CL1, and the count value into the 'H' period of CL1 and the 'L' period of the dot clock when the count value is m / 2. A control signal CLm / 2 that becomes “H” is generated and output to the signal line 110. At the same time, the data switch control signal 1L becomes 'H' in synchronization with the rising edge of CL1 and becomes 'L' in synchronization with the rising edge of CLm / 2, and its inverted signal 1
2L becomes 'H' in synchronization with the falling of R and CL1 and becomes 'L' in synchronization with the falling of CLm / 2 when the count value is m / 2. Generate each signal line 20
Output to 4, 205, 206, 207. As shown in FIG. 7, the control signals 1L and 2L are valid in the first half of the one horizontal cycle (H)
And 1R and 2R become valid (H) in the latter half 1/2 horizontal cycle.

Next, the operation of the scan switch control circuit 112 will be described with reference to FIGS.

The counter 301 of the scan switch control circuit 112
Counts CL1 to be transferred, and counts the count value on signal line 3.
The signal is transferred to the signal generation circuit 303 via the second circuit 02. Signal generation circuit 3
03 is, as shown in the timing chart of FIG. 8, from the transferred CL1, FLM and count value, during the 'H' period of the FLM and during the CL1 'H' period when the count value is n / 2 + 1. A control signal CLn / 2 that becomes H ′ is generated and output to the signal line 113. At the same time, FL
The control signal U of the scan switch 112, which becomes 'H' in synchronization with the rise of M, and the FLM becomes 'L' in synchronization with the rise of CLn / 2 in the 'L' period, and the inverted signal D thereof, Generate
Output to the signal lines 304 and 305, respectively. As shown in FIG. 8, the control signal U becomes valid (H) in the first half frame period of one frame period, and D becomes valid in the latter half frame period.

The description will be continued with reference to FIG.

The upper data driver 115 is connected to the data bus 105
Of the display data transferred via the display data, converts the display data of the odd-numbered dots into a liquid crystal drive voltage corresponding to the display data, and outputs the data to the upper data switch 117 via the output line 116.
Transfer to The upper data switch 117 applies the transferred liquid crystal drive voltage in accordance with the switch control signals 1L and 2L during the first half period of one horizontal period to the upper drain corresponding to each output line 116 in the left half of the liquid crystal panel 127. Output to line 118. Similarly, during the latter half of one horizontal period, the switch control signal 1
In accordance with R and 2R, the liquid crystal application voltage is output to the upper half drain line 118 corresponding to each output line 116 in the right half of the liquid crystal panel 127. At the same time, the lower data driver 119 takes in display data of even-numbered dots from the display data transferred via the data bus 105, converts the display data into a liquid crystal drive voltage corresponding to the display data, and outputs To the side data switch 121.

Like the upper data switch 117, the lower data switch 121 applies the transferred liquid crystal drive voltage to the left of the liquid crystal panel 127 according to the switch control signals 1L and 2L during the first half of one horizontal period. Output to half of the drain lines 122 corresponding to each output line 120. Similarly, the latter half of one horizontal period 1 /
In the second period, the liquid crystal application voltage is output to the right half of the liquid crystal panel 127 to the drain line 122 corresponding to each output line 120 according to the switch control signals 1R and 2R.

Thus, the upper data switch 117,
From the lower data switch 121, the LCD panel 1
The liquid crystal drive voltage is output to the drain lines 118 and 122 in the same part on the left and right sides of 27. At the same time, the scan driver 123
According to L1, n / 2 output lines 124 are changed from the first line to the n / 2th output line 124.
Select up to the line and enable it.

The scanning switch 125 operates in the first half of one frame period.
In the 1/2 period, n / 2 gate lines from the first half to the n / 2th line, which are the upper half, are selected from the n gate lines 126 according to the switch control signal U, and are enabled. The gate line corresponding to the output line 124 is enabled. Similarly, the latter half 1
In the / 2 period, according to the switch control signal D, select the n / 2 gate lines of the n / 2th line from the n / 2 + 1 which is the lower half,
The gate line 126 corresponding to the enabled output line 124 is enabled. A gate-on voltage for turning on the TFT of the dot of the liquid crystal panel 127 connected to each gate line 126 is applied from the scan driver 123 to the enabled gate line 126. A liquid crystal driving voltage is applied from the drain lines 118 and 122 to each dot connected to the gate line to which the gate-on voltage is applied, and display is performed.

Next, the operation of the data drivers 115 and 119 and the data switch 109 will be described with reference to FIGS. 4, 5 and 7.

As shown in the timing chart of FIG. 7, the upper data driver 115 first sets the display data D1 to Dm for one horizontal cycle transferred via the data bus 105 to the first half of one horizontal cycle. Of the display data of two cycles of display data D1 to Dm / 2, display data of m / 4 dots of odd-numbered dots is converted into data latch 401 according to the dot clock.
Are taken in one dot at a time. M / 4 for data latch 401
When the display data for the dots is taken in, the control signal CLm / 2 that becomes valid every 1/2 horizontal cycle becomes valid. The display data of m / 4 dots for the first half horizontal cycle taken into the data latch 401 is taken into the shift latch 402 at once via the data bus 402 in synchronization with the rising timing of CLm / 2. It is. The display data captured by the shift latch 402 is transferred to the voltage generation circuit 405 via the data bus 404 at one time.

The voltage generation circuit 405 converts the transferred display data into a corresponding liquid crystal applied voltage, and transfers it to the upper data switch 117 via the corresponding output line 116. In the upper data switch 117, the switch control signal 1L becomes valid (H) in the first half period of one horizontal cycle, so that the left half of the liquid crystal panel 127 has m / 4 upper drain lines 11
The left first switches SWL1-1 to SWL1-m / 4 for selecting 8 are turned on. Next, the second switch SWL2-1 to SWL2-m / 4 are turned on when the second switch SWL2-1 is enabled a little later than 1L during the same period. The liquid crystal drive voltage transferred from the output line 116 is the first half of the m / 2 upper drain lines 118 and the left half of the m / 2 upper drain lines 118 connected to the left switch in the ON state. Is output to

Next, when 1L falls, the left first switches SWL1-1 to SWL1-m / 4 are turned off, and 2L falls a little later than 1L, thereby causing the left second switch SWL2-m to fall.
From 1 the SWL2-m / 4 is turned off, and the transfer of the liquid crystal applied voltage ends. The transferred liquid crystal applied voltage is
It is applied to the corresponding odd-numbered horizontal dots in the left half of 7, and is held in each image dot until the left switch is turned on again in the next horizontal period.

When the switch is switched, the upper drain line
Although the voltage transferred to 118 fluctuates, the left first switch SW
L1-1 to SWL1-m / 4, left second switch SWL2-1 to SWL2-
By turning on and off before m / 4, the voltage fluctuation is absorbed by the left capacitor CL1-1 having a sufficiently large capacity from CL1-1 to CL1-m / 4, and the liquid crystal applied voltage applied to each dot of the liquid crystal panel 127 is Does not fluctuate.

Next, in the latter half period of one horizontal cycle,
Of the display data Dm / 2 + 1 to Dm in the 1/2 period, display data of m / 4 dots of odd-numbered dots are sequentially taken into the data latch 401 one by one according to the dot clock. When the display data of m / 4 dots is taken into the data latch 401, the control signal CLm / 2 which becomes valid every 1/2 horizontal cycle becomes valid. The display data of m / 4 dots for the latter half cycle taken into the data latch 401 is CLm / 2
At the same time, the data is taken into the shift latch 402 via the data bus 402 at a time. The display data captured by the shift latch 402 is transmitted to the data bus 404.
Are transferred to the voltage generation circuit 405 at a time via the LCD, are converted into liquid crystal applied voltages corresponding to the display data, and are transferred to the upper data switch 117 via the corresponding output lines 116.

In the upper data switch 117, the switch control signal 1R becomes valid (H) in the latter half period of one horizontal cycle, so that the right half of the liquid crystal panel 127 has m / 4 upper drain lines 118. Select the right first switch SWR1-1 to SWR1-m
/ 4 turns on. Next, a little later than 1R
When 2R is enabled, the right second switch SWR2-1 to SWR
2-m / 4 turns on. The liquid crystal drive voltage transferred from the output line 116 is m / 2 upper drain lines 118 during the latter half period.
Of the right half of the m /
It is output to the four upper drain lines 118. Next, when 1R falls, the right first switches SWR1-1 to SWR1-m / 4 are turned off, and 2R falls a little later than 1R, whereby the right second switches SWR2-1 to SWR2-m. m / 4 is turned off, and the transfer of the liquid crystal applied voltage ends.

The transferred liquid crystal application voltage is applied to the liquid crystal panel 12.
It is applied to the corresponding odd-numbered horizontal dots in the right half of 7 and held in each dot until the right switch is turned on again in the next one horizontal cycle period. The voltage fluctuation due to the on / off switching of the right switch is absorbed by the right capacitors CR-1 to CR-m / 4, as in the case of the left switch.

The operation of the lower data driver 119 and the lower data switch 121 is similar to that of the upper driver except that the data driver 119 takes in the even-numbered display data and outputs the corresponding liquid crystal applied voltage to the lower drain line 122. Data driver 11
5. Same as the upper data switch 117.

Next, referring to FIG. 6 and FIG.
The operation of 123 and scan switch 125 will be described.

The scanning driver 123 sequentially selects the n / 2 output lines 124 from the first line to the n / 2th line every one horizontal period in accordance with CL1 transferred via the signal line 107. A gate-on voltage for turning on a TFT of a dot connected to the gate line 126 is output to the selected scanning line 124. Output line 124
Is selected up to the (n / 2) th line, the control signal CLn / 2 that is enabled every 1/2 frame is enabled, and the scanning driver 123
The output line 124 is selected again from the first line. Scanning switch
At 125, as shown in the timing chart of FIG. 8, the control signal U is valid (H) during the first half of one frame, and the n / 2 upper switches SWU-1 to SWU-n / 2 Is turned on. The gate-on voltage transferred from the output line 124 is
One horizontal line from the first line to the (n / 2) th line is connected to n / 2 gate lines corresponding to each output line 124 in the upper half of the liquid crystal panel 127 via the upper switch 601 in the ON state. It is applied sequentially in each cycle. When the gate-on voltage is applied, the TFT of the dot connected to the gate line is turned on, and the liquid crystal application voltage is applied from the corresponding upper and lower drain lines 118 and 122. The upper half is displayed.

Next, in the second half period, the control signal U falls, and the upper switch is turned off. At the same time, the control signal D becomes valid (H), and n / 2 lower switches SWD-1
Turn SWD-n / 2 on. The gate-on voltage is applied to the liquid crystal panel 1 via the lower switch 602 which is in the on state.
The lower half 27 of the n / 2 gate lines 126 corresponding to the respective output lines 124 are sequentially applied from the (n / 2 + 1) th line to the nth line every one horizontal cycle. When the gate-on voltage is applied, the TFT of the dot connected to the gate line is turned on, and the liquid crystal application voltage is applied from the corresponding upper and lower drain lines 118 and 122. The lower half is displayed. Thus, in one frame period,
When the display for one frame is performed in order of 1/2 frame in order, the gate-on voltage is output from the first line to the gate line again, and the display of the next frame is performed in the same manner.

As described above, the switch circuit for selecting the drain line and the gate line for outputting the liquid crystal application voltage and the gate-on voltage is provided, and the liquid crystal panel is divided and driven by switching the drain line and the gate line corresponding to the display. can do. With such a driving circuit configuration and driving method, display can be performed on a liquid crystal panel even when the number of data drivers and scanning drivers is reduced.

In this embodiment, each of the upper and lower data drivers and the scanning driver is one, and the number of switch groups of the data switches and the scanning switches is 2 (horizontal) corresponding to the number of drivers and the number of output terminals thereof. Direction, upper vertical direction), the number of divisions of the liquid crystal panel was described as 4. However, the number of drivers, the number of switch groups of each switch, and the number of divisions of the liquid crystal panel were changed, and switch control signals, data drivers, and scan drivers were changed. By generating the control signal at an appropriate timing, display can be performed by a single upper and lower data driver and a single scan driver on a liquid crystal panel of any resolution.

By appropriately combining the number of output terminals of the data driver and the scanning driver with the resolution of the liquid crystal panel and the number of switch groups of the data switch and the scanning switch, the liquid crystal panel is driven by a plurality of data drivers and the scanning driver. You can also.

Further, by integrating the data driver, the scan driver, the data switch control circuit and the scan switch control circuit, the data switch and the scan switch on the same glass substrate as the liquid crystal panel using low-temperature Poly-Si,
High-definition, without reducing the performance of these circuits,
It is possible to cope with a narrow pitch.

Further, these circuits may not be integrated on the same glass substrate as the liquid crystal panel, but may be connected as external circuits around the liquid crystal panel as in a conventional liquid crystal display device.

Further, a liquid crystal display device can be similarly manufactured by using a substrate that can be used in a high-temperature process and using a high-temperature Poly-Si technique.

Next, a second embodiment of the present invention in which a data switch control circuit and a scan switch control circuit are incorporated in a data driver and a scan driver, respectively, will be described with reference to FIGS.

FIG. 9 is a configuration diagram of the liquid crystal display device of the second embodiment.

In FIG. 9, reference numeral 901 denotes an upper data driver;
Built-in data switch control circuit. A signal bus 902 transfers data switch control signals 1L, 2L, 1R, and 2R. Reference numeral 903 denotes a lower data driver which has a built-in data switch control circuit. A signal bus 904 transfers data switch control signals 1L, 2L, 1R, and 2R. A scan driver 905 has a built-in scan switch control circuit. 90
Reference numeral 6 denotes a signal bus for transferring the scan switch control signals U and D.

FIG. 10 is a configuration diagram of the upper and lower data drivers 901 and 903 of the second embodiment.

In FIG. 10, reference numeral 1001 denotes a data switch control circuit, and 1002 denotes a signal line, which transfers a control signal CLm / 2.

The structure and operation of the liquid crystal display device of this embodiment are the same as those of the first embodiment except that the data switch control circuit and the scan switch control circuit are built in the upper and lower data drivers 901 and 903 and the scan driver 905, respectively. This is the same as the liquid crystal display device.

In this embodiment, since the switch control circuit is built in the data driver and the scan driver, it is not necessary to provide the switch control circuit as an external circuit, so that the number of parts can be further reduced.

Also, a data driver incorporating the data switch control circuit of the present embodiment is used in only one of the upper and lower data drivers, and the other is not equipped with the same data switch control circuit as in the first embodiment. A configuration in which a control signal CLm / 2 and data switch control signals 1L, 2L, 1R, and 2R are supplied from a data driver having a built-in data switch control circuit by using a data driver is also possible.

Next, a third embodiment of the present invention in which a data switch control circuit and a scan switch control circuit are incorporated in a liquid crystal controller will be described with reference to FIG.

FIG. 11 is a configuration diagram of the liquid crystal display device of the third embodiment.

In FIG. 11, reference numeral 1101 denotes a liquid crystal controller.
Built-in data switch control circuit and scan switch control circuit. 1102 and 1103 are signal lines, each of which has a control signal CLm /
Transfer 2 and CLn / 2. 1104 and 1105 are signal buses for transferring data switch control signals 1L, 2L, 1R and 2R and scan switch control signals U and D, respectively.

The configuration and operation of the liquid crystal display device of this embodiment are the same as those of the display device of the first embodiment except that the data switch control circuit and the scan switch control circuit are built in the liquid crystal controller 1101.

In this embodiment, since a switch control circuit is built in the liquid crystal controller, a conventional data driver and scanning driver can be used.

Next, a fourth embodiment of the present invention using an information processing apparatus having a function of generating and transferring control signals for data switches and scanning switches will be described with reference to FIG.

FIG. 12 is a configuration diagram of the liquid crystal display device of the fourth embodiment.

In FIG. 12, reference numeral 1201 denotes an information processing apparatus such as a PC, which has a function of generating control signals for the upper and lower data switches 117 and 121 and the scanning switch 125. 1202 is a liquid crystal controller. 1203 and 1204 are signal lines, each of which is a control signal
Transfer CLm / 2 and CLn / 2. 1205 and 1206 are signal buses for transferring data switch control signals 1L, 2L, 1R and 2R and scan switch control signals U and D, respectively.

The configuration and operation of the liquid crystal display device of this embodiment is such that the upper and lower data drivers 115 and 119 have CLm instead of CL1.
/ 2, and sends CLn / 2 instead of FLM to the scan driver 123.
Transfer the upper and lower data switch 115, 121, scanning switch
It is the same as the display device of the first embodiment except that the control signal of 125 is transferred from the information processing device 1201.

In this embodiment, since the switch control signal is supplied from the information processing apparatus, it is not necessary to newly provide a switch control circuit, so that the number of parts can be further reduced.

[0076]

According to the present invention, a switch circuit for selecting a drain line and a gate line for outputting a liquid crystal applied voltage and a gate-on voltage is provided so as to divide a display of a liquid crystal panel into a plurality of blocks. By switching between the drain line and the gate line and performing divided driving, display can be performed on the liquid crystal panel even when the number of data drivers and scanning drivers is reduced. For this reason, the number of components can be reduced, high definition, miniaturization, and weight reduction can be achieved, and cost can be reduced.

Further, a data driver, a scan driver, a data switch control circuit and a scan switch control circuit, a data switch and a scan switch, which are drive circuits of the liquid crystal panel, are mounted on the same glass substrate as the liquid crystal panel by using low-temperature Poly-Si. In this way, it is possible to cope with higher definition, smaller size, and narrower pitch without deteriorating the performance of these circuits.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a data switch control circuit of FIG. 1;

FIG. 3 is a configuration diagram of a scanning switch control circuit of FIG. 1;

FIG. 4 is a configuration diagram of a data driver of FIG. 1;

FIG. 5 is a configuration diagram of the data switch of FIG. 1;

FIG. 6 is a configuration diagram of a scanning switch of FIG. 1;

FIG. 7 is an operation timing chart of the data switch control circuit and the data driver of the present invention.

FIG. 8 is an operation timing chart of the scan switch control circuit and the scan driver of the present invention.

FIG. 9 is a configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 10 is a configuration diagram of a data driver according to a second embodiment.

FIG. 11 is a configuration diagram of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 12 is a configuration diagram of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 13 is a configuration diagram of a conventional liquid crystal display device.

FIG. 14 is a data driver operation timing chart of a conventional liquid crystal display device.

FIG. 15 is a display operation timing chart of a conventional liquid crystal display device.

[Explanation of symbols]

101: information processing device, 102: liquid crystal controller, 103: signal bus, 104, 10
5 ... data bus, 106, 107, 108 ... signal line,
109: data switch control circuit, 110: signal line, 111: signal bus, 112: scanning switch control circuit, 113: signal line, 114: signal bus, 115: upper data driver, 116: output line, 117: upper data switch , 118 ... upper drain line, 119
… Lower data driver, 120… Output line, 121…
Lower data switch, 122: Lower drain line, 123: Scan driver, 124: Output line, 125: Scan switch, 126: Gate line, 127: Liquid crystal panel.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623V H04N 5/66 102 H04N 5/66 102B F-term (Reference) 2H093 NA16 NA22 NA80 NC13 NC16 NC22 NC23 NC26 NC34 ND34 ND49 ND55 NE07 NE10 5C006 AA01 AA16 AF42 AF44 BB14 BC03 BC12 BC20 BF03 BF04 BF16 BF22 BF37 EB05 FA43 5C058 AA09 BA03 BA25 BB22 BB25 5C080 DD05 DD25 DD02 DD25

Claims (5)

[Claims] 1. A liquid crystal panel having a plurality of switch elements and pixel electrodes arranged in a matrix and a plurality of gate lines and drain lines connected to the plurality of switch elements, and an external device such as an information processing apparatus. A controller for generating display data and a control signal for displaying on the liquid crystal panel from the transferred display data and control signal, and fetching the display data according to the control signal and generating a liquid crystal applied voltage corresponding to the display data A data driver, a data switch circuit for switching and applying the liquid crystal application voltage to a drain line corresponding to display data of an area where display is to be performed on the liquid crystal panel at regular intervals, and selecting to turn on the switch element. A scan driver for generating a voltage, and a selection voltage applied from an output line of the scan driver, the gate line A scan switch circuit for switching and applying a gate line corresponding to an output line of the scan driver of a gate line in a region where display of the liquid crystal panel is to be performed at regular intervals, and the data switch circuit and the scan switch circuit. A control circuit having a function of generating a control signal for controlling, wherein the data driver converts the display data to the liquid crystal application voltage according to a control signal generated by the controller and a timing of the control signal generated by the control circuit. And the number of output lines that output the liquid crystal application voltage is less than the number of drain lines. The scan driver according to a control signal generated by the controller and a timing of a control signal generated by the control circuit. , Sequentially selecting output lines of the scan driver at regular intervals, outputting a selection voltage to the selected output lines, The number of the output lines is less than the number of the gate lines, and the data switch circuit should display the liquid crystal applied voltage applied from the output lines of the data driver less than the number of the drain lines on the liquid crystal panel. The scan switch circuit has a function of switching to a drain line corresponding to each of the output lines of the region in accordance with the timing of a control signal generated by the control circuit and switching the output at regular intervals. The selection voltage applied from the output lines of the scanning lines smaller than the number of the gate lines is applied to the gate line corresponding to the output line of the gate line in the region where the display of the liquid crystal panel is to be performed by the control circuit. According to the timing of the signal, has a function of switching and outputting at regular intervals, the control circuit, so that the display is performed correctly on the liquid crystal panel, Serial data driver and a display control signal of the scan driver, a liquid crystal display device characterized by having a function of generating a control signal of the data switching circuit and the scan switch circuit. 2. The liquid crystal display device according to claim 1, wherein each of said data drivers outputs said liquid crystal applied voltage to a horizontal odd-numbered drain line and an even-numbered drain line, respectively. Wherein the number of the scanning drivers is one. 3. The liquid crystal display device according to claim 1, wherein the data switch circuit changes the voltage applied to the liquid crystal to the number of output lines of the data driver and the number of output lines of the data driver during a certain period for performing display in one horizontal period. In a divided period obtained by dividing one horizontal period determined by the number of drain lines into a plurality of periods, a liquid crystal applied voltage corresponding to each divided period corresponds to display data of a drain line in a region corresponding to display data of the liquid crystal panel. A liquid crystal display device having a function of switching to output to a drain line to be output and outputting a liquid crystal applied voltage for one horizontal period to all drain lines during one horizontal period. 4. The liquid crystal display device according to claim 1, wherein the scanning switch circuit applies the selection voltage to the number of output lines of the scanning driver and the gate line during a certain period for displaying one frame period. And a gate line corresponding to each output line of the scan driver in a region where display is to be performed in each of the divided periods of the liquid crystal panel in each divided period. A liquid crystal display device having a function of switching and outputting the selected voltage for each divided period, and outputting a selection voltage to all gate lines in one frame period. 5. The liquid crystal display device according to claim 1, wherein said control circuit controls said data driver to be transferred in one horizontal period.
The display data for the horizontal period sequentially takes in the display data of a portion corresponding to each of the plurality of divided periods of the one horizontal period, and generates a control signal for controlling to convert the display data to the liquid crystal applied voltage. And generating a control signal for controlling the scan driver to select an output line of the scan driver from a first line every time a plurality of divided periods of the one frame starts, and causing the data switch circuit to control the one horizontal line. For each of a plurality of divided periods of the period, the scan switch generates a control signal for controlling the liquid crystal applied voltage to be switched and output to a drain line of a region of the liquid crystal panel corresponding to display data of each divided period; Is controlled such that the scanning voltage is switched to the gate line in the area of the liquid crystal panel corresponding to each divided period and output in each of the plurality of divided periods of the one frame. The liquid crystal display device characterized by having a function of generating a control signal to.