JP2003255907A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of the degradation of picture quality due to display unevenness such as lateral smear caused by the waveform delay (distortion) of common electrode wirings which are provided respectively and independently in constituting a large-screen and high definition liquid crystal display device. <P>SOLUTION: The display device performs writing to entire display pixels existing on one horizontal line by separating a gate line making even numbered display pixels in display pixels of one horizontal line in selected states and a gate making odd numbered display pixels in selected states and by settling the holding of a half of gradation signals in the first half horizontal period in two horizontal periods and by settling the holding of the remaining half of gradation signals in the latter half horizontal period. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and its driving circuit, and more particularly to a display device using liquid crystal (including low-pitched polysilicon) and organic EL and its driving circuit.

[0002]

2. Description of the Related Art In recent years, active matrix type liquid crystal display devices having a large screen and high definition have been actively developed along with their application to notebook PC display devices, desktop PC monitors, TV monitors and the like. There is. In these large-screen, high-definition active matrix liquid crystal display devices, the viewing angle is an important image characteristic. In general, the TN type liquid crystal display system, which is widely used, applies an electric field in the vertical direction of the substrate and controls the direction of liquid crystal molecules in a plane perpendicular to the substrate. It depends heavily on it. On the other hand, an in-plane switching method (IPS) is attracting attention because it can realize a very excellent viewing angle characteristic in principle. The horizontal electric field method does not apply an electric field in the vertical direction of the substrate as in the normal TN type liquid crystal display method, but makes the direction of the electric field applied to the liquid crystal substantially parallel to the substrate so that the liquid crystal is in the plane of the substrate. In this method, the direction of molecules is controlled to modulate light. In such an IPS type liquid crystal display device, by providing a pixel electrode and a common electrode arranged in a comb shape in each pixel region, the direction of the electric field applied to the liquid crystal is controlled to be substantially parallel to the substrate. To do.

This IPS type liquid crystal display device has a problem that the aperture ratio (transmittance) is low because the pixel electrode and the common electrode are arranged in a comb shape as described above. This problem of transmittance can be improved by increasing the distance between the comb electrodes. When the comb-teeth electrodes are widened, it is necessary to increase the voltage applied between the comb-teeth electrodes, and it is also possible to improve the response speed of the liquid crystal by increasing the applied voltage. On the other hand, when the applied voltage is increased, new problems occur such as an increase in withstand voltage of the driving IC that drives the liquid crystal panel, an increase in driving power, and deterioration of TFT characteristics over time. The aperture ratio and the response speed, which are the problems in the characteristics of the IPS type liquid crystal display device, are improved without increasing the driving voltage supplied to the liquid crystal display element and without increasing the electrical load on the thin film transistor. A liquid crystal display device and its driving method are disclosed in JP-A-2001-228456.
Etc. are disclosed. This method is a method in which common electrode wirings independent of each other in the scanning line direction are provided and the modulation voltage to the pixel electrodes is supplied so that the voltage polarities of the adjacent signal wirings are opposite.

[0004]

However, according to the conventional driving method, when a large-screen / high-definition liquid crystal display device is constructed, the waveform delay (distortion) of the common electrode wiring provided independently of each other causes the image quality to deteriorate. Have a big impact. In a large-screen liquid crystal display device, since the wiring length of the common electrode wiring becomes long, the wiring resistance value of each common electrode wiring becomes large, and at the same time, the wiring capacitance also increases. Therefore, the time constant of each common electrode wiring becomes large, and the time required to reach the desired common electrode potential becomes long. In high-definition liquid crystal display devices,
1 because there are many horizontal lines to scan in one frame period
In the common electrode wiring in which the horizontal period is shortened, the screen is enlarged, and the time constant is increased, there arises a problem that the potential of the common electrode cannot reach a desired common electrode voltage within one horizontal period. Further, in the liquid crystal panel in which this problem occurs, deterioration of image quality such that display unevenness called lateral smear is likely to occur is also a problem.

It is an object of the present invention to provide a display device and a driving circuit for the display device in which display unevenness such as lateral smear is reduced.

[0006]

According to a first embodiment of the present invention, a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common lines substantially parallel to the gate lines. A wiring portion including an electrode line, a switching element formed near each intersection of the drain line and the gate line, a pixel electrode connected to an output terminal of the switching element, and a surface facing the pixel electrode. And a pixel portion including a pixel electrode connected to the common electrode line and a storage capacitor, an array substrate including the wiring portion and the pixel portion,
A counter substrate disposed opposite to the array substrate, a liquid crystal layer sandwiched between the array substrate and the counter substrate, and two polarizing plates disposed outside the array substrate and the counter substrate in the previous period. A liquid crystal panel, a signal output circuit for outputting a gradation signal corresponding to the display to the drain line, a gate scanning drive circuit for sequentially scanning the gate line for each horizontal period, and a common electrode line In a liquid crystal display device composed of a common electrode drive circuit which is driven independently of each other, two pixel lines adjacent to the pixel section connected to one common electrode line and forming one horizontal line are provided. Of these, a pixel array in which approximately half of the pixel portions are connected to one of the gate lines, and the remaining pixel portions that form the one horizontal line are pixel arrays connected to the other of the gate lines, and a certain horizontal period In the above When the scanning drive circuit selects the one gate line, the previous period signal output circuit applies the grayscale signal corresponding to the pixel electrodes of the substantially half of the pixel units, and the grayscale signals of the pixel electrodes and the common electrode. When the drive circuit controls the rotation of the liquid crystal by the electric field generated by the common electrode voltage applied to the common electrode, and in the horizontal period next to the horizontal period, the gate scanning drive circuit selects the other gate line, The signal output circuit applies a grayscale signal corresponding to the pixel electrode of the remaining pixel portion, and is generated by the grayscale signal of the pixel electrode and the common electrode voltage applied to the common electrode by the common electrode driving circuit. It is characterized in that the rotation of the liquid crystal is controlled by an electric field to activate the liquid crystal of all the pixel portions forming one horizontal line connected to the one common electrode line.

Further, the pixel portion forming one horizontal line connected to one common electrode line is alternately connected to two gate lines adjacent to the pixel portion for each pixel. Is characterized by.

The second embodiment of the present invention comprises a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common electrode lines substantially parallel to the gate lines. Wiring part, switching elements formed near the intersection of the drain line and the gate line, a pixel electrode connected to the output end of the switching element, and the common electrode facing the pixel electrode. A pixel portion formed of a pixel electrode connected to a line and a storage capacitor; an array substrate including the wiring portion and the pixel portion; a counter substrate arranged to face the array substrate; And a liquid crystal layer sandwiched between the counter substrate and the counter substrate, a liquid crystal panel composed of the array substrate and two polarizing plates provided outside the counter substrate, and the gate line for each horizontal period. Gate scanning that scans sequentially In a liquid crystal display device including a drive circuit and a common electrode drive circuit that independently drives the common electrode lines, a drain line is arbitrarily selected from a plurality of the drain lines corresponding to a predetermined number of time divisions. A time division switch that can be selected, a plurality of control signals that control the selection / non-selection state of the time division switch, and a plurality of gradation signal lines that propagate a gradation signal to the plurality of time division switches, A signal output circuit for outputting the gradation signal from the output terminal to the gradation signal line in a time series corresponding to a predetermined number of time divisions, and one horizontal line connected to one common electrode line. A pixel array in which a plurality of the pixel portions corresponding to the predetermined number of time divisions are alternately connected to the two gate lines adjacent to the constituent pixel portion is provided, and the gate scanning drive circuit is arranged in a certain horizontal period. Two games When one of the gate lines is selected, the grayscale signal line is propagated to the one or more drain lines selected by the time division switch through the time division switch. By applying the grayscale signal, the grayscale signals are sequentially applied to the pixel electrodes of the plurality of pixel portions corresponding to the predetermined number of time divisions in the selected state, and the grayscale signals of the pixel electrodes are , The common electrode driving circuit controls the rotation of the liquid crystal by an electric field generated by the common electrode voltage applied to the common electrode, and in the horizontal period next to the horizontal period, the gate scanning driving circuit controls the two gate lines. When the other one of the gate lines is selected, it is propagated to the one or more drain lines selected by the time division switch by the gradation signal line via the time division switch. Before By sequentially applying the gradation signals, the gradation signals are applied to the pixel electrodes of the plurality of pixel portions corresponding to the predetermined number of time divisions in the selected state, and the gradation signals of the pixel electrodes,
All the pixel units forming one horizontal line connected to the one common electrode line by controlling the rotation of the liquid crystal by the electric field generated by the common electrode driving circuit and the common electrode voltage applied to the common electrode. It is characterized by activating the liquid crystal of.

The first aspect of the present invention and the second aspect of the present invention
In the above configuration, the signal output circuit outputs grayscale signals having mutually different polarities from the adjacent output terminals, and the common electrode drive circuit is connected to the one common electrode line.
The common electrode voltage applied to the common electrode line during the selection period of the gate line selected first among the two gate lines adjacent to the pixel portion forming the horizontal line or before the selection period. It is characterized by changing the polarity.

Further, first, the time division switch selects all of the plurality of drain lines, applies a gradation signal to the drain lines via the time division switch, and thereafter, the predetermined time division number. In each of the plurality of selection periods divided by, one drain line is brought into a non-selected state in order to hold a grayscale signal in the drain line in order, and all the pixels on the gate line in the selected state are held. The liquid crystal cell in the pixel section is activated, and the signal output circuit outputs the gradation signal corresponding to the pixel section which is held in each selection period in time series according to the predetermined number of time divisions. Characterize things.

An initial selection period is provided in addition to the plurality of selection periods divided by the predetermined number of time divisions. First, the time division switch selects all of the plurality of drain lines in the initial selection period. Then, a grayscale signal is applied to the drain line through the time divisional switch, and then only one drain line is sequentially selected in each of the plurality of selection periods divided by the predetermined number of time divisions. Therefore, the drain lines are made to sequentially hold the gradation signals to activate the liquid crystal cells in all the pixel portions on the gate lines in the selected state, and the signal output circuit sets the initial selection period to the initial selection period. It is characterized in that the gradation signals corresponding to the pixels which are in the holding state in each of the selection times except the above are output in time series according to the predetermined number of time divisions.

Further, when the display section comprises one pixel with three pixels of R (red), G (green), and B (blue), the time division number by the time division switch is R,
It is characterized by three time divisions corresponding to G and B.

Further, the gate scanning drive circuit, the common electrode drive circuit, the time divisional switch, the switching element and the like are constituted by thin film transistors using poly-Si on the array substrate.

Further, it functions as a central control, and the calculation, logic,
And a central processing unit for performing effective determination and transmitting signals to and from an input device, an output device, and a storage device, the storage device used for storing instructions and data, and inputting information to an information device. The information device including the input device and the liquid crystal display device configured to output information from the inside of the information device to the outside and further output a signal for display. The liquid crystal display device according to the embodiment and the second embodiment of the present invention is provided.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing the configuration of a liquid crystal display device according to the first embodiment of the present invention. In FIG. 1, a plurality of drain lines 200 (D0, D1, D2, D3, D4, D5, ...) Corresponding to the horizontal resolution of the liquid crystal display device.
, A plurality of gate lines 400 (G0, G1, G2, G3, ...) One more than the vertical resolution of the liquid crystal display device are arranged to intersect. Further, a plurality of common electrode lines (hereinafter, common voltage lines) 600 (C0, C1,
C2, ...) Are arranged parallel to the gate lines 400. For example, the resolution of the liquid crystal display device is XGA (1024 × RG).
B × 768) color display panel, the number of drain lines 200 is 1024 × 3, and the number of gate lines 400 is 7.
There are 68 + 1 lines, and 768 common voltage lines 600 are arranged.

The signal output circuit 100 outputs to each drain line 200 a gradation signal corresponding to display data transferred from the outside to the liquid crystal display device. Gate scan drive circuit 30
0 sequentially drives each gate line 400. Further, the common drive circuit 500 drives each common voltage line 600.
Here, the signal output circuit 100 includes a grayscale signal (positive polarity grayscale signal) having a higher potential than the common voltage line 600 (a common potential) and a grayscale signal (negative polarity) having a lower potential than the common potential. And a sex gradation signal) are output in alternating current in one horizontal cycle. The gate scan driving circuit 300 selects one horizontal line in one horizontal period and sequentially repeats this to scan all the gate lines 400. In addition, the common drive circuit 500 drives each of the common lines 600 independently, and converts the positive common potential and the negative common potential into AC in a frame cycle and outputs the AC.

In the vicinity of the intersection where the drain line 200 and the gate line 400 are arranged to intersect with each other, the display pixel 800 (P0
0, P01, ..., P10, P11, ..., P20, P2
1, ...) Are arranged in a matrix. One display pixel 800 includes a switching element 801 and a liquid crystal capacitor 802. Although not shown here, a storage capacitor is also configured to suppress fluctuations in the potential held in the liquid crystal capacitor 802 during one frame period.

Here, a case where the switching element 801 included in the display pixel 800 is a TFT made of nMOS will be described. The drain terminal of each switching element 801 is connected to the drain line 200, the source terminal is connected to the other end of the liquid crystal capacitor 802, one end of which is connected to the common voltage line 600, and the gate is supplied from the gate line.
When a voltage is applied to the gate terminal and the switching element is turned on, the liquid crystal capacitance is charged with the gradation signal transferred from the signal output circuit.

In the first embodiment of the present invention, the display pixels (Pn0, Pn1, Pn2, Pn3, P) of one horizontal line are displayed.
...) (n = 0, 1, 2, ...) Of the n4, Pn5, ...) (n = 0, 1, 2, ...), the gate terminals of the switching elements included in the even-numbered display pixels (Pn0, Pn2, Pn4 ,.
(N = 0, 1, 2, 3, ...) And the gate terminals of the switching elements included in the odd-numbered display pixels (Pn1, Pn3, Pn5, ...) Are connected to the gate line Gn + 1 (n = 0,
1, 2, 3, ...). With this arrangement, when the gate ON voltage is applied to the gate line Gn + 1, the nth
The display pixels selected in the horizontal line are odd-numbered (Pn
1, Pn3, Pn5, ...) only, and the common voltage line C
The load on n is about half that of the conventional line-sequential drive. In addition, the n-th selected simultaneously from the gate line Gn + 1
The display pixels of the +1 horizontal line are also even (Pn0, Pn
2, Pn4, ...) and the load on the common voltage line Cn + 1 is about half that of the conventional line-sequential drive.
In the description of the first embodiment of the present invention, the above configuration will be described. However, as the display pixel connection method, other than the above,
Display pixels of one horizontal line (Pn0, Pn1, Pn2, P
Of n3, Pn4, Pn5, ... (n = 0, 1, 2, ...), odd-numbered display pixels (Pn1, Pn3, Pn5,
...) is connected to the gate line Gn (n = 0, 1, 2, 3, ...) And the switching elements included in the even-numbered display pixels (Pn0, Pn2, Pn4, ...). Gate terminal Gn + 1 (n
= 0, 1, 2, 3, ...). Even with this arrangement, the load on the common voltage lines Cn and Cn + 1 corresponding to the nth horizontal line and the (n + 1) th horizontal line selected by the gate line Gn + 1 is about half that of the conventional line-sequential driving. As a result, the arrival speed of the common voltage supplied to the common electrode by the common voltage line is approximately doubled (the time constant is approximately half) as compared with the conventional method, and it is possible to drive a large-screen / high-definition panel.

The operation of the liquid crystal display device according to the first embodiment of the present invention will be described with reference to the timing chart shown in FIG.

In FIG. 2, Tf is one frame period and Th is one horizontal period. G0, G1, G2, G
.. are drive waveforms of the gate lines 400 sequentially driven by the gate scan drive circuit 300. Each gate line G
0, G1, G2, G3, ... Are gate scan drive circuits 30.
By 0, the gate ON voltage (H
i voltage) is applied. The period in which the gate ON voltage is applied to each gate line is within one horizontal period Th.

The operation of writing the positive gradation signal on the even horizontal lines and writing the negative gradation signal on the odd horizontal lines in the first frame period Tf will be described below.

First, the gate scanning drive circuit 300 applies a gate ON voltage to the gate line G0 to display even-numbered display pixels P0 of the 0th horizontal line connected to the gate line G0.
The switching elements 0, P02, P04, ... Are turned on. The common drive circuit 500 applies a positive polarity common potential (Low level) for writing a positive polarity gradation signal to the liquid crystal capacitance to the common voltage line C0 corresponding to the 0th horizontal line. At this time, the signal output circuit 100 determines that the gate line G0
The positive gradation signal corresponding to the even-numbered display pixels P00, P02, P04, ... Of the 0th horizontal line selected by is output to the corresponding drain lines D0, D2, D4 ,. After the desired positive gradation signal is applied to the even-numbered display pixels of the 0th horizontal line while the gate line G0 is at the Hi level, the gate line G0 is in the OFF state (Low
Level) and holds the gradation signal written during one frame period. Next, when the gate ON voltage is applied to the gate line G1, the odd-numbered display pixels (P01, P03, P05, ...) Of the 0th horizontal line and the even-numbered display pixels (P10, P10, P12, P14, ...)
Is selected. Since the positive gradation signal is written in the 0th horizontal line, the common voltage line C0 is
A positive common potential is applied by the common drive circuit 500. On the contrary, since the negative gradation signal is written in the first horizontal line, the negative common potential (Hi level) is applied to the common voltage line C1 corresponding to the first horizontal line. Then, the signal output circuit 100 connects the drain lines D1, D3, D5, ... Connected to the odd-numbered display pixels (P01, P03, P05, ...) Of the 0th horizontal line to the positive electrodes corresponding to the respective display pixels. Output a sex gradation signal. At the same time, the even-numbered display pixels (P10, P12,
Drain lines D0, D2 connected to P14, ...
A negative gradation signal corresponding to each display pixel is output to D4, .... As a result, the gate line G1 becomes the OFF level and is in the holding state at the stage where the desired positive gradation signal or negative gradation signal is written in each display pixel.
Therefore, the positive gradation signal is held in all the display pixels on the 0th horizontal line after the two horizontal periods of the gate lines G0 and G1 as described above. Next, when the gate ON voltage is applied to the gate line G2, the odd-numbered display pixels (P11, P13, P15, ...) On the first horizontal line and the even-numbered display pixels (P20, P20, on the second horizontal line). P22, P2
4, ...) is selected. Since the negative gradation signal is written in the first horizontal line, the common voltage line C
A negative common potential is applied to 1. On the contrary, since the positive gradation signal is written in the second horizontal line, the positive common potential is applied to the common voltage line C2 corresponding to the second horizontal line. Then, the signal output circuit 100 causes the odd-numbered display pixels (P11, P13, P15,
...) connected to the drain lines D1, D3, D5, ...
Then, a negative gradation signal corresponding to each display pixel is output.
At the same time, the even-numbered display pixels (P
Drain line D connected to 20, P22, P24, ...
A positive gradation signal corresponding to each display pixel is output to 0, D2, D4, .... As a result, the gate line G2 becomes the OFF level and becomes in the holding state when the desired positive gradation signal or negative gradation signal is written in each display pixel. Therefore, after the two horizontal periods of the gate lines G1 and G2 as described above, the negative gradation signal is held in all display pixels on the first horizontal line. By repeating the above operation in sequence, it is possible to hold the positive gradation signal in all the even horizontal lines and hold the negative gradation signal in all the odd horizontal lines in the first frame.

The operation of writing a negative gradation signal on an even horizontal line and writing a positive gradation signal on an odd horizontal line in the next frame will be described below.

First, a gate ON voltage is applied to the gate line G0. Since the display pixel on the 0th horizontal line writes a negative polarity grayscale signal which is opposite to the positive polarity grayscale signal held in the previous frame, during the selection period of the gate voltage G0 or the gate voltage G0.
At the timing before selecting 0, the common voltage line C has been
The positive polarity common potential applied to 0 is inverted to the negative polarity common potential. Therefore, the AC cycle of the common potential applied to the common voltage line 600 becomes the frame cycle Tf as shown in FIG. Also, as before, the signal output circuit 1
00 is an even-numbered display pixel P00 of the 0th horizontal line,
The negative polarity grayscale signals corresponding to P02, P04, ... Are output to the corresponding drain lines D0, D2, D4 ,.
The FF state (Low level) is entered, and the gradation signal written during one frame period is held. Next, the gate line G
When the gate ON voltage is applied to 1, the odd-numbered display pixels (P01, P03, P05, ...) Of the 0th horizontal line
And the even-numbered display pixels of the first horizontal line (P10, P
12, P14, ...) are selected. Since the negative gradation signal is written in the 0th horizontal line, the negative common potential is continuously applied to the common voltage line C0. Also, the first
In order to write the positive gradation signal on the horizontal line, the positive common potential having the inverted polarity is applied to the common voltage line C1 corresponding to the first horizontal line. The timing of reversal at this time is the same as the timing described above. Then, the signal output circuit 100 connects the drain lines D1, D3, D5, ... Connected to the odd-numbered display pixels (P01, P03, P05, ...) Of the 0th horizontal line to the negative electrodes corresponding to the respective display pixels. Output a sex gradation signal. At the same time, the even-numbered display pixels (P10, P12,
Drain lines D0, D2 connected to P14, ...
A positive gradation signal corresponding to each display pixel is output to D4, .... At the stage where the desired positive gradation signal or negative gradation signal is written in each display pixel, the gate line G1 becomes OFF level and is in a holding state. Next, when the gate ON voltage is applied to the gate line G2, the odd-numbered display pixels (P11, P13, P1) of the first horizontal line are displayed.
5, ...) and an even-numbered display pixel (P
20, P22, P24, ...) are selected. Since the positive polarity gradation signal is written to the first horizontal line, the positive polarity common potential is applied to the common line C1 as before. On the contrary, since the negative gradation signal is written in the second horizontal line,
A negative common potential is applied to the common line C2 corresponding to the second horizontal line. The timing of alternating current here is also as described above. The signal output circuit 100 has the first
Odd-numbered display pixels on the horizontal line (P11, P13, P
15, ...) Drain lines D1, D3, D connected to
A positive gradation signal corresponding to each display pixel is output to 5, ... At the same time, a negative gradation signal corresponding to each display pixel is output to the drain lines D0, D2, D4, ... Connected to the even-numbered display pixels (P20, P22, P24, ...) Of the second horizontal line. To do. At the stage where the desired positive polarity gradation signal or negative polarity gradation signal is written in each display pixel, the gate line G2 becomes OFF level and is in a holding state. Therefore, by inverting the polarity of the common potential applied to the common voltage line 600 in the frame cycle, the polarity of the gradation signal held in each display pixel can be made alternating.

As described above, in the first embodiment of the present invention, among the display pixels of one horizontal line, the gate line that makes the even-numbered display pixel a selected state and the odd-numbered display pixel a selected state. , The gate line is separated, and in the first half horizontal period of the two horizontal periods, it is confirmed that half of the grayscale signals are held.
In the latter half of the horizontal period, holding of the remaining half gradation signal is confirmed, and writing to all the display pixels on one horizontal line is performed, so that the load of each common voltage line in one horizontal period is half that of the conventional one. Therefore, the writing speed of the common potential and the gradation signal becomes faster than that of the conventional method. Therefore, the liquid crystal display panel can have higher definition, larger size, and higher image quality.

Further, in the first embodiment of the present invention, the MOS-TFT which is the switching element of the display pixel portion may be formed of amorphous Si or low temperature polySi.

Further, in the first embodiment of the present invention, the switching element 801 is described as an nMOS-TFT, but other switching elements, pMOS-TF.
It may be T.

Furthermore, in the first embodiment of the present invention, the signal output circuit 100, the gate scanning drive circuit 300, and the common drive circuit 500 can be constituted by external LSI chips, and are low temperature polySi TFTs. It is also possible to incorporate the constructed circuit into a liquid crystal panel by forming it on a substrate on which a pixel portion is formed. Furthermore, the signal output circuit 1
It is also possible to adopt a hybrid system in which only 00 is an external LSI and the other gate scanning drive circuit 300 and common drive circuit 500 are built in the liquid crystal panel by using low temperature polySi. In addition, the low temperature p built into the liquid crystal display panel
The ollySi circuit may have a pMOS single channel, an nMOS single channel, or a cMOS configuration.

A second embodiment of the present invention will be described below with reference to FIGS. 3 to 6. The second embodiment of the present invention is
This is a case where RGB time division driving is performed using the first embodiment of the present invention.

FIG. 3 is a diagram showing the configuration of a liquid crystal display device according to the second embodiment of the present invention. In FIG. 3, a plurality of drain lines 200 (D0, D1, D2, D3, D4, D5, ...) Corresponding to the horizontal resolution of the liquid crystal display panel.
, A plurality of gate lines 400 (G0, G1, G2, G3, ...) One more than the vertical resolution of the liquid crystal display device are arranged to intersect. Further, a plurality of common voltage lines 600 (C0, C1, C2, ...) Corresponding to the vertical resolution are arranged in parallel with the gate line 400. For example, in the case of a color display panel with a liquid crystal display panel resolution of XGA (1024 × RGB × 768), the drain line 200 is 1024.
× 3, and the gate line 400 becomes 768 + 1,
768 common voltage lines 600 are arranged. The signal output circuit 100 outputs the gradation signal corresponding to the display data transferred from the outside to the liquid crystal display device by the signal line 101 (DR0, D).
Output to R1, ...). Each signal line 101 is connected to each of the time divisional switches 701 and 70 included in the time divisional switch group 700.
2 and 703, and the other end of each time divisional switch has three adjacent drain lines 200 (D0, D0,
D1, D2 or D3, D4, D5 or ...). Reference numeral 900 in FIG. 3 denotes a controller of the time divisional switch group 700, which outputs a control signal 901 for controlling the time divisional switches. The time divisional switch 701 is controlled by SA of the control signal 901, and the time divisional switch 7
When 01 is selected, the signal lines DR0, DR1, ...
Then, the drain lines D0, D3, ... Are brought into a connected state, and the gradation signal output from the signal output circuit 100 can be transferred to the display pixel 800. Similarly, the time division switch 70
2 is controlled by the control signal SB, and the time divisional switch 70
3 is controlled by a control signal SC, and connects each signal line DR and drain line D in the selected state. The gate scan driving circuit 300 sequentially drives each gate line 400. In addition, the common drive circuit 500 includes each common voltage line 6
Drive 00. Here, the signal output circuit 100 includes a grayscale signal (positive polarity grayscale signal) having a higher potential than the common voltage line 600 (a common potential) and a grayscale signal (negative polarity) having a lower potential than the common potential. And a sex gradation signal) are output in alternating current in one horizontal cycle. The gate scan drive circuit 300 is
All the gate lines 400 are scanned by selecting one horizontal line in one horizontal period and sequentially repeating this. In addition, the common drive circuit 500 independently drives each common voltage line 600 to convert the positive common potential and the negative common potential into AC in a frame cycle and output the AC.

In the vicinity of the intersection where the drain line 200 and the gate line 400 are arranged to intersect with each other, the display pixel 800 (P0
0, P01, ..., P10, P11, ..., P20, P2
1, ...) Are arranged on the matrix. One display pixel 800 includes a switching element 801 and a liquid crystal capacitor 802. Although not shown here, a storage capacitor is also configured to suppress fluctuations in the potential held in the liquid crystal capacitor 802 during one frame period. Here, the switching element 801 included in the display pixel 800 is a TF including an nMOS.
The case of T will be described. Each switching element 801
Has a drain terminal connected to the drain line 200, a source terminal connected to the other end of the liquid crystal capacitor 802 having one end connected to the common voltage line 600, and a gate ON voltage supplied from the gate line is applied to the gate terminal. When the switching element is turned on, the gradation signal held in the capacitance of the drain line 200 can be charged in the liquid crystal capacitance.

In the second embodiment of the present invention, the display pixels (Pn0, Pn1, Pn2, Pn3, Pn) of one horizontal line.
.. (n = 0, 1, 2, ...) Of the three adjacent display pixels are set as one group, and the gate terminals of the switching elements included in the display pixels of the adjacent groups are set to different gate lines. Connecting. In the case of this description, a certain display pixel group (Pn0, Pn1, Pn2)
The gate terminals of the switching elements included in ... Are connected to the gate lines Gn (n = 0, 1, 2, 3, ...) And the switching elements included in the other display pixel group (Pn3, Pn4, Pn5). Gate terminal to gate line Gn + 1
(N = 0, 1, 2, 3, ...). With this arrangement, when the gate ON voltage is applied to the gate line Gn + 1, the display pixels selected in the nth horizontal line are half of the display pixels included in one horizontal line, so that the load on the common voltage line Cn is reduced. It is about half that of conventional line-sequential drive. Further, since the display pixels of the (n + 1) th horizontal line simultaneously selected from the gate line Gn + 1 are half of the display pixels included in one horizontal line, the load on the common voltage line Cn + 1 is about half that of the conventional line-sequential driving. become.
Therefore, the load capacity of each common voltage line is halved compared to the conventional one, and the time constant is also halved. Therefore, even in a high-definition and large-screen liquid crystal display device, the convergence time of the common voltage supplied from the common voltage line is also reduced. It is shortened by almost half. In the description of the second embodiment of the present invention, the above configuration will be described. However, as a display pixel connection method, in addition to the above, one horizontal line of display pixels (Pn0, Pn1, Pn2, Pn3,
Pn4, Pn5, ...) (n = 0, 1, 2, ...)
The gate terminals of the switching elements included in the display pixel group (Pn3, Pn4, Pn5) ... Are connected to the gate line Gn (n
= 0, 1, 2, 3, ..., And the gate terminals of the switching elements included in the display pixel group (Pn0, Pn1, Pn2) ... Are connected to the gate line Gn + 1 (n = 0, 1,
2, 3, ...) may be connected. Even in this arrangement, the nth horizontal line and the n + 1th horizontal line selected by the gate line Gn + 1.
Common voltage lines Cn and Cn + 1 corresponding to horizontal lines
Also, the load on the line is about half that of the conventional line-sequential drive.

The operation of the liquid crystal display device according to the second embodiment of the present invention will be described above. The operations of the gate scanning drive circuit 300 and the common drive circuit 500 according to the second embodiment of the present invention are the same as those of the first embodiment of the present invention, and therefore will be omitted. Therefore, in the timing chart of FIG. 4, the operations of the signal output circuit 100, the time divisional switch group 700, and the controller 900 in the second embodiment of the present invention will be described.

In FIG. 4, Th is one horizontal period.
G0, G1, ... Are drive waveforms of the gate lines 400 sequentially driven by the gate scan drive circuit 300. Each gate line G0, G1, ...
The gate ON voltage (Hi voltage) is sequentially applied every horizontal period Th. The period in which the gate ON voltage is applied to each gate line is within one horizontal period Th. Further, one horizontal period Th is time-divided into three periods, and the control signal SA is brought into a selected state within the first period Ta, so that the signal lines DR0, DR1 ...
And the drain lines D0, D3, ... The signal lines DR0, DR1 ... Are connected to the drain lines D1, D4, ... By setting the control signal SB in the selected state within the next period Tb. By setting the control signal SC in the selected state within the last period Tc, the signal lines DR0, DR1 ...
2 and D5 ... are connected. This makes it possible to time-divisionally supply the grayscale signal supplied from the signal line 101 to the three adjacent drain lines D0, D1, and D2 within one horizontal period.

In the second embodiment of the present invention,
The operation of writing the positive polarity display signal on the horizontal line will be described. First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0 to display a pixel group (P0) of the 0th horizontal line connected to the gate line G0.
0, P01, P02) ... Switching elements are turned on. The common drive circuit 500 applies a positive polarity common potential (Low level) for writing a positive polarity gradation signal to the liquid crystal capacitance to the common voltage line C0 corresponding to the 0th horizontal line. In the first period Ta that is time-divided into three, the display pixel P output to the signal line DR0 by the signal output circuit 100.
The positive gradation signal corresponding to 00 is applied to the liquid crystal capacitance of the display pixel P00 via the time divisional switch 701 and the drain line D0 which are selected by the control signal SA. Next, in the period Tb, the positive polarity grayscale signal corresponding to the display pixel P01 output from the signal output circuit 100 to the signal line DR0 is supplied to the time divisional switch 702 and the drain line D1 which are selected by the control signal SB. It is applied to the liquid crystal capacitance of the display pixel P01 via Then, within the last period Tc, the signal output circuit 100 causes the signal line DR0
The positive gradation signal corresponding to the display pixel P02 output to the display pixel P02 is transmitted through the time divisional switch 703 and the drain line D2 which are selected by the control signal SC.
Applied to the liquid crystal capacitance of. As described above, after the desired gradation signals are applied to the three adjacent display pixel groups to bring them into the holding state, the gate line G0 is in the OFF state (L
ow level) and holds the gradation signal written during one frame period.

Next, when the gate ON voltage is applied to the gate line G1, the other display pixel group of the 0th horizontal line (P03, P04, P05) ... And the display pixel group of the first horizontal line (P10). , P11, P12) ... Are selected. Since the positive polarity gradation signal is written in the 0th horizontal line, the positive common potential is applied to the common voltage line C0 by the common drive circuit 500 as before. In addition, since the negative gradation signal is written in the first horizontal line as described in the first embodiment of the present invention, the negative common potential ((1) is supplied to the common voltage line C1 corresponding to the first horizontal line. Hi level) is applied. Then, in the first period Ta in which one horizontal period is time-divided into three, the display pixel P03 output to the signal line DR1 by the signal output circuit 100.
The positive grayscale signal corresponding to the time-division switch 701 and the drain line D3 selected by the control signal SA.
Is applied to the liquid crystal capacitance of the display pixel P03 via. Next, in the period Tb, the positive gradation signal corresponding to the display pixel P04 output to the signal line DR1 by the signal output circuit 100 is supplied to the time divisional switch 702 and the drain line D4 which are selected by the control signal SB. Through the display pixel P
Applied to the liquid crystal capacitor 04. And the last period Tc
In the above, the time-division switch 703 in which the positive gradation signal corresponding to the display pixel P05 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SC
And is applied to the liquid crystal capacitance of the display pixel P05 via the drain line D5.

In this way, after the desired gradation signal is applied to the other display pixel group to bring it into the holding state, the gate line G1 is turned off (Low level). Also, during this period, the display pixel group (P1) of the first horizontal line that is also selected by the gate line G1
0, P11, P12) ... Similarly, a negative gradation signal is applied. Therefore, as described above, the gate lines G0 and G1
After 2 horizontal periods of, the positive gradation signal is held in all the display pixels on the 0th horizontal line.

Another time division drive system in the second embodiment of the present invention will be described with reference to FIG. In FIG. 5, Th is one horizontal period. G0, G1, ... Are drive waveforms of the gate lines 400 sequentially driven by the gate scan drive circuit 300. Each gate line G0, G1 ...
The gate scanning drive circuit 300 sequentially applies the gate ON voltage (Hi voltage) every horizontal period Th. The period in which the gate ON voltage is applied to each gate line is within one horizontal period Th. In addition, one horizontal period Th is set to three periods T
It is divided into a, Tb, and Tc. By setting all the control signals SA, SB, and SC in the initial period Ta, the signal lines DR0, DR1, ... And the drain lines (D0, D1,
D2) and (D3, D4, D5) are connected, and the control signal SA is set to the OFF level within this Ta period to turn the time divisional switch 701 into the OFF state, and the signal lines DR0, DR
1 and the drain lines D0 and D3 are separated. In the next period Tb, the control signals SB and SC are continuously set to the selected state, and the control signal SB is set to the OFF level in this Tb period, so that the time divisional switch 702 is turned off and the signal lines DR0, DR1 and the drain lines D1 and D4 are separated. The control signal SC is continuously selected during the last period Tc, and the control signal SC is turned off within this Tc period.
By setting the level, the time divisional switch 703 is turned off, and the signal lines DR0 and DR1 and the drain lines D2 and D5 are set.
Separate and.

In the second embodiment of the present invention,
The operation of writing the positive polarity display signal on the horizontal line will be described. First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0 to display a pixel group (P0) of the 0th horizontal line connected to the gate line G0.
0, P01, P02) ... Switching elements are turned on. The common drive circuit 500 applies a positive polarity common potential (Low level) for writing a positive polarity gradation signal to the liquid crystal capacitance to the common voltage line C0 corresponding to the 0th horizontal line.

In the first period Ta, which is time-divided into three, the positive gradation signal corresponding to the display pixel P00 output to the signal line DR0 by the signal output circuit 100 is the control signal SA.
It is applied to the liquid crystal capacitance of the display pixel P00 via the time divisional switch 701 and the drain line D0 which are in the selected state. Next, in the period Tb, the signal output circuit 10
The positive gradation signal corresponding to the display pixel P01, which is 0 output to the signal line DR0, passes through the time divisional switch 702 and the drain line D1 which are selected by the control signal SB,
It is applied to the liquid crystal capacitance of the display pixel P01. Then, in the last period Tc, the signal output circuit 100 outputs the signal line D
The positive gradation signal corresponding to the display pixel P02 output to R0 is displayed on the display pixel P0 via the time divisional switch 703 and the drain line D2 which are selected by the control signal SC.
Applied to a liquid crystal capacitance of 2. As described above, after the desired gradation signals are applied to the three adjacent display pixel groups to bring them into the holding state, the gate line G0 is in the OFF state (L
ow level) and holds the gradation signal written during one frame period.

Next, when the gate ON voltage is applied to the gate line G1, the other display pixel group (P03, P04, P05) of the 0th horizontal line and the display pixel group of the first horizontal line (P10). , P11, P12) ... Are selected. Since the positive polarity gradation signal is written in the 0th horizontal line, the positive common potential is applied to the common voltage line C0 by the common drive circuit 500 as before. In addition, since the negative gradation signal is written in the first horizontal line as described in the first embodiment of the present invention, the negative common potential ((1) is supplied to the common voltage line C1 corresponding to the first horizontal line. Hi level) is applied. Then, in the first period Ta in which one horizontal period is time-divided into three, the display pixel P03 output to the signal line DR1 by the signal output circuit 100.
The positive grayscale signal corresponding to the time-division switch 701 and the drain line D3 selected by the control signal SA.
Is applied to the liquid crystal capacitance of the display pixel P03 via. Next, in the period Tb, the positive gradation signal corresponding to the display pixel P04 output to the signal line DR1 by the signal output circuit 100 is supplied to the time divisional switch 702 and the drain line D4 which are selected by the control signal SB. Through the display pixel P
Applied to the liquid crystal capacitor 04. And the last period Tc
In the above, the time-division switch 703 in which the positive gradation signal corresponding to the display pixel P05 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SC
And is applied to the liquid crystal capacitance of the display pixel P05 via the drain line D5.

As described above, after the desired gradation signal is applied to the other display pixel group to bring it into the holding state, the gate line G1 is turned off (Low level). Also, during this period, the display pixel group (P1) of the first horizontal line that is also selected by the gate line G1
0, P11, P12) ... Similarly, a negative gradation signal is applied. Therefore, as described above, the gate lines G0 and G1
After 2 horizontal periods of, the positive gradation signal is held in all the display pixels on the 0th horizontal line.

In the second embodiment of the present invention, another
One time division driving method will be described with reference to FIG. In FIG. 6, Th is one horizontal period. G0, G1 ...
Is a drive waveform of the gate line 400 sequentially driven by the gate scan drive circuit 300. Each gate line G0, G1
Is one horizontal cycle T by the gate scanning drive circuit 300.
A gate ON voltage (Hi voltage) is sequentially applied for each h.
The period in which the gate ON voltage is applied to each gate line is within one horizontal period Th. Moreover, one horizontal period Th is divided into three periods Ta, Tb, and Tc. First period Ta
Among them, the control signals SA, SB, and SC are all selected only during the Tp period, which is the precharge period, and the drain lines (D0, D1) connected to the signal lines DR0, DR1 ...
1, D2) and (D3, D4, D5) are precharged to a certain constant potential. After the precharge period Tp, the remaining S
B and SC are turned off, and the signal lines DR0, DR1,
Signal output circuit 1 to drain lines D0, D3, ...
The gradation signal output by 00 is written. Next period is Tb
Only the control signal SB is selected in the signal line DR
0, DR1, ... And the drain lines D1, D4 ,. By setting the control signal SC to the selected state within the last period Tc, the signal lines DR0, DR1 ... And the drain lines D2, D5.
... and connect. This makes it possible to time-divisionally supply the gradation signals supplied from the signal line 101 to the three adjacent drain lines D0, D1, and D2 within one horizontal period, and without changing the panel configuration. It becomes possible to precharge.

In the second embodiment of the present invention,
The operation of writing the positive polarity display signal on the horizontal line will be described. First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0 to display a pixel group (P0) of the 0th horizontal line connected to the gate line G0.
0, P01, P02) ... Switching elements are turned on. The common drive circuit 500 applies a positive polarity common potential (Low level) for writing a positive polarity gradation signal to the liquid crystal capacitance to the common voltage line C0 corresponding to the 0th horizontal line. In the precharge period, the drain lines D0 and D
1 and D2 are precharged toward the positive polarity grayscale signal corresponding to P00 output from the signal output circuit 100 by the signal output circuit 100, and after the precharge period, the time-division switch is selected by the control signal SA. A desired grayscale signal is applied to the liquid crystal capacitance of the display pixel P00 via the 701 and the drain line D0. Next, within the period Tb, the display pixel P output to the signal line DR0 by the signal output circuit 100.
The positive gradation signal corresponding to 01 is applied to the liquid crystal capacitance of the display pixel P01 via the time divisional switch 702 and the drain line D1 which are selected by the control signal SB. Then, in the final period Tc, the positive polarity grayscale signal corresponding to the display pixel P02 output from the signal output circuit 100 to the signal line DR0 is selected by the control signal SC, and the time divisional switch 703 and the drain line D2 are selected. Is applied to the liquid crystal capacitance of the display pixel P02 via. In this way, after the desired gradation signals are applied to the three adjacent display pixel groups to bring them into the holding state, the gate line G0
Becomes an OFF state (Low level) and holds the gradation signal written during one frame period. Next, when the gate ON voltage is applied to the gate line G1, the other display pixel group (P03, P04, P) of the 0th horizontal line.
05) ..., and the display pixel group of the first horizontal line (P1
0, P11, P12) ... Are selected. Since the positive polarity gradation signal is written in the 0th horizontal line, the positive common potential is applied to the common voltage line C0 by the common drive circuit 500 as before. In addition, since the negative gradation signal is written in the first horizontal line as described in the first embodiment of the present invention, the negative common potential ((1) is supplied to the common voltage line C1 corresponding to the first horizontal line. Hi level) is applied. Then, in the precharge period, the signal output circuit 100 causes the drain lines D3, D4, and D5 to be DR1.
Is precharged toward the negative polarity grayscale signal corresponding to P03 which is output to the control signal S after the precharge period.
A desired gradation signal is applied to the liquid crystal capacitance of the display pixel P03 via the time divisional switch 701 and the drain line D3 which are selected by A. Next, in the period Tb, the positive gradation signal corresponding to the display pixel P04 output from the signal output circuit 100 to the signal line DR1 is the control signal SB.
The voltage is applied to the liquid crystal capacitance of the display pixel P04 via the time divisional switch 702 and the drain line D4 which are in the selected state. Then, in the last period Tc, the positive polarity grayscale signal corresponding to the display pixel P05 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SC, and the time divisional switch 703 and the drain line D5 are selected. Is applied to the liquid crystal capacitance of the display pixel P05 via.

As described above, after the desired gradation signal is applied to the other display pixel group to bring it into the holding state, the gate line G1 is turned off (Low level). Also, during this period, the display pixel group (P1) of the first horizontal line that is also selected by the gate line G1 is selected.
0, P11, P12) ... Similarly, a negative gradation signal is applied. Therefore, as described above, the gate lines G0 and G1
After 2 horizontal periods of, the positive gradation signal is held in all the display pixels on the 0th horizontal line.

As described above, in the second embodiment of the present invention, the display pixels included in one horizontal line are grouped into three adjacent display pixels, and the adjacent display pixel groups have different gate lines. , The grayscale signal is applied to a certain display pixel group in a time division manner in a first half horizontal period of the two horizontal periods, and in the second half horizontal period, By applying a grayscale signal to one display pixel group in a time-divisional manner using a time-divisional switch, writing to all the display pixels on one horizontal line is performed, so that each common voltage line in one horizontal period Since it is possible to reduce the load to about half that of the conventional method, the writing speed of the common potential and the gradation signal becomes faster than that of the conventional method. Therefore, the liquid crystal display panel can have higher definition, larger size, and higher image quality.

Further, in the second embodiment of the present invention, the MOS-TFT which is the switching element of the display pixel portion may be formed of amorphous Si or low temperature polySi.

Further, in the second embodiment of the present invention, the timing for converting the common potential into an alternating current is as described in the first embodiment of the present invention.

In the second embodiment of the present invention, the switching element 801 has been described as an nMOS-TFT, but the other switching element, pMOS-TF.
It may be T or the like.

Further, in the second embodiment of the present invention, the signal output circuit 100, the gate scanning drive circuit 300, the time divisional switch group 700, and the common drive circuit 500 can be constituted by an external LSI chip, and , Low temperature poly
It is also possible to incorporate a circuit formed of TFTs made of Si into the liquid crystal panel by simultaneously forming the circuit on the substrate forming the display pixel portion. Furthermore, the signal output circuit 1
It is also possible to adopt a hybrid system in which only 00 is an external LSI and the other gate scanning drive circuit 300, time division switch group 700, and common drive circuit 500 are built in the liquid crystal panel by using low temperature polySi. In addition, the circuit of low temperature polySi built in the liquid crystal display panel is p
MOS single channel, nMOS single channel, or cMO
It may be an S configuration.

Furthermore, in the second embodiment of the present invention, when the signal output circuit 100 is an external IC, the number of output terminals can be reduced because it is time-division driving, so that cost reduction is expected. Be done. Further, even when the signal output circuit 100 is built in, since the DAC circuit and the data latch circuit can be reduced because the time-division driving is performed, the circuit can be downsized (narrow frame).

Also, regarding the second embodiment of the present invention, RGB
Although the time-divisional driving has been described as an example, the number of divisions is not limited to this, and the division may be performed by an arbitrary number n. In this case, according to the division number n, the drain line D corresponding to the display signal line DR
Is also n, the control signal of the time-division switch is also n (or n × 2), the division period is also changed accordingly, and the display pixel and the drain line which are in the voltage holding state in each selection period. This is possible by sequentially outputting the gradation signal corresponding to the signal output circuit 100.

Further, in the second embodiment of the present invention, RG
The arrangement of the B color pixels is not limited to this. Similarly, the order of the pixel electrode in the holding state and the color pixel corresponding to the drain line in each selection period is not limited.

The third embodiment of the present invention will be described below with reference to FIG.

The third embodiment of the present invention is an information device equipped with the liquid crystal display device described in the first embodiment of the present invention to the second embodiment of the present invention. The information device according to the third embodiment of the present invention is, for example, a computer, and as shown in the configuration diagram of the information device including the liquid crystal display device according to the third embodiment of the present invention shown in FIG. And the information device 100
The main components of 0 are a liquid crystal display device 1001, a central processing unit 1002, an input device 1003, a storage device 1004,
An output device 1005 and a power supply circuit 1006. The central processing unit 1002 acts as a central control, where calculations, logic and execution decisions are made. Further, 1007 is a system bus for transmitting signals from a central processing unit, an input unit, an output unit and a storage unit. The storage device 1004 is used to store instructions and data. The input device 1003 is
Information is input to the information device, and the input information may be data or a program. Also, the output device 1005
Is to output information from the inside of the information device to the outside world, and writes it to a printer or stores it in an auxiliary storage device such as a magnetic tape or a magnetic disk. The output device 1005 outputs a digital I / F signal of the display device, and, for example, a display data signal and a horizontal synchronizing signal that becomes effective once in one horizontal period, and once in one frame period. A liquid crystal display device 1 which is a display device including a signal including a vertical synchronizing signal, a clock signal, a display timing signal indicating a range of valid display data, etc.
Output to 001. In addition, the power supply circuit 1006 supplies power to the liquid crystal display device 1001 and other components of the information device 1000 that require power supply. The power supply circuit 1006 also generates and outputs a gradation reference voltage required by the liquid crystal display device 1001. The liquid crystal display device 100 described in the first embodiment of the present invention to the second embodiment of the present invention
By using No. 1, it is possible to realize the information device 1000 having a display device with a large screen, high definition, and high image quality.

Of the display pixels of one horizontal line, the gate lines that select even-numbered display pixels are separated from the gate lines that select odd-numbered display pixels, and the first half of the two horizontal periods is divided. By holding the half gradation signal in the horizontal period and by holding the remaining half gradation signal in the latter half of the horizontal period, writing to all the display pixels on one horizontal line is performed. Since the load on each common line in one horizontal period can be halved as compared with the conventional method, the writing speed of the common potential and the gradation signal becomes faster than that of the conventional method. Therefore, the liquid crystal display panel can have higher definition, larger size, and higher image quality.

Further, when the signal output circuit is an external LSI by using the time-divisional driving together, the number of LSI output terminals can be reduced, so that cost reduction is expected. Further, even when the signal output circuit is incorporated, since the DAC circuit and the data latch circuit can be reduced because the time-division driving is performed, the circuit can be downsized (narrow frame).

[0060]

According to the present invention, the effect of reducing display unevenness such as lateral smear can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a voltage waveform and timing chart according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a voltage waveform and timing chart according to the second embodiment of the present invention.

FIG. 5 is a voltage waveform and timing chart according to the second embodiment of the present invention.

FIG. 6 is a voltage waveform and timing chart according to the second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an information device including a liquid crystal display device according to a third embodiment of the present invention.

[Explanation of symbols]

100 ... Signal output circuit, 101 ... Signal line, 200 ... Drain line, 300 ... Gate scanning drive circuit, 400 ... Gate line, 500 ... Common drive circuit, 600 ... Common line, 70
0 ... time division switch group, 701 ... time division switch, 70
2 ... time division switch, 703 ... time division switch, 800
... Display pixel, 801 ... Switching element, 802 ... Liquid crystal capacity, 900 ... Controller, 901 ... Control signal, 10
00 ... Information equipment, 1001 ... Liquid crystal display device, 1002 ...
Central processing unit, 1003 ... Input device, 1004 ... Storage device, 1005 ... Output device, 1006 ... Power supply circuit, 100
7 ... System bus.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623U 623W 624 624B 624E 641 641C 642 642A (72) Inventor Hideo Sato Chiba Prefecture 3300 Hayano, Mobara-shi Hitachi, Ltd. Display group (72) Inventor Tomohiko Sato 3300, Hayano, Mobara-shi, Chiba Hitachi Ltd. Display group F-term (reference) 2H092 GA11 GA12 GA14 GA17 GA20 GA28 JA24 NA01 PA06 2H093 NC09 NC11 NC34 ND01 ND10 ND15 ND48 5C006 AA16 AA22 AC11 AC21 AC25 AC27 AF42 AF43 AF50 AF71 BB16 BC03 BC12 FA22 FA37 5C080 AA06 AA10 BB05 CC03 DD05 EE28 FF11 JJ02 JJ03 JJ04

Claims (10)

[Claims] 1. A wiring part comprising a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common electrode lines substantially parallel to the gate lines, and the drain line. And a pixel electrode connected to the output terminal of the switching element, and a pixel electrode facing the pixel electrode and connected to the common electrode line. An array substrate including a pixel portion configured by a storage capacitor, a counter substrate disposed to face the array substrate, a liquid crystal layer sandwiched between the array substrate and the counter substrate, and the array. A display panel including a substrate and two polarizing plates provided outside the counter substrate, a signal output circuit for outputting a grayscale signal corresponding to a display to the drain line, and the gate line extending horizontally. Sequentially for each period In a display device comprising a gate scanning drive circuit for scanning and a common electrode drive circuit for independently driving the common electrode line, the display device is connected to one common electrode line to form one horizontal line. Of the two gate lines adjacent to the pixel portion, approximately half the pixel portions are connected to one of the gate lines, and the remaining pixel portion forming the one horizontal line is the other gate line. When the gate scan drive circuit selects the one gate line in a certain horizontal period, the signal output circuit outputs a grayscale signal corresponding to the pixel electrodes of the approximately half of the pixel units. The direction of the liquid crystal is controlled by an electric field generated by applying a grayscale signal of the pixel electrode and a common electrode voltage applied to the common electrode by the common electrode driving circuit, and in the horizontal period next to the horizontal period, When the gate scan drive circuit selects the other gate line, the signal output circuit applies a grayscale signal corresponding to the pixel electrode of the remaining pixel portion, and the grayscale signal of the pixel electrode and the previous common electrode. The direction of the liquid crystal is controlled by the electric field generated by the common electrode voltage applied to the common electrode by the driving circuit.
A display device characterized by activating liquid crystals in all pixel portions forming one horizontal line connected to a common electrode line of a book. 2. The display device according to claim 1, wherein the pixel portion forming one horizontal line connected to one common electrode line is connected to two gate lines adjacent to the pixel portion. A display device characterized by being connected alternately for each pixel. 3. A wiring part comprising a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common electrode lines substantially parallel to the gate lines, and the drain line. And a pixel electrode connected to the output terminal of the switching element, and a pixel electrode facing the pixel electrode and connected to the common electrode line. An array substrate including a pixel portion configured by a storage capacitor, a counter substrate disposed to face the array substrate, a liquid crystal layer sandwiched between the array substrate and the counter substrate, and the array. A display panel including a substrate and two polarizing plates provided outside the counter substrate; a gate scanning drive circuit that sequentially scans the gate line every horizontal period; and a common electrode line Driven independently In the display device including a common electrode driving circuit, a time division switch capable of arbitrarily selecting a drain line from a plurality of the drain lines corresponding to a predetermined number of time divisions, and the selection of the time division switch. A plurality of control signal lines for controlling a non-selected state, a plurality of grayscale signal lines for transmitting grayscale signals to the plurality of time division switches, and a time series corresponding to a predetermined number of time divisions of the grayscale signals. A signal output circuit for outputting from the output terminal to the grayscale signal line, and to the two gate lines adjacent to the pixel portion forming one horizontal line connected to one common electrode line. A pixel array in which a plurality of the pixel portions corresponding to the predetermined number of time divisions are alternately connected, and in a certain horizontal period, the gate scanning drive circuit changes one of the two gate lines to one of the gate lines. If you choose, The grayscale signal propagated by the grayscale signal line is applied to the one or more drain lines that have been selected by the split switch via the time division switch, and thus the grayscale signal is brought into the selected state. The gradation signals are sequentially applied to the pixel electrodes of the plurality of pixel units according to the predetermined number of time divisions, and the gradation signals of the pixel electrodes and the common electrode voltage applied to the common electrode by the common electrode drive circuit. When the direction of the liquid crystal is controlled by an electric field generated by, and the gate scanning drive circuit selects the other gate line of the two gate lines in the horizontal period subsequent to the horizontal period, The grayscale signal propagated by the grayscale signal line is sequentially applied to the one or more drain lines selected by the split switch via the time division switch, whereby the selected state is set. Become A grayscale signal is applied to the pixel electrodes of a plurality of pixel portions according to the predetermined number of time divisions, and the grayscale signals of the pixel electrodes and the common electrode voltage applied to the common electrode by the common electrode drive circuit are applied. A display device characterized in that by controlling the direction of liquid crystal by a generated electric field, the liquid crystal of all pixel portions forming one horizontal line connected to the one common electrode line is activated. 4. The display device according to claim 1, wherein the signal output circuit outputs grayscale signals having mutually different polarities from adjacent output terminals, and the common electrode drive circuit is the one line. Of the two gate lines adjacent to the pixel portion forming one horizontal line connected to the common electrode line, the common electrode is selected during the selection period of the gate line selected first or before the selection period. A display device characterized by changing the polarity of a common electrode voltage applied to a line. 5. The display device according to claim 3, wherein the time division switch first selects all of the plurality of drain lines, and a gradation signal is applied to the drain lines via the time division switch. After that, in each of the plurality of selection periods divided by the predetermined number of time divisions, one drain line is sequentially set to a non-selection state so that the grayscale signal is sequentially held in the drain line, and the selection state is set. The liquid crystal cells in all the pixel portions on the gate line are activated, and the signal output circuit outputs the grayscale signal corresponding to the pixel portion which is held in each of the selection periods to the predetermined time division. A display device which outputs in time series according to the number. 6. The display device according to claim 3, wherein an initial selection period is provided in addition to the plurality of selection periods divided by the predetermined number of time divisions, and the time division switch is first provided in the initial selection period. Selects all of the plurality of drain lines, applies a gradation signal to the drain lines via the time division switch, and then sequentially selects 1 in each of the plurality of selection periods divided by the predetermined number of time divisions. By keeping only one drain line in the selected state, the drain lines are made to sequentially hold the gradation signals, and the liquid crystal cells in all the pixel parts on the gate line in the selected state are activated, and A display device, wherein the output circuit outputs, in a time series, grayscale signals corresponding to pixels that are in a holding state in each of the selection periods except the initial selection period, according to the predetermined number of time divisions. 7. The display device according to claim 3, 5, or 6, wherein the display section comprises one pixel with three pixels of R (red), G (green), and B (blue). In this case, the number of time divisions by the time division switch is R, G, and B.
A display device which is characterized by 3 time division corresponding to. 8. The display device according to claim 1, wherein the gate scan drive circuit, the common electrode drive circuit, the switching element and the like are pol on the array substrate.
A display device comprising a thin film transistor using y-Si. 9. The display device according to claim 3, 5, or 6, wherein the gate scanning drive circuit, the common electrode drive circuit, the time divisional switch, the switching element, and the like are provided on the array substrate. A display device comprising a thin film transistor using poly-Si above. 10. A central processing unit that functions as a central control, performs calculation, logic, and execution decision, and transmits signals to an input device, an output device, and a storage device, and is used for storing instructions and data. The storage device, the input device for inputting information to the information equipment, and the output device for outputting information from the inside of the information equipment to the outside and further outputting a signal for display In the information device provided with a display device, the display device is the display device according to any one of claims 1, 3, 5, and 6.