JP3891008B2 - Display device and information device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device and a driving circuit thereof, and more particularly to a display device using a liquid crystal (including low-pitched polysilicon) and an organic EL and a driving circuit thereof.
[0002]
[Prior art]
In recent years, active matrix liquid crystal display devices with large screens and high definition have been actively developed along with their application to notebook PC display devices, desktop PC monitors, TV monitors, and the like. In these large-screen, high-definition active matrix liquid crystal display devices, the viewing angle is an especially important image characteristic. In general, the TN type liquid crystal display system applies an electric field in the vertical direction of the substrate and controls the direction of the liquid crystal molecules in a plane perpendicular to the substrate. The dependency is large. On the other hand, a lateral electric field system (IPS) that can realize a viewing angle characteristic that is extremely excellent in principle has been attracting attention. In the horizontal electric field method, an electric field is not applied in the vertical direction of the substrate as in a normal TN liquid crystal display method, but the direction of the electric field applied to the liquid crystal is set to a direction substantially parallel to the substrate, and the liquid crystal is within the substrate surface This is a method of modulating light by controlling the direction of molecules. In such an IPS liquid crystal display device, the direction of the electric field applied to the liquid crystal is controlled in a direction substantially parallel to the substrate by providing a pixel electrode and a common electrode arranged in a comb shape in each pixel region. To do.
[0003]
This IPS liquid crystal display device has a problem that the aperture ratio (transmittance) is low because the pixel electrode and the common electrode are arranged in a comb shape as described above. This problem of transmittance can be improved by increasing the distance between the comb electrodes. When the comb electrodes are spread, it is necessary to increase the voltage applied between the comb electrodes, and the response speed of the liquid crystal can be improved by increasing the applied voltage. On the other hand, when the applied voltage is increased, new problems such as an increase in the withstand voltage of the driving IC that drives the liquid crystal panel, an increase in driving power, and deterioration of the TFT characteristics with time occur. The aperture ratio and the response speed, which are problems in the characteristics of such an IPS liquid crystal display device, are improved without increasing the driving voltage supplied to the liquid crystal display element and without increasing the electrical load on the thin film transistor. Japanese Patent Application Laid-Open No. 2001-228456 discloses a liquid crystal display device and a driving method thereof. This method is a method in which common electrode wirings independent from each other in the scanning line direction are provided, and the modulation voltage to the pixel electrode is supplied so that the voltage polarity of the adjacent signal wiring is in the reverse direction.
[0004]
[Problems to be solved by the invention]
However, in the conventional driving method, when a large-screen, high-definition liquid crystal display device is configured, the waveform delay (distortion) of the common electrode wiring provided independently greatly affects the image quality. In the large-screen liquid crystal display device, since the wiring length of the common electrode wiring becomes long, the wiring resistance value of each common electrode wiring increases, and at the same time, the wiring capacity increases. Therefore, the time constant of each common electrode wiring is increased, and the time required to reach the desired common electrode potential is increased. In a high-definition liquid crystal display device, since the number of horizontal lines scanned in one frame period is large, one horizontal period is shortened, and in a common electrode wiring having a large screen and a large time constant, the potential of the common electrode is 1 horizontal. There arises a problem that a desired common electrode voltage cannot be reached within the period. Further, in a liquid crystal panel in which this problem occurs, image quality deterioration such as display unevenness called horizontal smear is likely to occur.
[0005]
An object of the present invention is to provide a display device in which display unevenness such as lateral smear is reduced and a driving circuit thereof.
[0006]
[Means for Solving the Problems]
In the first embodiment of the present invention, a wiring portion is composed of a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common electrode lines substantially parallel to the gate lines. A switching element formed in the vicinity of the intersection of the drain line and the gate line, a pixel electrode connected to the output terminal of the switching element, and opposed to the pixel electrode and connected to the common electrode line A pixel portion composed of a pixel electrode and a storage capacitor, an array substrate including the wiring portion and the pixel portion, a counter substrate disposed to face the array substrate, and the counter substrate and the counter substrate A liquid crystal panel composed of a liquid crystal layer sandwiched between the substrate, the array substrate and two polarizing plates installed outside the counter substrate, and a gradation signal corresponding to the display on the drain line. Output signal output circuit In the liquid crystal display device including a gate scan driving circuit that sequentially scans the previous gate line every horizontal period and a common electrode driving circuit that is independently driven with respect to the common electrode line, the single common Of the two gate lines adjacent to the pixel portion connected to the electrode line and constituting one horizontal line, approximately half of the pixel portions are connected to one of the gate lines, and the rest constituting the one horizontal line The pixel portion is a pixel array connected to the other gate line, and when the gate scan driving circuit selects the one gate line in a certain horizontal period, the signal output circuit in the previous period is approximately half the number. A gradation signal corresponding to the pixel electrode of the pixel portion is applied, and the rotation of the liquid crystal is controlled by an electric field generated by the gradation signal of the pixel electrode and the common electrode voltage applied to the common electrode by the common electrode driving circuit. ,in front When the gate scan driving circuit selects the other gate line in the horizontal period next to the horizontal period, the signal output circuit applies a gradation signal corresponding to the pixel electrode of the remaining pixel portion, and the pixel One horizontal line connected to the one common electrode line by controlling the rotation of the liquid crystal by the electric field generated by the gray level signal of the electrode and the common electrode voltage applied to the common electrode by the common electrode driving circuit. The liquid crystal of all the pixel portions constituting the above is activated.
[0007]
In addition, the pixel portion configuring one horizontal line connected to one common electrode line is alternately connected to two gate lines adjacent to the pixel portion for each pixel. To do.
[0008]
In the second embodiment of the present invention, a wiring section including a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common electrode lines substantially parallel to the gate lines. A switching element formed in the vicinity of the intersection of the drain line and the gate line, a pixel electrode connected to the output terminal of the switching element, and opposed to the pixel electrode and connected to the common electrode line A pixel portion composed of a pixel electrode and a storage capacitor, an array substrate including the wiring portion and the pixel portion, a counter substrate disposed to face the array substrate, and the counter substrate and the counter substrate A liquid crystal panel composed of a liquid crystal layer sandwiched by a substrate, the array substrate and two polarizing plates installed outside the counter substrate, and the gate line are sequentially scanned every horizontal period. Gate scan drive circuit and In a liquid crystal display device including a common electrode driving circuit that is driven independently of the common electrode line, a drain line can be arbitrarily selected from a plurality of the drain lines corresponding to a predetermined number of time divisions. Possible time division switch, a plurality of control signals for controlling selection / non-selection of the time division switch, a plurality of gradation signal lines for transmitting gradation signals to the plurality of time division switches, and the gradation signal And a signal output circuit for outputting from the output terminal to the gradation signal line in time series corresponding to a predetermined number of time divisions, the pixels constituting one horizontal line connected to one common electrode line A pixel array in which a plurality of the pixel units corresponding to the predetermined time division number are alternately connected to the two gate lines adjacent to the unit, and the gate scan driving circuit includes two of the gate scan driving circuits in a certain horizontal period. Of the gate lines When the one of the gate lines is selected, the gray level propagated by the gray level signal line to the one or a plurality of drain lines selected by the time division switch via the time division switch. By applying a signal, gradation signals are sequentially applied to the pixel electrodes of the plurality of pixel portions corresponding to the predetermined number of time divisions in the selected state, and the gradation signals of the pixel electrodes and the common electrode The driving circuit controls the rotation of the liquid crystal with an electric field generated by the common electrode voltage applied to the common electrode, and the gate scanning driving circuit is already connected to the two gate lines in the horizontal period after the horizontal period. When one of the gate lines is selected, the gray level propagated by the gray level signal line to the one or more drain lines selected by the time division switch via the time division switch. Signal By sequentially applying, a gradation signal is applied to the pixel electrodes of the plurality of pixel portions corresponding to the predetermined number of time divisions in the selected state, and the gradation signal of the pixel electrode and the common electrode driving circuit Controls the rotation of the liquid crystal with the electric field generated by the common electrode voltage applied to the common electrode, thereby activating the liquid crystals of all the pixel portions constituting one horizontal line connected to the one common electrode line It is characterized by doing.
[0009]
In the first and second aspects of the present invention, the signal output circuit outputs gradation signals having different polarities from adjacent output terminals, and the common electrode driving circuit includes the one common electrode driving circuit. Among the two gate lines adjacent to each other that form a horizontal line connected to the common electrode line, the common line is selected during or before the selection period of the first selected gate line. The polarity of the common electrode voltage applied to the electrode line is changed.
[0010]
First, the time division switch selects all of the plurality of drain lines, applies a grayscale signal to the drain line through the time division switch, and then divides by the predetermined time division number. In each of the plurality of selection periods, by sequentially setting one drain line to a non-selected state, gradation signals are sequentially held in the drain line, and are present in all the pixel portions on the gate line in the selected state. The liquid crystal cell is activated, and the signal output circuit outputs a grayscale signal corresponding to the pixel portion that is held in each selection period in time series according to the predetermined time division number. And
[0011]
Further, an initial selection period is provided in addition to the plurality of selection periods divided by the predetermined time division number.First, in the initial selection period, the time division switch selects all the plurality of drain lines, By applying a grayscale signal to the drain line through the time division switch, and then setting only one drain line in a selected state in order in a plurality of selection periods divided by the predetermined time division number, Gradation signals are sequentially held in the drain line, the liquid crystal cells in all the pixel portions on the gate line in the selected state are activated, and the signal output circuit is configured to output each of the non-initial selection periods. A gradation signal corresponding to a pixel that is held in a selection time is output in time series according to the predetermined time division number.
[0012]
In the case where the display unit forms one pixel with three pixels of R (red), G (green), and B (blue), the number of time divisions by the time division switch is R, G, and 3 time division corresponding to B.
[0013]
Further, the gate scan driving circuit, the common electrode driving circuit, the time division switch, the switching element, and the like are configured by thin film transistors using poly-Si on the array substrate.
[0014]
It also functions as a central controller, performs computation, logic, and effective determination, and transmits signals to and from input devices, output devices, and storage devices, and is used for storing instructions and data. Liquid crystal display device comprising: storage device; input device for inputting information to information device; and output device for outputting information from inside to outside of information device and further outputting display signal The information apparatus comprising the liquid crystal display device according to the first embodiment of the present invention and the second embodiment of the present invention is provided.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0016]
FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention. In FIG. 1, a plurality of drain lines 200 (D0, D1, D2, D3, D4, D5,...) Corresponding to the horizontal resolution of the liquid crystal display device and a plurality of gates that are one more than the vertical resolution of the liquid crystal display device. Lines 400 (G0, G1, G2, G3,...) Are arranged to intersect. In addition, a plurality of common electrode lines (hereinafter, common voltage lines) 600 (C0, C1, C2,...) Corresponding to the vertical resolution are arranged in parallel with the gate lines 400. For example, in the case of a color display panel whose resolution of the liquid crystal display device is XGA (1024 × RGB × 768), the drain line 200 is 1024 × 3, the gate line 400 is 768 + 1, and the common voltage line 600 is 768. Be placed.
[0017]
The signal output circuit 100 outputs a gradation signal corresponding to display data transferred from the outside to the liquid crystal display device to each drain line 200. The gate scan driving circuit 300 sequentially drives each gate line 400. The common drive circuit 500 drives each common voltage line 600. Here, the signal output circuit 100 includes a gradation signal (positive gradation signal) having a higher potential than the potential (common potential) of the common voltage line 600 and a gradation signal (negative electrode) having a lower potential than the common potential. Sexual gradation signal) and output in a horizontal cycle. The gate scan driving circuit 300 scans all the gate lines 400 by selecting one horizontal line in one horizontal period and sequentially repeating this. Further, the common drive circuit 500 drives each common line 600 independently, and outputs a positive common potential and a negative common potential by alternating current with a frame period.
[0018]
Display pixels 800 (P00, P01,..., P10, P11,..., P20, P21,...) Are arranged in a matrix in the vicinity of the intersection where the drain line 200 and the gate line 400 are arranged to intersect. One display pixel 800 includes a switching element 801 and a liquid crystal capacitor 802. Although not shown here, a storage capacitor is also configured to suppress a change in potential held in the liquid crystal capacitor 802 in one frame period.
[0019]
Here, a case where the switching element 801 included in the display pixel 800 is a TFT made of an nMOS will be described. The drain terminal of each switching element 801 is connected to the drain line 200, the source terminal is connected to the other end of the liquid crystal capacitor 802 whose one end is connected to the common voltage line 600, and the gate ON voltage supplied from the gate line is When applied to the gate terminal and the switching element is turned on, the gradation signal transferred from the signal output circuit is charged in the liquid crystal capacitor.
[0020]
In the first embodiment of the present invention, even-numbered display pixels among display pixels (Pn0, Pn1, Pn2, Pn3, Pn4, Pn5,...) (N = 0, 1, 2,...) Of one horizontal line. The gate terminals of the switching elements included in (Pn0, Pn2, Pn4,...) Are connected to the gate line Gn (n = 0, 1, 2, 3,...), And the odd display pixels (Pn1, Pn3, Pn5,. ..) Are connected to the gate line Gn + 1 (n = 0, 1, 2, 3,...). With this arrangement, when the gate ON voltage is applied to the gate line Gn + 1, the display pixels selected in the nth horizontal line are only odd-numbered (Pn1, Pn3, Pn5,...) And the load on the common voltage line Cn. Is about half that of conventional line sequential driving. Further, the display pixels of the (n + 1) th horizontal line selected simultaneously from the gate line Gn + 1 are only even-numbered (Pn0, Pn2, Pn4,...), And the load on the common voltage line Cn + 1 is about half that of the conventional line sequential drive. become. In the description of the first embodiment of the present invention, the above configuration will be described. However, as a display pixel connection method, in addition to the above, display pixels of one horizontal line (Pn0, Pn1, Pn2, Pn3, Pn4, Pn5, ..) (N = 0, 1, 2,...), The gate terminals of the switching elements included in the odd-numbered display pixels (Pn1, Pn3, Pn5,...) Are connected to the gate lines Gn (n = 0, 1, 2,. .., And the gate terminals of the switching elements included in the even-numbered display pixels (Pn0, Pn2, Pn4,...) Are connected to the gate line Gn + 1 (n = 0, 1, 2, 3,...). You may do it. Even in this arrangement, the load on the common voltage lines Cn and Cn + 1 corresponding to the n-th horizontal line and the (n + 1) -th horizontal line selected by the gate line Gn + 1 is about half that of the conventional line-sequential driving. As a result, compared to the conventional method, the arrival speed of the common voltage supplied to the common electrode by the common voltage line is approximately doubled (the time constant is approximately half), which enables driving on a large screen / high-definition panel.
[0021]
The operation of the liquid crystal display device according to the first embodiment of the present invention will be described with reference to the timing chart shown in FIG.
[0022]
In FIG. 2, Tf is one frame period, and Th is one horizontal period. G0, G1, G2, G3,... Are drive waveforms of the gate lines 400 that are sequentially driven by the gate scan drive circuit 300. A gate ON voltage (Hi voltage) is sequentially applied to each gate line G0, G1, G2, G3,... By the gate scanning drive circuit 300 every horizontal period Th. The period during which each gate line is applied with the gate ON voltage is within one horizontal period Th.
[0023]
In the following, the operation of writing the positive gradation signal to the even horizontal line and writing the negative gradation signal to the odd horizontal line in the first frame period Tf will be described.
[0024]
First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0 to turn on the switching elements of the even-numbered display pixels P00, P02, P04,... Of the 0th horizontal line connected to the gate line G0. State. The common driving circuit 500 applies a positive common potential (Low level) for writing a positive gradation signal to the liquid crystal capacitor to the common voltage line C0 corresponding to the 0th horizontal line. At this time, the signal output circuit 100 outputs a positive polarity gradation signal corresponding to the even-numbered display pixels P00, P02, P04,... Of the 0th horizontal line selected by the gate line G0 to each corresponding drain line D0. , D2, D4,... After the desired positive polarity grayscale signal is applied to the even-numbered display pixels of the 0th horizontal line in the state where the gate line G0 is at the Hi level, the gate line G0 is in the OFF state (Low level). The written gradation signal is retained. Next, when the gate ON voltage is applied to the gate line G1, the odd-numbered display pixels (P01, P03, P05,...) Of the 0th horizontal line and the even-numbered display pixels (P10, P1 of the first horizontal line). P12, P14,...) Are selected. In order to write a positive gradation signal in the 0th horizontal line, a positive common potential is applied to the common voltage line C0 by the common drive circuit 500 in the same manner as before. On the contrary, in order to write a negative gradation signal to the first horizontal line, a negative common potential (Hi level) is applied to the common voltage line C1 corresponding to the first horizontal line. Then, the signal output circuit 100 has positive electrodes corresponding to the display pixels connected to the drain lines D1, D3, D5,... Connected to the odd-numbered display pixels (P01, P03, P05,...) Of the 0th horizontal line. A sex tone signal is output. At the same time, a negative gradation signal corresponding to each display pixel is applied to the drain lines D0, D2, D4,... Connected to the even-numbered display pixels (P10, P12, P14,...) Of the first horizontal line. Output. As a result, the gate line G1 is turned off and held at a stage where a desired positive tone signal or negative tone signal is written to each display pixel. Accordingly, the positive grayscale signal is held in all the display pixels on the 0th horizontal line through the two horizontal periods of the gate lines G0 and G1 as described above. Next, when the gate ON voltage is applied to the gate line G2, the odd-numbered display pixels (P11, P13, P15,...) Of the first horizontal line and the even-numbered display pixels (P20, P2 of the second horizontal line). P22, P24,...) Are selected. In order to write a negative gradation signal in the first horizontal line, a negative common potential is applied to the common voltage line C1 as before. On the contrary, in order to write the positive polarity gradation signal to the second horizontal line, the positive common potential is applied to the common voltage line C2 corresponding to the second horizontal line. Then, the signal output circuit 100 is connected to the drain lines D1, D3, D5,... Connected to the odd-numbered display pixels (P11, P13, P15,...) Of the first horizontal line. A sex tone signal is output. At the same time, the positive gradation signal corresponding to each display pixel is output to the drain lines D0, D2, D4,... Connected to the even-numbered display pixels (P20, P22, P24,...) Of the second horizontal line. To do. As a result, the gate line G2 is turned off and held at a stage where a desired positive polarity gradation signal or negative polarity gradation signal is written to each display pixel. Accordingly, the negative gradation signal is held in all the display pixels on the first horizontal line after two horizontal periods of the gate lines G1 and G2 as described above. By sequentially repeating the above-described operation, it is possible to hold positive polarity gradation signals in all even horizontal lines and hold negative polarity gradation signals in all odd horizontal lines in the first frame.
[0025]
Hereinafter, in the next frame, an operation of writing a negative gradation signal to an even horizontal line and writing a positive gradation signal to an odd horizontal line will be described.
[0026]
First, a gate ON voltage is applied to the gate line G0. The display pixels on the 0th horizontal line write a negative polarity grayscale signal opposite to the positive polarity grayscale signal held in the previous frame, so the timing before selecting the gate voltage G0 during the selection period of the gate voltage G0. Thus, the positive common potential applied to the common voltage line C0 is inverted to the negative common potential. Therefore, the AC cycle of the common potential applied to the common voltage line 600 is a frame cycle Tf as shown in FIG. Further, as in the past, the signal output circuit 100 outputs the negative gradation signal corresponding to the even-numbered display pixels P00, P02, P04,... Of the 0th horizontal line to the corresponding drain lines D0, D2,. After being output to D4,... And a desired negative polarity gradation signal is applied, the gate line G0 is turned off (Low level) and holds the written gradation signal for one frame period. Next, when the gate ON voltage is applied to the gate line G1, the odd-numbered display pixels (P01, P03, P05,...) Of the 0th horizontal line and the even-numbered display pixels (P10, P1 of the first horizontal line). P12, P14,...) Are selected. In order to write a negative gradation signal in the 0th horizontal line, a negative common potential is continuously applied to the common voltage line C0. Further, in order to write a positive polarity gradation signal to the first horizontal line, a positive common potential having an inverted polarity is applied to the common voltage line C1 corresponding to the first horizontal line. The inversion timing at this time is the same as the timing described above. Then, the signal output circuit 100 has negative electrodes corresponding to the display pixels connected to the drain lines D1, D3, D5,... Connected to the odd-numbered display pixels (P01, P03, P05,...) Of the 0th horizontal line. A sex tone signal is output. At the same time, the positive tone signal corresponding to each display pixel is applied to the drain lines D0, D2, D4,... Connected to the even-numbered display pixels (P10, P12, P14,...) Of the first horizontal line. Output. At the stage where a desired positive polarity gradation signal or negative polarity gradation signal is written to each display pixel, the gate line G1 becomes OFF level and enters a holding state. Next, when the gate ON voltage is applied to the gate line G2, the odd-numbered display pixels (P11, P13, P15,...) Of the first horizontal line and the even-numbered display pixels (P20, P2 of the second horizontal line). P22, P24,...) Are selected. In order to write the positive polarity gradation signal to the first horizontal line, the positive polarity common potential is applied to the common line C1 as before. On the other hand, in order to write a negative gradation signal to the second horizontal line, a negative common potential is applied to the common line C2 corresponding to the second horizontal line. Here, the timing of alternating current is also as described above. The signal output circuit 100 has positive electrodes corresponding to the display pixels connected to the drain lines D1, D3, D5,... Connected to the odd-numbered display pixels (P11, P13, P15,...) Of the first horizontal line. A sex tone signal is output. At the same time, the negative gradation signal corresponding to each display pixel is output to the drain lines D0, D2, D4,... Connected to the even-numbered display pixels (P20, P22, P24,...) Of the second horizontal line. To do. At the stage where a desired positive polarity gradation signal or negative polarity gradation signal is written to each display pixel, the gate line G2 becomes OFF level and enters a holding state. Therefore, by inverting the polarity of the common potential applied to the common voltage line 600 at the frame period, the polarity of the gradation signal held in each display pixel can be changed to AC.
[0027]
As described above, in the first embodiment of the present invention, among the display pixels of one horizontal line, the gate lines that select even-numbered display pixels and the gates that select odd-numbered display pixels. The lines are separated, and half of the gray signal is determined to be held in the first half of the two horizontal periods, and the remaining half of the gray signal is determined to be held in the second half of the horizontal period. By writing to all display pixels, the load on each common voltage line in one horizontal period can be halved compared to the conventional method. Increases speed. Therefore, this makes it possible to increase the definition, size, and image quality of the liquid crystal display panel.
[0028]
In the first embodiment of the present invention, the MOS-TFT which is the switching element of the display pixel portion may be formed of amorphous Si or low temperature polySi.
[0029]
In the first embodiment of the present invention, the switching element 801 is described as an nMOS-TFT. However, a pMOS-TFT which is another switching element may be used.
[0030]
Furthermore, in the first embodiment of the present invention, the signal output circuit 100, the gate scanning drive circuit 300, and the common drive circuit 500 can be configured by an external LSI chip, and are also configured by low-temperature polySi TFTs. Can be built in a liquid crystal panel by being formed on a substrate on which a pixel portion is formed. Further, a hybrid system is possible in which only the signal output circuit 100 is an external LSI, and the other gate scanning drive circuit 300 and common drive circuit 500 are built in the liquid crystal panel using low-temperature polySi. Further, the low-temperature polySi circuit built in the liquid crystal display panel may have a pMOS single channel, an nMOS single channel, or a cMOS configuration.
[0031]
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment of the present invention is a case where RGB time division driving is performed using the first embodiment of the present invention.
[0032]
FIG. 3 is a diagram showing a configuration of a liquid crystal display device according to the second embodiment of the present invention. In FIG. 3, a plurality of drain lines 200 (D0, D1, D2, D3, D4, D5,...) Corresponding to the horizontal resolution of the liquid crystal display panel, and a plurality of gates, one more than the vertical resolution of the liquid crystal display device. Lines 400 (G0, G1, G2, G3,...) Are arranged to intersect. A plurality of common voltage lines 600 (C0, C1, C2,...) Corresponding to the vertical resolution are arranged in parallel with the gate line 400. For example, in the case of a color display panel whose resolution of the liquid crystal display panel is XGA (1024 × RGB × 768), the drain line 200 is 1024 × 3, the gate line 400 is 768 + 1, and the common voltage line 600 is 768. Be placed. The signal output circuit 100 outputs a gradation signal corresponding to display data transferred from the outside to the liquid crystal display device to the signal line 101 (DR0, DR1,...). Each signal line 101 is connected to each time division switch 701, 702, and 703 included in the time division switch group 700, and the other end of each time division switch has three adjacent drain lines 200 (D0, D1). , D2, or D3, D4, D5, or ...). 3 is a controller of the time division switch group 700, and outputs a control signal 901 for controlling the time division switch. The time division switch 701 is controlled by the SA of the control signal 901. When the time division switch 701 is selected, the signal lines DR0, DR1,... And the drain lines D0, D3,. Can be transferred to the display pixel 800. Similarly, the time division switch 702 is controlled by the control signal SB, and the time division switch 703 is controlled by the control signal SC, and connects each signal line DR and the drain line D in the selected state. The gate scan driving circuit 300 sequentially drives each gate line 400. The common drive circuit 500 drives each common voltage line 600. Here, the signal output circuit 100 includes a gradation signal (positive gradation signal) having a higher potential than the potential (common potential) of the common voltage line 600 and a gradation signal (negative electrode) having a lower potential than the common potential. Sexual gradation signal) and output in a horizontal cycle. The gate scan driving circuit 300 scans all the gate lines 400 by selecting one horizontal line in one horizontal period and sequentially repeating this. Further, the common drive circuit 500 drives each common voltage line 600 independently, converts the positive common potential and the negative common potential into alternating currents in a frame cycle, and outputs them.
[0033]
Display pixels 800 (P00, P01,..., P10, P11,..., P20, P21,...) Are arranged on the matrix near the intersection where the drain line 200 and the gate line 400 are arranged to intersect. One display pixel 800 includes a switching element 801 and a liquid crystal capacitor 802. Although not shown here, a storage capacitor is also configured to suppress a change in potential held in the liquid crystal capacitor 802 in one frame period. Here, a case where the switching element 801 included in the display pixel 800 is a TFT made of an nMOS will be described. The drain terminal of each switching element 801 is connected to the drain line 200, the source terminal is connected to the other end of the liquid crystal capacitor 802 whose one end is connected to the common voltage line 600, and the gate ON voltage supplied from the gate line is When applied to the gate terminal and the switching element is turned on, the gradation signal held in the capacity of the drain line 200 can be charged to the liquid crystal capacity.
[0034]
In the second embodiment of the present invention, three adjacent display pixels among display pixels (Pn0, Pn1, Pn2, Pn3, Pn4, Pn5,...) (N = 0, 1, 2,...) Of one horizontal line. As one group, the gate terminals of the switching elements included in the display pixels of the adjacent group are connected to different gate lines. In the case of this description, the gate terminals of the switching elements included in a certain display pixel group (Pn0, Pn1, Pn2)... Are connected to the gate line Gn (n = 0, 1, 2, 3,. The gate terminals of the switching elements included in the display pixel groups (Pn3, Pn4, Pn5)... Are connected to the gate line Gn + 1 (n = 0, 1, 2, 3,...). With this arrangement, when the gate ON voltage is applied to the gate line Gn + 1, the display pixels selected in the nth horizontal line are half of the display pixels included in one horizontal line, so the load on the common voltage line Cn is Compared to conventional line-sequential driving, it is about half. In addition, since the display pixels of the (n + 1) th horizontal line selected simultaneously from the gate line Gn + 1 are also half of the display pixels included in one horizontal line, the load on the common voltage line Cn + 1 is also about half that of the conventional line sequential drive. become. Therefore, since the load capacity of each common voltage line is half that of the conventional one, the time constant is also approximately half, and therefore the convergence time of the common voltage supplied from the common voltage line is also approximately even in a high-definition and large-screen liquid crystal display device. Nearly half shortened. In the description of the second embodiment of the present invention, the above configuration will be described. However, as a display pixel connection method, in addition to the above, display pixels of one horizontal line (Pn0, Pn1, Pn2, Pn3, Pn4, Pn5, ...) (n = 0, 1, 2,...), The gate terminals of the switching elements included in the display pixel group (Pn3, Pn4, Pn5)... Are connected to the gate line Gn (n = 0, 1, 2, 3,. ..) And the gate terminals of the switching elements included in the display pixel group (Pn0, Pn1, Pn2)... May be connected to the gate line Gn + 1 (n = 0, 1, 2, 3,...). Even in this arrangement, the load on the common voltage lines Cn and Cn + 1 corresponding to the n-th horizontal line and the (n + 1) -th horizontal line selected by the gate line Gn + 1 is about half that of the conventional line-sequential driving.
[0035]
The operation of the liquid crystal display device according to the second embodiment of the present invention will be described above. Since the operations of the gate scanning drive circuit 300 and the common drive circuit 500 in the second embodiment of the present invention are the same as those in the first embodiment of the present invention, a description thereof will be omitted. Therefore, in the timing chart of FIG. 4, operations of the signal output circuit 100, the time division switch group 700, and the controller 900 in the second embodiment of the present invention will be described.
[0036]
In FIG. 4, Th is one horizontal period. G0, G1,... Are drive waveforms of the gate lines 400 that are sequentially driven by the gate scan drive circuit 300. A gate ON voltage (Hi voltage) is sequentially applied to each gate line G0, G1,... By the gate scanning drive circuit 300 every horizontal period Th. The period during which each gate line is applied with the gate ON voltage is within one horizontal period Th. Further, one horizontal period Th is time-divided into three periods, and the signal lines DR0, DR1,... Are connected to the drain lines D0, D3,. . The signal lines DR0, DR1,... And the drain lines D1, D4,... Are connected by selecting the control signal SB within the next period Tb. The signal lines DR0, DR1,... And the drain lines D2, D5,... Are connected by selecting the control signal SC within the last period Tc. Thus, it is possible to supply the grayscale signal supplied from the signal line 101 to the three drain lines D0, D1, and D2 adjacent in one horizontal period in a time division manner.
[0037]
The operation when writing the positive display signal to the 0th horizontal line in the second embodiment of the present invention will be described below. First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0, and turns on the switching elements of the display pixel groups (P00, P01, P02) of the 0th horizontal line connected to the gate line G0. And The common driving circuit 500 applies a positive common potential (Low level) for writing a positive gradation signal to the liquid crystal capacitor to the common voltage line C0 corresponding to the 0th horizontal line. In the first period Ta time-divided into three, the time-division switch 701 in which the positive polarity gradation signal corresponding to the display pixel P00 output from the signal output circuit 100 to the signal line DR0 is selected by the control signal SA. The voltage is applied to the liquid crystal capacitance of the display pixel P00 through the drain line D0. Next, in the period Tb, the positive polarity gradation signal corresponding to the display pixel P01 output from the signal output circuit 100 to the signal line DR0 is supplied to the time division switch 702 and the drain line D1 selected by the control signal SB. Through the liquid crystal capacitor of the display pixel P01. Then, in the last period Tc, the positive gray scale signal corresponding to the display pixel P02 output from the signal output circuit 100 to the signal line DR0 is selected by the time division switch 703 and the drain line D2 that are selected by the control signal SC. Is applied to the liquid crystal capacitance of the display pixel P02. As described above, after applying desired gradation signals to three adjacent display pixel groups to set the holding state, the gate line G0 is turned off (low level) and written for one frame period. Holds the gradation signal.
[0038]
Next, when the gate ON voltage is applied to the gate line G1, the other display pixel group (P03, P04, P05) of the 0th horizontal line and the display pixel group (P10, P11,. P12) is selected. In order to write the positive polarity gradation signal to the 0th horizontal line, the positive common potential is applied to the common voltage line C0 by the common drive circuit 500 as before. In addition, as described in the first embodiment of the present invention, the negative gradation signal is written to the first horizontal line, and therefore, the common voltage line C1 corresponding to the first horizontal line has a negative common potential ( Hi level) is applied. Then, in the first period Ta that is time-divided into three horizontal periods, the positive polarity gradation signal corresponding to the display pixel P03 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SA. This is applied to the liquid crystal capacitance of the display pixel P03 through the time division switch 701 and the drain line D3. Next, in the period Tb, the positive polarity gradation signal corresponding to the display pixel P04 output from the signal output circuit 100 to the signal line DR1 is supplied to the time division switch 702 and the drain line D4 that are selected by the control signal SB. Through the liquid crystal capacitor of the display pixel P04. In the last period Tc, the positive gray scale signal corresponding to the display pixel P05 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SC, and the time division switch 703 and the drain line D5 are selected. Is applied to the liquid crystal capacitance of the display pixel P05.
[0039]
Thus, after applying a desired gradation signal to each of the other display pixel groups to bring them into the holding state, the gate line G1 is turned off (Low level). In the meantime, the negative gradation signal is similarly applied to the display pixel groups (P10, P11, P12)... Of the first horizontal line which are also selected by the gate line G1. Accordingly, the positive grayscale signal is held in all the display pixels on the 0th horizontal line through the two horizontal periods of the gate lines G0 and G1 as described above.
[0040]
In the second embodiment of the present invention, another time division driving method will be described with reference to FIG. In FIG. 5, Th is one horizontal period. G0, G1,... Are drive waveforms of the gate lines 400 that are sequentially driven by the gate scan drive circuit 300. A gate ON voltage (Hi voltage) is sequentially applied to each gate line G0, G1,... By the gate scanning drive circuit 300 every horizontal period Th. The period during which each gate line is applied with the gate ON voltage is within one horizontal period Th. Further, one horizontal period Th is divided into three periods Ta, Tb, and Tc. The signal lines DR0, DR1,... Are connected to the drain lines (D0, D1, D2) and (D3, D4, D5) by selecting all the control signals SA, SB, and SC within the first period Ta. The time division switch 701 is turned off by setting the control signal SA to the OFF level within this Ta period, and the signal lines DR0, DR1 and the drain lines D0, D3 are disconnected. The control signals SB and SC are continuously selected within the next period Tb, and the control signal SB is set to the OFF level during this Tb period, thereby setting the time division switch 702 to the OFF state and the signal lines DR0, DR1 and drain lines D1 and D4 are disconnected. The control signal SC is continuously selected in Tc, which is the last period, and the control signal SC is set to the OFF level within this Tc period, so that the time division switch 703 is turned off, and the signal lines DR0, DR1 and The drain lines D2 and D5 are disconnected.
[0041]
The operation when writing the positive display signal to the 0th horizontal line in the second embodiment of the present invention will be described below. First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0, and turns on the switching elements of the display pixel groups (P00, P01, P02) of the 0th horizontal line connected to the gate line G0. And The common driving circuit 500 applies a positive common potential (Low level) for writing a positive gradation signal to the liquid crystal capacitor to the common voltage line C0 corresponding to the 0th horizontal line.
[0042]
In the first period Ta time-divided into three, the time-division switch 701 in which the positive polarity gradation signal corresponding to the display pixel P00 output from the signal output circuit 100 to the signal line DR0 is selected by the control signal SA. The voltage is applied to the liquid crystal capacitance of the display pixel P00 through the drain line D0. Next, in the period Tb, the positive polarity gradation signal corresponding to the display pixel P01 output from the signal output circuit 100 to the signal line DR0 is supplied to the time division switch 702 and the drain line D1 selected by the control signal SB. Through the liquid crystal capacitor of the display pixel P01. Then, in the last period Tc, the positive gray scale signal corresponding to the display pixel P02 output from the signal output circuit 100 to the signal line DR0 is selected by the time division switch 703 and the drain line D2 that are selected by the control signal SC. Is applied to the liquid crystal capacitance of the display pixel P02. As described above, after applying desired gradation signals to three adjacent display pixel groups to set the holding state, the gate line G0 is turned off (low level) and written for one frame period. Holds the gradation signal.
[0043]
Next, when the gate ON voltage is applied to the gate line G1, the other display pixel group (P03, P04, P05) of the 0th horizontal line and the display pixel group (P10, P11,. P12) is selected. In order to write the positive polarity gradation signal to the 0th horizontal line, the positive common potential is applied to the common voltage line C0 by the common drive circuit 500 as before. In addition, as described in the first embodiment of the present invention, the negative gradation signal is written to the first horizontal line, and therefore, the common voltage line C1 corresponding to the first horizontal line has a negative common potential ( Hi level) is applied. Then, in the first period Ta that is time-divided into three horizontal periods, the positive polarity gradation signal corresponding to the display pixel P03 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SA. This is applied to the liquid crystal capacitance of the display pixel P03 through the time division switch 701 and the drain line D3. Next, in the period Tb, the positive polarity gradation signal corresponding to the display pixel P04 output from the signal output circuit 100 to the signal line DR1 is supplied to the time division switch 702 and the drain line D4 that are selected by the control signal SB. Through the liquid crystal capacitor of the display pixel P04. In the last period Tc, the positive gray scale signal corresponding to the display pixel P05 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SC, and the time division switch 703 and the drain line D5 are selected. Is applied to the liquid crystal capacitance of the display pixel P05.
[0044]
Thus, after applying a desired gradation signal to each of the other display pixel groups to bring them into the holding state, the gate line G1 is turned off (Low level). In the meantime, the negative gradation signal is similarly applied to the display pixel groups (P10, P11, P12)... Of the first horizontal line which are also selected by the gate line G1. Accordingly, the positive grayscale signal is held in all the display pixels on the 0th horizontal line through the two horizontal periods of the gate lines G0 and G1 as described above.
[0045]
In the second embodiment of the present invention, another time-division driving method will be described with reference to FIG. In FIG. 6, Th is one horizontal period. G0, G1,... Are drive waveforms of the gate lines 400 that are sequentially driven by the gate scan drive circuit 300. A gate ON voltage (Hi voltage) is sequentially applied to each gate line G0, G1,... By the gate scanning drive circuit 300 every horizontal period Th. The period during which each gate line is applied with the gate ON voltage is within one horizontal period Th. Further, one horizontal period Th is divided into three periods Ta, Tb, and Tc. Within the first period Ta, the control signals SA, SB and SC are all selected only during the Tp period which is the precharge period, and the drain lines (D0, D1, D2) connected to the signal lines DR0, DR1,. , (D3, D4, D5) are precharged to a certain constant potential. After the precharge period Tp, the remaining SB and SC are turned off, and the gradation signal output by the signal output circuit 100 is written to the drain lines D0, D3,... Via the signal lines DR0, DR1,. The signal lines DR0, DR1,... And the drain lines D1, D4,... Are connected by selecting only the control signal SB within the next period Tb. The signal lines DR0, DR1,... And the drain lines D2, D5,... Are connected by selecting the control signal SC within the last period Tc. As a result, it is possible to supply the grayscale signal supplied from the signal line 101 to the three drain lines D0, D1, and D2 adjacent within one horizontal period in a time-sharing manner, and without changing the panel configuration. It is possible to precharge.
[0046]
The operation when writing the positive display signal to the 0th horizontal line in the second embodiment of the present invention will be described below. First, the gate scan driving circuit 300 applies a gate ON voltage to the gate line G0, and turns on the switching elements of the display pixel groups (P00, P01, P02) of the 0th horizontal line connected to the gate line G0. And The common driving circuit 500 applies a positive common potential (Low level) for writing a positive gradation signal to the liquid crystal capacitor to the common voltage line C0 corresponding to the 0th horizontal line. During the precharge period, the drain lines D0, D1, and D2 are precharged toward the positive tone signal corresponding to P00 output from the signal line DR0 by the signal output circuit 100. After the precharge period, the control signal SA Thus, a desired gradation signal is applied to the liquid crystal capacitance of the display pixel P00 via the time division switch 701 and the drain line D0 that are in the selected state. Next, in the period Tb, the positive polarity gradation signal corresponding to the display pixel P01 output from the signal output circuit 100 to the signal line DR0 is supplied to the time division switch 702 and the drain line D1 selected by the control signal SB. Through the liquid crystal capacitor of the display pixel P01. Then, in the last period Tc, the positive gray scale signal corresponding to the display pixel P02 output from the signal output circuit 100 to the signal line DR0 is selected by the time division switch 703 and the drain line D2 that are selected by the control signal SC. Is applied to the liquid crystal capacitance of the display pixel P02. As described above, after applying desired gradation signals to three adjacent display pixel groups to set the holding state, the gate line G0 is turned off (low level) and written for one frame period. Holds the gradation signal. Next, when the gate ON voltage is applied to the gate line G1, the other display pixel group (P03, P04, P05) of the 0th horizontal line and the display pixel group (P10, P11,. P12) is selected. In order to write the positive polarity gradation signal to the 0th horizontal line, the positive common potential is applied to the common voltage line C0 by the common drive circuit 500 as before. In addition, as described in the first embodiment of the present invention, the negative gradation signal is written to the first horizontal line, and therefore, the common voltage line C1 corresponding to the first horizontal line has a negative common potential ( Hi level) is applied. In the precharge period, the drain lines D3, D4, and D5 are precharged toward the negative gradation signal corresponding to P03 output from the signal output circuit 100 to DR1, and after the precharge period, the control signal SA Thus, a desired gradation signal is applied to the liquid crystal capacitance of the display pixel P03 via the time division switch 701 and the drain line D3 which are in the selected state. Next, in the period Tb, the positive polarity gradation signal corresponding to the display pixel P04 output from the signal output circuit 100 to the signal line DR1 is supplied to the time division switch 702 and the drain line D4 that are selected by the control signal SB. Through the liquid crystal capacitor of the display pixel P04. In the last period Tc, the positive gray scale signal corresponding to the display pixel P05 output from the signal output circuit 100 to the signal line DR1 is selected by the control signal SC, and the time division switch 703 and the drain line D5 are selected. Is applied to the liquid crystal capacitance of the display pixel P05.
[0047]
Thus, after applying a desired gradation signal to each of the other display pixel groups to bring them into the holding state, the gate line G1 is turned off (Low level). In the meantime, the negative gradation signal is similarly applied to the display pixel groups (P10, P11, P12)... Of the first horizontal line which are also selected by the gate line G1. Accordingly, the positive grayscale signal is held in all the display pixels on the 0th horizontal line through the two horizontal periods of the gate lines G0 and G1 as described above.
[0048]
As described above, in the second embodiment of the present invention, the display pixels included in one horizontal line are grouped into three adjacent display pixels, and the adjacent display pixel groups are selected by different gate lines. In the first half of the two horizontal periods, a grayscale signal is applied to a display pixel group in a time division manner using a time division switch, and the other display is performed in the second horizontal period. By applying a grayscale signal in a time division manner using a time division switch to a pixel group, writing to all display pixels on one horizontal line can be performed, thereby reducing the load on each common voltage line in one horizontal period. Since it can be reduced to about half of the conventional method, the writing speed of the common potential and the gradation signal is faster than the conventional method. Therefore, this makes it possible to increase the definition, size, and image quality of the liquid crystal display panel.
[0049]
In the second embodiment of the present invention, the MOS-TFT which is the switching element of the display pixel portion may be formed of amorphous Si or low temperature polySi.
[0050]
Further, in the second embodiment of the present invention, the timing at which the common potential is changed to the alternating current is as described in the first embodiment of the present invention.
[0051]
In the second embodiment of the present invention, the switching element 801 is described as an nMOS-TFT, but it may be a pMOS-TFT or the like which is another switching element.
[0052]
Further, in the second embodiment of the present invention, the signal output circuit 100, the gate scanning drive circuit 300, the time division switch group 700, and the common drive circuit 500 can be configured by an external LSI chip, and the low temperature polySi. It is also possible to incorporate a circuit constituted by TFTs made in the above in a liquid crystal panel by simultaneously forming a circuit on a substrate constituting a display pixel portion. Further, a hybrid system in which only the signal output circuit 100 is an external LSI and the other gate scanning drive circuit 300, the time division switch group 700, and the common drive circuit 500 are built in the liquid crystal panel using low-temperature polySi is also possible. is there. Further, the low-temperature polySi circuit built in the liquid crystal display panel may have a pMOS single channel, an nMOS single channel, or a cMOS configuration.
[0053]
Further, in the second embodiment of the present invention, when the signal output circuit 100 is an external IC, since it is time-division driving, the number of output terminals can be reduced, so that cost reduction is expected. Even when the signal output circuit 100 is built in, since the time division drive is used, the number of DAC circuits and data latch circuits can be reduced, so that the circuit can be made smaller (the frame is narrowed).
[0054]
In addition, although the RGB time division driving is described as an example for the second embodiment of the present invention, the number of divisions is not limited to this and may be divided by an arbitrary number n. In this case, according to the division number n, the number of drain lines D corresponding to the display signal line DR is also n, the control signal of the time division switch is n (or n × 2), and the division period is also the same. The signal output circuit 100 sequentially outputs the grayscale signals corresponding to the display pixels and drain lines that are changed according to the voltage and are held in the voltage holding state in each selection period.
[0055]
Further, the arrangement of the RGB color pixels in the second embodiment of the present invention is not limited to this. Similarly, the order of the pixel electrodes that are held in each selection period and the color pixels corresponding to the drain lines is not limited.
[0056]
Hereinafter, a third embodiment of the present invention will be described with reference to FIG.
[0057]
The third embodiment of the present invention is an information device including the liquid crystal display device described in the first to second embodiments of the present invention. The information device according to the third embodiment of the present invention is, for example, a computer, as shown in the configuration diagram of the information device including the liquid crystal display device according to the third embodiment of the present invention shown in FIG. The main components of the information device 1000 are a liquid crystal display device 1001, a central processing unit 1002, an input device 1003, a storage device 1004, an output device 1005, and a power supply circuit 1006. The central processing unit 1002 serves as a central control and performs calculation, logic and execution decisions. Reference numeral 1007 denotes a system bus, which transmits signals such as a central processing unit, an input device, an output device, and a storage device. The storage device 1004 is used for storing instructions and data. The input device 1003 is for inputting information to an information device, and the input information may be data or a program. The output device 1005 outputs information from the inside of the information device to the outside world, and writes the information to a printer or stores it in an auxiliary storage device such as a magnetic tape or a magnetic disk. The output device 1005 outputs a digital I / F signal of the display device, for example, a display data signal and a horizontal synchronization signal that becomes effective once in one horizontal period, and once in one frame period. A signal including a vertical synchronizing signal, a clock signal, a display timing signal indicating a range of effective display data, and the like that are valid at a rate of 1 is output to the liquid crystal display device 1001 which is a display device. The power supply circuit 1006 supplies power to the liquid crystal display device 1001 and other components that require the power supply of the information device 1000. The power supply circuit 1006 generates and outputs a gradation reference voltage required by the liquid crystal display device 1001. By using the liquid crystal display device 1001 described in the first embodiment to the second embodiment of the present invention, an information device 1000 having a display device with a large screen, high definition, and high image quality can be realized.
[0058]
Among the display pixels of one horizontal line, the gate line that selects the even-numbered display pixel and the gate line that selects the odd-numbered display pixel are separated, and the first half of the two horizontal periods By confirming the holding of half of the gradation signals and confirming the holding of the remaining half of the gradation signals in the second half horizontal period, writing to all the display pixels on one horizontal line results in 1 Since the load on each common line in the horizontal period can be halved compared to the conventional method, the writing speed of the common potential and the gradation signal is faster than the conventional method. Therefore, this makes it possible to increase the definition, size, and image quality of the liquid crystal display panel.
[0059]
In addition, when the signal output circuit is an external LSI by using time-division driving in combination, the number of LSI output terminals can be reduced, so that cost reduction is expected. Even when a signal output circuit is built in, the time division drive is used, so that the number of DAC circuits and data latch circuits can be reduced, so that the circuit scale can be reduced (the frame size is reduced).
[0060]
【The invention's effect】
According to the present invention, there is an effect that display unevenness such as lateral smear is reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.
FIG. 2 is a voltage waveform and timing chart according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.
FIG. 4 is a voltage waveform and timing chart according to a second embodiment of the present invention.
FIG. 5 is a voltage waveform and timing chart according to the second embodiment of the present invention.
FIG. 6 is a voltage waveform and timing chart according to the second embodiment of the present invention.
FIG. 7 is a block diagram illustrating a configuration of an information device including a liquid crystal display device according to a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Signal output circuit, 101 ... Signal line, 200 ... Drain line, 300 ... Gate scanning drive circuit, 400 ... Gate line, 500 ... Common drive circuit, 600 ... Common line, 700 ... Time division switch group, 701 ... Time division Switch 702 Time-division switch 703 Time-division switch 800 Display pixel 801 Switching element 802 Liquid crystal capacitor 900 Controller 901 Control signal 1000 Information device 1001 Liquid crystal display device 1002 ... Central processing unit, 1003 ... Input device, 1004 ... Storage device, 1005 ... Output device, 1006 ... Power supply circuit, 1007 ... System bus.

Claims (5)

  A wiring portion including a plurality of drain lines, a plurality of gate lines orthogonal to the drain lines, and a plurality of common electrode lines substantially parallel to the gate lines; the drain lines and the gate lines; A switching element formed in the vicinity of the intersection of the switching element, a pixel electrode connected to the output terminal of the switching element, a common electrode facing the pixel electrode and connected to the common electrode line, and a storage capacitor An array substrate including a pixel portion configured; a counter substrate disposed opposite to the array substrate; a liquid crystal layer sandwiched between the array substrate and the counter substrate; and the array substrate and the counter substrate. A display panel composed of two polarizing plates installed on the outside,
  A gate scan driving circuit for sequentially scanning the gate lines every horizontal period;
  In a display device composed of a common electrode drive circuit that is driven independently with respect to the common electrode line,
  A time division switch capable of arbitrarily selecting a drain line from the plurality of drain lines according to a predetermined number of time divisions;
  A plurality of control signal lines for controlling selection and non-selection of the time-division switch;
  A plurality of gradation signal lines for propagating gradation signals to the plurality of time division switches;
  A signal output circuit for outputting the gradation signal corresponding to display data from the output terminal to the gradation signal line in a time series corresponding to a predetermined number of time divisions;
  A plurality of pixel portions corresponding to the predetermined time division number are alternately connected to the two gate lines adjacent to the pixel portion constituting one horizontal line connected to one common electrode line. A pixel array,
  In a certain horizontal period, when the gate scan driving circuit selects one of the two gate lines,
  By applying the gradation signal propagated by the gradation signal line through the time division switch to one or a plurality of the drain lines selected by the time division switch, the selection state is obtained. The gradation signal is sequentially applied to the pixel electrodes of the plurality of pixel portions corresponding to the predetermined time division number, and the gradation signal of the pixel electrode and the common electrode driving circuit are applied to the common electrode. The direction of the liquid crystal is controlled by the electric field generated by the electrode voltage,
  In the horizontal period next to the horizontal period, when the gate scan driving circuit selects the other of the two gate lines,
  The gradation signal propagated by the gradation signal line is sequentially applied to one or a plurality of the drain lines selected by the time division switch via the time division switch. A grayscale signal is applied to pixel electrodes of a plurality of pixel portions corresponding to the predetermined number of time divisions in a state, and the grayscale signal of the pixel electrode and the common electrode driving circuit are applied to the common electrode By controlling the direction of the liquid crystal with the electric field generated by the electrode voltage, the liquid crystal of all the pixel portions constituting one horizontal line connected to the one common electrode line is activated,
  In the first selection period divided by the predetermined time division number, the time division switch selects all of the plurality of drain lines, and the grayscale signal is supplied to the plurality of drain lines via the time division switch. Applied,
  From the state in which the selected state of the plurality of drain lines is maintained, in the remaining selection periods divided by the predetermined number of time divisions, one drain line is sequentially unselected, so that the drain line Gradation signals are held in order, and the liquid crystal cells in all the pixel portions on the gate line in the selected state are activated,
  In addition, the signal output circuit outputs a grayscale signal corresponding to a pixel portion which is in a holding state in each selection period in time series according to the predetermined time division number.   The display device according to claim 1,
  The signal output circuit outputs gradation signals having different polarities from adjacent output terminals,
  The common electrode driving circuit is configured to select a gate line that is selected first among two gate lines adjacent to a pixel portion that constitutes one horizontal line connected to the one common electrode line. A display device, wherein the polarity of a common electrode voltage applied to the common electrode line is changed before the selection period. The display device according to claim 1,
In the case where the display unit forms one pixel with three pixels of R (red), G (green), and B (blue),
The display device according to claim 1, wherein the number of time divisions by the time division switch is three time divisions corresponding to R, G, and B.   The display device according to claim 1,
  The display device, wherein the gate scanning drive circuit, the common electrode drive circuit, the time division switch, the switching element, and the like are configured by thin film transistors using poly-Si on the array substrate.   A central processing unit that acts as a central control, performs computation, logic, and execution decisions, and transmits signals to and from input devices, output devices, and storage devices;
  The storage device used for storing instructions and data;
  The input device for inputting information to an information device;
  In the output device for outputting information from the inside to the outside of the information device and further outputting a display signal
  In the information device including the display device configured,
  The display device according to claim 1, wherein the display device is a display device according to claim 1.

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