JP5108680B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device capable of performing source block inversion driving.

  An active matrix type liquid crystal display device has a plurality of pixel electrodes arranged in a matrix, a gate line (scanning line) for each line of the plurality of pixel electrodes, and a data line (source line) for each column. Is arranged. A counter electrode for applying a common voltage is disposed opposite to the plurality of pixel electrodes, and a switch element is disposed between each gate line and each data line. A liquid crystal is sandwiched between the counter electrode and each pixel electrode.

  A liquid crystal driving method in such a liquid crystal display device will be briefly described. A common voltage Vcom is applied to the counter electrode, a gradation voltage Vs corresponding to display data is applied to the data line, and a gate voltage Vg for turning on the switch element is applied to the gate line. The When the gate voltage Vg of a certain gate line is set to a high potential (High), the corresponding switch element is turned ON, and when the gate voltage Vg is set to a low potential (Low) on the gate line, the corresponding switch element is Closed (OFF). When the gate voltage Vg falls, that is, when the switch element is turned off after being turned on, a difference Vs−Vcom between the gradation voltage Vs applied to the data line and the common voltage Vcom applied to the counter electrode. The corresponding picture element electrode and the auxiliary electrode provided auxiliary to the picture element electrode are charged. The charge charged in the pixel electrode and the auxiliary electrode is held until the switch element is turned on next time (until the next frame is driven), and during that time, the charge is filled between the pixel electrode and the counter electrode. Driving liquid crystal.

  Since the liquid crystal has the property that its characteristics deteriorate when a DC voltage is applied, in the above-described driving, in general, driving that reverses the polarity of the voltage applied to the liquid crystal (this is referred to as “liquid crystal Called “AC drive”). As one method of alternating current driving of liquid crystal, a line inversion method (row inversion method) in which the polarity of a voltage applied to the liquid crystal is inverted for each line (gate line) and for each frame is widely adopted. A pixel inversion method (dot inversion method) in which polarity inversion for each column is also added to polarity inversion for each frame and each line.

  In recent years, liquid crystal display devices have become larger in display screen, and accordingly, the conventional AC driving method cannot keep up with the clock speed or the need to improve the display quality of liquid crystal has arisen. . Therefore, many large liquid crystal display devices employ source block inversion (SBR) driving as the liquid crystal driving method.

  SBR drive refers to the polarity of the voltage applied to the liquid crystal, that is, the polarity of the difference Vs−Vcom between the gradation voltage Vs applied to the data line and the common voltage Vcom applied to the counter electrode. This refers to driving that is reversed for each line block consisting of a plurality of lines. Such SBR drive is disclosed in Patent Documents 1-3 as applying interlaced scanning. Among these, in Patent Documents 2 and 3, when interlaced scanning is performed in the order of blocks consisting of a plurality of odd lines to blocks consisting of a plurality of even lines in a certain frame, a plurality of even lines are used in the next frame. A technique is disclosed in which interlaced scanning is performed in the reverse order from a block to a block composed of a plurality of odd lines.

  A driving method in the case where interlaced scanning is applied to SBR driving will be described with reference to FIG. Here, description will be given by taking as an example SBR drive in which polarity inversion is performed in a cycle of 48 horizontal scanning periods (48H) and interlaced scanning (interlace writing) is performed in 96 line blocks.

  First, the gate voltage Vg is applied to the even-numbered gate lines in the order of the second gate line G0002, the fourth gate line G0004,..., The 48th gate line G0048, and the switch elements corresponding to the order are turned on / off. It is turned off. On the other hand, the data line has a gradation voltage Vs corresponding to the video data of the second line, the fourth line,..., The 48th line, and Vs−Vcom is + polarity in accordance with each timing. A gradation voltage Vs is input. The 0th picture element is dummy data.

  At the time of reversal from + polarity to -polarity, a 2H blanking period is inserted into the gate voltage Vg for the 48th gate line, and during this time, gradation corresponding to the video data of the next line (first line) is inserted. A gradation voltage Vs is inputted such that the voltage Vs is such that Vs−Vcom is negative. Note that the video data input in the blanking period (in this case, the video data of the first line) is not output. This blanking period is inserted to remove streaks that occur because the gradation voltage Vs changes slowly during polarity inversion, and after the 2H blanking period, the gradation voltage Vs slowly decreases. It is assumed that the charging voltage Vs−Vcom is sufficiently secured regardless of the change.

  After this blanking period, the gate voltage Vg is applied to the odd-numbered gate lines in the order of the first gate line G0001, the third gate line G0003,..., The 95th gate line G0095. The element is turned on / off. On the other hand, the data line has the gradation voltage Vs corresponding to the video data of the first line, the third line,..., The 95th line, and Vs−Vcom is −polarity in accordance with each timing. A gradation voltage Vs is input.

  Then, when the polarity is inverted from -polarity to + polarity, as a similar streak countermeasure, a blanking period of 2H is inserted into the gate voltage Vg for the 95th gate line, and during that time, the video of the next line (50th line) A gradation voltage Vs corresponding to data and having a polarity of Vs−Vcom is input. After this blanking period, the gate voltage Vg is applied to the even-numbered gate lines in the order of the 50th gate line G0050, the 52nd gate line G0052,..., And the 96th gate line G0096. The element is turned on / off. On the other hand, the data line has a gradation voltage Vs corresponding to the video data of the 50th line, the 52nd line,..., The 96th line, and Vs−Vcom is + polarity in accordance with each timing. A gradation voltage Vs is input.

  In the example of FIG. 9, a 2H blanking period is inserted into the gate voltage Vg for the 36th and 83rd gate lines, and during that time, video data of the next line (the 38th and 85th lines, respectively) is supported. The gradation voltage Vs thus input is input. This blanking period is inserted in order to adjust the waveform of the storage capacity (storage capacity) Cs of the auxiliary electrode in accordance with the 2H blanking period inserted as a streak countermeasure at the time of polarity reversal. The blanking period here is inserted after the input of the video data of the 36th line and the 83rd line, but the insertion position is not limited to this.

  In this way, the interlaced scanning is completed in the 96-line block while the polarity is inverted in the 48H cycle with the blanking period in the middle, and this driving is repeated in the 96-line cycle. In the example of FIG. 9, four blanking periods, that is, an average of 24H blanking periods are required for the 96 line block. Although the case where interlaced scanning is applied has been described, in SBR driving, it is necessary to insert a blanking period regardless of whether interlaced scanning is applied.

  The problem due to the blanking period will be described with reference to FIG. For simplification, FIG. 10 shows the waveform of the gate clock (GCK), which is the timing at which the gate voltage Vg is applied regardless of the target gate line, and the waveform of the gradation voltage Vs applied at that timing. The waveform of the common voltage Vcom is shown.

  In the example of FIG. 10, a 2H blanking period is inserted by keeping the gate voltage Vg at a high potential and not lowering it until 2H has elapsed. At this time, the grayscale voltage Vs input from the data line is applied with + polarity from the previous 2H for timing adjustment with the gate voltage Vg at the time of polarity reversal from −polarity to + polarity, as shown in FIG. Thus, the voltage value is maintained for each picture element of the line for a total period of 3H. This period of 3H is illustrated as the gradation voltage Vs for the 50th line in FIG. 9, and the gradation voltage Vs for the first line is the same only when it is inverted from + polarity to -polarity. Can be discussed.

  During this 3H period, as shown by [i] in FIG. 10, the common voltage Vcom converges to the original potential, and the charging voltage charged to the liquid crystal due to the difference from the gradation voltage Vs also converges to the original potential. . As described above, at the time of writing immediately after the non-writing period, the period after the change of the common voltage Vcom is as long as 3H, and the potential of the common voltage Vcom converges to the original potential, so that it can be charged with the correct charge voltage Vs−Vcom. .

  On the other hand, in the period other than immediately after the blanking period in the SBR drive, the liquid crystal is driven by changing the gate voltage Vg from a high potential to a low potential every 1H while changing the gate line to which the voltage is applied. At this time, the gradation voltage Vs input from the data line is maintained at a voltage value for each pixel of the line for a period of 1H. In FIG. 10, the gradation voltage Vs after the 3H period changes drastically so as to repeat a low potential and a high potential (for example, gradation level 0 representing black and gradation level 255 representing white, respectively). Assumes data to be used.

  In such a period in which the data changes drastically, the common voltage Vcom does not converge to the original potential, and the charging voltage Vs−Vcom does not converge to the original potential, as indicated by [iii] in FIG. Such unconvergence occurs when the impedance of the counter electrode in the liquid crystal panel is high. As described above, at the time of writing except immediately after the non-writing period, the period after the change of the common voltage Vcom is as short as 1H, and the potential of the common voltage Vcom does not converge to the original potential. Therefore, the incorrect charge voltage Vs−Vcom Charged.

Such a difference in charging voltage immediately after the blanking period and other than that, that is, a difference in displacement of the common voltage Vcom from 0 [V] occurs every time the blanking period is inserted. Among them, before and after the blanking period with polarity inversion exemplified in the 48th gate line and the 95th gate line in FIG. 9, when displaying an image of a specific pattern in which data changes drastically as exemplified in FIG. In addition, the data sum for each line (sum of the gradation voltages Vs for each line) may vary in polarity from line to line, that is, a large deviation may occur in the + -drive pattern of AC drive. Will deteriorate.
Japanese Patent Laid-Open No. 11-352938 JP 2000-250486 A JP 2000-250496 A

  As described above, the SBR drive has a problem that the displacement from 0 [V] of the common voltage Vcom applied to the counter electrode changes every time the blanking period is inserted. Since the common voltage Vcom is a reference value on the display of the liquid crystal panel, such a change can cause image quality deterioration. In particular, when displaying an image of a specific pattern, such a change causes image quality deterioration.

  The present invention has been made in view of the above situation, and in source block inversion (SBR) driving, the displacement of the common voltage from 0 [V] changes every time the blanking period is inserted. An object of the present invention is to provide a liquid crystal display device capable of preventing the image quality from being deteriorated between lines whose polarities are reversed when displaying an image of a specific pattern.

In order to solve the above-described problem, a first technical means of the present invention includes a plurality of pixel electrodes arranged in a matrix, and a counter electrode arranged to face the plurality of pixel electrodes. A liquid crystal sandwiched between the counter electrodes for each of the plurality of pixel electrodes, a gate line disposed for each line of the plurality of pixel electrodes, and each of the plurality of pixel electrodes. A data line arranged for each column, a switch element connected between each gate line and each data line, a gate drive circuit for applying a voltage to each gate line, and a display data corresponding to each data line A liquid crystal display device comprising a data driving circuit for applying a gradation voltage and a counter electrode driving circuit for applying a common voltage to the counter electrode, wherein the data writing is performed by the data driving circuit and the counter electrode driving circuit. For each line block consisting of multiple lines according to the order A voltage is applied so that the polarity of the voltage applied to the liquid crystal is reversed, and the gate driving circuit is adjacent to one of the column blocks defined as a block obtained by dividing the plurality of pixel electrodes into a plurality of columns. between the two column blocks, with different gate lines of interest to apply a voltage simultaneously have line voltage application, the gate drive circuit block by a gate for applying a voltage to each gate line for each of the column blocks It has a drive circuit and a control circuit for controlling a drive gate line of each block-specific gate drive circuit .

  According to a second technical means, in the first technical means, the column block is a block in which the plurality of pixel electrodes arranged in a matrix are divided into four or two for every plurality of columns. It is what.

  According to a third technical means, in the first technical means, the column block is a block in which the plurality of pixel electrodes are divided into four for each of a plurality of columns, and the gate driving circuit applies voltage in the first column block. With respect to the target gate line, (1) the voltage application target in the second column block adjacent to the first column block is shifted by one line, and (2) the second adjacent to the second column block. Each gate line is a gate line in which the voltage application target in the three column blocks is shifted by two lines, and (3) the voltage application target in the fourth column block adjacent to the third column block is a gate line shifted by three lines. In addition, voltage application is performed simultaneously.

  According to a fourth technical means, in the first technical means, the column block is a block in which the plurality of picture element electrodes are divided into four for each of a plurality of columns, and the gate driving circuit applies voltage in the first column block. With respect to the target gate line, (1) the voltage application target in the second column block adjacent to the first column block is shifted by two lines, and (2) adjacent to the second column block. Each gate line has a voltage application target in the third column block as a gate line of the same line, and (3) a voltage application target in a fourth column block adjacent to the third column block is a gate line shifted by two lines. In addition, voltage application is performed simultaneously.

  According to a fifth technical means, in the first technical means, the column block is a block obtained by dividing the plurality of pixel electrodes into two for each of a plurality of columns, and the gate driving circuit applies voltage in the first column block. A voltage applied to each gate line is simultaneously applied as a gate line in which the voltage application target in the second column block is shifted by two lines with respect to the target gate line.

A sixth technical means includes any one of the first to fifth technical means, wherein the data driving circuit and the counter electrode driving circuit are arranged so that the polarity is inverted for each liquid crystal in the line block and adjacent lines. A voltage is applied so that the polarity of the first liquid crystal is different between the blocks, or a voltage is applied so that the polarities are the same in the line block and between adjacent line blocks. It is characterized by.

  According to the liquid crystal display device of the present invention, at the time of source block inversion (SBR) driving, the displacement of the common voltage from 0 [V] changes every time the blanking period is inserted, and a specific pattern image is displayed. It is possible to prevent the image quality from deteriorating between the lines whose polarities are reversed.

  FIG. 1 is a diagram showing a configuration example of a liquid crystal panel mounted on a liquid crystal display device according to an embodiment of the present invention, in which 1 is a liquid crystal panel. In the following description, the liquid crystal display device according to the present embodiment will be described with the liquid crystal panel 1 shown in FIG. 1 and description of other components will be omitted. 1. Backlight unit that irradiates light from the back of 1, generation of gate control signal and source control signal (data signal) according to video signal, application of polarity (and application of polarity of common voltage), and timing control thereof The circuit etc. which perform etc. are provided.

  The liquid crystal panel 1 includes a plurality of picture element electrodes P (i, j) arranged in a matrix and counter electrodes 16b, 17b, which are arranged to face the plurality of picture element electrodes P (i, j). 18b, 19b and a TN (Twisted Nematic) type liquid crystal sandwiched between the counter electrodes 16b, 17b, 18b, 19b for each of the plurality of picture element electrodes P (i, j).

  The liquid crystal panel 1 further includes a gate line (scanning line) arranged for each line (each row) of the plurality of picture element electrodes P (i, j) and a plurality of picture element electrodes P (i, j). A pixel electrode and a data line (signal line) arranged for each column (each column) and a pixel electrode based on a signal (gate voltage) connected between each gate line and each data line. And a switch element T (i, j) that opens and closes the data line corresponding to. As the switch element, a switching transistor such as a TFT (Thin Film Transistor) is usually used.

  The liquid crystal panel 1 further includes a gate driving circuit (illustrated by the first to fourth gate drivers 11 to 14) for applying a voltage to each gate line, and data for applying a gradation voltage corresponding to display data to each data line. A driving circuit (illustrated by the source driver 10) and a counter electrode driving circuit (common electrode driving circuit) 15 that applies a common voltage to the counter electrodes 16b, 17b, 18b, and 19b are provided. The counter electrodes 16b, 17b, 18b, and 19b are illustrated separately for the sake of explanation, but may be a single counter electrode as long as a common voltage can be applied.

  The liquid crystal panel 1 of the present invention employs source block inversion (SBR) driving, and is applied to the liquid crystal for each line block composed of a plurality of lines according to the data writing order by the source driver 10 and the common electrode driving circuit 15. The voltage is applied so that the polarity of the applied voltage is reversed. Here, writing data means charging the pixel electrode with a voltage corresponding to the data. In practice, a voltage is applied to the liquid crystal by the pixel electrode P (i, j) and an auxiliary electrode made up of a capacitor provided in an auxiliary manner thereto. In the present invention, an auxiliary electrode voltage supply line (holding capacitor line) may be separately provided for each auxiliary electrode, and the above-described SBR drive may be executed.

  Examples of driving methods of the source driver 10 and the common electrode driving circuit 15 will be given. The input order (transfer order) of the video signals input to the source driver 10 may be changed according to the data writing order, or the output order of the video signals input by the source driver 10 may be changed. Good. The source driver 10 side inverts the polarity of the gradation voltage (the polarity of the source signal) for each data line for each of a plurality of lines according to the data writing order (that is, for each of the plurality of lines in the writing order). A voltage is applied to the pixel electrode. At this time, the common electrode driving circuit 15 side applies a common voltage by inverting the polarity in accordance with the polarity inversion. That is, the common electrode driving circuit 15 may adopt common inversion driving in which a common voltage having the same polarity as the gradation voltage is applied to the counter electrode. The SBR drive by the source driver 10 and the common electrode drive circuit 15 is not limited to this example. For example, the common electrode drive circuit 15 may be driven to supply a constant common voltage.

  Further, as SBR drive applicable in the present invention, the polarity of the first liquid crystal is different between adjacent line blocks so that the polarity is reversed for each liquid crystal in the line block by the source driver 10 and the common electrode drive circuit 15. A voltage may be applied so that the That is, as SBR driving, the dot inversion method is applied to each picture element in the line block, the polarities of the corresponding picture elements are inverted between adjacent blocks, and a certain line block is changed from the first picture element to +,- .., +,-,..., Polarity voltages are applied, the following line block applies the-, +,-, +, ... polarity voltages from the first pixel. Such driving is also possible.

  Further, in the present invention, the SBR drive in which a voltage is applied by the source driver 10 and the common electrode driving circuit 15 so as to have the same polarity in the line block and to make the polarity different between adjacent line blocks is applied. You can also In other words, in the present invention, it is also possible to apply SBR driving in which all are negative in a certain line block and positive in all subsequent line blocks.

  In the present invention, in any SBR drive, interlaced scanning may be employed, and the data writing order may be in accordance with interlaced scanning, or from the normal upper line to the lower line. Driving in which the subsequent order is the data writing order may be employed.

  Thus, the liquid crystal panel 1 is an active matrix type liquid crystal panel in which the switch elements T (i, j) are provided for the individual pixel electrodes P (i, j). Here, i = 1 to m and j = 1 to n. That is, in the liquid crystal panel 1, it is assumed that m × n picture element electrodes P (i, j) are arranged in a matrix of m rows and n columns. Although not shown, in the liquid crystal panel 1, the counter electrodes 16b, 17b, 18b, and 19b are provided on the glass substrate, and the switch element T (i, j), the pixel electrode P (i, j), and the gate Lines and data lines are provided on different glass substrates, and a liquid crystal layer is sandwiched between the substrates. Similarly to a general liquid crystal panel, one picture element electrode may be any one of an R electrode, a G electrode, and a B electrode, and the arrangement of RGB may be determined based on an arbitrary rule. For example, a configuration in which each pixel is divided into two or more sub-pixels, such as one pixel is composed of two rows of R, G, B in one row and G, B, R in the next row. It may be adopted. In this configuration, when each sub-pixel electrode is driven from an individual storage capacitor line, the sub-pixel electrode may be driven so as to adjust the area gradation of the same color picture element (or one pixel).

  As a main feature of the present invention, the gate drive circuit includes two adjacent columns among the column blocks 16 to 19 defined as blocks obtained by dividing the plurality of pixel electrodes P (i, j) into a plurality of columns. Voltage application is performed by changing the gate lines (lines) to which the voltage is applied simultaneously between the blocks. Each of the column blocks 16 to 19 is preferably a block in which a plurality of picture element electrodes P (i, j) are equally divided for each of a plurality of columns, but may be a block that is divided for a substantially equal number of columns. That's fine.

  Here, the column block 16 includes a first liquid crystal group 16a composed of a switch element T (i, j), a picture element electrode P (i, j), and the like. A second liquid crystal group 17a, a third liquid crystal group 18a, and a fourth liquid crystal group 19a. In order to apply the voltage for each of the column blocks 16 to 19 as described above, the gate driving circuit used in the liquid crystal panel 1 includes the first gate driver 11 for the first liquid crystal group 16a and the second gate driver for the second liquid crystal group 17a. It has a gate driver 12, a third gate driver 13 for the third liquid crystal group 18a, and a fourth gate driver 14 for the fourth liquid crystal group 19a. The drive lines of the gate drivers 11 to 14 are controlled by a control circuit (not shown). That is, the gate drive circuit in the liquid crystal panel 1 has a gate drive circuit for each block (respectively) for applying a voltage to each gate line for each column block, as exemplified by the first to fourth gate drivers 11 to 14. In addition, a control circuit for controlling the drive gate line (drive line) of each block-specific gate drive circuit is provided.

  Thus, in the gate drive circuit of the present invention, the display screen is divided into a plurality of columns, and the liquid crystal drive control is performed so as to change the phase of the display pattern for each divided column block. In other words, in the gate drive circuit of the present invention, when driving a certain line, the drive line is not driven as it is for all the lines as they are, but is driven for each video display area corresponding to the divided column block. Try to change.

  As a result, it is possible to prevent the average of the drive patterns from being biased to + or − due to the blanking period inserted when the polarity is reversed, and 0 [V of the common voltage Vcom as described in the related art. The change in the displacement from In the present invention, since the change in displacement of the common voltage Vcom from 0 [V] is improved in the SBR drive, the image quality can be prevented from deteriorating. In particular, it is possible to prevent the image quality from being deteriorated between lines whose polarities are reversed when displaying an image of a specific pattern, and it is possible to display an image with a higher quality image.

  In addition, since the drive method change point added in the present invention only shifts the drive line for each divided column block, the drive system can be dealt with without any significant change. Although FIG. 1 shows an example in which the gate drivers 11 to 14 are provided separately for the column blocks 16 to 19, the gate driving circuit may naturally be configured with one common circuit for the column blocks 16 to 19. In this case, separate gate lines may be wired to the column blocks 16 to 19 so that gate voltages having different phases can be applied to the column blocks 16 to 19. As an alternative method, the gray voltage of the data signal output from the source driver 10 may be set to 0 [V] in a portion corresponding to an unnecessary column block. These application examples of the gate driving circuit can be similarly applied to the following description.

  Hereinafter, the driving method for each column block of the present invention for obtaining the above-described effect will be described with reference to specific specific patterns. Here, as illustrated in FIGS. 1 and 2, a driving example of the gate driving circuit when the column block is a block obtained by dividing a plurality of pixel electrodes P (i, j) into four for each of a plurality of columns will be described.

  FIG. 2 is a diagram schematically showing an example of each video display area corresponding to each column block in the liquid crystal panel of FIG. FIG. 3 is a diagram for explaining an SBR driving method that does not depend on a conventional column block, and shows an example of a specific pattern. 4 to 6 are diagrams for explaining an example of the SBR driving method for each column block according to the present invention with respect to the specific pattern of FIG. FIG. 7 is a diagram showing an example of a waveform immediately after the blanking period in the SBR drive of the present invention, and FIG. 8 is a diagram for explaining a conventional SBR drive method that does not use the column block. It is a figure which shows another example.

  Here, in FIG. 2, the image display areas corresponding to the column blocks 16, 17, 18, and 19 in FIG. 1 among the entire image display areas 20 of the liquid crystal panel 1 are indicated by divided areas I, II, III, and IV, respectively. ing. 3 to 6 and 8 show the pixel data corresponding to these divided regions I to IV. However, FIG. 3 and FIG. 8 show the pixel data in the case of performing the conventional SBR drive, and actually only show the pixel data of each region corresponding to each of the divided regions I to IV. The aspect ratio of the entire video display area 20 is not limited to that shown in the figure.

  As shown in FIG. 2, each of the column blocks 16 to 19 is obtained by dividing the entire video display area 20 of the liquid crystal panel 1 into divided areas I to IV, and the divided areas I to IV are adjacent to each other in that order. .

  The image of the specific pattern illustrated in FIG. 3 is a staggered pattern in which RGB is switched every two horizontal scanning periods (that is, 2H_RGB staggered pattern), and only the pixel data on the 22nd to 29th lines are shown. Each line is shown in the data writing order. Although the 2H_RGB staggered pattern is small as a television image, it can be easily reproduced and sufficiently generated in an output image of a personal computer (PC) or the like, and can be generated by a measuring instrument. Then, the conventional SBR drive (including dot inversion drive) is adopted for the 2H_RGB staggered pattern of FIG. 3, and a + polarity voltage is applied to the liquid crystal in the line block before the 25th line, and blanking (not shown) is performed. Assume that a negative polarity voltage is applied to the liquid crystal in the line blocks after the 26th line after a period (a blanking period with polarity inversion). Since FIG. 3 shows an example in which dot inversion driving is further applied, lines before the 25th line become line blocks where each line starts with + polarity, and lines after the 26th line become each line block where each line starts with -polarity.

  When an attempt is made to display a 2H_RGB staggered pattern by such conventional SBR driving, the average sum of pixel data for each line is +64 for the 22nd and 23rd lines, -64 for the 24th to 27th lines, It becomes +64 in the 28th and 29th lines. Here, the smaller the absolute value of the average value, the higher the degree of convergence of the common voltage Vcom. The average value is completely converged at 0, and the two average values to be compared are opposite in polarity. It means that the average value of is wide. In the conventional SBR drive, as can be seen from the fact that there are as many as 128 pixel data values between the 23rd line and the 24th line and between the 27th line and the 28th line, There is a big difference in each average value. This means that the displacement of the common voltage Vcom from 0 [V] changes greatly every blanking period.

  As described above, in the 2H_RGB staggered pattern of FIG. 3, when the data sum of each line is different and the impedance of the counter electrode in the liquid crystal panel is high, the common voltage Vcom variation cannot be converged during the charging period, and the original voltage Since the liquid crystal applied voltage cannot be written in, a change in the displacement of the common voltage Vcom (a change taking into account the positive or negative of the displacement amount) occurs immediately after and during the blanking period.

  On the other hand, the gate drive circuit of the present invention applies voltage by shifting the phase by one line (by 1H) for each column block, for example. In the four divisions illustrated here, the line changes are 0H, 1H, 2H, and 3H. More specifically, the gate driving circuit is configured to (1) the first column block 16 with respect to the gate line to be applied with voltage in the first column block 16 (with respect to the phase of the voltage applied to the first column block 16). The voltage application target in the second column block 17 adjacent to is a gate line (line line of the line) shifted by one line (one horizontal scanning period), and (2) in the third column block 18 adjacent to the second column block 17 The voltage application target is a gate line shifted by two lines, and (3) the voltage application target in the fourth column block 19 adjacent to the third column block 18 is a gate line shifted by three lines, and voltage is applied to each gate line simultaneously. . Here, the first to fourth column blocks 16 to 19 are driven by the first to fourth gate drivers 11 to 14, respectively.

  Such voltage application will be described with reference to FIGS. When voltage is applied to the 22nd to 25th lines of the divided region I in FIG. 3, a voltage is applied to the 23rd to 26th lines surrounded by a solid line in the divided region II, respectively, A voltage is applied to the surrounded 24th to 27th lines, and a voltage is applied to each of the 25th to 28th lines surrounded by a two-dot chain line in each divided region IV. By such driving, as shown in FIG. 4, the sum of the pixel data becomes equal (the average value is 0) in each of the 22nd to 25th lines. In FIG. 4, it is assumed that the pixel data corresponding to the line number corresponds to the divided area I.

  As another driving example, the gate driving circuit of the present invention applies a voltage so as to repeat shifting the phase by two lines for each column block, for example. In the four divisions exemplified here, the line changes are 0H, 2H, 0H, and 2H. More specifically, the gate drive circuit has (1) a gate line in which the voltage application target in the second column block 17 is shifted by two lines with respect to the gate application target in the first column block 16 ( 2) The voltage application target in the third column block 18 is the gate line of the same line, and (3) The gate line is shifted from the voltage application target in the fourth column block 19 by two lines (that is, the gate of the same line as the second column block 17). As a line), a voltage is simultaneously applied to each gate line. Here, the first to fourth column blocks 16 to 19 are driven by the first to fourth gate drivers 11 to 14, respectively.

  Such voltage application will be described with reference to FIGS. When voltage is applied to the 22nd to 25th lines of the divided area I in FIG. 3, the voltage is applied to the 24th to 27th lines surrounded by the alternate long and short dash line in the divided area II, and the divided areas III are respectively left as they are. A voltage is applied to the 22nd to 25th lines, and a voltage is applied to each of the 24th to 27th lines surrounded by an alternate long and short dash line in each divided region IV. By such driving, as shown in FIG. 5, the sum of the pixel data becomes equal (the average value is 0) in each of the 22nd to 25th lines. In FIG. 5, it is assumed that the pixel data corresponding to the line number is for the divided areas I and III.

  As another driving example, the gate driving circuit of the present invention applies a voltage so as to shift the phase by two lines for each column block, for example. In the four divisions exemplified here, the line changes are 0H, 0H, 2H, and 2H. More specifically, the gate drive circuit is configured such that (1) the voltage application target in the second column block 17 is the gate line of the same line with respect to the voltage application target gate line in the first column block 16, and (2 ) A gate line in which the voltage application target in the third column block 18 is shifted by two lines, and (3) a gate line in which the voltage application target in the fourth column block 19 is shifted by two lines (that is, a gate on the same line as the third column block 18). As a line), a voltage is simultaneously applied to each gate line. Here, the first to fourth column blocks 16 to 19 are driven by the first to fourth gate drivers 11 to 14, respectively. Note that such a drive example is synonymous with setting the line change to 0H and 2H during two-division described later.

  Such voltage application will be described with reference to FIGS. When voltage is applied to the 22nd to 25th lines of the divided region I in FIG. 3, the voltage is applied to the 22nd to 25th lines as they are in the divided region II, and the divided regions III are surrounded by the one-dot chain lines. A voltage is applied to the 24th to 27th lines, and a voltage is applied to each of the 24th to 27th lines surrounded by an alternate long and short dash line in the divided region IV. By such driving, as shown in FIG. 6, the sum of the pixel data becomes equal (the average value is 0) in each of the 22nd to 25th lines. In FIG. 6, it is assumed that the pixel data corresponding to the line number is for divided areas I and II.

  The waveforms immediately after the blanking period in the SBR drive of the present invention as illustrated in FIGS. 4 to 6 have the same data sum for each line, and as a result, there is no change in a specific line. As described above, the common voltage Vcom is sufficiently converged regardless of immediately after the blanking period indicated by [i] or immediately after the blanking period indicated by [ii], and the occurrence of a change in displacement of the common voltage Vcom is suppressed. can do. Therefore, in the SBR drive illustrated in FIGS. 4 to 6, the image quality is not deteriorated even in the specific pattern. In particular, when displaying a still picture or a PC image, the superiority or inferiority of the image quality can be clearly seen, and therefore it is effective to employ the SBR drive of the present invention. In addition, according to the SBR drive of the present invention, the common voltage Vcom can be sufficiently converged without configuring the impedance of the counter electrode to be low, so that the image quality of the image is improved without being limited to the specific pattern. Can do.

  In addition, the SBR drive of the present invention and its effect have been described based on the 2H_RGB staggered pattern of FIG. 3, but the present invention also applies to a red (or green, blue) pattern in increments of 1 dot as illustrated in FIG. It will be beneficial.

  As described above, the column block has been described on the premise that all the pixel electrodes P (i, j) provided are divided into four blocks for each of a plurality of columns. However, in the liquid crystal panel of the present invention, the column block is The present invention can also be applied to a block in which all picture element electrodes P (i, j) provided are divided into two for each of a plurality of columns.

  When the column block is a block in which a plurality of pixel electrodes P (i, j) are divided into two for each of a plurality of columns, the gate drive circuit applies the first to the voltage application target gate line in the first column block. It is preferable to apply a voltage to each gate line at the same time as a gate line in which the voltage application target in the two column block is shifted by two lines. That is, the gate drive circuit may apply a voltage to the column block divided into two so that the change in the line of the other column block is 2H with respect to one column block (0H).

  Further, not limited to two divisions or four divisions, k may be 3 or more in a column block divided into 2k (k is a natural number). However, when k is large, the number of gates to be opened increases accordingly. Of course, when the 2k + 1 divided column block is used, the effect is reduced as compared with the case where the 2k divided column block is used. However, since the voltage of the common electrode converges near 0 [V], it is constant. The effect is obtained.

  As described above, the liquid crystal display device according to the present invention has been described. However, the above-described driving method does not always have to be adopted. For example, it is determined from the video signal whether the above-described driving is necessary, and the necessary frame is determined. Only the above-described driving for each column block may be executed. The driving method of the present invention can also be used in combination with driving in which the polarity of the gradation voltage applied to the data line is inverted for each frame.

It is a figure which shows one structural example of the liquid crystal panel mounted in the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows typically the example of each video display area corresponding to each column block in the liquid crystal panel of FIG. It is a figure for demonstrating the SBR drive method which does not depend on the conventional column block, and is a figure which shows an example of a specific pattern. FIG. 4 is a diagram for explaining an example of an SBR driving method for each column block according to the present invention with respect to the specific pattern of FIG. 3. FIG. 6 is a diagram for explaining another example of the SBR driving method for each column block according to the present invention with respect to the specific pattern of FIG. 3. FIG. 6 is a diagram for explaining another example of the SBR driving method for each column block according to the present invention with respect to the specific pattern of FIG. 3. It is a figure which shows an example of the waveform immediately after the blanking period in the SBR drive of this invention. It is a figure for demonstrating the SBR drive method which does not depend on the conventional column block, and is a figure which shows the other example of a specific pattern. It is a figure for demonstrating an example of the conventional SBR drive. It is a figure which shows an example of the waveform immediately after the blanking period in the conventional SBR drive.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel, 10 ... Source driver, 11 ... 1st gate driver, 12 ... 2nd gate driver, 13 ... 3rd gate driver, 14 ... 4th gate driver, 15 ... Common electrode drive circuit, 16 ... 1st column Block, 16a ... first liquid crystal group, 16b, 17b, 18b, 19b ... counter electrode, 17 ... second column block, 17a ... second liquid crystal group, 18 ... third column block, 18a ... third liquid crystal group, 19 ... Fourth column block, 19a... Fourth liquid crystal group, 20.

Claims (6)

A plurality of picture element electrodes arranged in a matrix, a counter electrode arranged to face the plurality of picture element electrodes, and the plurality of picture element electrodes are sandwiched between the counter electrodes. A liquid crystal; a gate line disposed for each line of the plurality of pixel electrodes; a data line disposed for each column of the plurality of pixel electrodes; a gate line and a data line; A switching element connected between the gate line, a gate driving circuit for applying a voltage to each gate line, a data driving circuit for applying a gradation voltage according to display data to each data line, and a common voltage to the counter electrode. A liquid crystal display device including a counter electrode driving circuit to apply,
A voltage is applied by the data driving circuit and the counter electrode driving circuit so that the polarity of the voltage applied to the liquid crystal is reversed for each line block composed of a plurality of lines according to the data writing order.
The gate driving circuit is configured such that, among column blocks defined as blocks obtained by dividing the plurality of pixel electrodes into a plurality of columns, gate lines to which a voltage is applied simultaneously are different between two adjacent column blocks. not to, have line voltage application,
The gate drive circuit includes a block-specific gate drive circuit that applies a voltage to each gate line for each column block, and a control circuit that controls the drive gate line of each block-specific gate drive circuit. A liquid crystal display device.   2. The liquid crystal display device according to claim 1, wherein the column block is a block in which the plurality of picture element electrodes arranged in a matrix are divided into four or two for every plurality of columns. Display device.   2. The liquid crystal display device according to claim 1, wherein the column block is a block obtained by dividing the plurality of picture element electrodes into four columns for each of a plurality of columns, and the gate driving circuit is a gate to which a voltage is applied in the first column block. (1) a gate line in which a voltage application target in a second column block adjacent to the first column block is shifted by one line with respect to the line; and (2) a third column adjacent to the second column block. The voltage application target in the block is a gate line shifted by two lines. (3) The voltage application target in the fourth column block adjacent to the third column block is a gate line shifted by three lines. A liquid crystal display device that performs application.   2. The liquid crystal display device according to claim 1, wherein the column block is a block obtained by dividing the plurality of picture element electrodes into four columns for each of a plurality of columns, and the gate driving circuit is a gate to which a voltage is applied in the first column block. (1) A gate line in which a voltage application target in a second column block adjacent to the first column block is shifted by two lines with respect to the line, and (2) a third line adjacent to the second column block. The voltage application target in the column block is the gate line of the same line, and (3) the voltage application target in the fourth column block adjacent to the third column block is the gate line shifted by two lines, A liquid crystal display device that performs application.   2. The liquid crystal display device according to claim 1, wherein the column block is a block in which the plurality of pixel electrodes are divided into two for each of a plurality of columns, and the gate driving circuit is a gate to which a voltage is applied in the first column block. A liquid crystal display device, wherein a voltage application target in the second column block is shifted by two lines with respect to the line, and a voltage is applied simultaneously to each gate line. In the liquid crystal display device according to any one of claims 1 to 5, wherein the data by the drive circuit and the counter electrode driving circuit, between and adjacent lines blocks as polar each liquid crystal in the line within the block is reversed The voltage is applied so that the polarity of the first liquid crystal is different, or the voltage is applied so that the polarities are the same in the line block and between the adjacent line blocks. A liquid crystal display device.

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