CN103558720A - Array substrate, driving method of array substrate, and liquid crystal display - Google Patents
Array substrate, driving method of array substrate, and liquid crystal display Download PDFInfo
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- CN103558720A CN103558720A CN201310572342.6A CN201310572342A CN103558720A CN 103558720 A CN103558720 A CN 103558720A CN 201310572342 A CN201310572342 A CN 201310572342A CN 103558720 A CN103558720 A CN 103558720A
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Abstract
The embodiment of the invention provides an array substrate, a driving method of the array substrate, and a liquid crystal display, and relates to the technical field of displays. The array substrate comprises a displaying driving circuit and a plurality of pixel units formed by a plurality of grid lines and a plurality of data lines which are arranged transversely and longitudinally in an intersecting manner, wherein a row of pixel units arranged in directions of the data lines forms a pixel unit row; each pixel unit row comprises a plurality of first pixel unit groups and a plurality of second pixel unit groups which are arranged at intervals; thin film transistors of the pixel units in the first pixel unit groups are connected with one data line; thin film transistors of the pixel units in the second pixel unit groups are connected with another adjacent data line; the displaying driving circuit is used for inputting source electrode signal voltage to the data lines, so that voltage polarities of at least partial two adjacent pixel unit rows are opposite; and in the same pixel unit row, voltage polarities of the first pixel unit groups and the second pixel unit groups are opposite. The array substrate can effectively improve flicker and color cast.
Description
Technical field
The present invention relates to display technology field, relate in particular to a kind of array base palte and driving method thereof, liquid crystal display.
Background technology
Liquid crystal display is by regulating the red, green, blue sub-pixel in each pixel to carry out display frame to the transit dose of light.Thereby liquid crystal display offers pixel electrode by data by source drive unit within the scan period and within the frame period, make above-mentioned data remain on this pixel electrode to drive the liquid crystal deflecting element in this pixel to carry out image demonstration.For improve liquid crystal panel display quality, avoid liquid crystal polarization uneven, pixel electrode need to adopt alternating voltage to drive, and needs the polarity of the data voltage on pixel electrode to meet the periodic reversion of certain rule.
Existing reversal of poles mode comprises the modes such as frame reversal of poles (Frame Inversion), line reversal of poles (Line Inversion) and point-polarity reversion (Dot Inversion).Wherein, in frame reversal of poles mode, all liquid crystal capacitances of a certain frame are all charged to a kind of identical polarity of voltage, all liquid crystal capacitances of its next frame are charged to again another identical polarity of voltage simultaneously, like this because there is grayscale difference between different polarity, the picture that display panels in frame reversal of poles shows easily produces flicker, and visual effect is bad.The shortcoming existing in order to improve frame reversal of poles mode, increasing people start to adopt the mode of line reversal of poles and point-polarity reversion to replace frame reversal of poles.In online reversal of poles mode, in a certain frame, the liquid crystal capacitance of adjacent two row or column is charged to contrary polarity of voltage, thereby can reduce in average mode the problem of film flicker in frame reversal of poles mode, but the signal in identical voltage polar orientation easily produces interference in linear reversal of poles; In point-polarity inversion mode, the polarity of voltage of the liquid crystal capacitance of the inferior pixel that in a certain frame, the polarity of voltage of the liquid crystal capacitance of each pixel is all adjacent is contrary, there is so a better average display effect, can so that the problem of film flicker greatly improve.But its weak point is, puts inversion mode and has larger power consumption.
In addition,, under some specific display mode, the bias voltage between each pixel cell cannot be offset completely, like this, public electrode voltages will by draw or drop-down, thereby make the pixel electrode of each colored pixels unit and the poor of public electrode increase or reduce, cause display frame to occur colour cast problem.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and driving method thereof, liquid crystal display, can equilibrium liquid LCD panel on the polarity of voltage between each pixel cell, improve flicker and color offset phenomenon.
In order to achieve the above object, the one side of the embodiment of the present invention, provides a kind of array base palte, comprises a plurality of pixel cells that formed by transverse and longitudinal many grid lines arranged in a crossed manner and data line; Wherein, also comprise display driver circuit;
Wherein, a row pixel cell of arranging along data line direction forms pixel cell row, and described pixel cell row comprise a plurality of the first pixel cell groups and the second pixel cell group that space arranges;
The thin film transistor (TFT) of the described pixel cell in described the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described the second pixel cell group is connected with another adjacent data line;
Described display driver circuit is for inputting source electrode signal voltage to data line, so that in two adjacent at least partly row pixel lists, the polarity of voltage of adjacent described pixel cell is contrary; And in the described pixel cell row of same row, the polarity of voltage of the pixel cell in adjacent pixel unit group is contrary.
The embodiment of the present invention on the other hand, provides a kind of liquid crystal display, and described liquid crystal display comprises array base palte as above.
The another aspect of the embodiment of the present invention, provides a kind of array base palte driving method, and for driving array base palte as above, described method comprises:
Display driver circuit is to data line input source electrode signal voltage;
Described source signal voltage drives the pixel cell being connected with described data line by described data line, so that the adjacent described pixel cell column voltage polarity of two row is contrary at least partly; And in the described pixel cell row of same row, described the first pixel cell group is contrary with the second pixel cell group polarity of voltage;
Wherein, a row pixel cell of arranging along data line direction forms pixel cell row, and described pixel cell row comprise a plurality of the first pixel cell groups and the second pixel cell group that space arranges; The thin film transistor (TFT) of the described pixel cell in described the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described the second pixel cell group is connected with another adjacent data line.
A kind of like this array base palte that the embodiment of the present invention provides and driving method thereof, liquid crystal display, array base palte comprises a plurality of pixel cell row, a row pixel cell of arranging along data line direction forms pixel cell row, in described pixel cell row, comprise again spaced a plurality of the first pixel cell group and the second pixel cell group, wherein in different pixels unit group, the connection of pixel cell is different, thereby can, by input specific source signal voltage to different data lines, realize at least partly the adjacent described pixel cell column voltage polarity of two row contrary; And in the described pixel cell row of same row, described the first pixel cell group is contrary with the second pixel cell group polarity of voltage.So, because the polarity of voltage between adjacent pixel unit group is contrary, thereby can cancel each other out bias voltage, the polarity of the voltage on equilibrium liquid LCD panel between each pixel cell, significantly improves flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that can realize between adjacent pixel unit group is contrary, the array base palte that adopts a kind of like this structure, because the polarity of voltage of each data line in each frame is without saltus step occurs repeatedly, therefore can effectively reduce the power consumption in array base palte driving process.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
The structural representation of display driver circuit in the array base palte that Fig. 2 provides for the embodiment of the present invention;
The structural representation of another array base palte that Fig. 3 provides for the embodiment of the present invention;
A kind of array base palte that Fig. 4 provides for the embodiment of the present invention drives the graph of a relation of signal;
The output signal schematic diagram of source drive unit in the array base palte that Fig. 5 provides for the embodiment of the present invention;
The array base palte point solarization image pixel array structural representation that Fig. 6 provides for the embodiment of the present invention;
The structural representation of the another array base palte that Fig. 7 provides for the embodiment of the present invention;
The schematic flow sheet of a kind of array base palte driving method that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The array base palte that the embodiment of the present invention provides, as shown in Figure 1, comprises display driver circuit 10 and a plurality of pixel cells 13 that formed by transverse and longitudinal many grid lines 11 arranged in a crossed manner and data line 12.
Each pixel cell row 130 comprises a plurality of the first pixel cell groups 131 and the second pixel cell group 132 that space arranges.
The thin film transistor (TFT) of the pixel cell in the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the pixel cell in the second pixel cell group is connected with another adjacent data line.For example: in pixel cell row 130, the thin film transistor (TFT) of each pixel cell 13 in the first pixel cell group 131 is all connected with the first data line 121, and the thin film transistor (TFT) of each pixel cell 13 in the second pixel cell group 132 is all connected with the second data line 122.
It should be noted that, in embodiments of the present invention, pixel cell row 130 refer to a row pixel cell 13 of arranging along data line direction.The quantity of pixel cell row 130 is relevant with pixel cell 13 quantity that are positioned at same row in array base palte, for example: pixel cell row 130 comprise and many grid lines and two data lines 121,122.In addition, in embodiments of the present invention, the first pixel cell group 131 and the second pixel cell group 132 can comprise the pixel cell 13 of equal number, in the first pixel cell group 131 or the second pixel cell group 132, the pixel cell 13 that all can comprise more than one longitudinal setting, the quantity of the pixel cell 13 that pixel cell group comprises can be selected according to actual requirement.In array base palte as shown in Figure 1, be to comprise in two data lines 121 and 122, the first pixel cell groups 131 and the second pixel cell group 132 and all comprise the explanation that a pixel cell 13 carries out for example with pixel cell row 130.
Wherein, display driver circuit 10 is for inputting source electrode signal voltages to data line 12, so that the adjacent described pixel cell column voltage polarity of two row is contrary at least partly; And in the described pixel cell row of same row, described the first pixel cell group is contrary with the second pixel cell group polarity of voltage.The adjacent described pixel cell column voltage polarity of two row is contrary, refers in adjacent pixel cell row, and the first pixel cell group of arranging along data line direction and the second pixel cell group polarity of voltage change contrary; For example: wherein the first pixel cell group of pixel cell row and the second pixel cell group according to+-+-+-... sequence alternate changes, the first pixel cell group of another pixel cell row and the second pixel cell group according to-+-+-+... sequence alternate changes.As shown in Figure 1, in two adjacent row pixel cell row 130, both polarity of voltages contrary (being also the pixel cell 13 of connection data line 121, contrary with pixel cell 13 polarity of voltages of connection data line 122) of the first pixel groups 131 of the first pixel groups 131 of connection data line 121 and connection data line 122; And in the described pixel cell row 130 of same row, adjacent pixel unit group 131 and 132 polarity of voltages contrary (be arranged in same row pixel cell row 130, the polarity of voltage of the pixel cell 13 in adjacent pixel unit group 131 and 132 is contrary).
A kind of like this array base palte that the embodiment of the present invention provides, comprise a plurality of pixel cell row, a row pixel cell of arranging along data line direction forms pixel cell row, in described pixel cell row, comprise again spaced a plurality of the first pixel cell group and the second pixel cell group, wherein in different pixels unit group, the connection of pixel cell is different, thereby can be by input specific source signal voltage to different data lines, the polarity of voltage of realizing the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.So, because the polarity of voltage between adjacent pixel unit is contrary, thereby can cancel each other out bias voltage, the polarity of the voltage on equilibrium liquid LCD panel between each pixel cell of at least part of viewing area, significantly improves flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that can realize between adjacent pixel unit is contrary, the array base palte that adopts a kind of like this structure, because the polarity of voltage of each data line in each frame is without saltus step occurs repeatedly, therefore can effectively reduce the power consumption in array base palte driving process.
Further, as shown in Figure 2, display driver circuit 10 specifically can comprise timing control unit 101, Polarity Control unit 102 and at least two source drive unit 103.
Wherein, at least two source drive unit 103 can comprise again at least one first source drive unit 1031 and at least one second source drive unit 1032, and each source drive unit 103 connects at least one respectively in data line 12(Fig. 2 not shown).
It should be noted that, in embodiments of the present invention, at least one first source drive unit 1031 is identical with the structure of at least one the second source drive unit 1032, the difference of the two is, the received polarity control signal in the first source drive unit 1031 and the second source drive unit 1032 is not identical, thereby make the two export respectively the source signal voltage with different polarity of voltages, in order to distinguish this two kinds of voltage output ends that polarity is different, can be distinguished at least one first source drive unit 1031 and at least one second source drive unit 1032 of called after.
Concrete, timing control unit 101 and Polarity Control unit 102 can be multiple electronic component, in embodiments of the present invention, timing control unit 101 is to take the explanation that timing controller TCON carries out as example, and Polarity Control unit 102 can be integrated on timing controller TCON equally.Certainly, this also only illustrates, and can adopt equally other circuit units that can realize above-mentioned functions or electronic component as timing control unit 101 and Polarity Control unit 102, and the present invention does not limit this.
One of mode: the array base palte that the embodiment of the present invention provides can also adopt structure as shown in Figure 3, wherein, in n row pixel cell row 130, the thin film transistor (TFT) of each pixel cell 13 in the first pixel cell group 131 is all connected with 2n-1 column data line, and the thin film transistor (TFT) of each pixel cell 13 in the second pixel cell group 132 is all connected with 2n column data line.
2n column data line is adjacent with 2n+1 column data line to be arranged between two row pixel cell row 130.
Wherein, n is natural number, and n is less than or equal to pixel cell row 130 quantity in array base palte half.
Concrete, the polarity of voltage of 2n-1 column data line can be contrary with the polarity of voltage of 2n column data line, and the polarity of voltage of 2n column data line can be identical with the polarity of voltage of 2n+1 column data line.
Adopt a kind of like this data line design of structure, by within a frame period, respectively to the voltage signal of the adjacent 2n column data line being set up in parallel and 2n+1 column data line input identical polar, the polarity of voltage that can realize the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.Owing to adopting two adjacent column data lines respectively to the partial pixel unit group input drive signal in two pixel cells row, therefore can greatly improve the reliability of signal driver, in addition, two adjacent column data line input signal polarity are identical, also can further avoid between data line, owing to there is poor the crosstalking of producing of polarity, further having improved the quality of display device.
In embodiments of the present invention, the first area that the first source drive unit 1031 can corresponding viewing area, the second area that the second source drive unit 1032 can corresponding described viewing area, wherein, the first area of viewing area does not overlap with second area.
The first source drive unit 1031 is inputted source electrode signal voltage polarity reversed in order to data line input source electrode signal voltage polarity and the second source drive unit 1032 to data line.
Wherein, the first area of viewing area or second area comprise many spaced data lines respectively.In the second area of Huo viewing area, the first area of viewing area, can adopt equally the polarity of voltage of 2n-1 column data line contrary with the polarity of voltage of 2n column data line, the polarity of voltage data entry mode identical with the polarity of voltage of 2n+1 column data line of 2n column data line.
Concrete, can adopt 10 pairs of display driver circuits as shown in Figure 2 array base palte as shown in Figure 3 to drive.Wherein, comprise that 2n for exporting the source drive unit 103 of source electrode signal voltage, the half side region, a left side of 1031 corresponding viewing areas, n the first source drive unit, the half side region, the right side of 1032 corresponding viewing areas, all the other n the second source drive unit.For example: D-IC_1 ... D-IC_n is positioned at left half side region, D-IC_n+1 ... D-IC_2n is positioned at right half side region, and each D-IC connects 4 data lines.
The input/output signal relation of source drive unit 103 as shown in Figure 4, the order that as can be seen here, can realize source drive unit 103 by controlling the first polarity inversion signal POL1, the second polarity inversion signal POL2 and polarity control signal POLC repeats output.
For example, with reference to figure 4, timing control unit 101 can be to the first polarity inversion signal POL1 of each source drive unit 103 input high level (H) and the second polarity inversion signal POL2 of low level (L).
According to the signal relation shown in Fig. 4, at N frame, when POLC=H, POL1=H, POL2=L, can so that source drive unit 103 half side area data line OUT_4n+1 to the OUT_4n+4 input left source electrode signal voltage polarity in half side region, a left side that is arranged in viewing area from left to right by the order repeated arrangement (as shown in dotted line frame as lower in Fig. 4) of positive and negative negative just (+--+); When POLC=L, POL1=H, POL2=L, can so that source drive unit 103 half side area data line OUT_4n+1 to the OUT_4n+4 input to the right source electrode signal voltage polarity in half side region, the right side that is arranged in viewing area from left to right by the order repeated arrangement (as shown in dotted line frame as upper in Fig. 4) of negative positive and negative (++-), corresponding source drive unit 103 output signals can be as shown in Figure 5.Adopt above-mentioned driving signal, some reversion effect as shown in Figure 6 can be realized in viewing area at least partly.
At N+1 frame, timing control unit 101 and Polarity Control unit 102 all reverse to source drive unit 103, so that source drive unit 103 output signals reverse, and then data line signal is reversed, realized equally at least part of viewing area point reversion effect.
The like, the voltage generation primary voltage reversal of poles of each frame data line.Be the polarity of voltage of each data line in each frame without saltus step occurs repeatedly, therefore can effectively reduce the power consumption in array base palte driving process.
Two of mode: the array base palte that the embodiment of the present invention provides can also adopt structure as shown in Figure 3, wherein, in n row pixel cell row 130, the thin film transistor (TFT) of each pixel cell 13 in the first pixel cell group 131 is all connected with 2n-1 column data line, and the thin film transistor (TFT) of each pixel cell 13 in the second pixel cell group 132 is all connected with 2n column data line.
2n column data line is adjacent with 2n+1 column data line to be arranged between two row pixel cell row 130.
Wherein, n is natural number, and n is less than or equal to pixel cell row 130 quantity in array base palte half.
According to the signal relation shown in Fig. 4, at N frame, when POL1=H, POL2=L, can so that source drive unit 103 half side area data line OUT_4n+1 to the OUT_4n+4 input left source electrode signal voltage polarity in half side region, a left side that is arranged in viewing area from left to right by the order repeated arrangement (as shown in dotted line frame as lower in Fig. 4) of positive and negative negative just (+--+); When POL1=L, POL2=H, can so that source drive unit 103 half side area data line OUT_4n+1 to the OUT_4n+4 input to the right source electrode signal voltage polarity in half side region, the right side that is arranged in viewing area from left to right by the order repeated arrangement (as shown in dotted line frame as upper in Fig. 4) of negative positive and negative (++-), corresponding source drive unit 103 signals can be as shown in Figure 5.Now, Polarity Control unit 102 is the source drive unit input POLC=H in half side region left, and the source drive unit input POLC=L in right half side region, by the effect of Polarity Control unit 102, on data line, all present+--++--+... +--+, according to+--+order repeated arrangement.Adopt above-mentioned driving signal, some reversion effect as shown in Figure 6 can be realized in viewing area.At N+1 frame, timing control unit 101 and Polarity Control unit 102 all reverse to source drive unit 103, so that source drive unit 103 output signals reverse, and then data line signal is reversed, realized equally at least part of viewing area point reversion effect.
At N+1 frame, timing control unit 101 and Polarity Control unit 102 all reverse to source drive unit 103 input signals, so that source drive unit 103 output signals reverse, and then data line signal is reversed, realized equally the some reversion effect of at least part of viewing area.
The like, the voltage generation primary voltage reversal of poles of each frame data line.Be the polarity of voltage of each data line in each frame without saltus step occurs repeatedly, therefore can effectively reduce the power consumption in array base palte driving process.
Adopt above-mentioned arbitrary driving aspect, all can realize at least part of viewing area point reversion effect as shown in Figure 6, wherein, each row pixel cell row are corresponding a kind of color respectively, and it is red that 3 adjacent row pixel cells row are respectively corresponding R(), G(is green), B(is blue) three kinds of pixel cells.In same row pixel cell row, the first pixel cell group of adjacent setting can be inputted identical gate drive signal with the pixel cell in the second pixel cell group, as shown in Figure 6, grid line G1 can input identical gate drive signal with grid line G2, and grid line G3 and grid line G4 can input identical gate drive signal.Wherein, show as lower than the pixel electrode in the pixel cell of reference level value and adopt oblique interstitial wire to represent, these pixel cells will be not luminous accordingly, and higher than the pixel electrode in the pixel cell of reference level value without interstitial wire, these pixel cells are by luminous.Can be clear that, adopt above-mentioned driving signal can realize the polarity of voltage of the pixel cell in the pixel cell group that the pixel cell in each pixel cell group is adjacent contrary.In addition, in array base palte as shown in Figure 6, because adjacent two row pixel cell groups connect respectively different data lines, the corresponding grid line of adjacent two row pixel cell group can be inputted identical gate drive signal can there is not crosstalking in the ranks yet, so, can effectively reduce quantity and the sweep frequency of grid line, thereby can reduce the design difficulty of array base palte, further reduce the power consumption in array base palte driving process.
Further, in embodiments of the present invention, as shown in Figure 6, two groups of adjacent gate drive signals can adopt identical square-wave signal of cycle, and between two groups of square-wave signals, can have the delay of semiperiod.Concrete, when half moment of grid line G1 and grid line G2 input high level gate drive signal, grid line G3 and grid line G4 start to carry out the input of high level gate drive signal.So, because next group gate drive signal is inputted corresponding grid line in advance, thereby can carry out precharge for corresponding pixel cell, and these pixel cells output display signal not now, after upper one group of gate drive signal has scanned, the pixel cell being driven by next group gate drive signal can be opened pixel cell rapidly, thereby can improve significantly the response speed of display panel, has greatly improved the quality of display device.
It should be noted that, the selection of above-mentioned driving signal also only illustrates, and in the process of using, can change as required the polarity of voltage that drives signal in reality.In embodiments of the present invention, be to be respectively R(redness with three adjacent pixel cells of level), G(is green), B(is blue) three kinds of pixel cells be combined as the explanation that example is carried out.
In the above-described embodiments, the polarity of voltage of the pixel cell that each pixel cell in each frame period on array base palte is all adjacent is contrary, adopts some reversion (1DOT) mode.Should expect, the above is only also to take the explanation that 1DOT mode carries out as example, and the array base palte described in the embodiment of the present invention can also adopt multiple some inversion mode.For example, in array base palte as shown in Figure 7, be the explanation of carrying out with 2 reversions (2DOT) inversion mode.Wherein, the first pixel groups 131 and the second pixel groups 132 all can comprise 2 pixel cells 13 of longitudinal arrangement.
Concrete, when the first pixel groups 131 and the contained pixel cell of the second pixel groups 132 13 quantity increase, similar with Fig. 6, in same row pixel cell row, the first pixel cell group of adjacent setting can be inputted identical gate drive signal with the pixel cell in the second pixel cell group.So, can greatly reduce quantity and the sweep frequency of grid line, realize low-power consumption and drive.But the increase along with the first pixel groups 131 and contained pixel cell 13 quantity of the second pixel groups 132, point inversion mode will level off to line inversion mode more, signal in identical voltage polar orientation also will more easily produce and disturb, therefore in the process of practical application, when the first pixel groups 131 and contained pixel cell 13 quantity of the second pixel groups 132 can be selected as required.Should be appreciated that in embodiments of the present invention, is to take the first pixel groups 131 and the second pixel groups 132 all can comprise 2 explanations that pixel cell 13 carries out as example of longitudinal arrangement, and the restriction of not the present invention being done.
After a frame scan finishes, for driving the source signal voltage of pixel cell that total polar is reversed.Thereby guarantee that the liquid crystal molecule in pixel cell region can not polarize because of long-term electric field action.
A kind of liquid crystal display that the embodiment of the present invention provides, this liquid crystal display comprises array base palte as above.
It should be noted that display device provided by the present invention can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer.
Wherein, the structure of array base palte has been done detailed description in the aforementioned embodiment, repeats no more herein.
The embodiment of the present invention also provides a kind of liquid crystal display, comprise array base palte, this array base palte comprises a plurality of pixel cell row, a row pixel cell of arranging along data line direction forms pixel cell row, described in each, in pixel cell row, comprise again spaced a plurality of the first pixel cell group and the second pixel cell group, wherein in different pixels unit group, the connection of pixel cell is different, thereby can by input specific source signal voltage to different data lines, to realize the polarity of voltage of the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent contrary.So, because the polarity of voltage between adjacent pixel unit is contrary, thereby can cancel each other out bias voltage, the polarity of the voltage on equilibrium liquid LCD panel between each pixel cell, significantly improves flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that can realize between adjacent pixel unit is contrary, the array base palte that adopts a kind of like this structure, because the polarity of voltage of each data line in each frame is without saltus step occurs repeatedly, therefore can effectively reduce the power consumption in array base palte driving process.
The embodiment of the present invention also provides a kind of array base palte driving method, and for driving array base palte as above, as shown in Figure 8, described method comprises:
S801, display driver circuit are to data line input source electrode signal voltage.
S802, source signal voltage drive the pixel cell being connected with this data line by data line, so that two adjacent row pixel cell column voltage polarity are contrary at least partly; And in same row pixel cell row, the first pixel cell group is contrary with the second pixel cell group polarity of voltage.
Wherein, a row pixel cell of arranging along data line direction forms pixel cell row, and each pixel cell row comprises a plurality of the first pixel cell groups and the second pixel cell group that space arranges; The thin film transistor (TFT) of the pixel cell in the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the pixel cell in the second pixel cell group is connected with another adjacent data line.For example: the first pixel cell group and the second pixel cell group comprise the pixel cell of equal number; The thin film transistor (TFT) of each pixel cell in the first pixel cell group is all connected with the first data line, and the thin film transistor (TFT) of each pixel cell in the second pixel cell group is all connected with the second data line.
A kind of like this array base palte driving method that the embodiment of the present invention provides, array base palte comprises a plurality of pixel cell row, a row pixel cell of arranging along data line direction forms pixel cell row, described in each, in pixel cell row, comprise again spaced a plurality of the first pixel cell group and the second pixel cell group, wherein in different pixels unit group, the connection of pixel cell is different, thereby can be by input specific source signal voltage to different data lines, the polarity of voltage of realizing the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.So, because the polarity of voltage between adjacent pixel unit is contrary, thereby can cancel each other out bias voltage, the polarity of the voltage on equilibrium liquid LCD panel between each pixel cell, significantly improves flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that can realize between adjacent pixel unit is contrary, the array base palte that adopts a kind of like this structure, because the polarity of voltage of each data line in each frame is without saltus step occurs repeatedly, therefore can effectively reduce the power consumption in array base palte driving process.
Further, display driver circuit specifically can comprise to data line input source electrode signal voltage:
Timing control unit is inputted the first polarity inversion signal and the second polarity inversion signal at least two source drive unit, the first polarity inversion signal and the second polarity inversion signal single spin-echo, so that at least two source drive unit are to data line input source electrode signal voltage.
The first polarity control signal is inputted to the first source drive unit in Polarity Control unit, to the second source drive unit, input the second polarity control signal, the first polarity control signal and the second polarity control signal single spin-echo, so that the source signal voltage that at least two source drive unit drive is realized reversal of poles.
Wherein, at least two source drive unit comprise at least one first source drive unit and at least one second source drive unit, and each source drive unit connects at least one respectively data line.
It should be noted that, in embodiments of the present invention, the structure of at least one first source drive unit and at least one the second source drive unit is just the same, the difference of the two is, the received polarity control signal in the first source drive unit and the second source drive unit is not identical, thereby make the two export respectively the source signal voltage with different polarity of voltages, in order to distinguish this two kinds of voltage output ends that polarity is different, can be distinguished at least one first source drive unit of called after and at least one second source drive unit.
Further, the array base palte that the embodiment of the present invention provides can also adopt structure as shown in Figure 3, wherein, in n row pixel cell row, described in each in the first pixel cell group, the thin film transistor (TFT) of pixel cell is all connected with 2n-1 column data line, and the thin film transistor (TFT) of each pixel cell in the second pixel cell group is all connected with 2n column data line.
2n column data line is adjacent with 2n+1 column data line to be arranged between two row pixel cell row.
Wherein, n is natural number, and n is less than or equal to the number of columns of pixel cell described in array base palte half.
Concrete, the polarity of voltage of 2n-1 column data line can be contrary with the polarity of voltage of 2n column data line, and the polarity of voltage of 2n column data line can be identical with the polarity of voltage of 2n+1 column data line.
Adopt a kind of like this data line design of structure, by within a frame period, to the voltage signal of the adjacent 2n column data line being set up in parallel and 2n+1 column data line input identical polar, can realize the polarity of voltage of the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent respectively contrary.Owing to adopting two adjacent column data lines respectively to the partial pixel unit group input drive signal in two pixel cells row, therefore can greatly improve the reliability of signal driver, in addition, two adjacent column data line input signal polarity are identical, also can further avoid between data line, owing to there is poor the crosstalking of producing of polarity, further having improved the quality of display device.
In embodiments of the present invention, the first area that the first source drive unit can corresponding viewing area, the second area that the second source drive unit can corresponding described viewing area, wherein, the first area of viewing area does not overlap with second area.
The first source drive unit is inputted source electrode signal voltage polarity reversed in order to data line input source electrode signal voltage polarity and the second source drive unit to data line.
Concrete, can adopt 10 pairs of display driver circuits as shown in Figure 2 array base palte as shown in Figure 3 to drive.Wherein, comprise that 2n for exporting the source drive unit of source electrode signal voltage, the half side region, a left side of corresponding viewing area, n the first source drive unit, the half side region, the right side of corresponding viewing area, all the other n the second source drive unit.
As shown in Figure 4, as can be seen here, the order that can realize source drive unit by controlling the first polarity inversion signal POL1, the second polarity inversion signal POL2 and polarity control signal POLC repeats output to the input/output signal relation of source drive unit.
For example, timing control unit can be to the first polarity inversion signal POL1 of each source drive unit input high level (H) and the second polarity inversion signal POL2 of low level (L).
Polarity Control unit can be to the first polarity control signal POLC1 of source drive unit input high level (H) that is positioned at the half side region, a left side of viewing area, to the second polarity control signal POLC2 of source drive unit input low level (L) that is positioned at the half side region, the right side of viewing area.
According to the signal relation shown in Fig. 4, can to data line, input source electrode signal voltage polarity from left to right by positive and negative negative positive order repeated arrangement so that be positioned at the source drive unit in the half side region, a left side of viewing area, polarity of voltage in pixel cell can be as shown in Figure 5, the source drive unit in half side region, the right side that makes to be positioned at viewing area to data line input source electrode signal voltage polarity from left to right by negative positive and negative order repeated arrangement.
Further, the array base palte driving method that the embodiment of the present invention provides can also be applicable to 2DOT inversion mode.For example, the first pixel groups and the second pixel groups all can comprise 2 pixel cells of longitudinal arrangement.Concrete driving method can be as previously mentioned.Adopt a kind of like this driving method can greatly reduce quantity and the sweep frequency of grid line, realize low-power consumption and drive.
After a frame scan finishes, for driving the source signal voltage of pixel cell that total polar is reversed.Thereby guarantee that the liquid crystal molecule in pixel cell region can not polarize because of long-term electric field action.
One of ordinary skill in the art will appreciate that: all or part of flow process that realizes said method embodiment can having arranged by the relevant hardware of computer program instructions and hardware related peripheral circuit, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium is the various media that can be program code stored such as USB flash disk, portable hard drive, ROM (read-only memory) (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disc or CD.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (15)
1. an array base palte, is characterized in that, comprises display driver circuit and a plurality of pixel cells that formed by transverse and longitudinal many grid lines arranged in a crossed manner and data line;
A row pixel cell of arranging along data line direction forms pixel cell row, and described pixel cell row comprise a plurality of the first pixel cell groups and the second pixel cell group that space arranges;
The thin film transistor (TFT) of the described pixel cell in described the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described the second pixel cell group is connected with another adjacent data line;
Described display driver circuit is for inputting source electrode signal voltage to data line, so that the adjacent described pixel cell column voltage polarity of two row is contrary at least partly; And in the described pixel cell row of same row, described the first pixel cell group is contrary with the second pixel cell group polarity of voltage.
2. array base palte according to claim 1, is characterized in that,
Described display driver circuit comprises timing control unit, Polarity Control unit and at least two source drive unit;
Described at least two source drive unit comprise at least one first source drive unit and at least one second source drive unit, and described in each, source drive unit connects at least one respectively described data line;
Described timing control unit, for inputting the first polarity inversion signal and the second polarity inversion signal at least two described source drive unit, described the first polarity inversion signal and described the second polarity inversion signal single spin-echo, so that described at least two source drive unit are to described data line input source electrode signal voltage;
Described Polarity Control unit, for inputting the first polarity control signal to described the first source drive unit, to described the second source drive unit, input the second polarity control signal, described the first polarity control signal and described the second polarity control signal single spin-echo, so that the source signal voltage that described at least two source drive unit drive is realized reversal of poles.
3. array base palte according to claim 2, is characterized in that, the first area of corresponding viewing area, described the first source drive unit, the second area of corresponding described viewing area, described the second source drive unit;
Described the first source drive unit is inputted source electrode signal voltage polarity reversed in order to described data line input source electrode signal voltage polarity and described the second source drive unit to described data line.
4. according to the arbitrary described array base palte of claim 1-3, it is characterized in that, at n, be listed as in described pixel cell row, described in each in described the first pixel cell group, the TFT of pixel cell is all connected with 2n-1 column data line, and the TFT of pixel cell is all connected with 2n column data line described in each in described the second pixel cell group;
2n column data line is adjacent with 2n+1 column data line to be arranged between the described pixel cell row of two row;
Wherein, described n is natural number, and described n is less than or equal to pixel cell number of columns described in described array base palte half.
5. array base palte according to claim 4, is characterized in that,
The polarity of voltage of described 2n-1 column data line is contrary with the polarity of voltage of described 2n column data line;
The polarity of voltage of described 2n column data line is identical with the polarity of voltage of described 2n+1 column data line.
6. array base palte according to claim 1, is characterized in that,
In the described pixel cell row of same row, the described first pixel cell group of adjacent setting is inputted identical gate drive signal with the pixel cell in described the second pixel cell group.
7. array base palte according to claim 1, is characterized in that, described the first pixel cell group and described the second pixel cell group comprise the described pixel cell of equal number;
Described the first pixel groups and described the second pixel groups include 2 described pixel cells of longitudinal arrangement.
8. a liquid crystal display, is characterized in that, described liquid crystal display comprises the array base palte as described in any one in claim 1-7.
9. an array base palte driving method, for driving the array base palte as described in as arbitrary in claim 1-7, is characterized in that, described method comprises:
Display driver circuit is to data line input source electrode signal voltage;
Described source signal voltage drives the pixel cell being connected with described data line by described data line, so that the adjacent described pixel cell column voltage polarity of two row is contrary at least partly; And in the described pixel cell row of same row, described the first pixel cell group is contrary with the second pixel cell group polarity of voltage;
Wherein, a row pixel cell of arranging along data line direction forms pixel cell row, and described pixel cell row comprise a plurality of the first pixel cell groups and the second pixel cell group that space arranges; The thin film transistor (TFT) of the described pixel cell in described the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described the second pixel cell group is connected with another adjacent data line.
10. array base palte driving method according to claim 9, is characterized in that, described display driver circuit comprises to data line input source electrode signal voltage:
Timing control unit is inputted the first polarity inversion signal and the second polarity inversion signal at least two described source drive unit, described the first polarity inversion signal and described the second polarity inversion signal single spin-echo, so that described at least two source drive unit are to described data line input source electrode signal voltage;
The first polarity control signal is inputted to described the first source drive unit in described Polarity Control unit, to described the second source drive unit, input the second polarity control signal, described the first polarity control signal and described the second polarity control signal single spin-echo, so that the source signal voltage that described at least two source drive unit drive is realized reversal of poles;
Wherein, described at least two source drive unit comprise at least one first source drive unit and at least one second source drive unit, and described in each, source drive unit connects at least one respectively described data line.
11. array base palte driving methods according to claim 10, is characterized in that, the first area of corresponding viewing area, described the first source drive unit, the second area of corresponding described viewing area, described the second source drive unit;
Described the first source drive unit is inputted source electrode signal voltage polarity reversed in order to described data line input source electrode signal voltage polarity and described the second source drive unit to described data line.
12. according to the arbitrary described array base palte driving method of claim 9-11, it is characterized in that, at n, be listed as in described pixel cell row, described in each in described the first pixel cell group, the TFT of pixel cell is all connected with 2n-1 column data line, and the TFT of pixel cell is all connected with 2n column data line described in each in described the second pixel cell group;
2n column data line is adjacent with 2n+1 column data line to be arranged between the described pixel cell row of two row;
Wherein, described n is natural number, and described n is less than or equal to pixel cell number of columns described in described array base palte half.
13. array base palte driving methods according to claim 12, is characterized in that,
The polarity of voltage of described 2n-1 column data line is contrary with the polarity of voltage of described 2n column data line;
The polarity of voltage of described 2n column data line is identical with the polarity of voltage of described 2n+1 column data line.
14. array base paltes according to claim 12, is characterized in that,
In the described pixel cell row of same row, the described first pixel cell group of adjacent setting is inputted identical gate drive signal with the pixel cell in described the second pixel cell group.
15. array base palte driving methods according to claim 9, is characterized in that, described the first pixel cell group and described the second pixel cell group comprise the described pixel cell of equal number;
Described the first pixel groups and described the second pixel groups include 2 described pixel cells of longitudinal arrangement.
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