CN103558720B - Array substrate, driving method of array substrate, and liquid crystal display - Google Patents
Array substrate, driving method of array substrate, and liquid crystal display Download PDFInfo
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- CN103558720B CN103558720B CN201310572342.6A CN201310572342A CN103558720B CN 103558720 B CN103558720 B CN 103558720B CN 201310572342 A CN201310572342 A CN 201310572342A CN 103558720 B CN103558720 B CN 103558720B
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Abstract
The embodiment of the invention provides an array substrate, a driving method of the array substrate, and a liquid crystal display, and relates to the technical field of displays. The array substrate comprises a displaying driving circuit and a plurality of pixel units formed by a plurality of grid lines and a plurality of data lines which are arranged transversely and longitudinally in an intersecting manner, wherein a row of pixel units arranged in directions of the data lines forms a pixel unit row; each pixel unit row comprises a plurality of first pixel unit groups and a plurality of second pixel unit groups which are arranged at intervals; thin film transistors of the pixel units in the first pixel unit groups are connected with one data line; thin film transistors of the pixel units in the second pixel unit groups are connected with another adjacent data line; the displaying driving circuit is used for inputting source electrode signal voltage to the data lines, so that voltage polarities of at least partial two adjacent pixel unit rows are opposite; and in the same pixel unit row, voltage polarities of the first pixel unit groups and the second pixel unit groups are opposite. The array substrate can effectively improve flicker and color cast.
Description
Technical field
The present invention relates to display technology field, particularly relate to a kind of array base palte and driving method, liquid crystal display.
Background technology
Liquid crystal display is by regulating the transit dose of red, green, blue sub-pixel to light in each pixel to carry out display frame.Data are supplied to pixel electrode by source drive unit and within the frame period, make above-mentioned data remain on this pixel electrode to drive the liquid crystal deflecting element in this pixel thus to carry out image display by liquid crystal display within the scan period.For improve liquid crystal panel display quality, avoid liquid crystal polarization uneven, pixel electrode needs to adopt alternating voltage to drive, and namely needs the periodic reversion polarity of the data voltage on pixel electrode being met to certain rule.
Existing reversal of poles mode comprises the modes such as frame reversal of poles (Frame Inversion), line reversal of poles (Line Inversion) and point-polarity reversion (Dot Inversion).Wherein, in frame reversal of poles mode, all liquid crystal capacitances of a certain frame are all charged to a kind of identical polarity of voltage, all liquid crystal capacitances of its next frame are charged to again another identical polarity of voltage simultaneously, like this because there is grayscale difference between different polarity, the picture of the display panels display in frame reversal of poles easily produces flicker, and visual effect is bad.In order to improve the shortcoming that frame reversal of poles mode exists, increasing people start to adopt the mode of line reversal of poles and point-polarity reversion to replace frame reversal of poles.In online reversal of poles mode, in a certain frame, the liquid crystal capacitance of adjacent rows or row is charged to contrary polarity of voltage, thus can reduce the problem of film flicker in frame reversal of poles mode in average mode, but the signal in linear reversal of poles in identical voltage polar orientation easily produces interference; In point-polarity inversion mode, in a certain frame, the polarity of voltage of the liquid crystal capacitance of the secondary pixel that the polarity of voltage of the liquid crystal capacitance of each pixel is all adjacent is contrary, inversion mode has a better average display effect like this, and the problem of film flicker can be made greatly to improve.But its weak point is, some inversion mode has larger power consumption.
In addition, under some specific display mode, the bias voltage between each pixel cell cannot be offset completely, like this, public electrode voltages will be pullup or pulldown, thus makes the difference of the pixel electrode of each colored pixels unit and public electrode increase or reduce, and causes display frame to occur colour cast problem.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and driving method, liquid crystal display, can the polarity of voltage on equilibrium liquid LCD panel between each pixel cell, improves flicker and color offset phenomenon.
In order to achieve the above object, the one side of the embodiment of the present invention, provides a kind of array base palte, comprises the multiple pixel cells formed by transverse and longitudinal many grid lines arranged in a crossed manner and data line; Wherein, also display driver circuit is comprised;
Wherein, the row pixel cell along the arrangement of data line direction forms pixel cell row, and described pixel cell row comprise multiple first pixel cell group and the second pixel cell group of spaced setting;
The thin film transistor (TFT) of the described pixel cell in described first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described second pixel cell group is connected with another adjacent data line;
Described display driver circuit is used for data line input source electrode signal voltage, and to make in two adjacent at least partly row pixel lists, the polarity of voltage of adjacent described pixel cell is contrary; And in the described pixel cell row of same row, the polarity of voltage of the pixel cell in adjacent pixel unit group is contrary.
The another aspect of the embodiment of the present invention, provides a kind of liquid crystal display, and described liquid crystal display comprises array base palte as above.
The another aspect of the embodiment of the present invention, provides a kind of array base palte driving method, and for driving array base palte as above, described method comprises:
Display driver circuit is to data line input source electrode signal voltage;
Described source signal voltage drives the pixel cell be connected with described data line by described data line, to make the described pixel cell column voltage polarity of two row adjacent at least partly contrary; And in the described pixel cell row of same row, described first pixel cell group is contrary with the second pixel cell group polarity of voltage;
Wherein, the row pixel cell along the arrangement of data line direction forms pixel cell row, and described pixel cell row comprise multiple first pixel cell group and the second pixel cell group of spaced setting; The thin film transistor (TFT) of the described pixel cell in described first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described second pixel cell group is connected with another adjacent data line.
So a kind of array base palte that the embodiment of the present invention provides and driving method, liquid crystal display, array base palte comprises multiple pixel cell row, a row pixel cell along the arrangement of data line direction forms pixel cell row, spaced multiple first pixel cell group and the second pixel cell group is comprised again in described pixel cell row, wherein in different pixels unit group, the connection of pixel cell is different, thus by inputting specific source signal voltage to different data lines, the described pixel cell column voltage polarity of two row adjacent at least partly can be realized contrary; And in the described pixel cell row of same row, described first pixel cell group is contrary with the second pixel cell group polarity of voltage.So, because the polarity of voltage between adjacent pixel unit group is contrary, thus the polarity of can cancel each other out bias voltage, the voltage on equilibrium liquid LCD panel between each pixel cell, significantly improve flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that namely can realize between adjacent pixel unit group is contrary, adopt a kind of like this array base palte of structure due in each frame the polarity of voltage of each data line without the need to repeatedly there is saltus step, therefore effectively can reduce the power consumption in array base palte driving process.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
The structural representation of display driver circuit in the array base palte that Fig. 2 provides for the embodiment of the present invention;
The structural representation of another array base palte that Fig. 3 provides for the embodiment of the present invention;
The graph of a relation of a kind of array base palte drive singal that Fig. 4 provides for the embodiment of the present invention;
The output signal schematic diagram of source drive unit in the array base palte that Fig. 5 provides for the embodiment of the present invention;
The array base palte point solarization image pixel array structural representation that Fig. 6 provides for the embodiment of the present invention;
The structural representation of the another array base palte that Fig. 7 provides for the embodiment of the present invention;
The schematic flow sheet of a kind of array base palte driving method that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The array base palte that the embodiment of the present invention provides, as shown in Figure 1, the multiple pixel cells 13 comprising display driver circuit 10 and formed by transverse and longitudinal many grid lines 11 arranged in a crossed manner and data line 12.
Each pixel cell row 130 comprise multiple first pixel cell group 131 and second pixel cell groups 132 of spaced setting.
The thin film transistor (TFT) of the pixel cell in the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the pixel cell in the second pixel cell group is connected with another adjacent data line.Such as: in pixel cell row 130, the thin film transistor (TFT) of each pixel cell 13 in the first pixel cell group 131 is all connected with the first data line 121, and the thin film transistor (TFT) of each pixel cell 13 in the second pixel cell group 132 is all connected with the second data line 122.
It should be noted that, in embodiments of the present invention, pixel cell row 130 refer to the row pixel cell 13 along the arrangement of data line direction.The quantity of pixel cell row 130 is relevant with pixel cell 13 quantity being positioned at same row in array base palte, such as: pixel cell row 130 comprise and many grid lines and two data lines 121,122.In addition, in embodiments of the present invention, first pixel cell group 131 and the second pixel cell group 132 can comprise the pixel cell 13 of equal number, in the first pixel cell group 131 or the second pixel cell group 132, all can comprise the more than one pixel cell 13 longitudinally arranged, the quantity of the pixel cell 13 that pixel cell group comprises can be selected according to actual requirement.In array base palte as shown in Figure 1, be comprise in two data lines 121 and 122, first pixel cell group 131 and the second pixel cell group 132 with pixel cell row 130 explanation all comprising a pixel cell 13 and carry out for example.
Wherein, display driver circuit 10 is for inputting source electrode signal voltage to data line 12, and to make at least partly, the described pixel cell column voltage polarity of adjacent two row is contrary; And in the described pixel cell row of same row, described first pixel cell group is contrary with the second pixel cell group polarity of voltage.The adjacent described pixel cell column voltage polarity of two row is contrary, and refer in adjacent pixel cell row, the first pixel cell group along the arrangement of data line direction is contrary with the change of the second pixel cell group polarity of voltage; Such as: wherein one pixel cell row the first pixel cell group and the second pixel cell group according to+-+-+-... sequence alternate change, another pixel cell row the first pixel cell group and the second pixel cell group according to-+-+-+... sequence alternate changes.As shown in Figure 1, in two adjacent row pixel cell row 130, first pixel groups 131 of connection data line 121 contrary with the polarity of voltage of both first pixel groups 131 of connection data line 122 (being also the pixel cell 13 of connection data line 121, contrary with pixel cell 13 polarity of voltage of connection data line 122); And in the described pixel cell row 130 of same row, adjacent pixel unit group 131 and 132 polarity of voltage contrary (be namely arranged in same row pixel cell row 130, the polarity of voltage of the pixel cell 13 in adjacent pixel unit group 131 and 132 is contrary).
So a kind of array base palte that the embodiment of the present invention provides, comprise multiple pixel cell row, a row pixel cell along the arrangement of data line direction forms pixel cell row, spaced multiple first pixel cell group and the second pixel cell group is comprised again in described pixel cell row, wherein in different pixels unit group, the connection of pixel cell is different, thus can by inputting specific source signal voltage to different data lines, the polarity of voltage realizing the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.So, because the polarity of voltage between adjacent pixel unit is contrary, thus the bias voltage that can cancel each other out, on equilibrium liquid LCD panel at least part of viewing area each pixel cell between the polarity of voltage, significantly improve and glimmer and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that namely can realize between adjacent pixel unit is contrary, adopt a kind of like this array base palte of structure due in each frame the polarity of voltage of each data line without the need to repeatedly there is saltus step, therefore effectively can reduce the power consumption in array base palte driving process.
Further, as shown in Figure 2, display driver circuit 10 specifically can comprise timing control unit 101, Polarity Control unit 102 and at least two source drive unit 103.
Wherein, at least two source drive unit 103 can comprise again at least one first source drive unit 1031 and at least one second source drive unit 1032, and each source drive unit 103 connects at least one in data line 12(Fig. 2 not shown respectively).
It should be noted that, in embodiments of the present invention, at least one first source drive unit 1031 is identical with the structure of at least one the second source drive unit 1032, the difference of the two is, first source drive unit 1031 is not identical with the polarity control signal received by the second source drive unit 1032, thus make the two export the source signal voltage with different polarity of voltage respectively, in order to distinguish the different voltage output end of this two kinds of polarity, at least one first source drive unit 1031 and at least one second source drive unit 1032 of called after can be distinguished.
Timing control unit 101, for inputting the first polarity inversion signal POL1(as illustrated in solid line in figure 2 at least two source drive unit 103) and the second polarity inversion signal POL2(is as shown in phantom in Figure 2), first polarity inversion signal POL1 is contrary with the second polarity inversion signal POL2 phase place, inputs source electrode signal voltage to make at least two source drive unit 103 to data line 12.
Polarity Control unit 102, for inputting the first polarity control signal POLC1(as shown in Fig. 2 chain lines to the first source drive unit 1031), the second polarity control signal POLC2(is inputted as shown in double dot dash line in Fig. 2) to the second source drive unit 1032, first polarity control signal POLC1 is contrary with the second polarity control signal POLC2 phase place, and the source signal voltage driven to make at least two source drive unit 103 realizes reversal of poles.
Concrete, timing control unit 101 and Polarity Control unit 102 can be multiple electronic component, in embodiments of the present invention, timing control unit 101 is the explanations carried out for timing controller TCON, and Polarity Control unit 102 can be integrated on timing controller TCON equally.Certainly, this also only illustrates, other circuit units that can realize above-mentioned functions or electronic component can be adopted equally as timing control unit 101 and Polarity Control unit 102, and the present invention does not limit this.
One of mode: the array base palte that the embodiment of the present invention provides can also adopt structure as shown in Figure 3, wherein, in the n-th row pixel cell row 130, the thin film transistor (TFT) of each pixel cell 13 in the first pixel cell group 131 is all connected with 2n-1 column data line, and the thin film transistor (TFT) of each pixel cell 13 in the second pixel cell group 132 is all connected with 2n column data line.
2n column data line is disposed adjacent with 2n+1 column data line between two row pixel cell row 130.
Wherein, n is natural number, and n is less than or equal to the half of pixel cell row 130 quantity in array base palte.
Concrete, the polarity of voltage of 2n-1 column data line can be contrary with the polarity of voltage of 2n column data line, and the polarity of voltage of 2n column data line can be identical with the polarity of voltage of 2n+1 column data line.
A kind of like this data line of structure is adopted to design, by within a frame period, the 2n column data line arranged respectively to adjacent, parallel and 2n+1 column data line input the voltage signal of identical polar, and the polarity of voltage that namely can realize the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.Owing to adopting two adjacent column data lines respectively to the partial pixel unit group input drive signal in two pixel cell row, therefore the reliability that signal drives can greatly be improved, in addition, two adjacent column data line input signal polarity are identical, also can avoid the crosstalk produced owing to there is polarity difference between data line further, further increase the quality of display device.
In embodiments of the present invention, the first source drive unit 1031 can the first area of corresponding viewing area, and the second source drive unit 1032 can the second area of corresponding described viewing area, and wherein, the first area of viewing area does not overlap with second area.
It is contrary that first source drive unit 1031 inputs source electrode signal voltage order of polarity to data line input source electrode signal voltage polarity and the second source drive unit 1032 to data line.
Wherein, the first area of viewing area or second area comprise many spaced data lines respectively.In first area in viewing area or the second area in viewing area, the polarity of voltage of 2n-1 column data line can be adopted equally contrary with the polarity of voltage of 2n column data line, the data entry mode that the polarity of voltage of 2n column data line is identical with the polarity of voltage of 2n+1 column data line.
Concrete, display driver circuit 10 as shown in Figure 2 can be adopted to drive array base palte as shown in Figure 3.Wherein, 2n is comprised for exporting a left side half side region of source drive unit 103, n first corresponding viewing areas of source drive unit 1031 of source electrode signal voltage, the right side half side region of all the other n the second corresponding viewing areas of source drive unit 1032.Such as: D-IC_1 ... D-IC_n is positioned at left half side region, D-IC_n+1 ... D-IC_2n is positioned at right half side region, and each D-IC connects 4 data lines.
The input/output signal relation of source drive unit 103 as shown in Figure 4, as can be seen here, repeat to export by the order controlling the first polarity inversion signal POL1, namely the second polarity inversion signal POL2 and polarity control signal POLC can realize source drive unit 103.
Such as, with reference to figure 4, timing control unit 101 can to the second polarity inversion signal POL2 of the first polarity inversion signal POL1 of each source drive unit 103 input high level (H) and low level (L).
Polarity Control unit 102 can to the first polarity control signal POLC1 of source drive unit 103 input high level (H) of a left side half side region being positioned at viewing area, to the second polarity control signal POLC2 of source drive unit 103 input low level (L) of the right side half side region being positioned at viewing area.
Signal relation according to Fig. 4, at N frame, as POLC=H, POL1=H, POL2=L, can make the source drive unit 103 of a left side half side region being arranged in viewing area left half side area data line OUT_4n+1 to OUT_4n+4 input source electrode signal voltage polarity from left to right by the order repeated arrangement (shown in dotted line frame as lower in Fig. 4) of positive and negative negative just (+--+); As POLC=L, POL1=H, POL2=L, can make the source drive unit 103 of the right side half side region being arranged in viewing area to the right half side area data line OUT_4n+1 to OUT_4n+4 input source electrode signal voltage polarity from left to right by the order repeated arrangement (as shown in dotted line frame Fig. 4 on) of negative positive and negative (-++-), corresponding source drive unit 103 outputs signal can be as shown in Figure 5.Adopt above-mentioned drive singal, at least part of viewing area can realize some inversion effect as shown in Figure 6.
At N+1 frame, timing control unit 101 and Polarity Control unit 102 all reverse to source drive unit 103, reverse to make source drive unit 103 output signal, and then data line signal is reversed, achieve at least part of viewing area point inversion effect equally.
The like, the voltage generation primary voltage reversal of poles of each frame data line.Namely in each frame, the polarity of voltage of each data line, without the need to repeatedly there is saltus step, therefore effectively can reduce the power consumption in array base palte driving process.
Mode two: the array base palte that the embodiment of the present invention provides can also adopt structure as shown in Figure 3, wherein, in the n-th row pixel cell row 130, the thin film transistor (TFT) of each pixel cell 13 in the first pixel cell group 131 is all connected with 2n-1 column data line, and the thin film transistor (TFT) of each pixel cell 13 in the second pixel cell group 132 is all connected with 2n column data line.
2n column data line is disposed adjacent with 2n+1 column data line between two row pixel cell row 130.
Wherein, n is natural number, and n is less than or equal to the half of pixel cell row 130 quantity in array base palte.
Signal relation according to Fig. 4, at N frame, as POL1=H, POL2=L, can make the source drive unit 103 of a left side half side region being arranged in viewing area left half side area data line OUT_4n+1 to OUT_4n+4 input source electrode signal voltage polarity from left to right by the order repeated arrangement (shown in dotted line frame as lower in Fig. 4) of positive and negative negative just (+--+); As POL1=L, POL2=H, can make the source drive unit 103 of the right side half side region being arranged in viewing area to the right half side area data line OUT_4n+1 to OUT_4n+4 input source electrode signal voltage polarity from left to right by the order repeated arrangement (as shown in dotted line frame on Fig. 4) of negative positive and negative (-++-), corresponding source drive unit 103 signal can be as shown in Figure 5.Now, the source drive unit input POLC=H of Polarity Control unit 102 half side region left, the source drive unit input POLC=L of right half side region, then by the effect of Polarity Control unit 102, all present on the data line+--++--+... +--+, namely according to+--+order repeated arrangement.Adopt above-mentioned drive singal, viewing area can realize some inversion effect as shown in Figure 6.At N+1 frame, timing control unit 101 and Polarity Control unit 102 all reverse to source drive unit 103, reverse to make source drive unit 103 output signal, and then data line signal is reversed, achieve at least part of viewing area point inversion effect equally.
At N+1 frame, timing control unit 101 and Polarity Control unit 102 all reverse to source drive unit 103 input signal, reverse to make source drive unit 103 output signal, and then data line signal is reversed, achieve the some inversion effect of at least part of viewing area equally.
The like, the voltage generation primary voltage reversal of poles of each frame data line.Namely in each frame, the polarity of voltage of each data line, without the need to repeatedly there is saltus step, therefore effectively can reduce the power consumption in array base palte driving process.
Adopt above-mentioned arbitrary drive singal mode, point inversion effect as shown in Figure 6 all can be realized at least part of viewing area, wherein, each row pixel cell row respectively corresponding a kind of color, it is red that 3 adjacent row pixel cells row are respectively corresponding R(), G(is green), B(is blue) three kinds of pixel cells.In same row pixel cell row, the the first pixel cell group be disposed adjacent can input identical gate drive signal with the pixel cell in the second pixel cell group, as shown in Figure 6, grid line G1 can input identical gate drive signal with grid line G2, and grid line G3 and grid line G4 can input identical gate drive signal.Wherein, show as and adopt oblique interstitial wire to represent lower than the pixel electrode in the pixel cell of reference level value, these pixel cells will be not luminous accordingly, and higher than the pixel electrode in the pixel cell of reference level value without interstitial wire, these pixel cells are by luminescence.Can be clear that, the polarity of voltage of the pixel cell in adopt above-mentioned drive singal to realize pixel cell group that the pixel cell in each pixel cell group is adjacent is contrary.In addition, in array base palte as shown in Figure 6, because adjacent rows pixel cell group connects different data lines respectively, grid line corresponding to adjacent rows pixel cell group can input the crosstalk that identical gate drive signal also can not occur in the ranks, so, effectively can reduce quantity and the sweep frequency of grid line, thus the design difficulty of array base palte can be reduced, reduce the power consumption in array base palte driving process further.
Further, in embodiments of the present invention, as shown in Figure 6, the square-wave signal that two groups of adjacent gate drive signals can adopt the cycle identical, and the delay of semiperiod between two groups of square-wave signals, can be had.Concrete, when the half moment of grid line G1 and grid line G2 input high level gate drive signal, grid line G3 and grid line G4 starts the input carrying out high level gate drive signal.So, because next group gate drive signal inputs corresponding grid line in advance, thus precharge can be carried out for corresponding pixel cell, and now these pixel cells not output display signal, after upper one group of gate drive signal has scanned, the pixel cell driven by next group gate drive signal can open pixel cell rapidly, thus can improve the response speed of display panel significantly, substantially increases the quality of display device.
It should be noted that, the selection of above-mentioned drive singal also only illustrates, in the process that reality uses, can change the polarity of voltage of drive singal as required.In embodiments of the present invention, be respectively R(redness with three pixel cells that level is adjacent), G(is green), B(is blue) three kinds of pixel cells be combined as the explanation that example carries out.
In the above-described embodiments, the polarity of voltage of the pixel cell that each pixel cell in each frame period on array base palte is all adjacent is contrary, namely adopts some reversion (1DOT) mode.Should expect, the above is also only the explanation carried out in 1DOT mode, and the array base palte described in the embodiment of the present invention can also adopt multiple some inversion mode.Such as, in array base palte as shown in Figure 7, be the explanation carried out with 2 reversion (2DOT) inversion modes.Wherein, the first pixel groups 131 and the second pixel groups 132 all can comprise 2 pixel cells 13 of longitudinal arrangement.
Concrete, when pixel cell 13 quantity contained by the first pixel groups 131 and the second pixel groups 132 increases, similar with Fig. 6, in same row pixel cell row, the first pixel cell group be disposed adjacent can input identical gate drive signal with the pixel cell in the second pixel cell group.So, greatly can reduce quantity and the sweep frequency of grid line, realize low-power consumption and drive.But along with the increase of pixel cell 13 quantity contained by the first pixel groups 131 and the second pixel groups 132, point inversion mode will level off to line inversion mode more, signal in identical voltage polar orientation also more easily will produce interference, therefore in the process of practical application, when pixel cell 13 quantity contained by the first pixel groups 131 and the second pixel groups 132 can be selected as required.Should be appreciated that in embodiments of the present invention, is the explanation that 2 pixel cells 13 that all can comprise longitudinal arrangement for the first pixel groups 131 and the second pixel groups 132 carry out, and the restriction not the present invention done.
After a frame scan terminates, for driving the source signal voltage of pixel cell, total polar is reversed.Thus guarantee that the liquid crystal molecule in pixel cell region can not polarize because of long-term electric field action.
A kind of liquid crystal display that the embodiment of the present invention provides, this liquid crystal display comprises array base palte as above.
It should be noted that display device provided by the present invention can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer.
Wherein, the structure of array base palte has done detailed description in the aforementioned embodiment, repeats no more herein.
The embodiment of the present invention also provides a kind of liquid crystal display, comprise array base palte, this array base palte comprises multiple pixel cell row, a row pixel cell along the arrangement of data line direction forms pixel cell row, spaced multiple first pixel cell group and the second pixel cell group is comprised again in each described pixel cell row, wherein in different pixels unit group, the connection of pixel cell is different, thus can to realize the polarity of voltage of the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent contrary by inputting specific source signal voltage to different data lines.So, because the polarity of voltage between adjacent pixel unit is contrary, thus the polarity of can cancel each other out bias voltage, the voltage on equilibrium liquid LCD panel between each pixel cell, significantly improve flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that namely can realize between adjacent pixel unit is contrary, adopt a kind of like this array base palte of structure due in each frame the polarity of voltage of each data line without the need to repeatedly there is saltus step, therefore effectively can reduce the power consumption in array base palte driving process.
The embodiment of the present invention also provides a kind of array base palte driving method, and for driving array base palte as above, as shown in Figure 8, described method comprises:
S801, display driver circuit are to data line input source electrode signal voltage.
S802, source signal voltage drive the pixel cell be connected with this data line by data line, to make two adjacent at least partly row pixel cell column voltage polarity contrary; And in same row pixel cell row, the first pixel cell group is contrary with the second pixel cell group polarity of voltage.
Wherein, the row pixel cell along the arrangement of data line direction forms pixel cell row, and each pixel cell row comprise multiple first pixel cell group and the second pixel cell group of spaced setting; The thin film transistor (TFT) of the pixel cell in the first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the pixel cell in the second pixel cell group is connected with another adjacent data line.Such as: the first pixel cell group and the second pixel cell group comprise the pixel cell of equal number; The thin film transistor (TFT) of each pixel cell in the first pixel cell group is all connected with the first data line, and the thin film transistor (TFT) of each pixel cell in the second pixel cell group is all connected with the second data line.
So a kind of array base palte driving method that the embodiment of the present invention provides, array base palte comprises multiple pixel cell row, a row pixel cell along the arrangement of data line direction forms pixel cell row, spaced multiple first pixel cell group and the second pixel cell group is comprised again in each described pixel cell row, wherein in different pixels unit group, the connection of pixel cell is different, thus can by inputting specific source signal voltage to different data lines, the polarity of voltage realizing the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.So, because the polarity of voltage between adjacent pixel unit is contrary, thus the polarity of can cancel each other out bias voltage, the voltage on equilibrium liquid LCD panel between each pixel cell, significantly improve flicker and color offset phenomenon.On the other hand, within a frame period, the data line of same pixel cell row is by the opposite polarity source signal voltage of difference input voltage, the polarity of voltage that namely can realize between adjacent pixel unit is contrary, adopt a kind of like this array base palte of structure due in each frame the polarity of voltage of each data line without the need to repeatedly there is saltus step, therefore effectively can reduce the power consumption in array base palte driving process.
Further, display driver circuit specifically can comprise to data line input source electrode signal voltage:
Timing control unit inputs the first polarity inversion signal and the second polarity inversion signal at least two source drive unit, first polarity inversion signal is contrary with the second polarity inversion signal phase place, to make at least two source drive unit to data line input source electrode signal voltage.
Polarity Control unit inputs the first polarity control signal to the first source drive unit, the second polarity control signal is inputted to the second source drive unit, first polarity control signal is contrary with the second polarity control signal phase place, and the source signal voltage driven to make at least two source drive unit realizes reversal of poles.
Wherein, at least two source drive unit comprise at least one first source drive unit and at least one second source drive unit, and each source drive unit connects at least one data line respectively.
It should be noted that, in embodiments of the present invention, the structure of at least one first source drive unit and at least one the second source drive unit is just the same, the difference of the two is, first source drive unit is not identical with the polarity control signal received by the second source drive unit, thus make the two export the source signal voltage with different polarity of voltage respectively, in order to distinguish the different voltage output end of this two kinds of polarity, at least one first source drive unit of called after and at least one second source drive unit can be distinguished.
Further, the array base palte that the embodiment of the present invention provides can also adopt structure as shown in Figure 3, wherein, in the n-th row pixel cell row, described in each in first pixel cell group, the thin film transistor (TFT) of pixel cell is all connected with 2n-1 column data line, and the thin film transistor (TFT) of each pixel cell in the second pixel cell group is all connected with 2n column data line.
2n column data line is disposed adjacent between two row pixel cells arrange with 2n+1 column data line.
Wherein, n is natural number, and n is less than or equal to the half of the number of columns of pixel cell described in array base palte.
Concrete, the polarity of voltage of 2n-1 column data line can be contrary with the polarity of voltage of 2n column data line, and the polarity of voltage of 2n column data line can be identical with the polarity of voltage of 2n+1 column data line.
A kind of like this data line of structure is adopted to design, by within a frame period, the polarity of voltage that namely voltage signal that the 2n column data line arranged respectively to adjacent, parallel and 2n+1 column data line input identical polar can realize the pixel cell in the pixel cell group that the pixel cell at least part of pixel cell group is adjacent is contrary.Owing to adopting two adjacent column data lines respectively to the partial pixel unit group input drive signal in two pixel cell row, therefore the reliability that signal drives can greatly be improved, in addition, two adjacent column data line input signal polarity are identical, also can avoid the crosstalk produced owing to there is polarity difference between data line further, further increase the quality of display device.
In embodiments of the present invention, the first source drive unit can the first area of corresponding viewing area, and the second source drive unit can the second area of corresponding described viewing area, and wherein, the first area of viewing area does not overlap with second area.
It is contrary that first source drive unit inputs source electrode signal voltage order of polarity to data line input source electrode signal voltage polarity and the second source drive unit to data line.
Concrete, display driver circuit 10 as shown in Figure 2 can be adopted to drive array base palte as shown in Figure 3.Wherein, comprise 2n for exporting the source drive unit of source electrode signal voltage, a left side half side region of n the corresponding viewing area of the first source drive unit, the right side half side region of all the other n the corresponding viewing areas of the second source drive unit.
The input/output signal relation of source drive unit as shown in Figure 4, as can be seen here, repeats to export by the order controlling the first polarity inversion signal POL1, namely the second polarity inversion signal POL2 and polarity control signal POLC can realize source drive unit.
Such as, timing control unit can to the second polarity inversion signal POL2 of the first polarity inversion signal POL1 of each source drive unit input high level (H) and low level (L).
Polarity Control unit can to the first polarity control signal POLC1 of source drive unit input high level (H) of a left side half side region being positioned at viewing area, to the second polarity control signal POLC2 of source drive unit input low level (L) of the right side half side region being positioned at viewing area.
Signal relation according to Fig. 4, the source drive unit of a left side half side region being positioned at viewing area can be made to data line input source electrode signal voltage polarity from left to right by positive and negative negative positive order repeated arrangement, polarity of voltage in pixel cell as shown in Figure 5, can make the source drive unit of the right side half side region being positioned at viewing area to data line input source electrode signal voltage polarity from left to right by negative positive and negative order repeated arrangement.
Further, the array base palte driving method that the embodiment of the present invention provides can also be applicable to 2DOT inversion mode.Such as, the first pixel groups and the second pixel groups all can comprise 2 pixel cells of longitudinal arrangement.Concrete driving method can be as previously mentioned.Adopt a kind of like this driving method greatly can reduce quantity and the sweep frequency of grid line, realize low-power consumption and drive.
After a frame scan terminates, for driving the source signal voltage of pixel cell, total polar is reversed.Thus guarantee that the liquid crystal molecule in pixel cell region can not polarize because of long-term electric field action.
One of ordinary skill in the art will appreciate that: having arranged of the hardware that all or part of flow process realizing said method embodiment can be correlated with by computer program instructions and hardware associated peripheral circuits, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium to be USB flash disk, portable hard drive, ROM (read-only memory) (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (13)
1. an array base palte, is characterized in that, the multiple pixel cells comprising display driver circuit and formed by transverse and longitudinal many grid lines arranged in a crossed manner and data line;
A row pixel cell along the arrangement of data line direction forms pixel cell row, and described pixel cell row comprise multiple first pixel cell group and the second pixel cell group of spaced setting;
The thin film transistor (TFT) of the described pixel cell in described first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described second pixel cell group is connected with another adjacent data line;
Described display driver circuit is used for data line input source electrode signal voltage, to make the described pixel cell column voltage polarity of two row adjacent at least partly contrary; And in the described pixel cell row of same row, described first pixel cell group is contrary with the second pixel cell group polarity of voltage;
Described display driver circuit comprises timing control unit, Polarity Control unit and at least two source drive unit;
Described at least two source drive unit comprise at least one first source drive unit and at least one second source drive unit, and described in each, source drive unit connects at least one described data line respectively;
Described timing control unit, for inputting the first polarity inversion signal and the second polarity inversion signal to described at least two source drive unit, described first polarity inversion signal and described second polarity inversion signal phase place are contrary, with at least two source drive unit described in making to described data line input source electrode signal voltage;
Described Polarity Control unit, for inputting the first polarity control signal to described first source drive unit, the second polarity control signal is inputted to described second source drive unit, described first polarity control signal and described second polarity control signal phase place are contrary, realize reversal of poles with the source signal voltage that at least two source drive unit described in making drive.
2. array base palte according to claim 1, is characterized in that, the first area of the corresponding viewing area of described first source drive unit, the second area of the corresponding described viewing area of described second source drive unit;
It is contrary that described first source drive unit inputs source electrode signal voltage order of polarity to described data line input source electrode signal voltage polarity and described second source drive unit to described data line.
3. array base palte according to claim 1 and 2, it is characterized in that, in the described pixel cell row of the n-th row, described in each in described first pixel cell group, the TFT of pixel cell is all connected with 2n-1 column data line, and described in each in described second pixel cell group, the TFT of pixel cell is all connected with 2n column data line;
2n column data line is disposed adjacent with 2n+1 column data line and arranges between described pixel cell arranges in two;
Wherein, described n is natural number, and described n is less than or equal to the half of pixel cell number of columns described in described array base palte.
4. array base palte according to claim 3, is characterized in that,
The polarity of voltage of described 2n-1 column data line is contrary with the polarity of voltage of described 2n column data line;
The polarity of voltage of described 2n column data line is identical with the polarity of voltage of described 2n+1 column data line.
5. array base palte according to claim 1, is characterized in that,
In the described pixel cell row of same row, the described first pixel cell group be disposed adjacent inputs identical gate drive signal with the pixel cell in described second pixel cell group.
6. array base palte according to claim 1, is characterized in that, described first pixel cell group and described second pixel cell group comprise the described pixel cell of equal number;
Described first pixel groups and described second pixel groups include 2 described pixel cells of longitudinal arrangement.
7. a liquid crystal display, is characterized in that, described liquid crystal display comprises the array base palte according to any one of claim 1-6.
8. an array base palte driving method, for drive as arbitrary in claim 1-6 as described in array base palte, it is characterized in that, described method comprises:
Display driver circuit is to data line input source electrode signal voltage;
Described source signal voltage drives the pixel cell be connected with described data line by described data line, to make two adjacent at least partly row pixel cell column voltage polarity contrary; And in the described pixel cell row of same row, the first pixel cell group is contrary with the second pixel cell group polarity of voltage;
Wherein, the described pixel cell of row along the arrangement of data line direction forms described pixel cell row, and described pixel cell row comprise the multiple described first pixel cell group of spaced setting and described second pixel cell group; The thin film transistor (TFT) of the described pixel cell in described first pixel cell group is connected with a data line, and the thin film transistor (TFT) of the described pixel cell in described second pixel cell group is connected with another adjacent data line;
Described display driver circuit comprises to data line input source electrode signal voltage:
Timing control unit inputs the first polarity inversion signal and the second polarity inversion signal at least two source drive unit, described first polarity inversion signal and described second polarity inversion signal phase place are contrary, with at least two source drive unit described in making to described data line input source electrode signal voltage;
Described Polarity Control unit inputs the first polarity control signal to the first source drive unit, the second polarity control signal is inputted to the second source drive unit, described first polarity control signal and described second polarity control signal phase place are contrary, realize reversal of poles with the source signal voltage that at least two source drive unit described in making drive;
Wherein, described at least two source drive unit comprise the first source drive unit described at least one and the second source drive unit described at least one, and described in each, source drive unit connects at least one described data line respectively.
9. array base palte driving method according to claim 8, is characterized in that, the first area of the corresponding viewing area of described first source drive unit, the second area of the corresponding described viewing area of described second source drive unit;
It is contrary that described first source drive unit inputs source electrode signal voltage order of polarity to described data line input source electrode signal voltage polarity and described second source drive unit to described data line.
10. array base palte driving method according to claim 8 or claim 9, it is characterized in that, in the described pixel cell row of the n-th row, described in each in described first pixel cell group, the TFT of pixel cell is all connected with 2n-1 column data line, and described in each in described second pixel cell group, the TFT of pixel cell is all connected with 2n column data line;
2n column data line is disposed adjacent with 2n+1 column data line and arranges between described pixel cell arranges in two;
Wherein, described n is natural number, and described n is less than or equal to the half of pixel cell number of columns described in described array base palte.
11. array base palte driving methods according to claim 10, is characterized in that,
The polarity of voltage of described 2n-1 column data line is contrary with the polarity of voltage of described 2n column data line;
The polarity of voltage of described 2n column data line is identical with the polarity of voltage of described 2n+1 column data line.
12. array base paltes according to claim 10, is characterized in that,
In the described pixel cell row of same row, the described first pixel cell group be disposed adjacent inputs identical gate drive signal with the pixel cell in described second pixel cell group.
13. array base palte driving methods according to claim 8, is characterized in that, described first pixel cell group and described second pixel cell group comprise the described pixel cell of equal number;
Described first pixel groups and described second pixel groups include 2 described pixel cells of longitudinal arrangement.
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| CN104090438B (en) | 2014-06-27 | 2016-08-17 | 京东方科技集团股份有限公司 | Array base palte, display device and driving method thereof |
| CN105093737A (en) * | 2015-07-28 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display |
| CN105185326B (en) * | 2015-08-12 | 2017-10-17 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel and its drive circuit |
| CN105182638A (en) | 2015-08-28 | 2015-12-23 | 重庆京东方光电科技有限公司 | Array substrate, display device and drive method thereof |
| CN106571122A (en) * | 2015-10-12 | 2017-04-19 | 群创光电股份有限公司 | Display device and drive method thereof |
| CN105278133A (en) * | 2015-10-27 | 2016-01-27 | 深超光电（深圳）有限公司 | Liquid crystal display device |
| CN106782404A (en) * | 2017-02-03 | 2017-05-31 | 深圳市华星光电技术有限公司 | Pixel driving framework and liquid crystal display panel |
| CN107463016A (en) * | 2017-09-22 | 2017-12-12 | 京东方科技集团股份有限公司 | A kind of array base palte and its driving method, display panel, display device |
| CN109285514B (en) * | 2018-10-31 | 2021-01-08 | 惠科股份有限公司 | Display panel manufacturing method, display panel and display device |
| CN109346020B (en) * | 2018-11-26 | 2020-06-02 | 深圳市华星光电半导体显示技术有限公司 | Display driving method and liquid crystal display device |
| CN109599072B (en) * | 2018-12-18 | 2021-04-02 | 惠科股份有限公司 | Display device, driving method and display |
| CN110379382A (en) * | 2019-06-06 | 2019-10-25 | 惠科股份有限公司 | Display panel, driving method thereof and display device |
| CN113219745B (en) * | 2021-04-20 | 2022-07-05 | 北海惠科光电技术有限公司 | Display panel, display device, and driving method of display panel |
| CN113223474A (en) * | 2021-04-30 | 2021-08-06 | 北海惠科光电技术有限公司 | Display panel driving circuit and driving method |
| CN113781971A (en) * | 2021-08-05 | 2021-12-10 | 合肥维信诺科技有限公司 | Display panel driving method and display panel |
| CN113674672B (en) * | 2021-08-18 | 2023-06-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel driving method and display panel |
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