JP2003167556A - Matrix type display device, and driving control device and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress power consumption by reducing charge/discharge to parasitic capacitance between pixel electrodes. <P>SOLUTION: Before writing signals, display signal of the negative polarity are held in all the pixel electrodes 409. For a 1st selection period, all the time- division switches 404 are brought into the ON state, to write R-corresponding display signals of the negative polarity to all the pixel electrodes 409. For a 2nd selection period, only the R-corresponding time-division switches (SW1, SW4,...) are brought into the OFF state, to write G-corresponding display signals of the negative polarity to G- and B-corresponding pixel electrodes (S2, S3, S5, S6,...) while making the R-corresponding pixel electrodes (S1, S4,...) holds the R-corresponding display signals. For a 3rd selection period, the G- corresponding time-division switches (SW2, SW5,...) are further kept at the OFF state, to write B-corresponding signals of the negative polarity to the B-corresponding pixel electrodes (S3, S6,...) while making the G-corresponding pixel electrodes (S2, S5,...) hold the G-corresponding display signals. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device having a plurality of drain lines and a plurality of gate lines which are orthogonal to each other, and a matrix type display section in which pixel electrodes are provided at intersections thereof. The present invention relates to a drive control device and a drive control method thereof.

[0002]

2. Description of the Related Art The field effect mobility of poly-Si is about 0.5 to 1 c which is the field effect mobility of amorphous Si.
Compared to m2 / Vs, it is as large as about several tens to 200 cm2 / Vs. Therefore, p is formed on the same substrate on which the liquid crystal display unit is formed.
By using the oli-Si TFT, a small and practical peripheral circuit such as a signal circuit or a scanning circuit can be formed. Further, by forming the peripheral circuit and the liquid crystal display section on the same substrate by using the poly-Si TFT, it is possible to reduce an interval between adjacent wirings in the wiring connection between the external peripheral circuit such as the driver IC and the liquid crystal display section. For the above reasons, it becomes possible to realize a high-resolution liquid crystal display device. However, when realizing a high-resolution and high-definition liquid crystal display device, the clock frequency of peripheral circuits, especially the signal circuit, becomes as high as several tens of MHz. Further, the operating frequency of the peripheral circuit using the poly-Si TFT is about several MHz to about 10M.
Since it is as low as about Hz, it is difficult to realize a high-resolution liquid crystal display device in which peripheral circuits are formed around the liquid crystal display section.

Therefore, as a method for realizing a high-resolution and high-definition liquid crystal display device using a poly-Si TFT, for example, a time division switch provided on the same substrate as the liquid crystal display section and a driver IC are used. An RGB time division driving method has been proposed. This method is disclosed in Japanese Patent Laid-Open No. 2000-2756.
As described in Japanese Patent No. 11, a driver IC is used as a signal circuit that requires high-speed operation. The driver IC can operate at a high frequency of several tens of MHz and can output a plurality of display signals collectively. In this RGB time division drive type liquid crystal display device, a driver I is provided through a time division switch provided on the same substrate as the liquid crystal display section.
One output terminal C is connected to three drain lines (drain lines corresponding to R, G, and B pixels) included in the liquid crystal display unit. In the RGB time division driving method, one horizontal period is time-divided into three periods, and one type of drain line is sequentially selected from three types of drain lines corresponding to RGB in each period. Then, the driver IC outputs the display data corresponding to the drain line selected by the time division switch from the output terminal. As a result, the liquid crystal in the liquid crystal panel is applied with the display signal corresponding to the display data,
Gradation display is realized. As described above, in the RGB time division driving method, since signals are output from one output terminal of the driver IC to three drain lines, the driver I
The number of C output terminals can be set to 1/3 of the number of drain lines (= number of horizontal pixels) of the liquid crystal display unit, and the number of driver ICs can be reduced as compared with the conventional line-sequential drive method. Become. In addition, the number of connection terminals between the driver IC and the substrate on which the liquid crystal display section and the time division switch are formed can be reduced to 1/3 of that of the conventional line-sequential drive method.
It becomes possible to realize a liquid crystal display device with higher definition and higher resolution.

Here, the liquid crystal display device disclosed in Japanese Patent Laid-Open No. 2000-275611 will be described in detail with reference to FIGS.

First, the structure of a conventional active matrix type liquid crystal display device will be described with reference to FIG.

In FIG. 1, 101 is a driver IC, and 102 is a liquid crystal panel 103 which outputs a display signal output from the driver IC (a positive [high] signal or a negative [low] signal with respect to the potential of the counter electrode). To the display signal line group (DR1, DR2, DR3, ...) The display signal line group 102 includes a time divisional switch group 104 (SW1, S
Drain line group 1 via W2, SW3, SW4, ...)
05 (D1, D2, D3, D4, ...). One display signal line DR has three time division switches S
The drain line D is connected to each of the three time divisional switches. For example, the display signal line DR1
Are connected to the drain lines D1, D2 and D3 via three adjacent time divisional switches SW1, SW2 and SW3. Further, the display signal lines DR2 and DR3 are
Similarly, it is connected to each drain line via the time divisional switch 104. In this case, the number of display signal outputs (= the number of display signal lines) of the driver IC 101 in the RGB time division driving can be set to 1/3 of the number of horizontal pixels of the liquid crystal panel 103. It should be noted that each of the RGB light emitting units is often set as one pixel, but in the present specification, each of the RGB light emitting units is defined as one pixel.
A gate scanning circuit 106 sequentially selects the gate scanning line group 107 (G1, G2, G3, ...). The number of gate scanning lines G is basically the number of pixels in the vertical direction of the liquid crystal panel.

Gate scan line group 107 and drain line group 10
A switch element 108 including, for example, an nMOS-TFT is disposed near each intersection with the switch 5. The gate of the switch element 108 is connected to the gate scanning line G,
The drain is connected to the drain line D, and the source is connected to the pixel electrode 109. The liquid crystal 110 is the pixel electrode 10
9 and the counter electrode 113. The voltage applied to the liquid crystal 110 is determined by the potential difference between the counter electrode 113 and the pixel electrode 109, and the liquid crystal display device performs gradation display by controlling this potential difference. In addition, in FIG.
Is a parasitic capacitance generated between adjacent pixel electrodes.

Next, the display operation of the liquid crystal display device described above will be described with reference to FIGS. 2 and 3.

The gate scanning circuit 106 sequentially selects the gate scanning lines G every horizontal period. If the gate scanning voltage is at the Hi level, the switching element 108 on the gate scanning line G
Is in the ON state. In RGB time-division driving, one horizontal period is time-divided into three periods. For example, the first first selection period is the R display signal writing period, the second second selection period is the G display signal writing period, and the last. The third selection period becomes the B display signal writing period. The driver IC 101 outputs a display signal corresponding to RGB so as to correspond to each period. Specifically, as shown in FIG. 3A, all the time divisional switches SW1, SW2, ... Are OFF before writing. Driver IC in the first selection period
Drain lines D1 and D1 in which the display signal of 101 corresponds to R
2 and 3 (b) so as to be supplied to 4, D7, ...
As shown in FIG.
4, SW7, ... Are selected and turned on. As a result, in the first selection period, the display signal corresponding to the display data of R is written in the pixel electrode 109 (S1) corresponding to R, and at the same time, the pixels corresponding to all R on one horizontal line are written. A display signal (negative polarity) corresponding to the display data is written. As a result, as shown in FIG. 2, the pixel electrode 109 (S1) corresponding to R changes from the positive potential to the negative potential. Similarly, in the second selection period, as shown in FIGS.
As shown in (c), the display signal of the driver IC 101 is supplied to the drain lines D2, D5, D8, ...
Only SW8, ... Are selected and turned on, and the display signal (negative polarity) corresponding to the display data of G is written in the pixel electrode 109 (S2) corresponding to G. In the third selection period, as shown in FIGS. 2 and 3D, the drain line D3 corresponding to the display signal of the driver IC 101 is B3.
As supplied to D6, D9, ..., Only the time divisional switches SW3, SW6, SW9, ... Corresponding to B are selected and turned on, and the pixel electrode 109 (S3) corresponding to B is selected.
, A display signal (negative polarity) corresponding to the display data of B is written. When the display signals corresponding to the display data are written in all the pixels on one horizontal line, the gate scanning circuit 1
By 06, the gate lines are sequentially selected, and the operation described above is repeated every time the gate lines are selected, and display for one frame is performed. The display for one frame is completed,
In the display control of the next frame, in order to prevent burn-in deterioration of the liquid crystal 110, a display signal having a polarity opposite to the potential of the counter electrode is written.

As shown in FIG. 2, the potential S1 of the pixel electrode corresponding to R is, for example, when the pixel electrode potential before writing is higher than the counter electrode potential, and the display signal supplied at the time of writing is the counter electrode. Since the negative polarity is lower than the potential,
The change in the potential S1 of the pixel electrode 109 corresponding to R in the first selection period becomes relatively large. Also, the second
The potential S of the pixel electrode 109 corresponding to G in the selection period
The change of 2 and the change of the potential S3 of the pixel electrode 109 corresponding to B in the third selection period are both relatively large. The amount of change in potential of the pixel electrode 109 is
The same applies to the case where the potential of the pixel electrode 109 before writing is negative and lower than the potential of the counter electrode.

[0011]

By the way, in the first selection period, as shown in FIG. 2B, SW1, SW4 and SW7 of the time divisional switch 104 are selected and turned on.
When a negative display signal is written from the drain lines D1, D4, D7 to the corresponding pixel electrode 109 in the N state, the potentials of the two pixel electrodes adjacent to the pixel electrode in which the negative display signal is written. Remains positive, charging / discharging of the inter-pixel electrode parasitic capacitance 111 (FIG. 2A) occurs. In addition, as described above, the potential variation amount of the pixel electrode changes because the pixel electrode potential changes from the positive polarity display signal to the negative polarity display signal or from the negative polarity display signal to the positive polarity display signal. large. Therefore, the charging / discharging current to the pixel electrode parasitic capacitance 111 becomes large. Such charging / discharging of the inter-pixel electrode parasitic capacitance 111 similarly occurs in the second and third selection periods.

Since the charge / discharge current of the parasitic capacitance 111 between the pixel electrodes is supplied from the driver IC 101, the charge / discharge power consumption of the panel increases, and finally the power consumption of the liquid crystal display device increases. Further, when the charge / discharge to the inter-pixel electrode parasitic capacitance 111 is large, the pixel electrode 109 cannot be raised to the target potential, and the target luminance cannot be obtained. That is, the conventional technique has a problem that the power consumption is large and the target brightness cannot be obtained.

The present invention focuses on such problems of the prior art, and provides a display device, a drive control device and a drive control method thereof, which can suppress power consumption and obtain a brightness extremely close to a target brightness. To aim.

[0014]

A drive control device for achieving the above object is a matrix in which a plurality of drain lines and a plurality of gate lines orthogonal to each other and pixel electrodes are provided corresponding to their intersections. In a drive control device for a mold display section, a display signal output unit that outputs a display signal in a time series corresponding to a predetermined number of time divisions to the plurality of pixel electrodes via the plurality of drain lines; For each drain line, a time divisional switch provided in each drain line, and a switch control means for controlling the operation of the plurality of time divisional switches, the switch control means, the gate line is extended. Of the plurality of pixel electrodes arranged in the same direction (hereinafter referred to as the horizontal direction), one horizontal direction period is set so that the potential difference between adjacent pixel electrodes becomes small. In the first selection period of the plurality of selection periods divided by the number of divisions, all the time divisional switches are turned on in the first selection period, and all the pixel electrodes arranged in the horizontal direction are output from the display signal output unit. A voltage corresponding to a display signal or a voltage close thereto is applied, and then a predetermined time divisional switch among a plurality of time divisional switches is sequentially turned on and / or off to all the pixels in each selection period. It is characterized in that the target voltage is held in all of the plurality of pixel electrodes while maintaining a state in which a voltage corresponding to the display signal is applied to the electrodes.

Here, in the drive control device, the display signal output means sequentially outputs display signals corresponding to a predetermined plurality of pixel electrode groups to the plurality of pixel electrodes during each selection period. , The switch control means turns on all time divisional switches in the first selection period,
After that, at the end of each selection period including the first selection period, the time-division switch group connected to one pixel electrode group of the predetermined plurality of pixel electrode groups is sequentially
The pixel electrode group may be turned off to hold a voltage corresponding to the corresponding display signal, and the display signal output means may be a plurality of pixels which are predetermined for the plurality of pixel electrodes. The corresponding display signal to the pixel electrode group of is output during each selection period, the switch control means turns on all the time-division switches in the first selection period, and in each subsequent selection period, Only the time divisional switch group connected to one pixel electrode group among a plurality of predetermined pixel electrode groups is sequentially turned on so that each pixel electrode group holds the voltage corresponding to the corresponding display signal. It may be one.

Further, a display device for achieving the above object is characterized by including the above drive control device and the matrix type display section which is drive-controlled by the drive control device. is there.

Further, a drive control method for achieving the above object is a matrix display in which a plurality of drain lines and a plurality of gate lines which are orthogonal to each other and pixel electrodes are provided corresponding to their intersections. In the drive control method of the unit, a display signal output step of outputting a display signal to the plurality of pixel electrodes via the plurality of drain lines in a time series corresponding to a predetermined number of time divisions; and a plurality of the drain lines. A switch control step of controlling the operation of the time-division switch provided in each drain line, and in the switch control step, a direction in which the gate line extends (hereinafter, referred to as a horizontal direction). ), A plurality of selection periods obtained by dividing one horizontal period by the predetermined number of time divisions so that the potential difference between adjacent pixel electrodes becomes small. In the first selection period, all time divisional switches are turned on, and a voltage corresponding to the display signal from the display signal output means or a voltage close thereto is applied to all the pixel electrodes arranged in the horizontal direction. Give,
After that, a predetermined time divisional switch among the plurality of time divisional switches is sequentially turned on and / or off, and a voltage corresponding to the display signal is applied to all the pixel electrodes in each selection period. It is characterized in that the target voltage is held in all of the plurality of pixel electrodes while maintaining the state.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a display device according to the present invention will be described below with reference to the drawings.

First, a display device as a first embodiment according to the present invention will be described with reference to FIGS.

FIG. 4 is a diagram showing the structure of the active matrix type liquid crystal display device of this embodiment. In FIG. 4, reference numeral 401 denotes a driver IC, and reference numeral 402 denotes a liquid crystal panel 403 which outputs a display signal (a positive polarity [high potential] signal or a negative polarity [low potential] signal to the counter electrode potential) output from the driver IC. Signal line group 402 for transferring to
(DR1, DR2, DR3, ...). Here, the driver IC 401 outputs display signals of the same polarity to the display signal line group 402 from the even and odd terminals. The display signal line group 402 includes a time division switch group 404 (SW1, SW2, S
W3, SW4, SW5, SW6, SW7, SW8, SW9,
Via the drain line group 405 (D1, D2, D3,
D4, D5, D6, D7, D8, D9, ...). Further, the time divisional switch group 404 includes the control signal group 41.
The display signal line DR and the drain line D are connected in the ON state by controlling the ON state or the OFF state by 2
In this state, the display signal line DR and the drain line D are not connected. Here, in the case of RGB time division driving, one display signal line DR is connected to three time division switches SW, and three drain lines D are connected to these three time division switches. For example, the display signal line DR1
Is connected to the drain lines D1, D2, D3 via three time divisional switches SW1, SW2, SW3. The three drain lines D are drain lines connected to the R, G, and B pixels, respectively. In the description here, R, G, and B are assigned to the three drain lines in order from the left, but this order is not particularly limited. Similarly, the other display signal lines (DR2, DR3, ...) Also have time division switches (SW4, SW5, SW6, SW7, SW8, SW).
Via the drain lines (D4, D5, D6, D)
7, D8, D9, ...). Therefore, the total number of display signal outputs of the driver IC 401 (= the total number of display signal lines)
Is 1/3 of the number of horizontal pixels of the liquid crystal panel 403. Here, the resolution of the liquid crystal panel is set to XGA (eXtended
Graphics Array) and the number of display signal outputs of the driver IC 401 is 256, the number of horizontal pixels of XGA is 30.
72 (= 1024 × RGB), so the driver IC 40
1 requires (3072/256) pieces, that is, 4 pieces. However, the number of output terminals per driver IC 401 and the number of driver ICs 401 used in the liquid crystal display device can be arbitrarily set according to the resolution of the liquid crystal panel 403.

Display data 424 sent from the outside
Is a display control signal 425, 42 suitable for the active matrix type liquid crystal panel 403 in the drive control circuit 420.
6, which is the driver IC 40 described above.
1 and the gate operation circuit 406. The drive control circuit 420 includes a TCON (Timing Convertor) circuit 421 that converts display data 424 from the outside into a drain display control signal 425 and a gate display control signal 426, and a switch controller 422 that controls the operation of the time divisional switch group 404. , And a power supply circuit 423. TCON circuit 4
21 and the switch controller 422 are connected by a synchronization signal line 427 in order to synchronize them.

Here, the time divisional switch group 404 provided on the liquid crystal panel 403 will be described with reference to FIG. Each time division switch (SW1, SW2, ...) is nM
It is composed of one OS-TFT. The terminal on the drain side of each time division switch has a corresponding display signal line (D
, R), and the source terminal is connected to each drain line (D1, D2, ...). In addition, the gate terminal of each time division switch is the switch controller 422.
From the switch control signal line 412. R
In the case of GB time division driving, the switch control signal line 412 is 3
You need a book. Of the three control signal lines 412, one is connected to the gate terminals of the time divisional switches (SW1, SW4, SW7, ...) Provided on the drain lines (D1, D4, D7, ...) Corresponding to R. ing. Similarly, the time divisional switches (SW2, SW5,
The gate terminal of SW8,) has three control signal lines 412
Another book of which is connected. Then, the time divisional switches (SW3, S) provided on the drain line corresponding to B
The remaining one control signal line 412 is connected to the gate terminals of W6, SW9 ,. The ON / OFF control of the time divisional switch is a positive logic operation because the switch is composed of the nMOS-TFT, the time divisional switch is turned on when the switch control signal is at the Hi level, and the display signal line D
The display signal transferred from R is applied to the drain line D.
On the contrary, when the switch control signal becomes Low level, the time divisional switch is turned off, and the display signal line DR and the drain line D are not connected. The case where the time divisional switch is composed of the nMOS-TFT has been described above. However, the time divisional switch may be a pMOS-TFT or a cMOS-TFT.
It may be formed of a TFT or the like. Time division switch is pMO
In the case of the S-TFT, each control signal operates in a negative logic, and in the case of the cMOS-TFT, two switch control signal lines are connected to each time division switch ( Since the control signal and its inverted signal), the total number of control signal line groups 412 is six.

Referring again to FIG. 4, a gate scanning circuit 406 includes gate scanning line group 407 (G1, G2, G).
3, ...) are sequentially selected. This gate scanning circuit 406
Are formed of, for example, p-Si TFTs or a-Si TFTs. The number of gate scanning lines G is at least the number of pixels in the vertical direction of the liquid crystal panel. A switch element 408 including, for example, an nMOS-TFT is arranged near each intersection of the gate scanning line group 407 and the drain line group 405. This switch element 408
May be a pMOS-TFT other than the nMOS-TFT, but will be described here as an nMOS-TFT. The gate of the switch element 408 is connected to the gate scanning line G, the drain is connected to the drain line D, and the source is connected to the pixel electrode 409 (S1, S2, S3, ...).
Reference numeral 413 denotes a counter electrode formed on the other substrate, which is provided so as to face the substrate on which the pixel electrode 409 is formed. However, this is the case of a liquid crystal whose transmittance is controlled by a vertical electric field, and in the case of a liquid crystal whose transmittance is controlled by a horizontal electric field,
The counter electrode 413 is formed on the same substrate as the pixel electrode 409. The liquid crystal 410 is sandwiched between the pixel electrode 409 and the counter electrode 413. The liquid crystal 410 has a transmittance of the counter electrode 4
It is determined by the potential difference between the potential of 13 and the potential of the pixel electrode 409, and the liquid crystal display device performs gradation display by controlling this potential difference. Note that 411 is a parasitic capacitance generated between the adjacent pixel electrodes 409.

Next, the display signal writing operation for one horizontal period will be described with reference to FIGS. 6 and 7.

In this embodiment, as shown in FIG. 6, when the rising edge of the gate scanning voltage is time 0, one horizontal period of the RGB time division driving is the first time period from time 0 to time T1.
Selection period, second selection period from time T1 to time T2,
And a third selection period from time T2 to time T3 and three periods. Here, the times T1, T2, and T3 are the time of the first selection period> the time of the second selection period>
It is set so as to satisfy the time relationship of the third selection period. Specifically, here, the time of the first selection period: the second
Selection period time: Third selection period time = 3: 2: 1. The gate selection period is within one horizontal period.

As shown in FIG. 6, before the display signal is written (before the time T0), all the pixel electrodes 409 hold the positive display signal and all the time division switches (SW).
, SW2, ...) Are in the off state (FIG. 7 (a)). The switch controller 422 displays the time T that is the first selection period.
Between 0 and time T1, all time division switches (SW1, SW2, SW3, SW4, S) corresponding to R, G, and B are included.
W5, SW6, SW7, SW8, SW9, ...)
The i-level switch control signals are output to turn them on (FIG. 7B), and from time T1 to time T2, which is the second selection period, the time division switch (SW) corresponding to R is selected.
1, SW4, SW7, ...) outputs a Low level switch control signal and turns them off (see FIG. 7).
(C)), and from the time T2 to the time T which is the third selection period.
Time division switch (SW2, SW5, SW) corresponding to G in 3
8, ...) are further output as Low level switch control signals to turn them off (FIG. 7 (d)), and finally after time T3, the time divisional switch (S
Further, a low level switch control signal is output to W3, SW6, SW9, ..., And these are turned off.

The driver IC 401 is at least time T
Display signal corresponding to R up to 1 (display signal corresponding to the drain line and the pixel electrode which are held at time T1)
And then outputs a display signal corresponding to G (a display signal corresponding to the drain line and the pixel electrode which is in the holding state at time T2) at least until time T2 and thereafter.
After that, the display signal corresponding to B (the display signal corresponding to the drain line and the pixel electrode that is in the holding state at time T3) is output at least until time T3 and later. Therefore, as shown in the voltage waveform of each pixel electrode potential in FIG. 6, at time T1, R
The pixel electrodes (S1, S4, ...) Corresponding to G hold the display signal (negative polarity) corresponding to R, and the pixel electrodes (S2, S5, ...) Corresponding to G at time T2 display signals corresponding to G. (Negative polarity) is held, and finally, at time T3, the pixel electrodes (S3, S6, ...) Corresponding to B hold the display signal (negative polarity) corresponding to B. After the above operation, the gate scanning voltage becomes the non-selection level, and the display signal corresponding to the display data is written and held in the pixels on all the horizontal lines.

Here, each pixel electrode (S1, S2, S3,
Paying attention to the potential fluctuation of (S4, S5, S6), the charging / discharging of the parasitic capacitance 411 between the pixel electrodes will be described. Figure 7 (a)
In the state before writing shown in (4), as described above, the positive polarity display signal is written and held in all the pixel electrodes. In the first selection period shown in FIG. 7B, since all the time divisional switches are selected, the three pixel electrodes (S1, S2, S3) connected to the display signal line DR1 and the display signal line DR2 are connected. Three connected pixel electrodes (S4, S5, S
The potential of 6) changes from positive polarity to negative polarity at the same phase and level. Therefore, 3 connected to the same display signal line
Charging / discharging does not occur in the parasitic capacitance 411 existing between the two pixel electrodes. Further, the potential difference between the pixel electrodes S3 and S4 that are connected to different display signal lines DR1 and DR2 and are adjacent to each other is extremely small because the display signals of the two electrodes change from the positive polarity to the negative polarity in the same direction. Therefore, although charging / discharging occurs in the parasitic capacitance existing between the electrodes, since the potential difference is extremely small, the amount of charging / discharging is small and the power consumed there is small. Next, in the second selection period shown in FIG. 7C, the potentials of the pixel electrodes (S1, S4) corresponding to R are in the holding state, and all the other pixel electrodes (S2, S3, S5,
Since the negative display signal corresponding to G is written, the potential of S6) changes in the same phase and the same level. Therefore, charge and discharge occur in the parasitic capacitance existing between the R pixel electrode in the holding state and the G and B pixel electrodes around the R pixel electrode.
The potential fluctuation amount of the G and B pixel electrodes is small because the negative polarity display signal of R is already written in the G and B pixel electrodes in the first selection period. The potential difference between the pixel electrode and the G and B pixel electrodes is also small. Therefore, the power consumed by charging / discharging with this parasitic capacitance becomes small. Similarly, in the third selection period shown in FIG. 7D, the B negative polarity display signal is written only in the B pixel electrode (S3, S6), and thus the B pixel electrode (S3, S3) is written. S
Only the potential of 6) changes. Therefore, charging and discharging occur in the parasitic capacitance existing between the changing B pixel electrode and the R and G pixel electrodes in the holding state around the B pixel electrode. Since the negative display signal of G is written in the B pixel electrode in the two selection periods, the potential difference between the B pixel electrode and the R and G pixel electrodes is small. Therefore, the power consumed by charging and discharging due to this parasitic capacitance is also reduced.

As described above, in this embodiment, 1
The horizontal period is time-divided into three periods of a first selection period (time 0 to T1), a second selection period (time T1 to T2), and a third selection period (time T2 to T3), and the first selection is performed. In the period, all the time divisional switches are turned on, the display signal corresponding to R is written to the drain line and all the pixel electrodes, and only the time divisional switch corresponding to R is turned off at the time T1, and in the second selection period, The display signal corresponding to R is held in the pixel electrode and the drain line corresponding to R, and to the drain line and the pixel electrode corresponding to G and B,
The display signal corresponding to G is written, the time divisional switch corresponding to G is turned off at time T2, and the display signal corresponding to G is held in the pixel electrode and drain line corresponding to G in the third selection period. A display signal corresponding to B is written to the drain line and the pixel electrode corresponding to B, and finally the time divisional switch corresponding to B is turned off at time T3,
The display signal corresponding to B is held in the pixel electrode and drain line corresponding to B, and the operation of writing the display signal corresponding to the display data to all the pixel electrodes on one horizontal line is performed. In the present embodiment, such an operation is performed by the liquid crystal panel 403 provided with the time divisional switch group 404, and the driver I that outputs a display signal to the liquid crystal panel 403.
By causing the switch controller 422 that controls the operation of the C401 and the time-division switch group 404 to cancel or reduce the potential fluctuation between the pixel electrodes at the time of writing, the parasitic capacitance 411 between the pixel electrodes is generated between the pixel electrodes. The charging / discharging power of can be reduced. As a result, in this embodiment, it is possible to suppress the power consumption of the liquid crystal display device and obtain a brightness extremely close to the target brightness. In the present embodiment, one horizontal period is not equally divided into three as in the conventional technique, that is, the time of the first selection period = the time of the second selection period = the time of the third selection period, and The time> the time of the second selection period> the third selection period is that the display signal is written to all the pixel electrodes in one horizontal line in the first selection period, and 2 in one horizontal line in the second selection period. This is because the display signal is written to the pixel electrode of / 3 and the display signal is written to the pixel electrode of ⅓ in one horizontal line in the third selection period, so that the signal writing load is different in each period. .

By the way, the present embodiment is shown in FIG.
As shown in FIG. 3, in the Lth frame, the polarity of the display signal of the Mth line is set to the positive polarity and the next line (M +
1) The polarities of the display signals of the lines are set to the same polarity, and the display signals of the positive polarity are written on all the horizontal lines,
As shown in FIG. 8 (a.2), in the next (L + 1) th frame, the frame inversion drive for writing the negative display signal on all the horizontal lines is performed. In this embodiment,
Although the polarity inversion cycle of the display signal is one frame, this inversion cycle may be set arbitrarily.

Although the frame inversion driving method is adopted in this embodiment, the line inversion driving method may be adopted. That is, as shown in FIG. 8 (b.1), the display signal of the Mth line in the Lth frame has a positive polarity, and the display signal of the (M + 1) th line, which is the next line, has a reverse polarity. As a certain negative polarity, the polarity of the display signal in one frame is inverted for each line, and in the (L + 1) th frame which is the next frame, the polarity of the display signal of the Mth line is the negative polarity which is the reverse polarity of the previous frame. Line inversion drive in which the polarity of the display signal of the (M + 1) th line, which is the next line, is positive.
In this line inversion drive method, the inversion cycle of the display signal polarity in each frame is set to one line cycle.
The inversion cycle of the display signal polarity may be set arbitrarily.
Further, the polarity inversion cycle between frames is one frame, but this cycle may be set arbitrarily.

Next, a display device as a second embodiment according to the present invention will be described with reference to FIGS. 9 to 11.

The liquid crystal display device of the present embodiment has the same hardware configuration as that of the first embodiment, except for the operation of the driver IC. Driver IC 40 of this embodiment
1 outputs display signals of opposite polarities to odd and even output terminals. For example, a positive (or negative) display signal is output to the display signal lines DR1, DR3, DR5, ... Connected to the odd terminals, and the display signal lines DR2, DR4, DR6 ,. A negative (or positive) display signal is output.

Next, referring to FIG.
The display signal writing operation in the horizontal period will be described. The gate scanning voltage G in FIG. 9 shows the gate voltage waveform of the horizontal line in the written state, and the gate selection period is within one horizontal period. Also in this embodiment, as in the first embodiment, one horizontal period is time-divided into three periods.

In the state before writing shown in FIG. 9, the state shown in FIG.
As shown in (a), a positive polarity display signal is written in the pixel electrodes (S1, S2, S3, S7, ...) Connected to the odd output terminals (DR1, DR3, ...) Of the driver IC 401. The pixel electrodes (S4, S5, S6, ...) That are held and connected to the even output terminals (DR2, ...) Of the driver IC 401 are written and held with the negative polarity display signal. Further, all the time divisional switches (SW1, SW2, ...) Are off. Figure 10 (b)
In the first selection period shown in (4), all the time divisional switches are selected and turned on, and the pixel electrodes (S1, S2, S3, S7, S7, S7, ...) Connected to the odd output terminals (DR1, DR3, ...) Of the driver IC 401. ...) is written with a negative polarity display signal of R, and the pixel electrodes (S4, S4) connected to the even output terminals (DR2, ...) Of the driver IC 401.
5, S6, ..., A positive polarity display signal of R is written. For this reason, the pixel electrodes (S) connected to the odd output terminals (DR1, DR3, ...) Of the driver IC 401.
1, S2, S3, S7, ...) are in phase with each other,
It changes at the same level. In addition, the pixel electrode (S) connected to the even output terminals (DR2, ...) Of the driver IC 401.
, S5, S6, ...) also change in phase and level. Therefore, charging / discharging does not occur in the parasitic capacitance 411 existing between these three pixel electrodes. In addition, the potential difference between the pixel electrodes S3 and S4 that are connected to different display signal lines DR1 and DR2 and are adjacent to each other changes the display signals from each other in the opposite polarities. Electric discharge occurs. Second shown in FIG. 10 (c)
In the selection period, the time division switch (SW1,
, SW) are turned off, the potentials of the pixel electrodes (S1, S4, S7, ...) Corresponding to R are held, and the other time division switches (SW2, SW3, SW) are held.
5, SW6, ...) are in the ON state and the other pixel electrodes (SW
2, SW3, SW5, SW6, ...)
The negative polarity display signal of G is written in the pixel electrodes (S2, S3, ...) Connected to the odd output terminals (DR1, DR3, ...) Of C401, and the even output terminals (DR2 ,. ) Connected to the pixel electrode (S
4, S5, S6, ...) is written with a G positive display signal. Therefore, the pixel electrodes (S2, S3) change in phase and at the same level with each other, and both pixel electrodes (S2, S3)
Charge / discharge does not occur in the parasitic capacitance between 3). In addition, the parasitic capacitance existing between the R pixel electrode (S1) in the holding state and the pixel electrodes (S2, S3) around it is charged and discharged, but the potential of this pixel electrode (S2, S3) The amount of change is
Since the R negative polarity display signal or the R positive polarity display signal has already been written in this pixel electrode (S2, S3) in the first selection period, the pixel signal is small and the R pixel electrode (S1) Also, the potential difference between the G and B pixel electrodes (S2, S3) in the vicinity thereof is small. Therefore, the power consumed by charging / discharging becomes small due to the parasitic capacitance between the R pixel electrode (S1) and the surrounding G and B pixel electrodes (S2, S3). Figure 10
In the third selection period shown in (d), the time divisional switches (SW1, SW2, SW4, SW5, SW) corresponding to R and G are provided.
, ...) is off, the potentials of the pixel electrodes (S1, S2, S4, S5, S7, ...) Corresponding to R and G are in the holding state, and the remaining time-division switches (SW corresponding to B)
3, SW6, ..., Are on, and the B pixel electrode (S3, S3, ...
The negative and positive display signals of B are written only in S6), and only the potentials of the pixel electrodes (S3, S6) change. Therefore, the parasitic capacitance existing between the fluctuating B pixel electrode and the R and G pixel electrodes in the holding state in the periphery thereof is charged and discharged, but the potential fluctuation amount between the pixel electrodes is already R Since the negative and positive display signals are written in the pixel electrodes B and B, the pixel signal becomes small. Therefore,
This parasitic capacitance also reduces the power consumed by charging and discharging.

As described above, in this embodiment, all the time divisional switches are turned on in the first selection period, the display signal corresponding to R is written in the drain line and the pixel electrode, and R is corresponded at time T1. Only the time division switch
In the FF state, in the second selection period, the display signal corresponding to R is held in the pixel electrode and the drain line corresponding to R, to the drain line and the pixel electrode corresponding to G and B,
A display signal corresponding to G is written, the time divisional switch corresponding to G is turned off at time T2, and the display signal corresponding to G is held in the pixel electrode and drain line corresponding to G in the third selection period. , The display signal corresponding to B is written to the drain line and the pixel electrode corresponding to B, and finally the time divisional switch corresponding to B is turned off at time T3, and the display signal corresponding to B is changed to the pixel corresponding to B. An operation of writing the display signal corresponding to the display data in all the pixel electrodes on one horizontal line while holding the electrodes and the drain lines is performed. In the present embodiment, such an operation is performed by the liquid crystal panel 403 having the time divisional switch group 404 and the driver IC 4 which outputs a display signal to the liquid crystal panel 403.
01, by causing the switch controller 422 for controlling the operation of the time divisional switch group 404 to cancel or reduce the potential variation between the pixel electrodes at the time of writing, to the inter-pixel electrode parasitic capacitance 411 generated between the pixel electrodes. The charging / discharging power of can be reduced. As a result, also in the present embodiment, it is possible to suppress the power consumption of the liquid crystal display device and obtain a brightness extremely close to the target brightness.

By the way, in the present embodiment, FIG.
As shown in 1), in the L-th frame, the display signals between all horizontal lines are set to display signals of the same polarity,
As shown in FIG. 11 (a.2), in the next (L + 1) th frame, pixel-by-column inversion driving is performed to write a display signal having a polarity opposite to that of the previous frame onto all horizontal lines. Although the polarity inversion cycle of the display signal is one frame in this embodiment, this cycle may be set arbitrarily. Further, in the driver IC 401 according to the present embodiment, the terminal interval for outputting the display signals with mutually opposite polarities has been described as one terminal, but by setting this terminal interval to a plurality, it is possible to perform column-by-column inversion driving in units of a plurality of pixels. It may be performed.

Further, although the present embodiment employs the pixel inversion column inversion drive system as described above, it may employ the pixel inversion dot inversion drive system. That is, as shown in FIG. 11 (b.1), the polarity of the display signal of the M-th line in the L-th frame and the polarity of the display signal of the (M + 1) -th line which is the next line are inverted, In the (L + 1) th frame, the dot inversion drive for each pixel may be performed to invert the polarities of the display signals of the Mth line and the (M + 1) th line to the polarity of the previous frame. Note that, here, in each frame, the inversion cycle of the display signal polarity is one line cycle, but the inversion cycle of the display signal polarity may be set arbitrarily. Also,
The polarity reversal period between frames is one frame,
This cycle may also be set arbitrarily.

Next, a display device according to a third embodiment of the present invention will be described with reference to FIGS. 12 and 13.

The liquid crystal display device of the present embodiment is different from that of the first embodiment only in the configuration of the time divisional switch group 404, and the other configurations are basically the same. The time divisional switch group 404 of this embodiment is formed of nMOS-TFTs. The time-division switch group 404 has the pMOS-TF, as described in the first embodiment.
It may be formed of T or cMOS-TFT. The selection order of the time divisional switches in the present embodiment differs depending on the time divisional switch groups connected to the adjacent display signal lines DR. For example, as shown in FIG. 12, the selection order of the time-division switches SW1, SW2, and SW3 connected to the display signal line DR1 and the adjacent display signal line D
A control signal line 412 is connected to the gate terminal of each time division switch so as to be symmetric (reverse) to the selection order of the time division switches SW4, SW5, and SW6 connected to R2. Therefore, in the present embodiment, when the time division switches connected to the odd-numbered (or even-numbered) display signal lines DR are selected in order from the drain line corresponding to R (from the drain line on the left), the even-numbered The time division switch connected to the (or odd number) display signal line DR is B
From the drain wire corresponding to (from the drain wire on the right)
It will be selected in order. That is, the operation of the switch controller 422 in this embodiment is the same as that of the first embodiment, but the arrangement of each time division switch for the switch controller 422 is different, and thus the operation of each time division switch is the first. Different from the embodiment.

Here, the display signal writing operation in one horizontal period will be described with reference to FIG. 13 by taking as an example the case where the driver IC 401 that outputs the display signal of the same polarity is used at the even and odd output terminals. The gate scanning voltage G in FIG. 13 shows the gate voltage waveform of the horizontal line in the written state, and its gate selection period is within one horizontal period. Also in the present embodiment, one horizontal period is time-divided into three periods as in the above embodiments.

Driver IC 401 in this embodiment
Also, similarly to the above-described embodiment, the R-corresponding display signal corresponding to the drain line and the pixel electrode which is in the holding state at time T1 is output at least until time T1 and thereafter, at least until time T2 and thereafter. The G-corresponding display signal corresponding to the drain line and the pixel electrode that is in the holding state at time T3 is output, and thereafter, at least until time T3 and thereafter, at time T3.
B corresponding to the drain line and pixel electrode that are held in
Output the corresponding display signal.

In the state before writing, as in the first embodiment, all the pixel electrodes 409 hold the positive display signal, and all the time division switches (SW1, SW2, SW3).
SW4, ...) Are off. In the first selection period, all the time divisional switches are selected and turned on, and the negative polarity display signal corresponding to R is written in all the pixel electrodes (S1, S2, S3, S4, ...). At time T1, the time divisional switches SW1, SW7, ... Corresponding to R connected to the odd-numbered display signal lines DR1, DR3 ,.
, The drain lines and the pixel electrodes (S1, S7, ...) Connected to 1, SW7, ... Hold the display signals corresponding to R, and at the same time, correspond to R connected to the even-numbered display signal lines DR2 ,. The time divisional switches SW6, ... (In the first embodiment, B) are turned off, and the drain lines and the pixel electrodes (S6, ...) Connected to the time divisional switches SW6 ,. Hold the display signal. Further, in the second selection period, the time divisional switches SW2, SW3, SW8, SW9, ... Corresponding to G and B connected to the odd-numbered display signal lines DR1, DR3 ,.
Is kept on, and this time division switch SW
2, the display signals corresponding to G are written and held in the drain lines and the pixel electrodes (S2, S3, S8, S9, ...) Connected to SW3, SW8, SW9 ,. , Corresponding to G and B connected to (corresponding to R and G in the first embodiment).
The time divisional switches SW4, SW5, ... Are also kept in the ON state, and the drain lines and the pixel electrodes (S4, S5, ...) Connected to the time divisional switches SW4, SW5 ,.
The display signal corresponding to is written and held. That is,
In the second selection period, the pixel electrodes (S1, S6, S7, ...)
To hold the display signal corresponding to R, and write the display signal corresponding to G to the remaining pixel electrodes (S2, S3, S4, S5, S8, S9, ...). At time T2, the time divisional switches SW2, SW corresponding to G connected to the odd-numbered and even-numbered display signal lines DR1, DR2, DR3 ,.
, 5 are turned off, and the drain lines and the pixel electrodes (S2, S5, S) connected to the time division switches SW2, SW5, SW8, ... In the third selection period.
, ...) to hold the display signal corresponding to G. Also,
In the third selection period, odd-numbered display signal lines DR1,
Time division switch S corresponding to B connected to DR3, ...
The W3, SW9, ... Are kept in the ON state, and the display signal corresponding to B is written and held in the drain line and the pixel electrode (S3, S9, ...) Connected to the time division switches SW3, SW9 ,. At the same time, the time divisional switches SW4, ... Corresponding to B (corresponding to G in the first embodiment) connected to the even-numbered display signal lines DR2 ,. Split switch SW4
A display signal corresponding to B is written and held in the drain line and the pixel electrode (S4, ...) Connected to. Finally, at time T3, odd-numbered display signal lines DR1, DR3, ...
Time-division switches SW3, SW corresponding to B connected to
.. are turned off, the time divisional switches SW3,
A drain line and a pixel electrode connected to SW9, ... Hold a display signal corresponding to B, and at the same time, correspond to B connected to an even-numbered display signal line DR2, ... (In the first embodiment, R The time divisional switches SW4, ... Are turned off to cause the drain lines and pixel electrodes connected to the time divisional switches SW4 ,. After the above operation, the gate scanning voltage becomes the non-selection level, and the display signal corresponding to the display data is written and held in the pixels on all the horizontal lines.

Here, pay attention to the potential fluctuation of each pixel electrode. In the first selection period, since the all-time division switch is selected, the three pixel electrodes (S1, S2, S3) connected to the display signal line DR1 and the three pixel electrodes (three pixel electrodes connected to the display signal line DR2 ( The potentials of S4, S5, and S6) change to a negative polarity display signal at the same phase and the same level. Therefore, charging / discharging does not occur in the parasitic capacitance existing between these three pixel electrodes. In addition, different display signal lines (DR1, D
R2) adjacent pixel electrodes (S3, S) connected to each other
In the case of 4), since the display signals have negative polarities in FIG. 13, the potential difference between these electrodes is small, and therefore,
The charge and discharge caused by the parasitic capacitance between the pixel electrodes is also small. In the second selection period, a negative display signal corresponding to G is written in the pixel electrodes (S2, S3) corresponding to G and B connected to the display signal line DR1 and simultaneously connected to the display signal line DR2. A negative display signal corresponding to G is written in the pixel electrodes (S4, S5) corresponding to G and B (corresponding to R and G in the first embodiment). Therefore, the potentials of the pixel electrodes (S2, S3, S4, S5) are basically displaced in the same phase and at the same level, and the potential difference between the pixel electrodes is extremely small. The charging and discharging hardly occur due to the parasitic capacitance. Further, between the pixel electrodes (S1, S6) holding the display signal and the pixel electrodes (S2, S5) adjacent to the pixel electrodes (S1, S6), the negative R display signal has already been written to the pixel electrodes (S1, S6). However, since the amount of change in potential between these pixel electrodes is small, the charge / discharge that occurs due to the parasitic capacitance between these pixel electrodes is also small. In the third selection period, a negative polarity display signal corresponding to B is written in the pixel electrode corresponding to B connected to the display signal line DR1.
At the same time, a negative display signal corresponding to B is written in the pixel electrode (S4) corresponding to B (corresponding to G in the first embodiment) connected to the display signal line DR2. Therefore, the pixel electrodes (S3, S4) and the pixel electrodes (S2, S5) adjacent to these pixel electrodes (S2, S4) are
The display signal of negative polarity G is already written in 5),
Since the amount of potential variation between these pixel electrodes is small, the charge and discharge generated by the parasitic capacitance between these pixel electrodes is also small.

As described above, also in this embodiment, since the charge / discharge power to the inter-pixel electrode parasitic capacitance 411 generated between the pixel electrodes can be reduced, the power consumption of the liquid crystal display device can be suppressed. , It is possible to obtain a brightness extremely close to the target brightness.

Also in this embodiment, a number of driving methods using the driver IC 401 that outputs the display signals of the same polarity at the even and odd output terminals as described in the first embodiment, that is, frame inversion driving. Method or line inversion drive method can be applied. Similarly, a large number of driving methods using the driver IC 401 that outputs display signals of opposite polarities at even and odd terminals as described in the second embodiment, that is, inversion driving method for each pixel unit and each pixel unit A reverse driving method can also be applied.

Further, in the present embodiment, the connection order of each time division switch and the switch controller 422 is changed from that of the first embodiment, so that the selection order of each time division switch is changed from that of the first embodiment. However, by changing the output order of the switch control signal 412 from the switch controller 422 without changing the connection order of each time division switch and the switch controller 422 from the first embodiment, the selection order of each time division switch is changed. You may change it.

Next, a display device according to a fourth embodiment of the present invention will be described with reference to FIGS. 14 and 15.

The liquid crystal display device of this embodiment has the same hardware configuration as that of the first embodiment, and the driver IC 401
And only the operation of the switch controller 422 is different.

The display signal writing operation in one horizontal period in the fourth embodiment of the present invention will be described with reference to FIG. The gate scanning voltage G in FIG. 14 shows the gate voltage waveform of the horizontal line in the written state, and the gate selection period is within one horizontal period. Further, in the present embodiment, one horizontal period is defined as an initial period from time 0 to time T when the rise of the gate scanning voltage is time 0,
It is time-divided into four periods: a first selection period from time T to time T1, a second selection period from time T1 to time T2, a third selection period from time T2 to time T3. However, since the R display signal to be written first is the initial period and the first selection period, as will be described later, it can be said that the period including the initial period and the first selection period is a broad sense of the first selection period. Therefore, the time relationship of each period is (initial period + first selection period) time> second selection period time> third selection period time.

Driver IC 401 in this embodiment
Also, similarly to the above-described embodiment, the display signals corresponding to the drain lines and the pixel electrodes that are in the holding state at time T1, specifically, the display signal of R is output at least until time T1 and thereafter at least time T1. Until T2 and thereafter, a display signal corresponding to the drain line and the pixel electrode that is in the holding state at time T2, specifically, a display signal of G is output, and then, the drain that is in the holding state at time T3 at least until the time T3 and thereafter. A display signal corresponding to the line and the pixel electrode, specifically, a B display signal is output.

In the state before writing shown in FIG. 14, FIG.
As shown in (a), all pixel electrodes (S1, S2, S
A positive polarity display signal is written and held in all of the time division switches (SW1, SW2, ...).
SW3, ...) Is off. In the initial period shown in FIG. 15 (b), all the time divisional switches are selected and turned on, and all pixel electrodes (S1, S2, S3, ...) Have R.
The negative display signal is written. However, in this initial period, the R display signal is not completely written, and at time T before the potentials of all the pixel electrodes reach the target potential of the R display signal, FIG. As shown in, the time division switch (SW
2, SW3, SW4, SW5, ...) are turned off, and in the first selection period from time T to time T1, G
And pixel electrodes (S2, S3, S4, S5) corresponding to B and
...) holds the potential before the target potential of the R display signal is reached. Further, in the first selection period, the time divisional switches (SW1, SW6, ...) Corresponding to R are maintained in the ON state, and at the end time T1 of the first selection period, the pixel electrodes (S1, S6, S6 corresponding to R). ...) to reach the target potential of the R display signal, and the time divisional switches (SW1, SW
, 6) are turned off to hold the R display signal.

In the second selection period from time T1 to time T2, as shown in FIG. 15D, after the start time T1 of this period, the time divisional switch (SW2, S) corresponding to G is generated.
Only the W5, ...) is turned on, and the display signal corresponding to G is written to the drain line and the pixel electrode (S2, S5, ...) Corresponding to G, and the time T2 when the second selection period ends.
Then, by turning off the time divisional switch, the display signal of G is held in the drain line and the pixel electrode.
In the third selection period from time T2 to time T3, FIG.
As shown in (e), after the start time T2 of this period,
Only the time divisional switches (SW3, SW6, ...) Corresponding to B are turned on, the display signal corresponding to B is written to the drain line and pixel electrode (S3, S6, ...) Corresponding to B, and the third selection is performed. At time T3 when the period ends, the time divisional switch is turned off to hold the display signal of B on the drain line and the pixel electrode. After the above operation, the gate scanning voltage becomes the non-selection level, and the display signal corresponding to the display data is written and held in the pixels on all the horizontal lines.

Here, paying attention to the potential fluctuation of each pixel electrode,
The charging / discharging of the inter-pixel electrode parasitic capacitance 411 will be described. First, in the initial period, since the all-time division switch is selected, the potentials of the three pixel electrodes (S1, S2, S3) connected to the display signal line DR1 and the three pixels connected to the display signal line DR2 are selected. The potentials of the electrodes (S4, S5, S6) change in the same phase and the same potential. Therefore, charging and discharging of the parasitic capacitance 411 existing between these three pixel electrodes does not occur. In addition, the potential difference between the pixel electrodes S3 and S4 that are connected to different display signal lines DR1 and DR2 and are adjacent to each other is small because the mutual display signals change from the positive polarity to the negative polarity in the same direction. Therefore, as shown in FIG. 15B, the charge / discharge to the inter-pixel electrode parasitic capacitance 411 occurring in the initial period becomes small. Next, in the first selection period, the potentials of the pixel electrodes (S2, S3, S5, S6) corresponding to G and B are in the holding state, and the pixel electrodes (S1, S6) corresponding to R are held.
Only, the display signal is written, so that the potential fluctuation occurs. However, in the initial period, the pixel electrodes (S2, S3, S5, S6) corresponding to G and B have already been written with a potential close to the negative R display signal.
The potential difference (S2, S3, S5, S6) between the pixel electrodes (S1, S4) and the surrounding pixel electrodes is small. Therefore, as shown in FIG. 15C, the charging / discharging to the inter-pixel electrode parasitic capacitance 411 that occurs during the first selection period becomes small. next,
In the second selection period, the potentials of the pixel electrodes (S1, S3, S4, S6) corresponding to R and B are in the holding state,
Only the pixel electrodes (S2, S5) corresponding to G have the potential fluctuation because the display signal is written. However, during the initial period and the first selection period, the R pixel electrodes (S1, S
4) and the B pixel electrodes (S3, S6) are held at a potential close to the negative polarity display signal of G, so that the G pixel electrodes (S2, S5) and the pixel electrodes (S1, S3, S3) around them are held. S
4, S6) is small. Therefore. Figure 15 (d)
As shown in, the charge / discharge to the inter-pixel electrode parasitic capacitance 411 that occurs in the second selection period becomes small. Furthermore, in the third selection period, the pixel electrodes (S1, S
The potentials of (2, S4, S5) are in the holding state, and only the pixel electrodes (S3, S6) corresponding to B have the potential fluctuation because the display signal is written. However, from the initial period to the second
Throughout the selection period, R pixel electrodes (S1, S4) and G
Since the pixel electrodes (S2, S5) of B hold a potential close to the negative display signal of B, the pixel electrodes of B (S3, S5).
6) and its surrounding pixel electrodes (S1, S2, S4, S5)
And the potential difference with is small. Therefore. As shown in FIG. 15E, the inter-pixel electrode parasitic capacitance 411 generated in the third selection period.
The charge and discharge to and from it also becomes smaller.

As described above, also in this embodiment, since the charge / discharge power to the inter-pixel electrode parasitic capacitance 411 generated between the pixel electrodes can be reduced, the power consumption of the liquid crystal display device can be suppressed. , It is possible to obtain a brightness extremely close to the target brightness.

Also in this embodiment, a large number of driving methods using the driver IC 401 that outputs the display signals of the same polarity at the even and odd output terminals as described in the first embodiment, that is, the frame inversion driving is used. Method or line inversion drive method can be applied. Similarly, a large number of driving methods using the driver IC 401 that outputs display signals of opposite polarities at even and odd terminals as described in the second embodiment, that is, inversion driving method for each pixel unit and each pixel unit A reverse driving method can also be applied. Furthermore, this embodiment can also be applied to the case where the selection order of the time divisional switches is different in the time divisional switch groups connected to the adjacent display signal lines DR, as described in the third embodiment.

Further, in each of the above embodiments, the gate scanning circuit 406 may be built in the liquid crystal panel 403, or may be arranged as an external circuit around the liquid crystal panel 403. The driver IC 401 is arranged in the periphery in the schematic diagram shown in FIG.
A signal driver circuit having the same function as C is provided on the liquid crystal panel 4
It may be built in 03.

Further, in each of the above embodiments, one horizontal period is basically divided into three, taking RGB time division driving as an example. However, the number of divisions is not limited to this, and division is performed by an arbitrary number n. May be. In this case, according to the number of divisions n, the number of control signal lines of the time division switch, that is, the switch controller 42.
The number of 2 output terminals is also n (or n × 2). Then, the division period is also changed accordingly, and the display signals corresponding to the pixel electrodes and the drain lines that are in the voltage holding state in each selection period are sequentially output by the driver IC 401.

In each of the above embodiments, RGB
The color pixel array is not limited to this. Similarly, the order of the pixel electrode in the holding state and the color pixel corresponding to the drain line in each selection period is not limited.

Each of the above embodiments is an example in which the present invention is applied to a liquid crystal display device, but has a plurality of drain lines and a plurality of gate lines which are orthogonal to each other, and corresponds to the intersection thereof. The present invention can be applied to any matrix type display device provided with pixel electrodes, for example, an EL (Electro Luminescence) display device and a plasma display device.

Here, the active matrix type EL display device will be briefly described with reference to FIGS.

As shown in FIG. 16, the organic EL panel 17
In 01, as in the respective embodiments of the liquid crystal display device described above,
A time divisional switch group 404, a drain line group 405, a gate scanning circuit 406, and a gate scanning line group 407 are provided. In the vicinity of the intersection of multiple drain lines and gate lines,
The switch element 408 is provided, and the organic EL
The pixel 1702 is connected. Organic EL pixel 1702
17, has an organic EL element 1801 and a display data holding capacitor section 1802. The pixel electrode of the organic EL pixel 1702 is the display data storage capacitor unit 180.
Part of 2 is formed.

Also for the EL display device as described above, the time divisional switch group 4 is used as in the above-described embodiments.
04 and driver IC 401 operation control,
It is possible to reduce the charging / discharging power to the parasitic capacitance between the pixel electrodes, which is generated between the pixel electrodes.

Next, one embodiment of the information equipment equipped with the above-mentioned display device will be described with reference to FIG.

The information equipment 1601 of this embodiment is a computer, and includes a display device 1602 and a central processing unit 160.
3, input device 1604, storage device 1605, output device 1
606 and a power supply circuit 1607. The central processing unit 1603 acts as a central control, and calculation, logic, and execution decisions are made. Reference numeral 1608 denotes a system bus, which includes a central processing unit 1603, an input device 1604,
It is used for signal transmission between the output device 1606, the storage device 1605, and the like. Storage device 1605
Is used to store programs and data. The input device 1604 is where information is input to the information device,
The input information may be data or a program. Output device 1
Reference numeral 606 is a place where information is output from the inside of the information device to the outside world, and is written to a printer or stored in an auxiliary storage device such as a magnetic tape or a magnetic disk. In addition, the central processing unit 1603 uses a digital I / F signal of the display device, for example, a display data signal, and a horizontal synchronizing signal that becomes valid once in one horizontal period, and once in one frame period. A signal including a vertical synchronizing signal, a clock signal, a display timing signal indicating a range of valid display data, and the like, which are valid in, is output to the liquid crystal display device 1602 which is a display device. Further, the power supply circuit 1607 supplies power to the display device 1602 and other components of the information device 1601 that require power. The power supply circuit 1607 also generates and outputs a gradation reference voltage required by the display device 1602.

Since the information device 1601 of this embodiment uses the low power consumption display device 1602 described in each of the above embodiments, the power consumption can be reduced. Therefore, a great effect can be obtained by applying the present invention to a notebook personal computer and a portable information terminal device such as an electronic notebook, which require lower power consumption among the information devices.

[0067]

According to the present invention, a plurality of time divisional switches are controlled so that all the pixel electrodes first hold a voltage corresponding to a display signal, and then, among the plurality of time divisional switches. While turning on and / or turning off the predetermined time divisional switch of, the voltage corresponding to the display signal is applied to all the pixel electrodes in each selection period, so that the adjacent pixel electrodes The potential difference between them can be reduced. As a result, the charging / discharging power to the parasitic capacitance existing between the adjacent pixel electrodes can be reduced, the consumption electrode can be suppressed, and the brightness extremely close to the target brightness can be obtained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a configuration of a liquid crystal display device in a conventional technique.

FIG. 2 is a voltage waveform and timing chart in the related art.

FIG. 3 is a schematic diagram of writing a display signal to a pixel electrode in the related art.

FIG. 4 is an explanatory diagram showing a configuration of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a time divisional switch according to the first embodiment of the present invention.

FIG. 6 is a voltage waveform and timing chart in the first embodiment according to the present invention.

FIG. 7 is a schematic diagram of writing a display signal to a pixel electrode according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram showing polarity inversion of a display signal according to the first embodiment of the present invention.

FIG. 9 is a voltage waveform and timing chart in the second embodiment according to the present invention.

FIG. 10 is a schematic diagram of writing a display signal to a pixel electrode according to the second embodiment of the present invention.

FIG. 11 is an explanatory diagram showing polarity inversion of a display signal according to the second embodiment of the present invention.

FIG. 12 is a configuration diagram of a time divisional switch according to a third embodiment of the present invention.

FIG. 13 is a voltage waveform and timing chart in the third embodiment according to the present invention.

FIG. 14 is a voltage waveform and timing chart in the fourth embodiment according to the present invention.

FIG. 15 is a schematic diagram of writing a display signal to a pixel electrode according to a fourth embodiment of the invention.

FIG. 16 is an explanatory diagram showing a configuration of an EL display device.

FIG. 17 is an explanatory diagram showing a configuration of an EL organic pixel.

FIG. 18 is a block diagram showing a configuration of an information device including a display device according to an embodiment of the present invention.

[Description of Reference Signs] 401, 101 ... Driver IC, 102, 402 ... Display signal line group, 103, 403 ... Liquid crystal panel, 104, 40
4 ... Time division switch group, 105, 405 ... Drain line group, 106, 406 ... Gate scanning circuit, 107, 407
... Gate scanning line group, 108, 408 ... Switch element, 1
09, 409 ... Pixel electrode, 110 ... Liquid crystal, 111, 41
DESCRIPTION OF SYMBOLS 1 ... Parasitic capacitance, 113,413 ... Counter electrode, 420 ... Drive control circuit, 421 ... TCON circuit, 422 ... Switch controller, 1601 ... Information equipment provided with a liquid crystal display device,
1602 ... Liquid crystal display device, 1603 ... Central processing unit, 1604 ... Input device, 1605 ... Storage device, 160
6 ... Output device, 1607 ... Power supply circuit, 1608 ... System bus, 1701 ... Organic EL panel, 1702 ... Organic E
L pixels.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G09G 3/20 G09G 3/20 611J 621 621M 623 623R 623V 680 680G 3/30 3/30 J (72) Invention Person Hideo Sato 3300, Hayano, Mobara-shi, Chiba F-term in the Hitachi Display Group (reference) 2H093 NA16 NA23 NA34 NA63 NB10 NC16 NC34 NC44 NC71 ND39 5C006 AA22 AC27 AC28 AF43 AF44 AF51 AF53 AF69 AF71 BB16 BC03 BC11 BC20 BC23 FA37 FA47 5C080 AA06 AA10 BB05 CC03 DD05 DD12 DD26 EE28 FF11 JJ02 JJ03 JJ04 JJ06

Claims (14)

[Claims] 1. A drive control device for a matrix type display section, comprising: a plurality of drain lines and a plurality of gate lines which are orthogonal to each other; and a pixel electrode corresponding to an intersection of the plurality of drain lines. Display signal output means for outputting a display signal to the plurality of pixel electrodes in a time series corresponding to a predetermined number of time divisions, and a plurality of drain lines for each of the plurality of drain lines. A switch control means for controlling the operation of the division switch, wherein the switch control means is adjacent to one of the plurality of pixel electrodes arranged in a direction in which the gate line extends (hereinafter, referred to as a horizontal direction). In order to reduce the potential difference between the matching pixel electrodes, all the time-division switches are selected in the first selection period among a plurality of selection periods obtained by dividing one horizontal period by the predetermined number of time divisions. Of the plurality of time division switches are sequentially turned on by applying a voltage corresponding to the display signal from the display signal output means or a voltage close thereto to all the pixel electrodes arranged in the horizontal direction. Turn on and / or off a given time division switch,
In each selection period, while maintaining a state in which a voltage corresponding to the display signal is applied to all the pixel electrodes, a target voltage is held in all of the plurality of pixel electrodes, matrix display Drive control device. 2. A drive control device for a matrix type display section, comprising: a plurality of drain lines and a plurality of gate lines which are orthogonal to each other; and pixel electrodes corresponding to the intersections thereof. Display signal output means for outputting a display signal to the plurality of pixel electrodes in a time series corresponding to a predetermined number of time divisions, and a plurality of drain lines for each of the plurality of drain lines. A switch control means for controlling the operation of the division switch; and the display signal output means, in the plurality of selection periods in which one horizontal period is divided by the predetermined number of time divisions, to the plurality of pixel electrodes. On the other hand, sequentially outputting corresponding display signals to a plurality of predetermined pixel electrode groups, the switch control means turns on all the time divisional switches in the first selection period of the plurality of selection periods. To, then at the end of each selection period, including the outermost first selection period, a time-division switches, wherein connected to one pixel electrode group of the plurality of pixel electrodes a predetermined,
A drive control device for a matrix type display section, characterized in that the pixel electrode groups are sequentially turned off to hold a voltage corresponding to the corresponding display signal. 3. The drive control device for a matrix type display unit according to claim 2, wherein the time of each selection period becomes shorter in the subsequent selection period, and the display signal output means changes the time of each selection period. Correspondingly, the corresponding indicator is output in each selection period, and the switch control means turns on and / or off each time divisional switch group in each selection period corresponding to the time of each selection period, A drive control device for a matrix type display section, which is characterized in that: 4. A drive control device for a matrix type display section, comprising: a plurality of drain lines and a plurality of gate lines which are orthogonal to each other; and pixel electrodes corresponding to the intersections thereof. Display signal output means for outputting a display signal to the plurality of pixel electrodes in a time series corresponding to a predetermined number of time divisions, and a plurality of drain lines for each of the plurality of drain lines. A switch control means for controlling the operation of the division switch; and the display signal output means, in the plurality of selection periods in which one horizontal period is divided by the predetermined number of time divisions, to the plurality of pixel electrodes. On the other hand, sequentially outputting corresponding display signals to a plurality of predetermined pixel electrode groups, the switch control means turns on all the time divisional switches in the first selection period of the plurality of selection periods. Then, in each subsequent selection period, only the time divisional switch group connected to one pixel electrode group of the predetermined plurality of pixel electrode groups is sequentially turned on, and A drive control device for a matrix type display unit, which holds a voltage corresponding to a corresponding display signal. 5. The drive control device for a matrix type display unit according to claim 4, wherein the total time of the first selection period and the next selection period is longer than the other selection periods. The time of each subsequent selection period becomes shorter as it becomes a later selection period, and the display signal output means outputs the corresponding display signal in each selection period corresponding to the time of each selection period, and the switch control. The drive control device for a matrix type display unit, wherein the means turns on and / or off each time divisional switch group in each selection period corresponding to the time of each selection period. 6. The drive control device for a matrix type display unit according to claim 2, wherein the display signal output means has a plurality of output terminals, and each output terminal includes: One time division switch from each of the plurality of time division switch groups is connected in parallel, and the switch control means is a plurality of time division switches connected in parallel to the odd-numbered output terminals of the display means output means. The operation control order and the operation control order of the plurality of time divisional switches connected in parallel to the even-numbered output terminals of the display means output means are the same order. Control device. 7. The drive control device for a matrix type display section according to claim 2, wherein the display signal output means has a plurality of output terminals, and each output terminal has a plurality of output terminals. One time division switch from each of the plurality of time division switch groups is connected in parallel, and the switch control means is a plurality of time division switches connected in parallel to the odd-numbered output terminals of the display means output means. The operation control order and the operation control order of the plurality of time-division switches connected in parallel to the even-numbered output terminals of the display means output means are opposite to each other. Drive controller. 8. The drive control device for a matrix type display unit according to claim 2, wherein the display signal output means has a plurality of output terminals, and odd numbered output terminals. And the even-numbered output terminals output display signals of the same polarity. 9. The drive control device for a matrix type display unit according to claim 2, wherein the display signal output means has a plurality of output terminals and odd numbered output terminals. And the even-numbered output terminals output display signals having polarities opposite to each other. 10. The drive control device for a matrix type display unit according to claim 2, wherein the matrix type display unit is R (red), G (green), and B (blue). When the pixel electrode group corresponding to R, the pixel electrode group corresponding to G, and the pixel electrode group corresponding to B are included as the plurality of pixel electrode groups, the pixel electrode corresponding to R is The number of selection periods for holding the voltage corresponding to the corresponding display signal in each of the group, the pixel electrode group corresponding to G, and the pixel electrode group corresponding to B is three corresponding to the number of electrode pixel groups. There is a drive control device for a matrix type display section. 11. A drive control device according to claim 1, a plurality of the time divisional switches, and the matrix type display unit which is drive-controlled by the drive control device. A matrix type display device characterized in that 12. The matrix type display device according to claim 11, wherein the display section and the plurality of time division switches are provided on the same substrate, and the plurality of time division switches are made of poly-Si. A matrix type display device comprising a thin film transistor. 13. The display device according to claim 11, an input device for receiving data or instructions from the outside, and the display device according to the data or instructions received by the input device. An information device, comprising: an arithmetic unit for giving display data to the. 14. A drive control method for a matrix type display section, wherein a plurality of drain lines and a plurality of gate lines which are orthogonal to each other and pixel electrodes are provided corresponding to their intersections. A display signal output step of outputting a display signal to the plurality of pixel electrodes in time series corresponding to a predetermined number of time divisions; and a time division provided in each drain line for each of the plurality of drain lines. A switch control step of controlling the operation of the switch, wherein in the switch control step, among the plurality of pixel electrodes arranged in a direction in which the gate line extends (hereinafter, referred to as a horizontal direction), In order to reduce the potential difference between the matching pixel electrodes, all the time-division switches are selected in the first selection period among a plurality of selection periods obtained by dividing one horizontal period by the predetermined number of time divisions. Is turned on to apply a voltage corresponding to the display signal from the display signal output means or a voltage close thereto to all the pixel electrodes arranged in the horizontal direction. While turning on a predetermined time divisional switch of the above and / or off state, while maintaining a state in which a voltage corresponding to the display signal is applied to all the pixel electrodes in each selection period,
A drive control method for a matrix type display section, characterized in that a target voltage is held in all of a plurality of pixel electrodes.