JP2008033296A - Liquid crystal device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal device materializing a small-area switching element for alternately supplying high potential and low potential to a common electrode forming a capacitor between pixel electrodes. <P>SOLUTION: The liquid crystal device includes a scanning line Y, a data line X, a pixel electrode 55 disposed in accordance with their intersection, a common electrode 56 forming a capacitor between the pixel electrodes, a control circuit 30 alternately supplying a voltage VCOML of low potential and a voltage VCOMH of high potential to the common electrode, a scanning line driving circuit 10 successively supplying a selection voltage selecting the scanning line to the scanning line, and a data line driving circuit 20 alternately supplying an image signal of a positive polarity, and an image signal of a negative polarity to the data line when the scanning line is selected. The control circuit includes an element to output selectively the voltage VCOML and the voltage VCOMH to the common electrode. The voltage VCOML is connected to the Nch switching element, and the voltage VCOMH is connected to the Pch switching element. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal device and an electronic apparatus.

  Conventionally, a liquid crystal device is known as a display device. The liquid crystal device includes, for example, a liquid crystal panel and a backlight that supplies light to the liquid crystal panel.

  The liquid crystal panel includes an element substrate, a counter substrate disposed opposite to the element substrate, and a liquid crystal provided between the element substrate and the counter substrate.

  The element substrate includes a plurality of scanning lines and a plurality of auxiliary capacitance lines alternately provided at predetermined intervals, and a plurality of data lines provided at predetermined intervals so as to intersect the plurality of scanning lines and the plurality of auxiliary capacitance lines. A scanning line driving circuit connected to the plurality of scanning lines, a data line driving circuit connected to the plurality of data lines, and a control circuit for driving the auxiliary capacitance lines connected to the plurality of auxiliary capacitance lines. Have.

  Pixels are provided at intersections between the scanning lines and the data lines. The pixel includes a pixel capacitor composed of a pixel electrode and a common electrode, a thin film transistor (hereinafter referred to as a TFT (Thin Film Transistor)) as a switching element, and one electrode (auxiliary capacitor electrode) connected to a capacitor line and the other electrode And a storage capacitor (auxiliary capacitor) connected to the pixel electrode. A plurality of pixels are arranged in a matrix to form a display area.

  A scanning line is connected to the gate of the TFT, a data line is connected to the source of the TFT, and a pixel electrode and the other electrode of the auxiliary capacitor are connected to the drain of the TFT.

  The capacitor line driving circuit supplies a predetermined voltage to each capacitor line.

  The scanning line driving circuit supplies a selection voltage for selecting a scanning line to each scanning line in a predetermined order. When a selection voltage is supplied to the scanning line, all TFTs connected to the scanning line are turned on.

  The data line driving circuit supplies an image signal to each data line, and writes an image voltage based on the image signal to the pixel electrode via the TFT in the on state.

  Here, the data line driving circuit supplies an image signal having a voltage (hereinafter referred to as positive polarity) having a potential higher than that of the common electrode to the data line, and an image voltage based on the positive polarity image signal is supplied to the pixel. Positive polarity writing to be written to the electrodes, and an image signal having a voltage lower than the common electrode voltage (hereinafter referred to as negative polarity) is supplied to the data line, and the image voltage based on the negative polarity image signal is supplied to the pixel. Negative polarity writing to the electrodes is alternately performed.

  The counter substrate has color filters such as R (red), G (green), and B (blue) corresponding to each pixel.

  The above liquid crystal device operates as follows.

  That is, by sequentially supplying the selection voltage to the scanning line, all the TFTs connected to the certain scanning line are turned on, and all the pixels related to the scanning line are selected. Then, an image signal is supplied to the data line in synchronization with the selection of these pixels. Then, an image signal is supplied to all the selected pixels via the on-state TFTs, and an image voltage based on the image signal is written to the pixel electrode.

  When an image voltage is written to the pixel electrode, a driving voltage is applied to the liquid crystal due to a potential difference between the pixel electrode and the common electrode. When a driving voltage is applied to the liquid crystal, the alignment and order of the liquid crystal change, and the light from the backlight that transmits the liquid crystal changes. The changed light passes through the color filter, so that gradation display is performed.

  Note that the driving voltage applied to the liquid crystal is held by a storage capacitor for a period longer by three digits than the period during which the image voltage is written.

  By the way, the liquid crystal device as described above is used in, for example, a portable device. In this portable device, in recent years, reduction of power consumption is required. Therefore, after writing the image voltage to the pixel electrode, the TFT is turned off and the capacitance potential (VST) of the auxiliary capacitance line is changed from the high potential (VSTH) to the low potential (VSTL), or from the low potential to the high potential. There has been proposed a liquid crystal device that can reduce power consumption by performing so-called capacitance line swing driving called SSL (Swing Storage Line) (see, for example, Patent Document 1).

  In addition, a common electrode (COM electrode) such as IPS (In-Plane Switching) or FFS (Fringe Field Switching) having a pixel electrode and a common electrode constituting a pixel capacitor is disposed on one of the pair of substrates sandwiching the liquid crystal. In a horizontal electric field type liquid crystal device that also functions as an auxiliary capacitor electrode and integrally forms a pixel capacitor and an auxiliary capacitor, a high potential (VCOMH) or low potential (VCOML) voltage is supplied to the common electrode, and then a negative polarity Power consumption can be reduced and deterioration in display quality can be suppressed by performing capacitive line swing driving in a lateral electric field system called so-called COM division driving, which supplies an image signal or a positive image signal to a data line. A liquid crystal device has been proposed by the present applicant.

JP 2002-196358 A

  In the above-described capacitive line swing drive, in order to realize low power consumption, in the case of SSL, a switching element that connects VSTH / VSTL to the auxiliary capacitive line, and in the case of COM split drive, VCOMH / It has been found that a low on-resistance of the switching element connecting VCOML is a major factor, and a CMOS switch is used for the purpose of reducing the on-resistance with an arbitrary voltage. Such a switching element is formed in the periphery of the pixel region of the liquid crystal device, that is, a so-called frame region. Since the frame region affects the size of the liquid crystal device, it is desired to reduce the circuit area required for the switching element. There was a request.

  Accordingly, the present invention has been made in view of the above-described problem, and in a liquid crystal device including a pixel electrode and a capacitor electrode constituting a pixel capacitor on one of a pair of substrates holding a liquid crystal, a capacitor line It is an object of the present invention to provide a liquid crystal device capable of reducing the circuit area of a switching element used for swing driving, and an electronic device including the liquid crystal device.

  The liquid crystal device of the present invention corresponds to a plurality of scanning lines (corresponding to scanning lines Y and Y ′ in the embodiment) and a plurality of data lines intersecting the scanning lines (data lines X and X ′ in the embodiment). ) And a plurality of pixel electrodes (corresponding to the pixel electrodes 55 and 55 ′ in the embodiment) provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, or electrodes connected to the pixel electrodes A capacitor electrode (corresponding to the common electrodes 56, 56 ′ or the auxiliary capacitor electrode 57 ′ in the embodiment) provided corresponding to the pixel electrode and forming a capacitance with the pixel electrode; A voltage (corresponding to VCOML or VSTL in the embodiment) and a second voltage having a higher potential than the first voltage (corresponding to VCOMH or VSTH in the embodiment) are alternately supplied to the capacitor electrode. A control circuit (corresponding to the control circuits 30, 30A, 30 ′ in the embodiment) and a scanning line driving circuit for sequentially supplying a selection voltage for selecting the scanning line to the plurality of scanning lines (in the embodiment, the scanning line driving circuit). 10 and 10 ′), and when the scanning line is selected, a positive polarity image signal having a higher potential than the first voltage and a negative polarity image signal having a lower potential than the second voltage A liquid crystal device (in the embodiment, the liquid crystal devices 1, 1A, 1 ′) including a data line driving circuit (in the embodiment, corresponding to the data line driving circuits 20, 20 ′) that alternately supplies the data to the plurality of data lines. And the control circuit selects the first voltage and the second voltage alternately and outputs them to the capacitor electrode (in the embodiment, the Pch transfer gate RP). The single-channel switching element that outputs the first voltage is an N-channel switching element (corresponding to the Nch transfer gate RN in the embodiment) and outputs the second voltage. The single-channel switching element is a P-channel switching element (corresponding to the Pch transfer gate RP in the embodiment).

  According to the present invention, the switching element that alternately selects and outputs the first voltage and the second voltage to the capacitor electrode can be made into a single channel, which can contribute to the narrowing of the frame of the liquid crystal device. Furthermore, by using a single channel, a low on-resistance can be realized, which can contribute to low power consumption.

  According to the present invention, the gate voltage supplied to the N-channel switching element and the P-channel switching element is such that the higher voltage is higher than the second voltage, and the lower voltage is lower than the first voltage. By adopting such a configuration, it is possible to contribute to efficient reduction of on-resistance and reduction of switching element off-leakage.

  According to the present invention, the gate voltage supplied to the N-channel switching element and the P-channel switching element is obtained by subtracting the absolute value of the threshold value of the P-channel switching element from the second voltage when the gate voltage is higher. Since each of the switching elements can be turned off below the threshold value by adopting a configuration in which the lower voltage is lower than the voltage obtained by adding the absolute value of the threshold value of the N-channel switching element to the first voltage. Thus, it is possible to prevent off-leak more reliably.

  According to the invention, the capacitive electrode is a common electrode, and a plurality of scanning lines, a plurality of data lines, and a plurality of lines provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines are provided. A first substrate having a common electrode provided opposite to the pixel electrode, a second substrate disposed opposite to the first substrate, and between the first substrate and the second substrate A liquid crystal device, wherein the liquid crystal device supplies the selection voltage to the scanning line by the scanning line driving circuit after supplying the first voltage to the common electrode by the control circuit; The positive image signal is supplied to the data line by a data line driving circuit, the second voltage is supplied to the common electrode by the control circuit, and then the selection voltage is applied to the scanning line by the scanning line driving circuit. When we supply To, and configured to supply the negative polarity image signal to the data lines by the data line driving circuit. Thus, after supplying the first voltage to the common electrode, the positive image signal is supplied to the data line, and after supplying the second voltage to the common electrode, the negative image signal is supplied to the data line. A so-called COM divided drive type liquid crystal device can be obtained.

  According to the present invention, the plurality of scanning lines, the data lines, and the plurality of scanning lines are provided corresponding to the intersections of the data lines, and the liquid crystal is sandwiched between the common electrode and the pixel electrode. A switching element that is interposed between the liquid crystal capacitor and the data line and the pixel electrode, and is turned on when the scanning line is on-potential, and turned off when the scanning line is off-potential, A liquid crystal device including a storage capacitor connected to a pixel electrode, wherein a control circuit that alternately supplies a first voltage and a second voltage having a higher potential than the first voltage to the common electrode; A scanning line driving circuit for sequentially supplying a selection voltage for selecting a scanning line to the plurality of scanning lines; a positive polarity image signal having a potential higher than the first voltage when the scanning line is selected; Negative polarity with lower potential than the second voltage A data line driving circuit that alternately supplies an image signal to the plurality of data lines, and the control circuit includes an N-channel switching element that outputs the first voltage to the common electrode, and the second voltage. A P-channel switching element that outputs to the common electrode, and the potential of the data line corresponds to the writing of a positive image signal when the scanning line is on-potential, After the scanning line transitions to the off-potential, the second voltage is supplied to the storage capacitor electrode of the storage capacitor, while the potential of the data line at the on-potential corresponds to writing of a negative image signal. If so, a configuration suitable for a so-called SSL driving type liquid crystal device in which the first voltage is supplied to the auxiliary capacitance electrode after the scanning line has transitioned to an off potential can be obtained.

  According to another aspect of the invention, an electronic apparatus includes the above-described liquid crystal device.

  According to the present invention, there are effects similar to those described above.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of embodiments and modifications, the same constituent elements are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  The first to third embodiments are examples of a horizontal electric field type liquid crystal device adopting COM division driving, and the fourth embodiment is a vertical electric field method adopting SSL driving (pixel electrodes formed on a pair of substrate inner surfaces, respectively. And a so-called vertical electric field generated by the common electrode is used to drive the liquid crystal).

<First Embodiment: Example of COM Split Drive>
FIG. 1 is a block diagram of a horizontal electric field type liquid crystal device 1 employing COM division driving according to the first embodiment of the present invention.

  The liquid crystal device 1 includes a liquid crystal panel AA and a backlight 41 that is disposed opposite to the liquid crystal panel AA and emits light. The liquid crystal device 1 performs transmissive display using light from the backlight 41.

  The liquid crystal panel AA includes a display area A having a plurality of pixels 50, and a scanning line driving circuit 10, a data line driving circuit 20, and a control circuit 30 that are provided around the display area A and drive the pixels 50.

  The backlight 41 is provided on the back surface of the liquid crystal panel AA, and is composed of, for example, a cold cathode fluorescent tube (CCFL), an LED (light emitting diode), or electroluminescence (EL), and transmits light to the pixels 50 of the liquid crystal panel AA. Supply.

  Hereinafter, the configuration of the liquid crystal panel AA will be described in detail.

  The liquid crystal panel AA includes 320 scanning lines Y (Y1 to Y320) and 320 common lines Z (Z1 to Z320) alternately provided at predetermined intervals, and these scanning lines Y (Y1 to Y320) and the common lines. 240 columns of data lines X (X1 to X240) provided so as to intersect the lines Z (Z1 to Z320). Pixels 50 are provided at the intersections of the scanning lines Y and the data lines X.

  The pixel 50 includes a TFT 51, a pixel electrode 55, a common electrode 56 provided to face the pixel electrode 55, and one electrode (auxiliary capacitance electrode) connected to the common line Z, and the other electrode (pixel electrode 55 or The electrode layer connected to the pixel electrode 55) is composed of a storage capacitor 53 as an auxiliary capacitor connected to the pixel electrode 55. The pixel electrode 55 and the common electrode 56 constitute a pixel capacitor 54.

  The common electrode 56 is divided for each horizontal line corresponding to the scanning line Y. The plurality of common electrodes 56 divided for each horizontal line are each connected to a corresponding common line Z.

  The scanning line Y is connected to the gate of the TFT 51, the data line X is connected to the source of the TFT 51, and the other electrode of the pixel electrode 55 and the storage capacitor 53 is connected to the drain of the TFT 51. Therefore, the TFT 51 is turned on when a selection voltage is applied from the scanning line Y, and the data line X and the pixel electrode 55 and the other electrode of the storage capacitor 53 are brought into conduction.

  FIG. 2 is an enlarged plan view of the pixel 50. 3 is a cross-sectional view of the pixel 50 shown in FIG.

  As shown in FIG. 3, the liquid crystal panel AA includes an element substrate 60 as a first substrate having a plurality of pixel electrodes 55, a counter substrate 70 as a second substrate disposed opposite to the element substrate 60, and an element substrate. 60 and a liquid crystal provided between the counter substrate 70.

  As shown in FIG. 2, in the element substrate 60, each pixel 50 is surrounded by scanning lines Y made of two conductive materials adjacent to each other and data lines X made of two conductive materials adjacent to each other. It has become an area. That is, each pixel 50 is partitioned by the scanning line Y and the data line X.

  In the present embodiment, the TFT 51 is an inverted staggered low-temperature polysilicon TFT, and in the vicinity of the intersection of the scanning line Y and the data line X, a region 50C (indicated by a broken line in FIG. 2) where the TFT 51 is formed. Are provided).

  First, the element substrate 60 will be described.

  The element substrate 60 has a glass substrate 68, and a glass substrate 68 is provided on the entire surface of the element substrate 60 in order to prevent changes in the characteristics of the TFT 51 due to surface roughness and contamination of the glass substrate 68. An insulating film (not shown) is formed.

  A scanning line Y made of a conductive material is formed on the base insulating film.

  The scanning line Y is provided along the boundary between adjacent pixels 50, and constitutes the gate electrode 511 of the TFT 51 in the vicinity of the intersection with the data line X.

  A gate insulating film 62 is formed over the entire surface of the element substrate 60 on the scanning lines Y, the gate electrodes 511, and the base insulating film.

  In the region 50C where the TFT 51 is formed on the gate insulating film 62, a semiconductor layer (not shown) made of low-temperature polysilicon and an ohmic contact layer (not shown) made of N + low-temperature polysilicon are opposed to the gate electrode 511. Are stacked. A source electrode 512 and a drain electrode 513 are laminated on the ohmic contact layer, thereby forming a low-temperature polysilicon TFT.

  The source electrode 512 is formed of the same conductive material as the data line X. That is, the source electrode 512 protrudes from the data line X. The data line X is provided so as to intersect the scanning line Y and the common line Z.

  As described above, the gate insulating film 62 is formed on the scanning line Y, and the data line X is formed on the gate insulating film 62. For this reason, the data line X is insulated from the scanning line Y by the gate insulating film 62.

  A first insulating film 63 is formed over the entire surface of the element substrate 60 on the data line X, the source electrode 512, the drain electrode 513, and the gate insulating film 62.

  A common line Z made of a transparent conductive material such as ITO (Indium Tin Oxide) is formed on the first insulating film 63. The common line Z is provided along the scanning line Y, and the common line Z is integrally formed with the common electrode 56 divided for each horizontal line.

  A second insulating film 64 is formed over the entire surface of the element substrate 60 on the common line Z, the common electrode 56, and the first insulating film 63.

  A pixel electrode 55 made of a transparent conductive material such as ITO (Indium Tin Oxide) is formed on the second insulating film 64 in a region facing the common electrode 56. The pixel electrode 55 is connected to the drain electrode 513 through a contact hole (not shown) formed in the first insulating film 63 and the second insulating film 64 described above.

  In the pixel electrode 55, a plurality of slits 55A for generating a fringe field (electric field E) are provided at predetermined intervals between the pixel electrode 55 and the common electrode 56. That is, the liquid crystal of the liquid crystal device 1 operates in the FFS mode.

  An alignment film (not shown) made of an organic film such as a polyimide film is formed on the pixel electrode 55 and the second insulating film 64 over the entire surface of the element substrate 60.

  Next, the counter substrate 70 will be described.

  The counter substrate 70 has a glass substrate 74, and a light shielding film 71 as a black matrix is formed on the glass substrate 74 at a position facing the scanning line Y. A color filter 72 is formed in a region on the glass substrate 74 excluding the region where the light shielding film 71 is formed.

  An alignment film (not shown) is formed on the entire surface of the counter substrate 70 on the light shielding film 71 and the color filter 72.

  Returning to FIG. 1, the scanning line driving circuit 10 sequentially supplies a selection voltage for turning on the TFT 51 to the plurality of scanning lines Y. For example, when a selection voltage is supplied to a certain scanning line Y, all the TFTs 51 connected to the scanning line Y are turned on, and all the pixels 50 related to the scanning line Y are selected.

  The data line driving circuit 20 supplies an image signal to the data line X, and writes an image voltage based on the image signal to the pixel electrode 55 via the TFT 51 in the on state.

  Here, the data line driving circuit 20 supplies a positive image signal having a higher potential than the voltage of the common electrode 56 to the data line X, and writes an image voltage based on the positive image signal to the pixel electrode 55. Positive polarity writing and negative polarity writing in which a negative image signal having a potential lower than the voltage of the common electrode 56 is supplied to the data line X and an image voltage based on the negative polarity image signal is written to the pixel electrode 55. Are alternately performed for each horizontal line.

The control circuit 30 alternately supplies a voltage VCOML as a first voltage and a voltage VCOMH as a second voltage having a higher potential than the voltage VCOML to the common line Z.
The circuit elements constituting the scanning line driving circuit 10, the data line driving circuit 20, the control circuit 30, and the like are formed in the peripheral area (frame area) of the display area A using the SOG technique.

  The liquid crystal device 1 described above operates as follows.

  That is, first, either the voltage VCOML or the voltage VCOMH is selectively supplied from the control circuit 30 to the common line Z.

  Specifically, the voltage VCOML and the voltage VCOMH are alternately supplied to each common line Z every frame period. For example, when the voltage VCOML is supplied to the p-th common line Zp (p is an integer satisfying 1 ≦ p ≦ 320) in one frame period, the voltage VCOMH is applied to the common line Zp in the next one frame period. Supply. On the other hand, when the voltage VCOMH is supplied to the common line Zp in one frame period, the voltage VCOML is supplied to the common line Zp in the next one frame period.

  Further, different voltages are supplied to adjacent common lines Z. For example, when the voltage VCOML is supplied to the common line Zp in one frame period, the common line Z (p−1) in the (p−1) th row and the (p + 1) th row in the same one frame period. The voltage VCOMH is supplied to the common line Z (p + 1). On the other hand, when the voltage VCOMH is supplied to the common line Zp in one frame period, the voltage VCOML is supplied to the common line Z (p−1) and the common line Z (p + 1) in the same one frame period.

  Next, by sequentially supplying a selection voltage from the scanning line driving circuit 10 to the 320 scanning lines Y (Y1 to Y320), all the TFTs 51 connected to the scanning lines Y are sequentially turned on, and each scanning is performed. All the pixels 50 related to the line Y are sequentially selected.

  Next, in synchronization with the selection of the pixels 50, a positive image signal, a negative image signal, and one horizontal line are transferred from the data line driving circuit 20 to the data line X according to the voltage of the common electrode 56. Supply alternately every time.

  Specifically, when the voltage VCOML is supplied to the common line Zp related to the selected pixel 50 among the 320 common lines Z (Z1 to Z320), a positive image signal is supplied to the data line X. . On the other hand, when the voltage VCOMH is supplied to the common line Zp related to the selected pixel 50 among the 320 common lines Z (Z1 to Z320), a negative image signal is supplied to the data line X.

  Then, an image signal is supplied to all the pixels 50 selected by the scanning line driving circuit 10 from the data line driving circuit 20 via the data line X and the on-state TFT 51, and an image voltage based on this image signal is applied to the pixel electrode. 55 is written. As a result, a potential difference is generated between the pixel electrode 55 and the common electrode 56, and a driving voltage is applied to the liquid crystal.

  When a driving voltage is applied to the liquid crystal, the alignment and order of the liquid crystal change, and the light from the backlight 41 that transmits the liquid crystal changes. The changed light passes through the color filter, so that gradation display is performed.

  Note that the drive voltage applied to the liquid crystal is held by the storage capacitor 53 for a period that is three digits longer than the period during which the image voltage is written.

  FIG. 4 is a block diagram of the control circuit 30.

  The control circuit 30 includes 320 unit control circuits P (P1 to P320) corresponding to 320 rows of scanning lines Y (Y1 to Y320). Each unit control circuit P is supplied with a voltage VCOML, a voltage VCOMH, and a polarity control signal POL that selects either the voltage VCOML or the voltage VCOMH.

  The unit control circuit P includes a latch circuit Q (Q1 to Q320) that holds the polarity control signal POL, and a selection circuit R (R1 to R320) that selectively outputs either the voltage VCOML or the voltage VCOMH according to the polarity control signal. And).

  The latch circuit Q can be roughly divided into two types from the method of holding the polarity control signal POL. One is a latch circuit Q1 provided corresponding to the first scanning line Y1, and a latch circuit Q320 provided corresponding to the 320th scanning line Y320. The other is latch circuits Q2 to Q319 excluding the above-described latch circuits Q1 and Q320.

  First, the latch circuits Q2 to Q319 will be described below.

  A latch circuit Qq provided corresponding to the scanning line Yq in the q-th row (q is an integer satisfying 2 ≦ q ≦ 319) includes a negative OR operation circuit (hereinafter referred to as a NOR circuit) 31, Inverter 32, second inverter 33, first clocked inverter 34, and second clocked inverter 35.

  The two input terminals of the NOR circuit 31 are connected to the scanning line Y (q−1) in the (q−1) th row and the scanning line Y (q + 1) in the (q + 1) th row, respectively. . The output terminal of the NOR circuit 31 is connected to the input terminal of the first inverter 32, the inverting input control terminal of the first clocked inverter 34, and the non-inverting input control terminal of the second clocked inverter 35. Has been.

  The output terminal of the first inverter 32 is connected to the non-inverting input control terminal of the first clocked inverter 34 and the inverting input control terminal of the second clocked inverter 35.

  The polarity control signal POL is input from the input terminal of the first clocked inverter 34. The input terminal of the second inverter 33 is connected to the output terminal of the first clocked inverter 34.

  The output terminal of the second inverter 33 is connected to the input terminal of the second clocked inverter 35, and the input terminal of the second inverter 33 is connected to the output terminal of the second clocked inverter 35. Yes.

  The above latch circuit Qq operates as follows.

  That is, when the selection voltage is supplied to at least one of the scanning line Y (q−1) and the scanning line Y (p + 1), the NOR circuit 31 included in the latch circuit Qq outputs an L level signal. This L level signal is input to the inverting input control terminal of the first clocked inverter 34, and is inverted by the first inverter 32, and is input to the non-inverting input of the first clocked inverter 34 as an H level signal. Input to the terminal. Therefore, the first clocked inverter 34 is turned on and inverts and outputs the polarity control signal POL. The polarity control signal POL output after being inverted from the first clocked inverter 34 is inverted by the second inverter 33 and output.

  As described above, when the selection voltage is supplied to at least one of the scanning line Y (q−1) and the scanning line Y (q + 1) by the scanning line driving circuit, the latch circuit Qp outputs the polarity control signal POL. take in.

  On the other hand, when the selection voltage is not supplied to both the scanning line Y (q−1) and the scanning line Y (p + 1), the NOR circuit 31 included in the latch circuit Qq outputs an H level signal. This H level signal is input to the non-inverting input control terminal of the second clocked inverter 35, and is inverted by the first inverter 32, and is input to the inverting input of the second clocked inverter 35 as an L level signal. Input to the terminal. Therefore, the second clocked inverter 35 is turned on and inverts and outputs the polarity control signal POL output from the second inverter 33. The polarity control signal POL output after being inverted from the second clocked inverter 35 is input again by the second inverter 33.

  As described above, if the selection voltage is not supplied to both the scanning line Y (q−1) and the scanning line Y (p + 1) by the scanning line driving circuit, the latch circuit Qp receives the polarity control signal POL that has already been captured. It is held by the second inverter 33 and the second clocked inverter 35.

  Next, the latch circuits Q1 and Q320 will be described below.

  Latch circuits Q1 and Q320 include a low-potential power supply of voltage VLL that outputs an L level signal, instead of NOR circuit 31, as compared with latch circuit Qq described above. Other configurations are the same as those of the above-described latch circuit Qq.

  These latch circuits Q1 and Q320 operate as follows.

  That is, an L level signal is always output from the low potential power source of the voltage VLL. This L level signal is input to the inverting input control terminal of the first clocked inverter 34, and is inverted by the first inverter 32, and is input to the non-inverting input of the first clocked inverter 34 as an H level signal. Input to the control terminal. For this reason, the first clocked inverter 34 is always in the on state, and always inverts and outputs the polarity control signal POL. The polarity control signal POL output after being inverted from the first clocked inverter 34 is inverted by the second inverter 33 and output.

  As described above, the latch circuits Q1 and Q320 always take in the polarity control signal POL.

  The selection circuit R includes an inverter 36, a first transfer gate 37, and a second transfer gate 38.

  The input terminal of the inverter 36 is connected to the output terminal of the second inverter 33 included in the latch circuit Q. The output terminal of the inverter 36 is connected to the non-inverting input control terminal of the first transfer gate 37 and the second terminal. The inverting input control terminal of the transfer gate 38 is connected.

  The output terminal of the second inverter 33 included in the latch circuit Q is connected to the inverting input control terminal of the first transfer gate 37, and the common line Z is connected to the output terminal of the first transfer gate 37. Yes.

  The voltage VCOMH is input from the input terminal of the first transfer gate 37 provided in the selection circuit R provided corresponding to the odd-numbered scanning lines Y. On the other hand, the voltage VCOML is input from the input terminal of the first transfer gate 37 provided in the selection circuit R provided corresponding to the even-numbered scanning line Y.

  The non-inverting input control terminal of the second transfer gate 38 is connected to the output terminal of the second inverter 33 provided in the latch circuit Q, and the common line Z is connected to the output terminal of the second transfer gate 38. ing.

  The voltage VCOML is input from the input terminal of the second transfer gate 38 provided in the selection circuit R provided corresponding to the odd-numbered scanning lines Y. On the other hand, the voltage VCOMH is input from the input terminal of the second transfer gate 38 provided in the selection circuit R provided corresponding to the even-numbered scanning line Y.

  The above selection circuit R operates as follows.

  That is, when the L level polarity control signal POL is output from the second inverter 33 provided in the latch circuit Q, the L level polarity control signal POL is input to the inverting input control terminal of the first transfer gate 37. Inverted by the inverter 36 and input to the non-inverting input control terminal of the first transfer gate 37 as the H level polarity control signal POL. For this reason, the first transfer gate 37 is turned on.

  If the first transfer gate 37 in the on state is provided in the selection circuit R provided corresponding to the odd-numbered scanning lines Y, the voltage VCOMH is output to the common line Z. On the other hand, if the first transfer gate 37 in the on state is provided in the selection circuit R provided corresponding to the even-numbered scanning line Y, the voltage VCOML is output to the common line Z.

  On the other hand, when the H level polarity control signal POL is output from the second inverter 33 provided in the latch circuit Q, the H level polarity control signal POL is input to the non-inverting input control terminal of the second transfer gate 38. At the same time, it is inverted by the inverter 36 and input to the inverting input control terminal of the second transfer gate 38 as the L level polarity control signal POL. For this reason, the second transfer gate 38 is turned on.

  If the second transfer gate 38 in the on state is provided in the selection circuit R provided corresponding to the odd-numbered scanning lines Y, the voltage VCOML is output to the common line Z. On the other hand, if the second transfer gate 38 in the on state is provided in the selection circuit R provided corresponding to the even-numbered scanning line Y, the voltage VCOMH is output to the common line Z.

<Modification of Selection Circuit R of First Embodiment>
FIG. 5 is a block diagram of a selection circuit RA which is a modification of the selection circuit R, and shows an example in which a single channel switching transistor is used as a switching element used for a transfer gate.

  The selection circuit RA includes a Pch transfer gate RP composed of a Pch switching element and an Nch transfer gate RN composed of an Nch switching element.

  The voltage VCOMH is connected to the input terminal of the Pch transfer gate RP, the output terminal of the latch circuit Q is connected to the control terminal (gate terminal) of the Pch transfer gate RP, and the output terminal of the Pch transfer gate RP is A common line Z is connected.

  By connecting the voltage VCOMH to the input terminal of the Pch transfer gate RP, the gate-source voltage VGS can be made larger than when the voltage VCOMH is connected to the input terminal of the Nch transfer gate RN. In addition, a low on-resistance and a reduction in off-leak can be realized.

  The voltage VCOML is connected to the input terminal of the Nch transfer gate RN, the output terminal of the latch circuit Q is connected to the control terminal (gate terminal) of the Nch transfer gate RN, and the output terminal of the Nch transfer gate RN is A common line Z is connected.

  By connecting the voltage VCOML to the input terminal of the Nch transfer gate RN, the gate-source voltage VGS can be made larger than when the Pch transfer gate RP is used, so that the operation is good and the on-resistance is further reduced. In addition, off-leakage can be reduced.

  When the selection circuit RA is used, the second inverter 33 is deleted and inverted from the first clocked inverter 34 in the latch circuit Q provided corresponding to the scanning line Y of the even-numbered row. The polarity control signal POL output in this way is output as it is, so that the voltage VCOMH and the voltage VCOML can be alternately output to the common line Z.

  The above selection circuit RA operates as follows.

  That is, when the L level polarity control signal POL is output from the latch circuit Q, the L level polarity control signal POL is input to the control terminal of the Pch transfer gate RP. For this reason, the Pch transfer gate RP is turned on. The Pch transfer gate RP in the on state outputs the voltage VCOMH to the common line Z.

  On the other hand, when the H level polarity control signal POL is output from the latch circuit Q, the H level polarity control signal POL is input to the control terminal of the Nch transfer gate RN. For this reason, the Nch transfer gate RN is turned on. The Nch transfer gate RN in the on state outputs the voltage VCOML to the common line Z.

  As described above, in the selection circuit RA, the circuit area can be reduced by using a single channel switching element used for the transfer gate as compared with the case where the CMOS switching element used in the selection circuit R is used. . In addition, the selection circuit RA is configured such that the Pch switching element is connected to the high potential voltage VCOMH and the Nch switching element is connected to the low potential voltage VCOML, and each is turned on exclusively. Driving with only one control signal is possible, and it is not necessary to form an inversion signal using the inverter 36 unlike the selection circuit R, so that the inverter 36 can be reduced. Therefore, a further reduction in circuit area can be realized.

  The potential relationship between the voltage VCOMH and the voltage VCOML and the polarity control signal POL applied to the gate terminal as the gate potential of the switching element is as follows: gate high voltage (high potential of the polarity control signal POL)> voltage VCOMH> voltage VCOML> gate Low. The voltage (the low potential of the polarity control signal POL) is configured to satisfy the relationship.

  With such a configuration, even if the switching element used for the transfer gate is made into a single channel, it is possible to efficiently reduce the on-resistance and reduce the off-leakage of the switching element.

  More preferably, the potential relationship between the voltage VCOMH and the voltage VCOML and the polarity control signal POL applied to the gate terminal as the gate potential of the switching element is expressed as follows: gate high voltage> voltage VCOMH− | Pch transfer gate threshold value |> voltage VCOML + | By configuring so as to satisfy the threshold value of the Nch transfer gate |> gate low voltage, each switching element can be turned off below the threshold value, so that off-leakage can be reliably prevented.

  For example, the gate high voltage is set to 8V, which is the same as the voltage VGH described later, the gate low voltage is set to -4V, the voltage VCOMH is set to 4V, and the voltage VCOML is set to 0V.

  The operation of the control circuit 30 including the latch circuit Q and the selection circuit R (or the selection circuit RA) will be described with reference to FIG.

  FIG. 6 is a timing chart of the control circuit 30.

  First, at time t1, the polarity control signal POL is set to the voltage VLL, and the polarity control signal POL is set to the L level. Then, the unit control circuits P1 and P320 always use the latch circuits Q1 and Q320 to fetch the polarity control signal POL, and the L level polarity control signal POL (if the selection circuit RA is used, the latch circuit Q320 controls the H level polarity. The signal POL) is taken in, and the voltage VCOMH and the voltage VCOML are output by the selection circuits R1 and R320, respectively. Therefore, the common line Z1 connected to the unit control circuit P1 becomes the voltage VCOMH, and the common line Z320 connected to the unit control circuit P320 becomes the voltage VCOML.

  The voltage VGH is 8V and the voltage VGL is −4V.

  Next, at time t2, the selection voltage is supplied from the scanning line driving circuit 10 to the first scanning line Y1, and the voltage of the scanning line Y1 is set to the voltage VGH. Then, the unit control circuit P2 provided corresponding to the scanning line Y2 adjacent to the scanning line Y1 is controlled by the latch circuit Q2 by the L level polarity control signal POL (if the selection circuit RA is used, by the latch circuit Q2). The H level polarity control signal POL) is taken in, and the voltage VCOML is output by the selection circuit R2. For this reason, the common line Z2 connected to the unit control circuit P2 becomes the voltage VCOML.

  Next, at time t3, the supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y1 is stopped, and the voltage of the scanning line Y1 is set to the voltage VGL.

  At the same time, a selection voltage is supplied from the scanning line driving circuit 10 to the second scanning line Y2, and the voltage of the scanning line Y2 is set to the voltage VGH. Then, the unit control circuit P3 provided corresponding to the scanning line Y3 adjacent to the scanning line Y2 takes in the L level polarity control signal POL by the latch circuit Q3, and outputs the voltage VCOMH by the selection circuit R3. . For this reason, the common line Z3 connected to the unit control circuit P3 becomes the voltage VCOMH.

  Next, at time t4, supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y2 is stopped, and the voltage of the scanning line Y2 is set to the voltage VGL.

  At the same time, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y3 in the third row, and the voltage of the scanning line Y3 is set to the voltage VGH. Then, the unit control circuit P4 provided corresponding to the scanning line Y4 adjacent to the scanning line Y3 uses the L level polarity control signal POL (when the selection circuit RA is used, the latch circuit Q4 The H level polarity control signal POL) is taken in, and the voltage VCOML is output by the selection circuit R4. For this reason, the common line Z4 connected to the unit control circuit P4 becomes the voltage VCOML.

  The unit control circuit P2 provided corresponding to the scanning line Y2 adjacent to the scanning line Y3 takes in the L-level polarity control signal POL by the latch circuit Q2, and outputs the voltage VCOML by the selection circuit R2. . For this reason, the common line Z2 connected to the unit control circuit P2 becomes the voltage VCOML.

  Next, at time t5, supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y3 is stopped, and the voltage of the scanning line Y3 is set to the voltage VGL.

  At the same time, the selection voltage is supplied from the scanning line driving circuit 10 to the fourth scanning line Y4, and the voltage of the scanning line Y4 is set to the voltage VGH. Then, the unit control circuit P5 provided corresponding to the scanning line Y5 adjacent to the scanning line Y4 takes in the L level polarity control signal POL by the latch circuit Q5, and outputs the voltage VCOMH by the selection circuit R5. . For this reason, the common line Z5 connected to the unit control circuit P5 becomes the voltage VCOMH.

  The unit control circuit P3 provided corresponding to the scanning line Y3 adjacent to the scanning line Y4 takes in the L level polarity control signal POL by the latch circuit Q3 and outputs the voltage VCOMH by the selection circuit R3. . For this reason, the common line Z3 connected to the unit control circuit P3 becomes the voltage VCOMH.

  Thereafter, when the selection voltage is supplied from the scanning line driving circuit 10 to the odd-numbered scanning lines Y (except for the first-row scanning lines Y1), the operation is performed at time t4, and the even-numbered scanning lines Y are operated. When a selection voltage is supplied to (except for the scanning line Y320 in the 320th row), the operation is performed at time t5.

  Next, at time t7, supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y320 in the 320th row is stopped, and the voltage of the scanning line Y320 is set to the voltage VGL.

  At the same time, the polarity control signal POL is set to the voltage VHH, and the polarity control signal POL is set to the H level. Then, the unit control circuits P1 and P320 always use the latch circuits Q1 and Q320 to take in the polarity control signal POL, and the H level polarity control signal POL (if the selection circuit RA is used, the latch circuit Q320 controls the L level polarity. The signal POL) is taken in, and the voltage VCOML and the voltage VCOMH are output by the selection circuits R1 and R320, respectively. Therefore, the common line Z1 connected to the unit control circuit P1 becomes the voltage VCOML, and the common line Z320 connected to the unit control circuit P320 becomes the voltage VCOMH.

  Next, at time t8, similarly to time t2, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y1, and the voltage of the scanning line Y1 is set to the voltage VGH. Then, since the unit control circuit P2 outputs the voltage VCOMH, the common line Z2 connected to the unit control circuit P2 becomes the voltage VCOMH.

  Next, at time t9, similarly to time t3, supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y1 is stopped, and the voltage of the scanning line Y1 is set to the voltage VGL.

  At the same time, similarly to the time t3, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y2, and the voltage of the scanning line Y2 is set to the voltage VGH. Then, since the unit control circuit P3 outputs the voltage VCOML, the common line Z3 connected to the unit control circuit P3 becomes the voltage VCOML.

  Next, at time t10, similarly to time t4, the supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y2 is stopped, and the voltage of the scanning line Y2 is set to the voltage VGL.

  At the same time, similarly to time t4, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y3, and the voltage of the scanning line Y3 is set to the voltage VGH. Then, since the unit control circuit P4 outputs the voltage VCOMH, the common line Z4 connected to the unit control circuit P4 becomes the voltage VCOMH.

  Similarly to time t4, the unit control circuit P2 outputs the voltage VCOMH, so the common line Z2 connected to the unit control circuit P2 becomes the voltage VCOMH.

  Next, at time t11, similarly to time t5, the supply of the selection voltage from the scanning line driving circuit 10 to the scanning line Y3 is stopped, and the voltage of the scanning line Y3 is set to the voltage VGL.

  At the same time, similarly to time t5, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y4, and the voltage of the scanning line Y4 is set to the voltage VGH. Then, since the unit control circuit P5 outputs the voltage VCOML, the common line Z5 connected to the unit control circuit P5 becomes the voltage VCOML.

  Similarly to time t5, the unit control circuit P3 outputs the voltage VCOML, so the common line Z3 connected to the unit control circuit P3 becomes the voltage VCOML.

  Thereafter, when a selection voltage is supplied from the scanning line driving circuit 10 to the odd-numbered scanning lines Y (except for the scanning lines Y1), the operation is performed at time t10, and the even-numbered scanning lines Y (however, scanning is performed). When a selection voltage is supplied to (except for the line Y320), the operation is performed at time t11.

  The operation of the liquid crystal device 1 including the control circuit 30 will be described with reference to FIGS.

  FIG. 7 is a timing chart at the time of positive polarity writing of the liquid crystal device 1. FIG. 8 is a timing chart at the time of negative polarity writing of the liquid crystal device 1.

  7 and 8, GATE (r) is the voltage of the scanning line Yr of the r-th row (r is an integer satisfying 1 ≦ r ≦ 320) among the 320 scanning lines Y, and SOURCE (s). Is the voltage of the data line Xs of the s-th column (s is an integer satisfying 1 ≦ s ≦ 240) among the 240 data lines X. PIX (r, s) is a pixel electrode 55 provided in the pixel 50 in the r-th row and the s-th column provided corresponding to the intersection of the scanning line Yr in the r-th row and the data line Xs in the s-th column. Is the voltage. VCOM (r) is a voltage of the common electrode 56 connected to the common line Zr in the r-th row.

  First, the positive polarity writing of the liquid crystal device 1 will be described with reference to FIG.

  At time t21, the control circuit 30 supplies the voltage VCOML to the common line Zr. Then, the voltage VCOM (r) of the common electrode 56 connected to the common line Zr gradually decreases and becomes the voltage VCOML at time t22.

  When the voltage VCOM (r) of the common electrode 56 connected to the common line Zr decreases, the voltage PIX (r, s) of the pixel electrode 55 included in the pixel 50 in the r-th row and the s-th column is equal to the voltage VCOM (r) and the voltage. It decreases so as to keep the potential difference from PIX (r, s). For this reason, the voltage PIX (r, s) of the pixel electrode 55 included in the pixel 50 in the r-th row and the s-th column gradually decreases and becomes the voltage VP1 at time t22.

  At time t23, the scanning line driving circuit 10 supplies a selection voltage to the scanning line Yr. Then, the voltage GATE (r) of the scanning line Yr rises and becomes the voltage VGH at time t24. Thereby, all the TFTs 51 connected to the scanning line Yr are turned on.

  At time t25, the data line driving circuit 20 supplies a positive image signal to the data line Xs. Then, the voltage SOURCE (s) of the data line Xs gradually rises and becomes the voltage VP3 at time t26.

  The voltage SOURCE (s) of the data line Xs is an image voltage based on a positive-polarity image signal, and the pixel electrode 55 included in the pixel 50 in the r-th row and s-th column via the on-state TFT 51 connected to the scanning line Yr. Is written to. For this reason, the voltage PIX (r, s) of the pixel electrode 55 included in the pixel 50 in the r-th row and the s-th column gradually increases, and has the same potential as the voltage SOURCE (s) of the data line Xs at time t26. The voltage becomes VP3.

  At time t27, the scanning line driving circuit 10 stops supplying the selection voltage to the scanning line Yr. Then, the voltage GATE (r) of the scanning line Yr decreases and becomes the voltage VGL at time t28. As a result, all the TFTs 51 connected to the scanning line Yr are turned off.

  Next, the negative polarity writing of the liquid crystal device 1 will be described with reference to FIG.

  At time t31, the control circuit 30 supplies the voltage VCOMH to the common line Zr. Then, the voltage VCOM (r) of the common electrode 56 connected to the common line Zr gradually increases and becomes the voltage VCOMH at time t32.

  When the voltage VCOM (r) of the common electrode 56 connected to the common line Zr rises, the voltage PIX (r, s) of the pixel electrode 55 included in the pixel 50 in the r row and s column becomes the voltage VCOM (r) and the voltage It rises so as to keep the potential difference from PIX (r, s). For this reason, the voltage PIX (r, s) of the pixel electrode 55 included in the pixel 50 in the r-th row and the s-th column gradually increases and becomes the voltage VP6 at time t32.

  At time t33, the scanning line driving circuit 10 supplies a selection voltage to the scanning line Yr. Then, the voltage GATE (r) of the scanning line Yr increases and becomes the voltage VGH at time t34. Thereby, all the TFTs 51 connected to the scanning line Yr are turned on.

  At time t35, the data line driving circuit 20 supplies a negative image signal to the data line Xs. Then, the voltage SOURCE (s) of the data line Xs gradually decreases and becomes the voltage VP4 at time t36.

  The voltage SOURCE (s) of the data line Xs is an image voltage based on a negative image signal, and the pixel electrode 55 included in the pixel 50 in the r-th row and the s-th column through the on-state TFT 51 connected to the scanning line Yr. Is written to. For this reason, the voltage PIX (r, s) of the pixel electrode 55 included in the pixel 50 in the r-th row and the s-th column gradually decreases and has the same potential as the voltage SOURCE (s) of the data line Xs at time t36. The voltage becomes VP4.

  At time t37, the scanning line driving circuit 10 stops supplying the selection voltage to the scanning line Yr. Then, the voltage GATE (r) of the scanning line Yr decreases and becomes the voltage VGL at time t38. As a result, all the TFTs 51 connected to the scanning line Yr are turned off.

  According to this embodiment, there are the following effects.

  (1) After supplying the voltage VCOML to the common line Z and setting the voltage of the common electrode 56 to the voltage VCOML, a positive image signal is supplied to the data line X, and the positive image voltage is applied to the pixel electrode 55. I wrote. In addition, after supplying the voltage VCOMH to the common line Z and setting the voltage of the common electrode 56 to the voltage VCOMH, a negative image signal is supplied to the data line X, and a negative image voltage is written to the pixel electrode 55. It is. For this reason, unlike the conventional example described above, the charge does not move between the storage capacitor 53 and the pixel capacitor 54. Therefore, even if characteristic variations occur in the storage capacitor 53, the voltage of the pixel electrode 55 does not vary. . Therefore, it is possible to suppress a decrease in display quality.

  (2) The voltage VCOM (r) of the common electrode 56 is changed to the voltage VCOML or the voltage VCOMH. Therefore, since the voltage of one electrode (auxiliary capacitance electrode) of the storage capacitor 53 can be changed in the same manner as the common electrode 56, the storage capacitor 53 can be formed integrally with the pixel capacitor 54. Accordingly, the liquid crystal device 1 according to the present invention includes the pixel electrode 55 and the common electrode 56 constituting the pixel capacitor 54 on the element substrate 60 of the element substrate 60 and the counter substrate 70 as a pair of substrates that sandwich the liquid crystal. Can be configured.

  (3) The common electrode 56 is divided for each horizontal line. Then, the voltage VCOML and the voltage VCOMH are alternately supplied to the common electrode 56 for each horizontal line, and in accordance with the voltage of the common electrode 56, a positive image signal and a negative image signal are obtained. The data lines X were alternately supplied to each horizontal line. For this reason, the pixels 50 that have been written with a positive polarity and the pixels 50 that have been written with a negative polarity can be mixed in one frame, and flicker can be offset between these pixels 50, resulting in lower display quality. Can be further suppressed.

  (4) The control circuit 30 is provided with 320 unit control circuits P (P1 to P320) corresponding to 320 rows of scanning lines Y (Y1 to Y320), and each unit control circuit P includes a latch circuit Q and A selection circuit R is provided. Therefore, the control circuit 30 can selectively supply either the voltage VCOML or the voltage VCOMH to the common electrode 56.

  (5) When the selection voltage is supplied to the scanning line Y adjacent to the scanning line Y corresponding to the unit control circuit P, the latch circuit Q holds the polarity control signal. For this reason, the plurality of unit control circuits P sequentially hold the polarity control signals based on the selection voltages sequentially supplied to the plurality of scanning lines Y by the scanning line driving circuit 10. For this reason, since the control circuit 30 does not require a sequential transfer circuit such as a shift register circuit in order to sequentially transfer the polarity control signal to the plurality of unit control circuits P, the power consumption can be reduced.

  (6) The polarity control signal POL is always taken in by the latch circuits Q1 and Q320, and when the selection voltage is supplied to at least one of the two adjacent scanning lines Y by the latch circuits Q2 to Q319, the polarity control signal Was imported. Therefore, not only when the scanning line driving circuit 10 selects the scanning line Y1 to the scanning line Y320, but also when the scanning line driving circuit 10 selects the scanning line Y320 to the scanning line Y1 in order, the control circuit 30 Can sequentially transfer polarity control signals to a plurality of unit control circuits P.

  (7) In the selection circuit RA, the circuit area can be reduced by making the switching element used for the transfer gate into a single channel as compared with the case where the CMOS switching element used in the selection circuit R is used. .

  In the selection circuit RA, the Pch switching element is connected to the voltage VCOMH, the Nch switching element is connected to the voltage VCOML, and each of the selection circuits RA is turned on exclusively. Driving with only one control signal is possible, and it is not necessary to form an inversion signal using the inverter 36 unlike the selection circuit R, so that the inverter 36 can be reduced. Therefore, a further reduction in circuit area can be realized.

  The potential relationship between the voltage VCOMH, the voltage VCOML, and the polarity control signal POL applied to the gate terminal as the gate voltage of the switching element satisfies the relationship of gate high voltage> voltage VCOMH> voltage VCOML> gate low voltage. By configuring, even if the switching element used for the transfer gate is made into a single channel, it is possible to effectively reduce the on-resistance and reduce the off-leakage of the switching element.

  More preferably, the potential relationship between the voltage VCOMH and the voltage VCOML and the polarity control signal POL applied to the gate terminal of the switching element is expressed as follows: gate high voltage> voltage VCOMH− | Pch transfer gate threshold value |> voltage VCOML + | Nch Since the switching elements can be turned off below the threshold value, the off-leakage can be surely prevented.

<Second Embodiment: Example of COM Split Drive>
FIG. 9 is a block diagram of a control circuit 30A according to the second embodiment of the present invention.

  In the present embodiment, the configuration of the latch circuit Q1A provided corresponding to the first scanning line Y1 and the latch circuit Q320A provided corresponding to the 320th scanning line Y320 is the first implementation. Is different from the latch circuits Q1 and Q320. About another structure, it is the same as that of 1st Embodiment, and abbreviate | omits description.

  In place of the selection circuit R, a selection circuit RA can be used. In this case, as described in the modification of the first embodiment, the second inverter 33 is deleted in the latch circuit Q provided corresponding to the scanning line Y of the even-numbered row, and the first The polarity control signal POL that is inverted and output from the clocked inverter 34 is output as it is, so that the voltage VCOMH and the voltage VCOML are alternately output to the common line Z.

  Each of the latch circuits Q1A and Q320A includes a first inverter 32, a second inverter 33, a first clocked inverter 34, a second clocked inverter 35, and a third inverter 39. .

  The scanning line Y1 is connected to the input terminal of the third inverter 39 provided in the latch circuit Q1A, and the scanning line Y320 is connected to the input terminal of the third inverter 39 provided in the latch circuit Q320A. The output terminals of the third inverter 39 include an input terminal of the first inverter 32, an inverting input control terminal of the first clocked inverter 34, and a non-inverting input control terminal of the second clocked inverter 35. , Is connected.

  The latch circuit Q1A operates as follows.

  That is, when the selection voltage is supplied to the scanning line Y1, the third inverter 39 provided in the latch circuit Q1A outputs an L level signal. This L level signal is input to the inverting input control terminal of the first clocked inverter 34, and is inverted by the first inverter 32, and is input to the non-inverting input of the first clocked inverter 34 as an H level signal. Input to the terminal. Therefore, the first clocked inverter 34 is turned on and inverts and outputs the polarity control signal POL. The polarity control signal POL output after being inverted from the first clocked inverter 34 is inverted by the second inverter 33 and output.

  Further, when the selection voltage is supplied to the scanning line Y320, the latch circuit Q320A is inverted and output from the first clocked inverter 34 in the same manner as the above-described latch circuit Q1A (however, when the selection circuit RA is used). The output polarity control signal POL is output as it is).

  As described above, when the selection voltage is supplied to the scanning line Y1 by the scanning line driving circuit 10, the latch circuit Q1A takes in the polarity control signal POL and the scanning line driving circuit 10 supplies the selection voltage to the scanning line Y320. Then, the latch circuit Q320A takes in the polarity control signal POL.

  FIG. 10 is a timing chart of the control circuit 30A.

  The timing chart of the control circuit 30A shown in FIG. 10 differs from the timing chart of the control circuit 30 of the first embodiment shown in FIG.

  The common line Z1 supplies a selection voltage from the scanning line driving circuit 10 to the scanning line Y1, and at the same time, the voltage is inverted.

  Specifically, at time t41, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y1, and at the same time, the unit control circuit P1A takes in the L level polarity control signal POL by the latch circuit Q1A, The selection circuit R1 outputs a voltage VCOMH. For this reason, the common line Z1 connected to the unit control circuit P1A becomes the voltage VCOMH.

  At time t44, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y1, and at the same time, the unit control circuit P1A takes in the H level polarity control signal POL by the latch circuit Q1A, and selects the selection circuit R1. Thus, the voltage VCOML is output. For this reason, the common line Z1 connected to the unit control circuit P1A becomes the voltage VCOML.

  Similarly to the common line Z1, the common line Z320 is supplied with a selection voltage from the scanning line driving circuit 10 to the scanning line Y320, and at the same time, the polarity of the voltage is inverted.

  Specifically, at time t43, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y320, and at the same time, the unit control circuit P320A causes the L level polarity control signal POL (selection circuit RA to be selected) by the latch circuit Q320A. , The latch circuit Q320A takes in the H level polarity control signal POL), and the selection circuit R320 outputs the voltage VCOML. For this reason, the common line Z320 connected to the unit control circuit P320A becomes the voltage VCOML.

  At time t44, the selection voltage is supplied from the scanning line driving circuit 10 to the scanning line Y320, and at the same time, the unit control circuit P320A takes in the H level polarity control signal POL by the latch circuit Q320A, and selects the selection circuit R320. Thus, the voltage VCOMH is output. For this reason, the common line Z320 connected to the unit control circuit P320A becomes the voltage VCOMH.

  According to this embodiment, there are the following effects.

  (8) As shown in FIG. 2, the common electrode 56 is divided for each horizontal line. For this reason, if the voltage of the common electrode 56 is different for each adjacent horizontal line, an electric field is generated between them, and the alignment and order of the liquid crystal may be slightly changed. In particular, in the first embodiment, as illustrated in FIG. 6, the voltage of the common line Z319 is the voltage VCOMH and the voltage of the common line Z320 is the voltage VCOML during the period from time t6 to t7. Here, the period of time t6 to t7 corresponds to a period three times as long as the period of selecting the scanning line Y by the scanning line driving circuit 10. Therefore, an electric field is generated between the common electrode 56 connected to the common line Z319 and the common electrode 56 connected to the common line Z320 during the period of time t6 to t7, and the alignment and order of the liquid crystal are changed. There was a case where it changed greatly.

  Therefore, at the same time as the selection voltage is supplied to the scanning line Y320, the polarity of the voltage of the common line Z320 is inverted, and a period in which the voltage of the common line Z319 and the voltage of the common line Z320 are different is a period of time t42 to t43. It was. Here, the period from time t42 to t43 corresponds to a period twice as long as the period for selecting the scanning line Y by the scanning line driving circuit 10, and therefore, compared with the first embodiment, the voltage of the common line Z319 is common. The period in which the voltage of the line Z320 is different is short. Therefore, compared with the first embodiment, an electric field is generated between the common electrode 56 connected to the common line Z319 and the common electrode 56 connected to the common line Z320, and the alignment and order of the liquid crystal are The change can be suppressed.

<Third Embodiment: Example of COM Split Drive>
FIG. 11 is an enlarged plan view of a pixel 50A according to the third embodiment of the present invention.

  This embodiment is different from the pixel 50 of the first embodiment in that the pixel 50A includes the auxiliary common line ZA and the contact portion 58. About another structure, it is the same as that of 1st Embodiment, and abbreviate | omits description.

  The auxiliary common line ZA is made of a conductive metal and is provided corresponding to the common electrode 56 provided by being divided for each horizontal line. The auxiliary common line ZA is formed along the scanning line Y.

  The contact portion 58 is made of a conductive metal, and is connected to the auxiliary common line ZA in the region 581, and is connected to the common electrode 56 and the common line Z in the region 582.

  According to this embodiment, there are the following effects.

  (9) An auxiliary common line ZA made of conductive metal is provided corresponding to the common electrode 56 divided and provided for each horizontal line, and the common electrode 56 is connected via a contact portion 58 made of conductive metal. The common line Z and the auxiliary common line ZA were connected. Therefore, the time constant of the common electrode 56 and the common line Z can be reduced.

<Fourth Embodiment: Example of SSL Drive>
FIG. 12 is a block diagram of a vertical electric field mode liquid crystal device 1 ′ employing SSL driving that varies the voltage of the capacitor line according to the fourth embodiment of the present invention.

  The liquid crystal device 1 ′ includes a liquid crystal panel AA ′ and a backlight 41 ′ disposed opposite to the liquid crystal panel AA ′ and emitting light. The liquid crystal device 1 ′ performs transmissive display using light from the backlight 41 ′.

  The liquid crystal panel AA ′ includes a display area A ′ having a plurality of pixels 50 ′, a scanning line driving circuit 10 ′ that is provided around the display area A ′, and drives the pixels 50 ′, a data line driving circuit 20 ′, And a control circuit 30 '.

  The backlight 41 ′ is provided on the back surface of the liquid crystal panel AA ′, and is composed of, for example, a cold cathode fluorescent tube (CCFL), an LED (light emitting diode), or electroluminescence (EL), and the pixel 50 of the liquid crystal panel AA ′. 'Supply the light.

  Hereinafter, the configuration of the liquid crystal panel AA 'will be described in detail.

  The liquid crystal panel AA ′ includes 320 scanning lines Y ′ (Y′1 to Y′320) and 320 common lines Z ′ (Z′1 to Z′320) alternately provided at predetermined intervals, 240 columns of data lines X ′ (X′1 to X′240) provided so as to intersect the scanning lines Y ′ (Y′1 to Y′320) and the auxiliary capacitance lines SC (SC1 to SC320); Is provided. Pixels 50 ′ are provided at intersections between the scanning lines Y ′ and the data lines X ′.

  The pixel 50 ′ includes a TFT 51 ′, a pixel electrode 55 ′, a common electrode 56 ′ provided to face the pixel electrode 55 ′, and one electrode (auxiliary capacitance electrode 57 ′) connected to the auxiliary capacitance line SC. The other electrode (the pixel electrode 55 ′ or the electrode layer connected to the pixel electrode 55 ′) is constituted by a storage capacitor 53 ′ as an auxiliary capacitor connected to the pixel electrode 55 ′. The pixel electrode 55 'and the common electrode 56' constitute a pixel capacitor 54 '. The liquid crystal panel AA ′ is bonded so that an element substrate on which various elements, a pixel electrode 55 ′, and the like are formed, and a counter substrate on which a common electrode 56 ′ is formed so that the electrode formation surfaces face each other across the liquid crystal. It has been configured.

  The common electrode 56 'is formed on almost the entire surface of the counter substrate. A configuration may be adopted in which each horizontal line is divided corresponding to the scanning line Y ′. In this case, the plurality of common electrodes 56 ′ divided for each horizontal line are connected by a common line Z ′.

  The scanning line Y ′ is connected to the gate of the TFT 51 ′, the data line X ′ is connected to the source of the TFT 51 ′, and the other electrode of the pixel electrode 55 ′ and the storage capacitor 53 ′ is connected to the drain of the TFT 51 ′. Is connected. Accordingly, the TFT 51 'is turned on when a selection voltage is applied from the scanning line Y', and the data line X ', the pixel electrode 55', and the other electrode of the storage capacitor 53 'are brought into conduction.

  The scanning line driving circuit 10 'includes a shift register, an output control circuit, and a buffer circuit, and sequentially supplies a selection voltage for turning on the TFT 51' to the plurality of scanning lines Y '. For example, when a selection voltage is supplied to a certain scanning line Y ′, all the TFTs 51 ′ connected to the scanning line Y ′ are turned on, and all the pixels 50 ′ related to the scanning line Y ′ are selected.

  The data line driving circuit 20 ′ supplies an image signal to the data line X ′, and writes an image voltage based on the image signal to the pixel electrode 55 ′ through the TFT 51 ′ in the on state.

  Here, the data line driving circuit 20 ′ supplies a positive polarity image signal having a higher potential than the voltage of the common electrode 56 ′ to the data line X ′, and applies an image voltage based on the positive polarity image signal to the pixel electrode. The negative polarity image signal having a lower potential than the voltage of the common electrode 56 ′ is supplied to the data line X ′, and the image voltage based on the negative polarity image signal is applied to the pixel electrode 55. The negative polarity writing to 'is alternately performed for each horizontal line.

  The control circuit 30 ′ alternately supplies the voltage VSTL as the first voltage and the voltage VSTH as the second voltage having a higher potential than the voltage VSTL to the auxiliary capacitance line SC.

  The control circuit 30 ′ includes 320 unit control circuits P ′ (P ′ 1 to P ′ 320) corresponding to 320 rows of scanning lines Y ′ (Y ′ 1 to Y ′ 320). Each unit control circuit P ′ is supplied with a voltage VSTL, a voltage VSTH, and a polarity control signal POL for selecting either the voltage VSTL or the voltage VSTH.

  The unit control circuit P ′ includes a latch circuit Q ′ that holds the polarity control signal POL, and a selection circuit R ′ that selectively outputs either the voltage VSTL or the voltage VSTH according to the polarity control signal.

  FIG. 13 is a block diagram showing a circuit configuration of the selection circuit R ′, and shows an example in which a single-channel switching transistor is used as a switching element used for a transfer gate.

  The selection circuit R ′ includes a Pch transfer gate RP ′ composed of a Pch switching element and an Nch transfer gate RN ′ composed of an Nch switching element.

  The voltage VSTH is connected to the input terminal of the Pch transfer gate RP ′, the output terminal of the latch circuit Q ′ is connected to the control terminal (gate terminal) of the Pch transfer gate RP ′, and the output of the Pch transfer gate RP ′. The storage capacitor line SC is connected to the terminal.

  By connecting the voltage VSTH to the input terminal of the Pch transfer gate RP, the gate-source voltage VGS can be made larger than when the voltage VSTH is connected to the input terminal of the Nch transfer gate RN. In addition, a low on-resistance and a reduction in off-leak can be realized.

  The voltage VSTL is connected to the input terminal of the Nch transfer gate RN ′, the output terminal of the latch circuit Q ′ is connected to the control terminal (gate terminal) of the Nch transfer gate RN ′, and the output of the Nch transfer gate RN ′. The storage capacitor line SC is connected to the terminal.

  By connecting the voltage VSTL to the input terminal of the Nch transfer gate RN, the gate-source voltage VGS can be made larger than when the Pch transfer gate RP is used, so that the operation is good and the on-resistance is further reduced. In addition, off-leakage can be reduced.

  The above selection circuit R ′ operates as follows.

  That is, when the L level polarity control signal POL is output from the latch circuit Q ', the L level polarity control signal POL is input to the control terminal of the Pch transfer gate RP'. Therefore, the Pch transfer gate RP ′ is turned on. The Pch transfer gate RP ′ that has been turned on outputs the voltage VSTH to the storage capacitor line SC.

  On the other hand, when the H level polarity control signal POL is output from the latch circuit Q ', the H level polarity control signal POL is input to the control terminal of the Nch transfer gate RN'. Therefore, the Nch transfer gate RN ′ is turned on. The Nch transfer gate RN ′ that has been turned on outputs the voltage VSTL to the storage capacitor line SC.

  As described above, in the selection circuit R ′, the circuit area can be reduced by making the switching element used for the transfer gate a single channel as compared with the case where the selection circuit R uses a CMOS switching element. Further, the Pch switching element is connected to the high-potential voltage VSTH, and the Nch switching element is connected to the low-potential voltage VSTL. Can be driven by only one control signal, and an inverter circuit required when a CMOS switching element is used is not required. Therefore, the circuit area can be further reduced.

  The potential relationship between the voltage VSTH, the voltage VSTL, and the polarity control signal POL applied to the gate terminal as the gate voltage of the switching element is as follows: gate high voltage (high potential of the polarity control signal POL)> voltage VTH> voltage VSTL> gate Low. The voltage (the low potential of the polarity control signal POL) is configured to satisfy the relationship.

  With such a configuration, even if the switching element used for the transfer gate is made into a single channel, it is possible to efficiently reduce the on-resistance and reduce the off-leakage of the switching element.

  More preferably, the potential relationship between the voltage VSTH, the voltage VSTL, and the polarity control signal POL applied to the gate terminal as the gate voltage of the switching element is expressed as follows: Gate High voltage> Voltage VSTH− | Pch threshold of transfer gate |> Voltage VSTL + | By configuring so as to satisfy the threshold value of the Nch transfer gate |> gate low voltage, each switching element can be turned off below the threshold value, so that off-leakage can be reliably prevented.

  For example, the gate high voltage is set to 8V, which is the same as a voltage VGH described later, the gate low voltage is set to -4V, the voltage VSTH is set to 4V, and the voltage VSTL is set to 0V.

  The liquid crystal device 1 'as described above operates as follows.

  By sequentially supplying a selection voltage from the scanning line driving circuit 10 ′ to the 320 scanning lines Y ′ (Y′1 to Y′320), all the TFTs 51 ′ connected to the scanning lines Y ′ are sequentially turned on. In this manner, all the pixels 50 ′ relating to each scanning line Y ′ are sequentially selected.

  Next, in synchronization with the selection of the pixels 50 ′, a positive image signal and a negative image signal are alternately supplied from the data line driving circuit 20 ′ to the data line X ′ for each horizontal line. .

  Next, either the voltage VSTL or the voltage VSTH is selectively supplied from the control circuit 30 ′ to the auxiliary capacitance line SC. Specifically, when a positive image signal is supplied to the pixel 50 ′ related to the selected scanning line Y ′ among the 320 scanning lines Y ′, the auxiliary capacitance line SCp related to the selected pixel 50 ′. Is supplied with a voltage VSTH. On the other hand, when a negative image signal is supplied to the pixel 50 ′ related to the selected scanning line Y ′ among the 320 scanning lines Y ′, the voltage VSTL is applied to the auxiliary capacitance line SCp related to the selected pixel 50 ′. Supply.

  That is, either the voltage VSTL or the voltage VSTH is selectively supplied from the control circuit 30 ′ to the auxiliary capacitance line SC according to the polarity of the pixel signal supplied to the pixel 50 ′.

  A voltage VSTL and a voltage VSTH are alternately supplied to each auxiliary capacitance line SC every frame period. For example, when the voltage VSTL is supplied to the p-th storage capacitor line SCp (p is an integer satisfying 1 ≦ p ≦ 320) in one frame period, the voltage is applied to the storage capacitor line SCp in the next one frame period. Supply VSTH. On the other hand, when the voltage VSTH is supplied to the auxiliary capacitance line SCp in one frame period, the voltage VSTL is supplied to the auxiliary capacitance line SCp in the next one frame period.

  Also, different voltages are supplied to adjacent storage capacitor lines SC. For example, when the voltage VSTL is supplied to the storage capacitor line SCp in one frame period, the storage capacitor line SC (p−1) in the (p−1) th row and the (p + 1) th row in the same one frame period. The voltage VSTH is supplied to the auxiliary capacitance line SC (p + 1) of the eye. On the other hand, when the voltage VSTH is supplied to the auxiliary capacitance line SCp in one frame period, the voltage VSTL is supplied to the auxiliary capacitance line SC (p−1) and the auxiliary capacitance line SC (p + 1) in the same one frame period. To do.

  As described above, after the positive image voltage is written to the pixel electrode 55 ', the voltage of the storage capacitor line SC is increased. For this reason, the voltage of the pixel electrode 55 ′ increases by the sum of the voltage increased by the positive image voltage and the voltage increased by the charge corresponding to the increase of the voltage of the auxiliary capacitance line SC. .

  On the other hand, after the negative image voltage is written to the pixel electrode 55 ′, the voltage of the storage capacitor line SC is lowered. For this reason, the voltage of the pixel electrode is reduced by the sum of the voltage reduced by the negative image voltage and the voltage reduced by the charge corresponding to the amount of reduction of the voltage of the capacitor line.

  Therefore, by changing the voltage of the storage capacitor line SC, the voltage of the pixel electrode 55 ′ can be changed with reference to the voltage of the common electrode 56 ′, and the amplitude of the drive voltage applied to the liquid crystal can be increased. Therefore, even if the amplitude of the image voltage is reduced, the amplitude of the drive voltage applied to the liquid crystal can be secured, so that the power consumption can be reduced by reducing the amplitude of the image voltage.

  The operation of this drive voltage will be described with reference to FIGS.

  FIG. 14 is a timing chart at the time of positive polarity writing of the liquid crystal device according to the fourth embodiment. FIG. 15 is a timing chart at the time of negative polarity writing of the liquid crystal device according to the fourth embodiment.

  14 and 16, GATE (m) is the voltage of the scanning line Y ′ in the m-th row (m is an integer satisfying 1 ≦ m ≦ 320) among the 320 scanning lines Y ′, and VST ( m) is the voltage of the auxiliary capacitance line SC of the mth row among the 320 capacitance lines. SOURCE (n) is the voltage of the data line of the nth column (n is an integer satisfying 1 ≦ n ≦ 240) among the 240 data lines X ′. Further, PIX (m, n) is a pixel electrode provided in the pixel in the m-th row and the n-th column provided corresponding to the intersection of the scanning line Y ′ in the m-th row and the data line X ′ in the n-th column. VST (m) is a voltage of the common electrode 56 ′ included in the pixel in the m-th row and the n-th column.

  First, the positive polarity writing of the liquid crystal device will be described with reference to FIG.

  At time t51, the scanning line driving circuit 10 'supplies a selection voltage to the m-th scanning line Y'. Then, the voltage GATE (m) of the m-th scanning line rises and becomes the voltage VGH at time t52. As a result, all TFTs connected to the m-th scanning line are turned on.

  At time t53, the data line driving circuit 20 'supplies a positive image signal to the n-th data line X'. Then, the voltage SOURCE (n) of the data line X ′ in the nth column gradually rises to become the voltage VP8 at time t54.

  The voltage SOURCE (n) of the n-th data line X ′ is an image voltage based on a positive image signal, and is supplied to the m-th row via the on-state TFT 51 ′ connected to the m-th scanning line Y ′. Data is written to the pixel electrode 55 ′ included in the pixel in the nth column. Therefore, the voltage PIX (m, n) of the pixel electrode 55 ′ included in the pixel 50 ′ of the m-th row and the n-th column gradually increases, and at time t54, the voltage SOURCE ( The voltage VP8 is the same potential as n).

  At time t55, the scanning line driving circuit 10 'stops supplying the selection voltage to the m-th scanning line Y'. Then, the voltage GATE (m) of the m-th scanning line Y ′ decreases and becomes the voltage VGL at time t56. As a result, all the TFTs 51 ′ connected to the m-th scanning line Y ′ are turned off.

  At the same time, the control circuit 30 ′ supplies a voltage for increasing the voltage of the storage capacitor line SC to the m-th row storage capacitor line SC. As a result, the voltage VST (m) of the m-th auxiliary capacitance line SC gradually increases, and reaches the voltage VSTH at time t57.

  When the voltage VST (m) of the m-th storage capacitance line SC increases, in all the pixels 50 ′ related to the m-th storage capacitance line SC, the charge corresponding to the increased amount is stored in the storage capacitors 53 ′ and the pixels. It is distributed between the capacity 54 '. For this reason, the voltage PIX (m, n) of the pixel electrode 55 ′ included in the pixel 50 ′ in the m-th row and n-th column gradually increases, and reaches the voltage VP 9 at time t 57.

  Next, the negative polarity writing of the liquid crystal device will be described with reference to FIG.

  At time t61, the scanning line driving circuit 10 'supplies a selection voltage to the m-th scanning line Y'. Then, the voltage GATE (m) of the m-th scanning line Y ′ rises and becomes the voltage VGH at time t62. As a result, all TFTs connected to the m-th scanning line Y ′ are turned on.

  At time t63, the data line driving circuit 20 'supplies a negative image signal to the n-th data line X'. Then, the voltage SOURCE (n) of the data line X ′ in the nth column gradually decreases and reaches the voltage VP11 at time t64.

  The voltage SOURCE (n) of the n-th column data line X ′ is an image voltage based on a negative-polarity image signal, and is supplied to the m-th row n through the on-state TFT connected to the m-th row scanning line Y ′. Writing is performed to the pixel electrode 55 ′ included in the pixel 50 ′ in the column. Therefore, the voltage PIX (m, n) of the pixel electrode 55 ′ included in the pixel 50 ′ of the m-th row and the n-th column gradually decreases, and at time t64, the voltage SOURCE ( The voltage VP11 is the same potential as n).

  At time t65, the scanning line driving circuit 10 'stops supplying the selection voltage to the m-th scanning line Y'. Then, the voltage GATE (m) of the m-th scanning line Y ′ decreases and becomes the voltage VGL at time t66. As a result, all TFTs connected to the m-th scanning line Y ′ are turned off.

  At the same time, the control circuit 30 'supplies a voltage for reducing the voltage of the auxiliary capacitance line SC to the m-th auxiliary capacitance line SC. Then, the voltage VST (m) of the m-th auxiliary capacitance line SC gradually decreases and becomes the voltage VSTL at time t67.

    When the voltage VST (m) of the m-th storage capacitance line SC decreases, in all the pixels 50 ′ related to the m-th storage capacitance line SC, the charge corresponding to the decreased amount is stored in the storage capacitors 53 ′ and the pixels. It is distributed between the capacity 54 '. For this reason, the voltage PIX (m, n) of the pixel electrode 55 ′ included in the pixel 50 ′ in the m-th row and n-th column gradually decreases, and reaches the voltage VP 10 at time t 67.

<Modification>
Note that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within a scope in which the object of the present invention can be achieved are included in the present invention.

  For example, in each of the above-described embodiments, 320 rows of scanning lines Y and 240 columns of data lines X are provided. However, the present invention is not limited to this. For example, 480 rows of scanning lines Y and 640 columns of rows are provided. And a data line X.

  In each of the above-described embodiments, the transmissive display is performed. However, the present invention is not limited to this. For example, the transmissive display using light from the backlight 41 and the reflection using reflected light of external light are used. A transflective display having both mold display and display may be performed.

  In each of the above-described embodiments, the TFT 51 made of low-temperature polysilicon is provided as the TFT. However, the present invention is not limited to this. For example, a TFT made of amorphous polysilicon may be provided.

  In each of the above-described embodiments, the second insulating film 64 is formed on the common electrode 56 and the pixel electrode 55 is formed on the second insulating film 64. However, the present invention is not limited to this. A second insulating film 64 may be formed on the second insulating film 64, and the common electrode 56 may be formed on the second insulating film 64.

  In each of the above-described embodiments, the liquid crystal operates in the FFS mode. However, the present invention is not limited to this, and the liquid crystal may operate in the IPS mode, for example.

  In each of the above-described embodiments, the common electrode 56 is divided and provided for each horizontal line. However, the present invention is not limited thereto, and may be provided for every two horizontal lines or every three horizontal lines.

  Here, for example, when the common electrode 56 is divided and provided for every two horizontal lines, the control circuit 30 supplies the voltage VCOML and the voltage VCOMH to each of the two common lines Z connected to each common electrode 56. Alternately. In addition, the data line driving circuit 20 alternately performs positive polarity writing and negative polarity writing every two horizontal lines corresponding to the common electrode 56.

<Application example>
Next, an electronic apparatus to which the liquid crystal device 1 according to the first embodiment described above is applied will be described.

  FIG. 16 is a perspective view illustrating a configuration of a mobile phone to which the liquid crystal device 1 is applied. A mobile phone 3000 as an electronic device includes a plurality of operation buttons 3001, scroll buttons 3002, and the liquid crystal device 1. By operating the scroll button 3002, the screen displayed on the liquid crystal device 1 is scrolled.

  As electronic devices to which the liquid crystal device 1 is applied, in addition to those shown in FIG. 16, personal computers, information portable terminals, digital still cameras, liquid crystal televisions, viewfinder type, monitor direct-view type video tape recorders, car navigation devices , Pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. And the liquid crystal device mentioned above is applicable as a display part of these various electronic devices.

1 is a block diagram of a liquid crystal device according to a first embodiment of the present invention. FIG. 3 is an enlarged plan view of a pixel included in the liquid crystal device. FIG. 3 is a cross-sectional view of a pixel included in the liquid crystal device. FIG. 3 is a block diagram of a control circuit included in the liquid crystal device. The block diagram which shows the modification of the selection circuit R of the said control circuit. 4 is a timing chart of a control circuit included in the liquid crystal device. 4 is a timing chart at the time of positive writing of the liquid crystal device. 6 is a timing chart at the time of negative writing of the liquid crystal device. The block diagram of the control circuit which concerns on 2nd Embodiment of this invention. 4 is a timing chart of the control circuit. The enlarged plan view of the pixel concerning a 3rd embodiment of the present invention. The block diagram of the liquid crystal device which concerns on 4th Embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration of a selection circuit of the liquid crystal device. 4 is a timing chart at the time of positive writing of the liquid crystal device. 4 is a timing chart at the time of positive polarity writing and negative polarity writing of the liquid crystal device. The perspective view which shows the structure of the mobile telephone to which the liquid crystal device mentioned above is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1A, 1 '... Liquid crystal device, 10, 10' ... Scan line drive circuit, 20, 20 '... Data line drive circuit, 30, 30A, 30' ... Control circuit, 31 ... NOR circuit, 32 ... 1st Inverter 33 ... second inverter 34 ... first clocked inverter 35 ... second clocked inverter 36 ... inverter 37 ... first transfer gate 38 ... second transfer gate 39 ... first 3, 41, 41 ′... Backlight, 50, 50 ′... Pixel, 51, 51 ′. TFT, 511... Gate electrode, 512. Storage capacitor 54, 54 '... pixel capacitance, 55, 55' ... pixel electrode, 55A ... slit, 56, 56 '... common electrode, 57' ... auxiliary capacitor electrode, 60 ... as the first substrate Sub-substrate, 62... Gate insulating film, 63... First insulating film, 64... Second insulating film, 68, 74 .. glass substrate, 70 .. counter substrate as second substrate, 71. 3000: mobile phone as an electronic device, AA, AA '... liquid crystal panel, A, A' ... display area, E ... electric field, P, P1-P320, P ', P'1-P'320 ... unit control circuit, POL, polarity control signal, Q, Q1 to Q320, Q ′, latch circuit, R, R1 to R320, RA, R ′, selection circuit, RP, RP ′, Pch transfer gate, RN, RN ′, Nch transfer gate, SC, SC1 to SC320 ... auxiliary capacitance line, VCOML, VSTL ... voltage as the first voltage, VCOMH, VSTH ... voltage as the second voltage, VLL ... voltage, X, X1 to X240, X ', X'1 X'240 ... data line, Y, Y1 to Y320, Y ', Y'1 to Y'320 ... scanning line, Z, Z1 to Z320, Z', Z'1 to Z'320 ... common line, ZA ... auxiliary Common line.

Claims (9)

A plurality of scan lines;
A plurality of data lines intersecting the scan lines;
A plurality of pixel electrodes provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
A capacitor electrode provided corresponding to the pixel electrode and forming a capacitor with the pixel electrode or an electrode layer connected to the pixel electrode;
A control circuit that alternately supplies a first voltage and a second voltage having a higher potential than the first voltage to the capacitor electrode;
A scanning line driving circuit for sequentially supplying a selection voltage for selecting the scanning line to the plurality of scanning lines;
When the scanning line is selected, a positive polarity image signal having a higher potential than the first voltage and a negative polarity image signal having a lower potential than the second voltage are alternately supplied to the plurality of data lines. A data line driving circuit, and a liquid crystal device comprising:
The control circuit includes a single-channel switching element that alternately selects the first voltage and the second voltage and outputs the selected voltage to the capacitor electrode.
The single channel switching element that outputs the first voltage is an N channel switching element, and the single channel switching element that outputs the second voltage is a P channel switching element.   The gate voltage supplied to the N-channel switching element and the P-channel switching element is characterized in that the higher voltage is higher than the second voltage, and the lower voltage is lower than the first voltage. The liquid crystal device according to claim 1.   The gate voltage supplied to the N-channel switching element and the P-channel switching element is such that the higher voltage is higher than the voltage obtained by subtracting the absolute value of the threshold value of the P-channel switching element from the second voltage. 2. The liquid crystal device according to claim 1, wherein the voltage is lower than a voltage obtained by adding an absolute value of a threshold value of an N-channel switching element to the first voltage.   The liquid crystal device according to claim 1, wherein the capacitor electrode is a common electrode.   The liquid crystal device according to claim 1, wherein the capacitor electrode is an auxiliary capacitor electrode. The liquid crystal device according to claim 4,
The plurality of scanning lines, the plurality of data lines, a plurality of pixel electrodes provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, and a common provided to face the pixel electrodes A first substrate having electrodes;
A second substrate disposed opposite to the first substrate, and a liquid crystal provided between the first substrate and the second substrate,
In the liquid crystal device, after the first voltage is supplied to the common electrode by the control circuit, the selection voltage is supplied to the scanning line by the scanning line driving circuit, and the positive image is supplied by the data line driving circuit. Supplying a signal to the data line;
After the second voltage is supplied to the common electrode by the control circuit, the selection voltage is supplied to the scanning line by the scanning line driving circuit, and the negative image signal is supplied to the data by the data line driving circuit. A liquid crystal device characterized by being supplied to a wire. A plurality of scanning lines, a plurality of data lines, a plurality of pixel electrodes provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines, and a common electrode provided to face the pixel electrodes. A first substrate having;
A second substrate disposed opposite to the first substrate; a liquid crystal provided between the first substrate and the second substrate;
A control circuit that alternately supplies a first voltage and a second voltage having a higher potential than the first voltage to the common electrode;
A scanning line driving circuit for sequentially supplying a selection voltage for selecting the scanning line to the plurality of scanning lines;
When the scanning line is selected, a positive image signal having a higher potential than the first voltage and a negative image signal having a lower potential than the second voltage are alternately switched to the plurality of data lines. A data line driving circuit for supplying to the liquid crystal device,
The control circuit includes an N-channel switching element that outputs the first voltage to the common electrode, and a P-channel switching element that outputs the second voltage to the common electrode,
After the first voltage is supplied to the common electrode by the control circuit, the selection voltage is supplied to the scanning line by the scanning line driving circuit, and the positive image signal is supplied to the data by the data line driving circuit. Supply to the wire,
After the second voltage is supplied to the common electrode by the control circuit, the selection voltage is supplied to the scanning line by the scanning line driving circuit, and the negative image signal is supplied to the data by the data line driving circuit. A liquid crystal device characterized by being supplied to a wire. A plurality of scanning lines, a data line, a liquid crystal capacitor provided corresponding to the intersection of each of the plurality of scanning lines and the data line, and a liquid crystal sandwiched between a common electrode and a pixel electrode; A switching element, which is interposed between the data line and the pixel electrode, turns on when the scanning line is on potential, and turns off when the scanning line is off potential, and a storage capacitor having one end connected to the pixel electrode A liquid crystal device comprising:
A control circuit that alternately supplies a first voltage and a second voltage having a higher potential than the first voltage to the common electrode;
A scanning line driving circuit for sequentially supplying a selection voltage for selecting the scanning line to the plurality of scanning lines;
When the scanning line is selected, a positive image signal having a higher potential than the first voltage and a negative image signal having a lower potential than the second voltage are alternately switched to the plurality of data lines. A data line driving circuit for supplying to
The control circuit includes an N-channel switching element that outputs the first voltage to the common electrode, and a P-channel switching element that outputs the second voltage to the common electrode,
If the potential of the data line corresponds to the writing of a positive image signal when the scanning line is on-potential, the storage capacitor assists after the scanning line transitions to the off-potential. If the second voltage is supplied to the capacitor electrode and the potential of the data line at the ON potential corresponds to the writing of a negative image signal, the scanning line transits to the OFF potential. And supplying the first voltage to the storage capacitor electrode later.   An electronic apparatus comprising the liquid crystal device according to claim 1.

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