JP2009205044A - Electrooptical device, drive circuit, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress display unevenness generated in a horizontal direction, in a configuration in which a voltage of a common electrode 108 is changed. <P>SOLUTION: The common electrode 108 includes thin film transistors (TFTs) 171 to 174, and 179 in each of 1 to 320 lines. Each scan line is selected twice for preliminary writing and main writing. When a scan line 112 of an i-th row is selected, either the TFT 171 or 172 of the i-th row is turned on and the other is turned off, and this on/off state continues after selection ends. When the scan line 112 of the i-th row is selected for the main writing, the common electrode 108 of the i-th row is connected to either of signal lines 61 and 62, as the TFT 179 of the i-th row is turned on. At this time, a first common signal output circuit 31 or a second common signal output circuit 32 is controlled so that the common electrode of the i-th row may become a voltage Vsl or Vsh according to a writing polarity. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a technique for suppressing display unevenness generated in a horizontal direction when a voltage of a common electrode is changed in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. In order to suppress the voltage amplitude of the data line when the pixel capacitor is AC driven. A technique is known in which the common electrode is individualized for each scanning line, and when the scanning line is selected, the common electrode corresponding to the selected scanning line is set to one of binary voltages corresponding to the writing polarity. (See Patent Document 1).
See Japanese Patent Application Laid-Open No. 2005-3000948

However, with this technique, display irregularities in the horizontal direction are likely to occur as the common electrode is individualized for each scanning line.
The present invention has been made in view of such circumstances, and one of its purposes is to provide a technique for suppressing the occurrence of display unevenness in a configuration in which common electrodes are individually driven.

In order to achieve the above object, a drive circuit of an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of common electrodes provided corresponding to the plurality of scanning lines, Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each having one end connected to the data line and the one end and the other end when the scanning line is selected And a pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode. A driving circuit, wherein one of the plurality of scanning lines is selected as a preliminary write and the other one is selected as a main write, and the selected two scan lines are sequentially shifted. Driving circuit and scanning line driving When one scanning line is selected as the document write by road,
A common electrode driving circuit for connecting a common electrode corresponding to the one scanning line to a predetermined power supply line, and a pixel corresponding to the one scanning line when the one scanning line is selected as main writing. If the positive polarity writing is designated, the common signal controlled so that the common electrode corresponding to the one scanning line becomes the first voltage is negatively applied to the pixel corresponding to the one scanning line. If writing is designated, the common electrode corresponding to the one scanning line has the second voltage higher than the first voltage.
A common signal output circuit for supplying a common signal controlled to a voltage to the predetermined power supply line, and a pixel corresponding to the one scanning line when the one scanning line is selected as the main writing. On the other hand, a data line driving circuit for supplying a data signal having a voltage corresponding to the gradation of the pixel through the data line is provided.
According to the present invention, since the pixel capacitance holds the same polarity voltage by the preliminary writing before the main writing, the burden at the time of writing the voltage corresponding to the gradation is reduced and generated at the time of the main writing. Noise is reduced. In addition, since the common electrode corresponding to the scanning line for the main writing is controlled to be the first or second voltage, the voltage corresponding to the gradation is more accurately written to the pixel capacitance in combination with the noise reduction. It becomes possible.

In the present invention, the predetermined power supply lines are first and second power supply lines, and the common electrode driving circuit is configured so that positive polarity writing is designated for a pixel corresponding to the one scanning line. The common electrode corresponding to the one scanning line is connected to the first power supply line, and if negative writing is designated, the common electrode corresponding to the one scanning line is connected to the second power supply line. And the common signal output circuit includes first and second common signal output circuits, and the first common signal output circuit is connected to the pixel corresponding to the scanning line selected for the main writing. A common signal controlled so that a common electrode corresponding to the selected scanning line becomes the first voltage is supplied to the first feeder line, and the second common signal output circuit is Corresponding to the scanning line selected as the main writing A configuration in which a common signal controlled so that a common electrode corresponding to the selected scanning line becomes the second voltage is supplied to the second power supply line when negative polarity writing is designated for the element. Also good. In this configuration, the common electrode driving circuit includes first to fourth transistor pairs corresponding to the plurality of common electrodes, and among the first to fourth transistors corresponding to the one common electrode, The source electrode of the first transistor is connected to the first power supply line, the source electrode of the second transistor is connected to the second power supply line, the drain electrode of the first transistor and the drain electrode of the second transistor are the The first transistor is connected to one common electrode, and the third transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, and a source electrode that supplies either an on signal or an off signal. The drain electrode is connected to the signal line, the drain electrode is connected to the gate electrode of the first transistor, and the fourth transistor has its gate The pole is connected to the scanning line corresponding to the one common electrode, the source electrode is connected to a second signal line having a logic level exclusive to the first signal line, and the drain electrode is connected to the gate of the second transistor. It may be connected to an electrode. Further, in this configuration, the first common signal output circuit has the common electrode corresponding to the scanning line in the period in which the positive polarity writing is designated for the pixel corresponding to the scanning line selected as the main writing. The first voltage is controlled to be the first voltage, or the common electrode corresponding to the scanning line is controlled to be the first voltage in the second half of the period, and the first voltage is buffered in the other period. Supplying a voltage to the first feeder line;
The common signal output circuit controls the common electrode corresponding to the scanning line to be the second voltage during a period in which negative polarity writing is designated for the pixel corresponding to the scanning line selected as the main writing. Or in the latter half of the period, the common electrode corresponding to the scanning line is the second
The voltage may be controlled to be a voltage, and in another period, a voltage obtained by buffering the second voltage may be supplied to the second power supply line.

On the other hand, in the present invention, the predetermined feeding line is a third feeding line, and the common electrode driving circuit corresponds to the one scanning line when the one scanning line is selected as the main writing. A common electrode is connected to the third power supply line, and the common signal output circuit corresponds to the one scanning line if the positive polarity writing is designated for the pixel corresponding to the one scanning line. A common signal that is controlled so that the common electrode becomes the first voltage, and if negative writing is designated, the common signal that is controlled so that the common electrode corresponding to the one scanning line becomes the second voltage. Signal
It is good also as a structure which each supplies to the said 3rd electric power feeding line. In this configuration, the common electrode driving circuit includes first to fifth transistor groups corresponding to the plurality of common electrodes, and among the first to fifth transistors corresponding to the one common electrode, A source electrode of the first transistor is connected to a first power supply line to which the first voltage is supplied; a source electrode of the second transistor is connected to a second power supply line to which the second voltage is supplied; The first
The drain electrode of the transistor and the drain electrode of the second transistor are connected to the one common electrode, the third transistor has its gate electrode connected to the scanning line corresponding to the one common electrode, and its source electrode turned on Connected to a first signal line for supplying either a signal or an off signal, a drain electrode thereof is connected to a gate electrode of the first transistor, and a gate electrode of the fourth transistor is connected to the one common electrode. Connected to the corresponding scanning line, its source electrode is connected to a second signal line having a logic level exclusive to the first signal line, its drain electrode is connected to the gate electrode of the second transistor, and The transistor has a gate electrode connected to the scanning line corresponding to the one common electrode, and a source electrode connected to the third feeder line. It is continued, the drain electrode may be connected to the common electrode of the one. In the above configuration, if the positive polarity writing is designated for the pixel corresponding to the one scanning line, the common signal output circuit, in the first half of the period in which the one scanning line is selected, A voltage obtained by buffering the first voltage is supplied to the third power supply line, and the common electrode corresponding to the scanning line is controlled to be the first voltage in the period, or in the second half of the period, If the common electrode corresponding to one scanning line is controlled to be the first voltage and negative writing is designated, the common corresponding to the scanning line is selected in the period during which the one scanning line is selected. The electrode is controlled to become the second voltage, or in the first half of the period, a voltage obtained by buffering the second voltage is supplied to the third feeder line, and in the second half of the period, the one scanning line Corresponding to Mon electrode may be controlled to be the second voltage.
The present invention can be conceptualized not only as a drive circuit for an electro-optical device, but also as an electro-optical device, and further as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, in the electro-optical device 10, a scanning line driving circuit 140, a common electrode driving circuit 170, and a data line driving circuit 190 are arranged around the display region 100, and
The control circuit 20 is configured to control each of these units.

The display area 100 is an area in which the pixels 110 are arranged. In this embodiment, 320 scanning lines 112 are provided so as to extend in the row (X) direction, and 240 columns of data lines 114 are provided.
Are provided so as to extend in the column (Y) direction. The scanning lines 11 in the 1st to 320th rows
Corresponding to the intersection of 2 and the data lines 114 in the 1st to 240th columns, the pixels 110 are respectively arranged. Therefore, in the present embodiment, the pixels 110 are arranged in a matrix of 320 vertical rows × 240 horizontal columns in the display area 100. However, the present invention is not intended to be limited to this arrangement.
Corresponding to the scanning lines 112 in the 1st to 320th rows, the common electrodes 108 are provided extending in the X direction. For this reason, in this embodiment, 1 to 1 corresponding to each scanning line.
The common electrodes 108 in the 320th row are provided.

A detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating a configuration of the pixel 110, and is adjacent to the i row and the (i + 1) row adjacent thereto in the downward direction, and the j column and the column adjacent thereto in the right direction (
The configuration of a total of 4 pixels of 2 × 2 corresponding to the intersection with the j + 1) column is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 110 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 110 are arranged. It is a symbol in the case of showing generally, and is an integer of 1 or more and 240 or less.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 1 that functions as a pixel switching element.
16, a pixel capacitor (liquid crystal capacitor) 120, and a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in the i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. The source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to one end of the pixel capacitor 120 and the storage capacitor 130, respectively. The other end of the pixel capacitor 120 and the other end of the storage capacitor 130 are connected to the i-th common electrode 108, respectively.
In FIG. 2, Yi and Y (i + 1) are the scanning lines 1 in the i and (i + 1) th rows, respectively.
12, and Ci and C (i + 1) are i and (i + 1), respectively.
) The voltage of the common electrode 108 in the row is shown.

Although not particularly shown, this embodiment has a configuration in which liquid crystal is sealed between an element substrate and a counter substrate, and is an FPS (fr) that is a modification of the IPS mode in which the electric field direction applied to the liquid crystal is the substrate surface direction.
inge field switching) mode.
Specifically, since the common electrode is formed in a band shape on the element substrate and the comb-like pixel electrode is formed via the insulating layer, a dielectric electrode is formed between the pixel electrode 118 and the common electrode 108. It becomes a kind of capacitance due to the structure through the body liquid crystal, and the electric field applied to the liquid crystal changes in the direction along the substrate surface according to the effective value of the voltage held by this capacitance component. .
Here, in this embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value increases. The normally white mode in which the amount of light to be reduced is reduced and finally the black display with the minimum transmittance is achieved.
The storage capacitor 130 is a capacitance component generated by a stacked structure in which the pixel electrode 118 and the common electrode 108 are interposed via an insulating layer.
In the present embodiment, any mode other than the FFS mode may be used as long as the electrical equivalent circuit is a circuit as shown in FIG.

Returning to FIG. 1 again, the control circuit 20 outputs various control signals to output the electro-optical device 10.
It controls each part in the above.
For example, as shown in FIG. 4, the control circuit 20 generates two clock signals Cly having a duty ratio of 50% and two pulses corresponding to a half cycle of the clock signal Cly.
Is output as a start pulse Dy.

As described above, peripheral circuits such as the scanning line driving circuit 140, the common electrode driving circuit 170, and the data line driving circuit 190 are provided around the display region 100. Among these, the scanning line driving circuit 140 applies the scanning signals Y1, Y2, Y3,..., Y320 to the first, second, third,. This is supplied to the scanning line 112.
More specifically, the scanning line driving circuit 140 sequentially shifts the start pulse Dy every time the logic level of the clock signal Cly changes as shown in FIG. 4, and the scanning signals Y1, Y2, Y3.
, Y4,..., Y320. For this reason, when the scanning signal to a certain scanning line reaches the first H level in the period of one frame, it then becomes the L level over the period of the half cycle of the clock signal Cly, and then reaches the second H level. It will be.

Note that when viewed from a certain scanning line, the period during which the scanning signal to the scanning line is at the H level for the first time in one frame is a period for preliminary writing, and as indicated by hatching in FIG. The period for which the H level is reached for the second time is the period for the main writing. Here, the preliminary writing means that a voltage having the same polarity as the main writing is written in the pixel capacitor 120 in advance before the main writing. The main writing is positive or negative. The voltage corresponding to the gradation is set to the pixel capacitance 12
To write to zero. Therefore, the main writing period for one scanning line is a half cycle of the clock signal Cly, which corresponds to the horizontal scanning period (H) for the row.
Note that a period during which the scanning signal is at the L level is a non-selection period.
In this embodiment, in the period of one frame, in addition to the effective scanning period Fa from when the scanning signal Y1 becomes H level for the main writing until the scanning signal Y320 becomes the L level for the main writing, other than that Vertical blanking periods are included. In the scanning signal, the H level is the selection voltage Vdd, and the L level is the non-selection voltage Vss.

Of the control signals output from the control circuit 20, signals other than the start pulse Dy and the clock signal Cly will be described.
First, as shown in FIG. 4, the latch pulse Lp is output at a timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 sequentially shifts the start pulse Dy in accordance with the clock signal Cly, whereby the scanning signal Y1.
Since ~ Y320 is output, the output timing of the latch pulse Lp may be considered as the timing when any one of the scanning signals becomes H level.

Next, if the polarity designation signal Pol is at the H level, positive polarity writing is designated for pixels in odd (1, 3, 5,..., 319) rows, and even (2, 4, 6,...) Is designated. 320) Specify negative polarity writing for pixels in the row, and if L level, specify negative polarity writing for pixels in the odd row and positive polarity writing for pixels in the even row. Is a signal that specifies. Here, as shown in FIG. 4, since the polarity designation signal Pol is at the H level over n frames, a scanning line inversion (line inversion) system in which the writing polarity to the pixel is inverted for each scanning line is adopted. The polarity instruction signal Pol becomes L level in the next (n + 1) frame, and the writing polarity is inverted for each row as compared with the n frame. The reason for reversing the writing polarity in this way is to prevent deterioration of the liquid crystal due to application of a DC component.
As for the writing polarity in the present embodiment, when holding the voltage in the pixel capacitor 120, the case where the potential of the pixel electrode 118 is higher than the potential of the common electrode 108 is called positive polarity, This is called negative polarity. For voltage, unless otherwise specified,
A ground potential of a power supply (not shown) is used as a reference for zero voltage.

On the other hand, the polarity specifying signal Pol is logically inverted by the NOT circuit 50 and output as a signal / Pol.
The polarity designation signal Pol is transmitted via the signal line 164a (first signal line) and the signal / Pol is
The signal is supplied to the common electrode driving circuit 170 via the signal line 164b (second signal line). The H and L levels of the polarity designation signal Pol (signal / Pol) are the TFTs 171 and 172 described later.
, The TFTs 171 and 172 are turned on and off, respectively. For this reason, the polarity designation signal Pol is a signal that designates the write polarity of odd / even rows, and also functions as an on signal and an L level off signal among the logic levels. .

In the n frame, the signal S1a becomes H level in the horizontal scanning period in which the first, fifth, ninth,...
In the +1) frame, the second, sixth, tenth,..., 318th row of the even-numbered rows is a signal that is at the H level in the horizontal scanning period in which the main writing is performed and is at the L level in the other periods.
The signal S2a becomes H level in the horizontal scanning period in which the second, sixth, tenth,..., 318th line is the main writing in the n frame, and becomes L level in the other period, while the signal S2a becomes 1, in the (n + 1) frame. The fifth, ninth,..., 317th line is a signal that becomes H level in the horizontal scanning period in which the main writing is performed and becomes L level in other periods. The signals S1a and S2a are n, (n +
1) There is a reverse relationship when comparing frames.

In the n frame, the signal S1b is at the H level in the horizontal scanning period in which the remaining odd-numbered rows 3, 7, 11,..., 319 are main writing and at the L level in the other periods, while (n + 1). ) In the frame, the remaining 4, 4, 12,..., 320th line of the even-numbered lines is a signal that becomes H level in the horizontal scanning period in which main writing is performed, and becomes L level in other periods.
The signal S2b is at the H level in the horizontal scanning period in which the fourth, eighth, twelfth, 320th rows are in the main writing in the n frame and at the L level in the other period, while the signal S2b is at the three levels in the (n + 1) frame. The seventh, eleventh,..., 319th line is a signal that is at the H level in the horizontal scanning period in which the main writing is performed and is at the L level in the other periods. For signals S1b and S2b,
When comparing n, (n + 1) frames, the opposite relationship is obtained.

In other words, the signal S1a or S1b is at the H level during the main writing for the odd-numbered row in the n frame, and for the even-numbered row in the (n + 1) frame. Since this is the period for the main writing, it is a horizontal scanning period in which the positive writing is designated in the main writing in any frame.
On the other hand, the signal S2a or S2b is at the H level during the n frame during the main writing for the even-numbered rows, and for the (n + 1) frame, the main writing is performed for the odd-numbered rows. Therefore, in any frame, it is a horizontal scanning period in which negative writing is designated in the main writing.

Next, the signal H1 is a signal that becomes L level in the second half of the horizontal scanning period in which the signal S1a or S1b becomes H level and becomes H level in other periods. Therefore, in other words, the signal H1 is a signal that becomes L level only in the latter half of the horizontal scanning period in which positive writing is designated in the main writing.
On the other hand, the signal H2 is a signal that is at the L level in the second half of the horizontal scanning period in which the signal S2a or S2b is at the H level and is at the H level in other periods. Therefore, in other words, the signal H2 is a signal that becomes L level only in the second half of the horizontal scanning period in which negative polarity writing is designated in the main writing.
The target signal Vc1ref is constant at the voltage Vsl, and the target signal Vc2ref is constant at the voltage Vsh.
Here, the voltages Vsl and Vsh have a relationship of (Vss ≦) Vsl <Vsh (≦ Vdd), and the voltage Vsl is relatively lower than the voltage Vsh.

The first common signal output circuit 31 supplies the first common signal Vc1 to the first power supply line 161. Similarly, the second common signal output circuit 32 supplies the second common signal Vc2 to the second power supply line 162. . Details of the first common signal output circuit 31 and the second common signal output circuit 32 will be described later.

In the present embodiment, the common electrode driving circuit 170 includes a set of n-channel TFTs 171 to 174 and 179 provided corresponding to the common electrodes 108 in the first to 320th rows.
Taking the i-th row as an example, the source electrode of the TFT 171 (first transistor) in the i-th row is connected to the first power supply line 161, and the source electrode of the TFT 172 (second transistor) in the i-th row is the second. The drain electrodes of the TFTs 171 and 172 are connected to the i-th common electrode 108 in common with the power supply line 162.
On the other hand, the i-th TFT 173 (third transistor) has its gate electrode connected to the i-th scanning line 112 and its drain electrode connected to the gate electrode of the i-th TFT 171. The i-th TFT 174 (fourth transistor) has its gate electrode connected to the i-th scanning line 112 and its drain electrode connected to the gate electrode of the i-th TFT 172.
Here, if i is an odd number, the source electrode of the TFT 173 is connected to the signal line 164a,
While the source electrode of the TFT 174 is connected to the signal line 164b, if i is an even number, TF
The source electrode of T173 is connected to the signal line 164b, and the source electrode of the TFT 174 is connected to the signal line 164a. That is, the connection destination of the source electrode of the TFTs 173 and 174 is
The relationship is switched between the odd and even lines.

The i-th TFT 179 has its gate electrode connected to the i-th scanning line 112 and its source electrode connected to the i-th common electrode 108. Here, the drain electrode of the TFT 179 is alternately connected to the detection lines 165a and 165b every two rows. Specifically, 1, 2,
The drain electrodes of the TFTs 179 in the fifth, sixth, ninth, tenth,..., 317 and 318 rows are connected to the detection line 165a, and the third, fourth, seventh, eighth, eleventh, twelve,. TFT
A drain electrode 179 is connected to the detection line 165b.

The detection line 165a is connected to the signal line 61 via the switch 41 and to the signal line 62 via the switch 43, respectively. Similarly, the detection line 165b is connected to the signal line 61 via the switch 42 and to the signal line 62 via the switch 44, respectively.
Here, the switch 41 is turned on when the signal S1a is at the H level and turned off when the signal S1a is at the L level. Similarly, the switches 42, 43, 44 are connected to signals S1b, S2a, S2b, respectively.
Is turned on when H is H level and turned off when L is L level.

Next, the configuration of the first common signal output circuit 31 will be described. FIG. 3 is a diagram illustrating a configuration of the first common signal output circuit 31.
As shown in this figure, the first common signal output circuit 31 includes an operational amplifier 300, switches 311 and 312, a NOT circuit 315, and a resistance element 316.
The output terminal of the operational amplifier 300 is connected to one end of the first power supply line 161 and the switch 311, and the signal line 61 is connected to one end of the switch 312. The other ends of the switches 311 and 312 are commonly connected to the inverting input terminal (−) of the operational amplifier 300. In other words, the switch 311 includes the output terminal (first feeding line 161) of the operational amplifier 300 and the inverting input terminal (−
) And the switch 312 is electrically inserted between the signal line 61 and the inverting input terminal (−).

On the other hand, in the first common signal output circuit 31, the non-inverting input terminal (+) of the operational amplifier 300.
Is supplied with the target signal Vc1ref from the control circuit 20. In addition to the switch 311, a resistance element 316 is inserted between the output terminal and the inverting input terminal (−) of the operational amplifier 300.
The switches 311 and 312 are exclusively turned on and off according to the logic level of the signal H1 supplied from the control circuit 20. Specifically, the switches 311 and 312 are turned on and off when the signal H1 is at the H level, and are turned off and on when the signal H1 is at the L level.

When the signal H1 is at the H level in this way, the operational amplifier 300 becomes a voltage follower circuit by turning on and off the switches 311 and 312. Therefore, the first common signal output circuit 31.
Is buffering the voltage of the target signal Vc1ref as it is to obtain the first common signal Vc1.
It outputs to the 1st electric power feeding line 161.
On the other hand, when the signal H1 is at the L level, the voltage of the signal line 61 is fed back to the inverting input terminal (−) of the operational amplifier 300 by turning the switches 311 and 312 off and on, so that the first common signal output circuit 31 The first common signal Vc 1 controlled so that the voltage of the signal line 61 becomes the voltage of the target signal Vc 1 ref is output.
As described above, since the signal H1 becomes the L level in the latter half of the horizontal scanning period in which the positive polarity writing is designated in the main writing, the first common signal output circuit 31 The first common signal Vc1 controlled so that the voltage of the signal line 61 becomes the voltage Vsl of the target signal Vc1ref is output, and the first common signal Vc1 obtained by simply buffering the voltage Vsl of the target signal Vc1ref is output in other periods. Will do.

The configuration of the second common signal output circuit 32 is the same as that of the first common signal output circuit 31 except for the supplied signal and the connection destination, as shown in parentheses in FIG. Yes.
Therefore, when the signal H2 is at the H level, the operational amplifier 300 becomes a voltage follower circuit, and the second common signal output circuit 32 buffers the voltage of the target signal Vc2ref as it is to obtain the second common signal Vc2. 2 output to the feeder line 162. On the other hand, when the signal H2 is at the L level, the voltage of the signal line 62 is fed back to the inverting input terminal (−) of the operational amplifier 300. Therefore, the second common signal output circuit 32 has the voltage of the signal line 62 of the target signal Vc2ref. The second common signal Vc2 controlled so as to be equal to the voltage is output.
As described above, since the signal H2 becomes L level in the latter half of the horizontal scanning period in which negative polarity writing is designated in the main writing, the second common signal output circuit 32 The second common signal Vc2 controlled so that the voltage of the signal line 62 becomes the voltage Vsh of the target signal Vc2ref is output, and the second common signal Vc2 obtained by simply buffering the voltage Vsh of the target signal Vc2ref is output in other periods. Will do.

In principle, the data line driving circuit 190 is configured so that the scanning signal is H by the scanning line driving circuit 140.
The voltage corresponding to the gradation level and the voltage corresponding to the polarity specified by the polarity instruction signal Pol for the pixel 110 located in the scanning line that is in the main writing period among the scanning lines that are level. The data signal is supplied to the data line 114.
However, as an exception, the data line driving circuit 190 has the same gradation level and the same polarity voltage signal in the main writing period of the first and second rows after the preliminary writing period of the first and second scanning lines. Is supplied to the data line 114 as a data signal.
Note that in the preliminary writing period of the scanning lines of the first and second rows, a voltage signal having another gradation level in the subsequent main writing period and having the same polarity may be supplied to the data line 114 as a data signal. good.

Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation level (brightness) of the corresponding pixel 110. Display data Da for designating the data is stored. The display data Da stored in each storage area is supplied with the changed display data Da by the control circuit 20 when the display contents are changed, and the contents of the storage area are rewritten.
The data line driving circuit 190 reads out the display data Da of the pixel 110 located on the selected scanning line for one row from the storage area, and if positive polarity writing is designated, the data line driving circuit 190 determines the floor designated by the read display data. If negative polarity writing is designated in the data signal of the voltage that becomes higher with respect to the voltage Vsl as the gradation level becomes darker, the voltage Vsh becomes smaller as the gradation level designated by the read display data becomes darker. Are converted into data signals having voltages on the lower side of the signal, and supplied to the data line 114. The data line driving circuit 190 executes such an operation for each of the 1st to 240th columns positioned on the scanning line to be the main writing.
Note that the data line driving circuit 190 keeps counting the latch pulse Lp over a period of one frame to determine which row's scanning signal is at the H level, and the period when the latch pulse Lp is at the H level at the supply timing. Know the start timing.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
First, in the n frame, only the scanning signal Y1 becomes H level for the preliminary writing of the first row by the scanning line driving circuit 140 first.
When the scanning signal Y1 becomes H level, the TFTs 173 and 174 in the first row are turned on. In the n frame, since the polarity designation signal Pol and the signal / Pol are at the H and L levels, respectively, these voltages are applied to the gate electrodes of the TFTs 171 and 172, respectively. For this reason, TFT1
Since 71 and 172 are turned on and off, the common electrode 108 in the first row is connected to the first power supply line 161.
Here, when the scanning signal Y1 becomes H level for preliminary writing of the first row, the signal H1 is H
The first common signal Vc1 output to the first feeder 161 is the target signal Vc1.
A voltage obtained by buffering the voltage Vsl of ref is applied to the common electrode 108 in the first row.

On the other hand, the data line driving circuit 190 is an exceptional operation. That is, the data line driving circuit 1
90 reads out the display data Da of the pixels in the first row and the 1st to 240th columns, and as the gradation specified by the display data Da becomes darker, the positive polarity with the voltage Vsl as a reference is set to the higher side. Voltage data signals X1 to X240 are converted into 1 to 240 columns of data lines 11 respectively.
4 is supplied.
When the scanning signal Y1 becomes the H level, the TFT 11 in the pixels in the first row and the first column to the first row and the 240th column.
6 is turned on, the voltages of the data signals X1 to X240 are applied to these pixel electrodes 118. Since the common electrode 108 in the first row should be at the buffered voltage Vsl, the parallel capacitances of the pixel capacitor 120 and the storage capacitor 130 in the first row and first column to the first row and 240 column each have a gradation. The corresponding positive voltage is written prior to the main writing.

Next, only the scanning signal Y2 becomes H level for the preliminary writing of the second row.
When the scanning signal Y2 becomes the H level, the TFTs 173 and 174 in the second row are turned on. However, since the source electrodes are in a relationship of being replaced with the odd rows, the TFTs 171 and 172 are
Turn off and on respectively. For this reason, the common electrode 108 in the second row is connected to the second power supply line 162.
Here, when the scanning signal Y2 becomes H level for preliminary writing of the second row, the signal H2 is H
The second common signal Vc2 output to the second feeder 162 is the target signal Vc2.
This is a voltage obtained by buffering the voltage Vsh of ref, and this voltage is applied to the common electrode 108 in the second row.

Further, the data line driving circuit 190 performs an exceptional operation. That is, the data line driving circuit 1
Reference numeral 90 reads the display data Da of the pixels in the second row and the 1st to 240th columns, and converts the read display data Da into data signals X1 to X240 having negative polarity voltages corresponding to the gradations. Supplied to the data lines 114 of ~ 240 columns.
When the scanning signal Y2 becomes H level, T in the pixels of 2 rows 1 column to 2 rows 240 columns is determined.
Since the FT 116 is turned on, the voltages of the data signals X1 to X240 are applied to these pixel electrodes 118. Since the common electrode 108 in the second row should be the buffered voltage Vsh, the parallel capacitance of the pixel capacitor 120 and the storage capacitor 130 in the second row and first column to the second row and 240th column has a negative electrode corresponding to each gradation. The voltage of the sex is written prior to the main writing.

When the scanning signal Y2 becomes H level, the scanning signal Y1 becomes L level, so that the TFTs 173 and 174 in the first row are all turned off. However, since the gate electrodes of the TFTs 171 and 172 in the first row hold the H and L levels, which are in the previous state, due to the parasitic capacitance, the on and off states of the TFTs 171 and 171 in the first row are maintained. As a result, the common electrode 108 in the first row is also maintained at the voltage Vsl.

Next, the scanning signal Y3 becomes H level for the preliminary writing of the third row, and the scanning signal Y1 becomes H level for the main writing of the first row.
When the scanning signals Y3 and Y1 become H level, the TFTs 173 and 174 in the third row and the first row are used.
Since the TFTs 171 and 172 in the third row and the first row are turned on and off, respectively, the common electrodes 108 in the third row and the first row should be at the voltage Vsl.
In particular, when the scanning signal Y1 becomes H level, the TFT 179 in the first row is turned on.
The common electrode 108 in the row is connected to the detection line 165a. In the n frame, the signal S1a becomes H level in the horizontal scanning period for the main writing in the first row, the switch 41 is turned on, and the positive writing is designated in the first row. L in the second half of the horizontal scanning period
Become a level. Therefore, in the second half of the horizontal scanning period, the common electrode 1 in the first row
Negative feedback control is performed so that 08 becomes the voltage Vsl of the target signal Vc1ref by the first common signal output circuit 31. For this reason, the common electrode 108 in the first row is accurately set to the voltage Vsl at the end of the horizontal scanning period.
Since the third row TFT 179 is also turned on, the third row common electrode 108 is connected to the detection line 16.
5b, but signals S1b and S2b are both at L level (switches 42 and 44 are off)
Therefore, the voltage of the common electrode 108 in the third row does not affect the operations of the first common signal output circuit 31 and the second common signal output circuit 32. Second common signal output circuit 3
2 only buffers the voltage Vsh of the target signal Vc2ref.

The data line driving circuit 190 operates in principle. That is, the data line driving circuit 190 reads out the display data Da of the pixels in the first row and the 1st to 240th columns, and the read display data Da is used as the positive voltage data signals X1 to X240 according to the gradation. And supplied to the data lines 114 of 1 to 240 columns.
When the scanning signal Y1 becomes the H level, the TFTs 116 in the pixels of the first row and the first column to the first row and the 240th column are turned on, and the voltages of the data signals X1 to X240 are applied to these pixel electrodes 118, Since the common electrode 108 in the first row is controlled to be at the voltage Vsl, the parallel capacitance of the pixel capacitor 120 and the storage capacitor 130 in the first row and first column to the first row and 240 column has a positive polarity corresponding to each gradation. The voltage will be written correctly.
Further, when the scanning signal Y3 becomes H level, the TFTs 116 in the pixels in the 3rd row and 1st column to the 3rd row and 240th column are turned on, and the data signals X1 to X24 are supplied to these pixel electrodes 118.
Since a voltage of 0 is applied, the pixel capacitor 120 and the storage capacitor 1 of 3 rows and 1 column to 3 rows and 240 columns
In the 30 parallel capacitors, a positive voltage corresponding to the gradation of the pixels in the first row and the first column to the first row and the 240th column is written prior to the main writing in the third row.

When the scanning signal Y3 becomes H level, the scanning signal Y2 becomes L level, so that the TFTs 173 and 174 in the second row are all turned off. However, since the gate electrodes of the TFTs 171 and 174 in the second row hold the L and H levels, which are the previous states, due to the parasitic capacitance, the off and on states of the TFTs 171 and 171 in the second row are maintained. As a result, the common electrode 108 in the second row is kept at the voltage Vsh.

Subsequently, the scanning signal Y4 becomes H level for the preliminary writing of the fourth row, and the scanning signal Y2 becomes H level for the main writing of the second row.
When the scanning signals Y4 and Y2 become H level, the TFTs 173 and 174 in the fourth and second rows
Since the TFTs 171 and 172 in the fourth and second rows are turned off and on, respectively, the common electrodes 108 in the fourth and second rows should be at the voltage Vsh, respectively.
In particular, when the scanning signal Y2 becomes H level, the TFT 179 in the second row is turned on.
The common electrode 108 in the row is connected to the detection line 165a. In the n-th frame, the signal S2a becomes H level during the horizontal scanning period for the main writing of the second row, the switch 43 is turned on, and the negative writing is designated for the second row. L in the second half of the horizontal scanning period
Become a level. Therefore, in the second half of the horizontal scanning period, the common electrode 1 in the second row
Negative feedback control is performed by the second common signal output circuit 32 so that 08 becomes the voltage Vsh of the target signal Vc2ref. Therefore, the common electrode 108 in the second row is accurately at the voltage Vsh at the end of the horizontal scanning period.
Since the TFT 179 in the fourth row is also turned on, the common electrode 108 in the fourth row is connected to the detection line 16.
Although the signals S1b and S2b are both at the L level, the voltage of the common electrode 108 in the fourth row affects the operations of the first common signal output circuit 31 and the second common signal output circuit 32. Never give. The first common signal output circuit 31 outputs the voltage Vs of the target signal Vc1ref.
Only l is buffered.

In addition, the data line driving circuit 190 operates in principle, and reads the display data Da of the pixels in the second row and columns 1 to 240, and the read display data Da has a negative voltage corresponding to the gradation. Data signals X1 to X240 are converted into data signals 114 of 1 to 240 columns, respectively.
To supply. Thereby, the pixel capacitor 120 and the storage capacitor 13 of 2 rows and 1 column to 2 rows and 240 columns.
In the parallel capacitor of 0, a negative polarity voltage corresponding to each gradation is accurately written, and 4 rows 1
The parallel capacity of the pixel capacitor 120 and the storage capacitor 130 in columns to 4 rows and 240 columns is 2 rows and 1 column to 2 columns.
A negative voltage corresponding to the gradation of the pixels in the row 240 column is written prior to the main writing in the fourth row.

When the scanning signals Y4 and Y2 become H level, the scanning signals Y3 and Y1 become L level, so that the TFTs 173 and 174 in the third row and the first row are both turned off. However, since the gate electrodes of the TFTs 171 and 174 in the third row and the first row hold the H and L levels, which are the previous states, due to the parasitic capacitance, the on and off states of the TFTs 171 and 172 in the first row are maintained. As a result, the common electrodes 108 in the third row and the first row are maintained at the voltage Vsl.
In particular, in the first row of common electrodes, the scanning signal Y1 is again H in the next (n + 1) frame.
The voltage Vsl is maintained until the level is reached. When the scanning signal Y1 becomes L level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned off, but the common electrode 10 in the first row is turned off.
Since 8 is maintained at the voltage Vsl, the voltage written in the pixel capacitor 120 in the first row does not change.

Next, when the scanning signal Y5 becomes H level for the preliminary writing of the fifth row and the scanning signal Y3 becomes H level for the main writing of the third row, the common of the fifth and third rows Electrode 108
Should be the voltage Vsl.
In particular, when the scanning signal Y3 becomes H level, the TFT 179 in the third row is turned on.
The common electrode 108 in the row is connected to the detection line 165b. Further, since the signal S1b becomes H level and the switch 42 is turned on, the common electrode 108 in the third row is set to the voltage Vsl of the target signal Vc1ref by the first common signal output circuit 31 in the latter half of the horizontal scanning period. Negative feedback control is performed so that the voltage Vsl is accurately set at the end of the horizontal scanning period.
Since the TFT 179 in the fifth row is also turned on, the common electrode 108 in the fifth row is connected to the detection line 16.
5a, but signals S1a and S2a are both at L level (switches 41 and 43 are off)
Therefore, the voltage of the common electrode 108 in the fifth row does not affect the operations of the first common signal output circuit 31 and the second common signal output circuit 32. Second common signal output circuit 3
2 only buffers the voltage Vsh of the target signal Vc2ref.

In addition, the data line driving circuit 190 operates in principle, and reads the display data Da of the pixels in the third row and the first to 240th columns, and the read display data Da has a positive voltage corresponding to the gradation. Data signals X1 to X240 are converted into data signals 114 of 1 to 240 columns, respectively.
To supply. As a result, the pixel capacitor 120 and the storage capacitor 13 in the 3 rows and 1 column to the 3 rows and 240 columns.
In the parallel capacitor of 0, a positive voltage corresponding to each gradation is accurately written, and 5 rows 1
The parallel capacity of the pixel capacitor 120 and the storage capacitor 130 of columns to 5 rows and 240 columns is 3 rows and 1 column to 3 columns.
The positive voltage corresponding to the gradation of the pixel in the row 240 column is written prior to the main writing in the fifth row.
When the scanning signals Y5 and Y3 are at the H level, the scanning signals Y4 and Y2 are at the L level, so that the TFTs 173 and 174 in the fourth row and the second row are both turned off. However, the gate electrodes of the TFTs 171 and 172 in the fourth row and the second row hold the L and H levels, which are the previous states, due to the parasitic capacitance, so the TFTs 171 and 172 in the first row are turned off and on. As a result, the common electrodes 108 in the fourth and second rows are maintained at the voltage Vsh.
In particular, in the second row common electrode, the scanning signal Y2 is again H in the next (n + 1) frame.
The voltage Vsh is maintained until the level is reached. When the scanning signal Y2 becomes L level, the TFTs 116 in the pixels in the 2nd row and the 1st column to the 2nd row and the 240th column are turned off, but the common electrode 10 in the second row is turned off.
Since 8 is maintained at the voltage Vsh, the voltage written in the pixel capacitor 120 in the second row does not change.

When the scanning signal Y6 becomes H level for the preliminary writing of the sixth row and the scanning signal Y4 becomes H level for the main writing of the fourth row, the common electrodes of the sixth and fourth rows 10
Each of 8 should be a voltage Vsh.
In particular, when the scanning signal Y4 becomes H level, the TFT 179 in the fourth row is turned on.
The common electrode 108 in the row is connected to the detection line 165b. Further, since the signal S2b becomes H level and the switch 44 is turned on, in the latter half of the horizontal scanning period, the common electrode 108 in the fourth row is connected to the voltage Vsh of the target signal Vc2ref by the second common signal output circuit 32. Thus, negative feedback control is performed so that the voltage Vsh is accurately set at the end of the horizontal scanning period.
Since the TFT 179 in the sixth row is also turned on, the common electrode 108 in the sixth row is connected to the detection line 16.
Although the signals S1a and S2a are both at the L level, the voltage of the common electrode 108 in the sixth row affects the operations of the first common signal output circuit 31 and the second common signal output circuit 32. Never give. The first common signal output circuit 31 outputs the voltage Vs of the target signal Vc1ref.
Only l is buffered.

In addition, the data line driving circuit 190 operates in principle, and reads the display data Da of the pixels in the fourth row and columns 1 to 240, and the read display data Da has a negative voltage corresponding to the gradation. Data signals X1 to X240 are converted into data signals 114 of 1 to 240 columns, respectively.
To supply. Thereby, the pixel capacitor 120 and the storage capacitor 13 of 4 rows and 1 column to 4 rows and 240 columns are provided.
In the parallel capacitor of 0, a negative polarity voltage corresponding to each gradation is accurately written, and 6 rows 1
The parallel capacitance of the pixel capacitor 120 and the storage capacitor 130 of columns to 6 rows and 240 columns is 4 rows and 1 column to 4 columns.
A negative voltage corresponding to the gradation of the pixel in the row 240 column is written prior to the main writing in the sixth row.
When the scanning signals Y6 and Y4 are at the H level, the scanning signals Y5 and Y3 are at the L level, so that the TFTs 173 and 174 in the fifth row and the third row are both turned off. However, since the gate electrodes of the TFTs 171 and 172 in the fifth row and the third row hold the H and L levels, which are the previous states, due to the parasitic capacitance, the TFTs 171 and 172 in the first row are turned on and off. As a result, the common electrodes 108 in the fifth and third rows are kept at the voltage Vsl.
In particular, the common electrode in the third row has the scanning signal Y3 set to H again in the next (n + 1) frame.
The voltage Vsl is maintained until the level is reached. When the scanning signal Y3 becomes L level, the TFTs 116 in the pixels in the 3rd row and the 1st column to the 3rd row and the 240th column are turned off, but the common electrode 10 in the third row is turned off.
Since 8 is maintained at the voltage Vsl, the voltage written in the pixel capacitor 120 in the third row does not change.

In the nth frame, the same operation is repeated until the scanning signal Y320 becomes H level for the main writing of the 320th row.
Thereby, in n frames, the pixel capacitance 120 in the odd-numbered 1, 3, 5,.
The storage capacitor 130 holds a positive voltage corresponding to each gradation, while an even number 2
.., 320, the pixel capacitors 120 and the storage capacitors 130 hold negative voltages corresponding to the respective gradations.
The same operation is repeated in the next (n + 1) frame. However, since the writing polarity of each row is inverted, the pixel capacitors 120 and the storage capacitors 130 in the odd rows each have a negative voltage corresponding to the gradation. On the other hand, the pixel capacitors 120 and the storage capacitors 130 in the even-numbered rows respectively hold positive voltages corresponding to the gradations.

FIG. 5 is a diagram illustrating a voltage relationship between the scanning signal, the common electrode, and the pixel electrode. The voltage of the pixel electrode 118 in i row and j column is indicated by Pix (i, j), and the pixel in i row (j + 1) column is illustrated. The voltage of the electrode 118 is P
It is indicated by ix (i + 1, j).
As shown in this figure, the voltage Ci of the i-th common electrode 108 is set to the H level for the pre-writing if the positive writing is designated in the i-th row. When
When the TFT 171 (173) is turned on, the voltage Vsl is maintained, and when the TFT 171 continues to be on, the voltage Vsl is maintained. When the scanning signal Yi becomes H level again for the main writing, the voltage Vsl is similarly obtained. The voltage Vsl is maintained by continuing the ON state.

Further, since negative polarity writing is designated for the i-th row in the next frame, the voltage Ci of the i-th common electrode 108 has the scanning signal Yi set to H level for preliminary writing. When the TFT 172 (174) is turned on, the voltage Vsh is maintained, and when the TFT 172 is continuously turned on, the voltage Vsh is maintained. When the scanning signal Yi becomes H level again for the main writing, the voltage Vsh is similarly obtained. Thereafter, the voltage Vsh is maintained by continuing the ON state of the TFT 172.
Therefore, the voltage Ci of the common electrode 108 in the i-th row is the voltage Vsh when the positive polarity writing is designated in the i-th row and the scanning signal Yi becomes H level for the preliminary writing. On the other hand, if negative polarity writing is designated in the i-th row, the voltage Vsl is switched to the voltage Vsh when the scanning signal Yi becomes H level for preliminary writing. .

On the other hand, the voltage Pix (i, j) of the pixel electrode 118 in the i-th row and j-th column is the pixel level of the pixel in the (i−2) th row and j-th column before the second row during the positive polarity pre-writing in the i-th row. The positive voltage according to the tone is maintained, and the positive voltage according to the gray level of the pixel in the i row and j column, which is the row, is held at the time of positive writing in the i-th row. Further, the voltage Pix (i, j) is obtained when the negative polarity preliminary writing in the i-th row is performed.
The negative voltage according to the gray level of the pixel in the (i-2) row and j column before the second row, and in the negative main writing in the i row, the level of the pixel in the i row and j column that is the row concerned The negative polarity voltage corresponding to the tone is maintained.
Since the present embodiment is a scanning line inversion method, the voltage C (i + 1) of the common electrode 108 in the (i + 1) th row is delayed by a horizontal scanning period compared to the voltage Ci, and
The voltage switches in the opposite direction.

Here, when the pixel capacitor 120 is configured to write one of the positive polarity and the negative polarity at a time in a state where one of the positive polarity and the negative polarity voltage is held, voltage writing from one to the other can be performed. However, in this embodiment, a voltage having the same polarity as that of the main writing is written in advance by preliminary writing, and a voltage corresponding to the gradation is written by the main writing. As a result, the amount of voltage writing in the main writing can be reduced, resulting in a reduction in noise.
Further, since the i-th common electrode 108 is negatively feedback controlled in the second half of the horizontal scanning period in which the i-th scanning line is selected for the main writing, the voltage at the end of the i-th main writing is determined. Vsl
, Vsh. For this reason, the voltage corresponding to the gradation can be accurately written to the pixel capacitor 120 during the main writing, so that display unevenness can be suppressed and the common electrode 108 is connected to the first power supply line 161 and the second power supply line 161. Since the on-resistances of the TFTs 171 and 172 connected to the power supply line 162 may be relatively large, a large transistor size is not required. As a result, a so-called frame size outside the display region can be reduced.
Further, the i-th common electrode 108 is negatively feedback controlled in the second half of the horizontal scanning period in which the i-th scanning line is selected for the main writing. Voltage Vsl
, Vsh is only switched from one to the other, and the voltage is not switched during the main writing of the i-th row. For this reason, high performance is not required for the operational amplifier 300 of the first common signal output circuit 31 and the second common signal output circuit 32 in combination with the reduction of noise, thereby preventing an increase in circuit scale and power consumption. Can be suppressed.

On the other hand, the voltage of the data signal supplied to the data line 114 of each column is switched at the start timing of the horizontal scanning period. Therefore, it is considered that the common electrode 108 that intersects with the data line 114 of each column and has a large degree of capacitive coupling is greatly affected by noise at the start timing of the horizontal scanning period. Therefore, in the configuration in which negative feedback control is performed so that the common electrode 108 in the i-th row becomes the voltage Vsl or the voltage Vsh over the entire period in which the scanning signal Yi is at the H level when viewed in the i-th row, the scanning signal Yi Immediately after the voltage becomes H level, the current consumed by the operational amplifier 300 may increase or the operational amplifier 300 may oscillate. However, in this embodiment, in the first half period immediately after the scanning signal Yi becomes H level, it functions as a mere voltage follower circuit, not as a negative feedback control, so that such a possibility can be reduced.
Note that negative feedback control may be performed over the entire horizontal scanning period as long as a slight increase in current consumption or micro-oscillation is negligible. When the negative feedback control is configured throughout the horizontal scanning period, a circuit for switching between the negative feedback control and the voltage follower function may be omitted.

Second Embodiment
In the first embodiment, when positive writing is designated in the horizontal scanning period in which, for example, the odd-numbered i-th row is the main writing in the n frame, the first writing is performed in the latter half of the horizontal scanning period.
The common signal output circuit 31 supplies the common signal Vc1 controlled so that the common electrode 108 in the i-th row becomes the voltage Vsl to the first power supply line 161. The common signal Vc1 is a signal that is controlled so that the common electrode 108 in the i-th row becomes the voltage Vsl. Therefore, the common signal Vc1 may take a voltage away from the voltage Vsl temporarily.
Here, in the n frame, the first power supply line 161 that supplies the common signal Vc1 is a common electrode other than the i-th row, for example, an odd-numbered common electrode that has been completely written, or an even-numbered row that has not been preliminarily written. In these other rows, the common electrode fluctuates in the vicinity of the voltage Vsl.
In these other rows, it is a non-selection period, and the TFT 116 is off.
One end of the pixel electrode 118 and one end of the storage capacitor 130 are not electrically connected to any part. Therefore, the holding voltage of these parallel capacitors is not affected by the voltage fluctuation of the common electrode. However, voltage fluctuations due to the common electrode in these other rows are not preferable for reducing power consumption because power is wasted due to parasitic capacitance.
Here, attention is paid to the first power supply line 161, but the same applies to the second power supply line 162.

Further, in the first embodiment, the TFTs 171 and 172 in each row continue to be turned on alternately every period corresponding to one frame, so that the ratio of the on period in the operation period is 50%.
It becomes. The period in which the other transistors, for example, TFTs 173 and 174 are turned on, is only a selection period for preliminary writing and main writing in a period corresponding to one frame.
The ratio of the period in which 71 and 172 are on is overwhelmingly higher than other transistors.
Here, when a transistor is driven in a state in which the ratio of the on-period is high, the characteristics of the transistor are deteriorated. Specifically, the on-resistance gradually increases due to an increase in threshold voltage. As described above, in the first embodiment, the on-resistances of the TFTs 171 and 172 may be relatively large, but it is needless to say that deterioration should still be considered.

Therefore, a second embodiment that takes into account the reduction in power consumption and the degradation of the TFTs 171 and 172 will be described next.

FIG. 6 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment. The electro-optical device according to the second embodiment is different from the first embodiment shown in FIG. 1 mainly in the following points.
That is, in the electro-optical device according to the second embodiment, first, the TFT 175 is provided in each row of the common electrode driving circuit 170, and secondly, the common signal output circuit 33 and the switches 45 and 46 are provided. And thirdly, the control circuit 20 determines that the target signal Vc1ref
Instead of outputting Vc2ref, the target signal Vc3ref is output and the common signal Vc1 is output.
Is different from the first embodiment in that the signal is directly output to the first power supply line 161 and the common signal Vc2 is output to the second power supply line 162, respectively.
For this reason, the second embodiment will be described focusing on these differences.

First, the first point will be described. Each of the common electrodes 108 in rows 1 to 320 has T
FT175 is provided. In the i-th row, the i-th TFT 175 has its gate electrode connected to the i-th common electrode 108 and its source electrode connected to the third feeder 163.
The drain electrode is connected to the i-th common electrode 108. In the second embodiment, the common signal Vc3 is supplied to the third feeder 163 by the common signal output circuit 33.

Next, the second point will be described. The detection line 165a is connected to the detection line 1 via the switch 45.
65b is connected to the signal line 63 via the switch 46, respectively.
Here, the switch 45 is turned on when the signal S3a is at the H level and turned off when the signal S3a is at the L level. Similarly, the switch 46 is turned on when the signal S3b is at the H level and turned off when the signal S3b is at the L level.
As shown in FIG. 7, the signal S3a is the same in n frames and (n + 1) frames (that is, independent of the write polarity), 1, 2, 5, 6, 9, 10,. ,
The 317th and 318th lines are at the H level in the horizontal scanning period in which the main writing is performed. Signal S3b is
As shown in the figure, it is the same in n frames and (n + 1) frames, and 3,
Lines 4, 7, 8, 11, 12,.
For this reason, in the horizontal scanning period in which the main writing is performed in each row, of the detection lines 165a and 165b, the one connected to the drain electrode of the TFT 179 in the row in which the main writing is performed is the signal line 6.
3 is connected.

As shown in parentheses in FIG. 3, the common signal output circuit 33 has the same configuration as the first common signal output circuit 31 and the second common signal output circuit 32 except for the connection destination and signal supply. ing.
As shown in FIG. 7, the signal H3 that defines the on / off state of the switches 311 and 312 in the common signal output circuit 33 is H level in the first half period of each horizontal scanning period and L level in the second half period.

Further, the third point will be described. As shown in FIG. 7, the target signal Vc3ref is n
In the frame, the odd-numbered row becomes the voltage Vsl in the horizontal scanning period selected for the main writing,
While the even-numbered row has the voltage Vsh in the horizontal scanning period selected for the main writing, the odd-numbered row has the voltage Vsh in the horizontal scanning period selected for the main writing in the (n + 1) frame. The voltage Vsl is obtained in the horizontal scanning period selected for inclusion.
That is, the target signal Vc3 becomes the voltage Vsl in the horizontal scanning period in which the positive writing is designated for the row for the main writing, while the horizontal signal in which the negative writing is designated for the row for the main writing. The voltage becomes Vsh during the scanning period.

In such a configuration, if i is an odd number and positive writing is designated at the time of main writing, in the horizontal scanning period in which the i-th row is selected for main writing, Since both the i-th TFTs 173 and 174 are turned on, the i-th TFTs 171 and 172 are turned on and off, respectively, and the i-th common electrode 108 is connected to the first power supply line 161.
Further, the TFT 179 in the i-th row is turned on, and among the detection lines 165a and 165b,
The one connected to the drain electrode of the i-th TFT 179 is connected to the signal line 63.
Here, in the horizontal scanning period in which positive writing is designated in the main writing of the i-th row, the target signal Vc3ref becomes the voltage Vsl. Therefore, the common signal output circuit 33 outputs the voltage Vsl in the first half of the horizontal scanning period. Of the common electrode 10 in the i-th row in the second half period.
The voltages controlled so that 8 becomes the voltage Vsl are used as the common signal Vc3, respectively.
To 63.
In the horizontal scanning period in which the i-th row is selected for the main writing, the i-th TFT 175 is turned on, so that the i-th common electrode 108 is connected to the first feed line 161 and the third feed line 163.
As a result, the common electrode 108 in the i-th row is controlled to be the voltage Vsl.

In the horizontal scanning period in which the i-th row is selected for the main writing, the (i-2) -th row is simultaneously selected for the preliminary writing. Therefore, the TFTs 171, 175, 17 in the (i-2) -th row
9 should also be turned on to switch from the voltage Vsh to the voltage Vsl. However, since the detection line connected to the drain electrode of the TFT 179 in the (i-2) th row is not connected to the signal line 63, negative feedback is not applied to the common electrode 108 in the (i-2) th row. No loop is formed. For this reason, there is a possibility that the common electrode in the (i-2) th row for preliminary writing does not match the voltage Vsl. However, since the purpose of preliminary writing is to reduce the voltage writing amount of the pixel capacitor 120 in the subsequent main writing, even if the common electrode does not match the voltage Vsl in the preliminary writing, the influence is ignored. be able to.

On the other hand, in the even (i + 1) th row following the odd number i, negative polarity writing is designated at the time of the main writing. Therefore, in the horizontal scanning period in which the (i + 2) th row is selected for the main writing, TF of i line
T171 and 172 are turned off and on, respectively, and the common electrode 108 in the (i + 1) th row is the second
Connected to the feeder line 162. Of the detection lines 165 a and 165 b, the one connected to the drain electrode of the TFT 179 in the (i + 1) th row is connected to the signal line 63.
Here, in the horizontal scanning period in which negative polarity writing is designated in the main writing of the (i + 1) th row,
Since the target signal Vc3ref becomes the voltage Vsh, the common signal output circuit 33 sets the buffering voltage of the voltage Vsh in the first half of the horizontal scanning period, and the common electrode 108 in the (i + 1) th row becomes the voltage Vsh in the second half. The controlled voltages are output to the third feeder 163 as the common signal Vc3. For this reason, the common electrode 108 in the (i + 1) th row is controlled to be at the voltage Vsh.
In the next frame, the on / off states of the TFTs 171 and 172 are inverted, and the voltages Vsl and Vsh of the target signal Vc3ref are also inverted.

In the second embodiment, when the i-th row is selected for the main writing, the common signal Vc3 (that is, the i-th common electrode 108 becomes the voltage Vsl or Vsh) by the common signal output circuit 33. In addition to the i-th common electrode, only the (i-2) -th common electrode for which preliminary writing is performed is supplied. Therefore, i, (i-2)
Since the common electrodes other than the row are only connected to either the first feed line 161 or the second feed line 162, the voltage does not fluctuate, and the power consumed by the parasitic capacitance can be suppressed. it can.
In the second embodiment, since the common signal Vc3 is supplied to the common electrode of the row selected for the main writing via the TFT 175 of the row, the TFTs 171 and 172 simply set the common electrode to Vsl, Only the function held in Vsh is sufficient. Therefore, TFTs 171 and 172
The on-resistance of can cope with the deterioration. Note that the period during which the TFT 175 is turned on is only the horizontal scanning period for the preliminary writing and the main writing. Therefore, the characteristics are not deteriorated unlike the TFTs 171 and 172.

<Application and modification of embodiment>
In the first and second embodiments described above, when the i-th row is set as the main write, the (i + 2) row that is two rows lower than that is set as the preliminary write. The reason for adopting such a configuration is that, in the scanning line inversion method, the row below the row for the main writing by a multiple of 2 has the same polarity as the main writing.
Accordingly, when the i-th line is set as the main writing, for example, the (i + 4) line below the 4th line may be set as the preliminary writing. However, if there is a gap between the main writing row and the preliminary writing row, the period for holding the voltage by the preliminary writing, that is, the period for holding the voltage unrelated to the contents to be displayed in the row becomes longer. .

In the embodiment, since the scanning line inversion method in which the writing polarity to the pixel is inverted for each scanning line in one frame, the connection destination of the source electrode of the TFTs 173 and 174 is switched between the odd and even rows. If the frame inversion method is adopted in which the writing polarity is uniform over one frame, it is not necessary to switch the connection destination of the source electrodes of the TFTs 173 and 174 between the odd and even rows.
Further, if the surface inversion method is used, when the i-th line is set to the main writing, for example, (i + 1)
) A configuration may be adopted in which the row is preliminarily written. However, in the configuration in which the i-th row and the (i + 1) -th row adjacent to each other are selected in this way, the two rows of TFTs 179 adjacent to each other are simultaneously turned on. In the configuration shown in FIG. 1, for example, when the first and second rows are selected at the same time, it becomes impossible to detect only the voltage of the common electrode in the first row that is the main write. It is necessary to select the detection line connected to the common electrode for the main writing by the switches 41 to 44 from the two separated detection lines.
Conversely, in the configuration in which the i-th row and the (i + 2) -th row are simultaneously selected as in the first and second embodiments, the drain electrodes of the TFT 179 are alternately connected to the detection lines 165a and 165b every two rows. This is because the detection lines corresponding to the two rows selected at the same time can be separated by the alternate connection every two rows in this way, and the two separated detection lines are connected to the common electrode for the main writing. This is because the detection lines can be selected by the switches 41 to 44.

In the above-described embodiment, the buffering voltages Vsl and Vsh are supplied to the common electrode 108 corresponding to the row for the main writing in the first half of the horizontal scanning period. You may supply the buffering voltage of the voltage swung in the direction which cancels.
In any case, in the second half of the horizontal scanning period, it is desirable to perform negative feedback control so that the common electrode 108 corresponding to the main writing row becomes the voltages Vsl and Vsh.

Further, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. Further, the pixel capacitor 120 is not limited to the transmissive type, but may be a reflective type, or may be a so-called transflective type that combines both the transmissive type and the reflective type.
In addition, one dot may be configured by three pixels of R (red), G (green), and B (blue), and color display may be performed. Further, for example, G is changed to YG (yellowish green) and EG. (Emerald green) may be divided into four dots of one color to form a wide color band.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 8 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, a mobile phone 1200 includes the electro-optical device 10 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that the components of the electro-optical device 10 corresponding to the display region 100 do not appear as appearance.

As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 8, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. , Car navigation device, pager, electronic notebook,
Examples include calculators, word processors, workstations, videophones, POS terminals, photo storage viewers, devices with touch panels, and the like. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the 1st common signal output circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 31 ... 1st common signal output circuit, 32 ... 2nd common signal output circuit, 50 ... NOT circuit, 100 ... Display area, 108 ... Common electrode, 110 ...
Pixel, 112... Scanning line, 114... Data line, 116... TFT, 120.
... Scanning line driving circuit, 170 ... Common electrode driving circuit, 161 ... First feeding line, 162 ... Second feeding line, 164a ... First signal line, 164b ... Second signal line, 171-174, 179 ... TFT
, 190 ... data line driving circuit, 1200 ... mobile phone

Claims (9)

A plurality of scan lines;
Multiple data lines,
A plurality of common electrodes provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines,
A pixel switching element having one end connected to the data line and turned on between the one end and the other end when the scanning line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode;
A pixel containing
A drive circuit for an electro-optical device having:
A scanning line driving circuit for selecting one of the plurality of scanning lines as preliminary writing and selecting the other one as main writing, and sequentially moving the two scanning lines to be selected;
A common electrode driving circuit for connecting a common electrode corresponding to the one scanning line to a predetermined power supply line when one scanning line is selected as the main writing by the scanning line driving circuit;
When the one scanning line is selected as the main writing,
If positive polarity writing is designated for the pixel corresponding to the one scanning line, a common signal controlled so that the common electrode corresponding to the one scanning line becomes the first voltage,
If negative polarity writing is designated for the pixel corresponding to the one scanning line, control is performed so that the common electrode corresponding to the one scanning line becomes a second voltage higher than the first voltage. A common signal output circuit for supplying the common signal to the predetermined power supply line,
Data that supplies a data signal having a voltage corresponding to the gradation of the pixel to the pixel corresponding to the one scanning line via the data line when the one scanning line is selected as the main writing. A line drive circuit;
A drive circuit for an electro-optical device, comprising: The predetermined power supply lines are first and second power supply lines,
The common electrode drive circuit is
If positive polarity writing is designated for the pixel corresponding to the one scanning line, the common electrode corresponding to the one scanning line is connected to the first power supply line, while negative polarity writing is designated. If so, the common electrode corresponding to the one scanning line is connected to the second feeder line,
The common signal output circuit includes first and second common signal output circuits,
The first common signal output circuit includes:
A common signal that is controlled so that the common electrode corresponding to the selected scanning line becomes the first voltage when the positive polarity writing is designated for the pixel corresponding to the scanning line selected as the main writing. To the first feeder line,
The second common signal output circuit is:
A common signal controlled so that the common electrode corresponding to the selected scanning line becomes the second voltage when negative polarity writing is designated for the pixel corresponding to the scanning line selected as the main writing. The driving circuit of the electro-optical device according to claim 1, wherein the driving circuit is supplied to the second feeding line. The common electrode drive circuit is
Each of the first to fourth transistor sets corresponding to the plurality of common electrodes,
Of the first to fourth transistors corresponding to the one common electrode,
A source electrode of the first transistor is connected to the first feeder;
A source electrode of the second transistor is connected to the second feeder line;
The drain electrode of the first transistor and the drain electrode of the second transistor are connected to the one common electrode;
The third transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, a source electrode connected to a first signal line for supplying either an on signal or an off signal, and a drain thereof. An electrode is connected to the gate electrode of the first transistor;
The fourth transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, a source electrode connected to a second signal line having a logic level exclusive to the first signal line, and a drain thereof. The drive circuit of the electro-optical device according to claim 2, wherein the electrode is connected to a gate electrode of the second transistor. The first common signal output circuit includes:
Control is performed so that the common electrode corresponding to the scanning line becomes the first voltage in the period in which positive polarity writing is designated for the pixel corresponding to the scanning line selected as the main writing, or the latter half of the period The common electrode corresponding to the scanning line is controlled to be the first voltage, and in other periods, the buffered voltage of the first voltage is supplied to the first feeder line,
The second common signal output circuit is:
Control is performed so that the common electrode corresponding to the scanning line becomes the second voltage in a period in which negative polarity writing is designated for the pixel corresponding to the scanning line selected as the main writing, or the latter half of the period The common electrode corresponding to the scanning line is controlled to be the second voltage, and a voltage obtained by buffering the second voltage is supplied to the second feeding line in the other period. The drive circuit for the electro-optical device according to claim 2. The predetermined power supply line is a third power supply line;
The common electrode drive circuit is
When the one scanning line is selected as the main writing, a common electrode corresponding to the one scanning line is connected to the third feeding line,
The common signal output circuit is:
If the positive polarity writing is designated for the pixel corresponding to the one scanning line, the common signal controlled so that the common electrode corresponding to the one scanning line becomes the first voltage is set to the negative polarity. When writing is designated, a common signal controlled so that a common electrode corresponding to the one scanning line becomes the second voltage is supplied to the third power supply line, respectively. 2. A drive circuit of the electro-optical device according to 1. The common electrode drive circuit is
Each having a set of first to fifth transistors corresponding to the plurality of common electrodes,
Of the first to fifth transistors corresponding to the one common electrode,
A source electrode of the first transistor is connected to a first feeder line to which the first voltage is fed;
A source electrode of the second transistor is connected to a second feeder line to which the second voltage is fed;
The drain electrode of the first transistor and the drain electrode of the second transistor are connected to the one common electrode;
The third transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, a source electrode connected to a first signal line for supplying either an on signal or an off signal, and a drain thereof. An electrode is connected to the gate electrode of the first transistor;
The fourth transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, a source electrode connected to a second signal line having a logic level exclusive to the first signal line, and a drain thereof. An electrode connected to the gate electrode of the second transistor;
The fifth transistor has a gate electrode connected to the scanning line corresponding to the one common electrode, a source electrode connected to the third power feed line, and a drain electrode connected to the one common electrode. The drive circuit of the electro-optical device according to claim 5. The common signal output circuit is:
If positive polarity writing is designated for the pixel corresponding to the one scanning line, a voltage obtained by buffering the first voltage is set to the third voltage in the first half of the period during which the one scanning line is selected. The power supply line is supplied, and the common electrode corresponding to the scanning line is controlled to be the first voltage in the period. Alternatively, in the second half of the period, the common electrode corresponding to the one scanning line is the first voltage. Control to be a voltage,
If negative polarity writing is designated, the common electrode corresponding to the scanning line is controlled to be the second voltage in the period in which the one scanning line is selected, or in the first half of the period,
A voltage obtained by buffering the second voltage is supplied to the third power supply line, and the common electrode corresponding to the one scanning line is controlled to be the second voltage in the second half of the period. The drive circuit for the electro-optical device according to claim 5. A plurality of scan lines;
Multiple data lines,
A plurality of common electrodes provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines,
A pixel switching element having one end connected to the data line and turned on between the one end and the other end when the scanning line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode;
A pixel containing
A scanning line driving circuit for selecting one of the plurality of scanning lines as preliminary writing and selecting the other one as main writing, and sequentially moving the two scanning lines to be selected;
A common electrode driving circuit for connecting a common electrode corresponding to the one scanning line to a predetermined power supply line when one scanning line is selected as the main writing by the scanning line driving circuit;
When the one scanning line is selected as the main writing,
If positive polarity writing is designated for the pixel corresponding to the one scanning line, a common signal controlled so that the common electrode corresponding to the one scanning line becomes the first voltage,
If negative polarity writing is designated for the pixel corresponding to the one scanning line, control is performed so that the common electrode corresponding to the one scanning line becomes a second voltage higher than the first voltage. A common signal output circuit for supplying the common signal to the predetermined power supply line,
Data that supplies a data signal having a voltage corresponding to the gradation of the pixel to the pixel corresponding to the one scanning line via the data line when the one scanning line is selected as the main writing. A line drive circuit;
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 8.

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