JP4215109B2 - Electro-optical device, drive circuit, and electronic device - Google Patents

Description

  The present invention relates to a technique for suppressing a voltage amplitude of a data line with a simple configuration and preventing deterioration of display quality in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. When this pixel capacitor needs to be AC driven, the voltage amplitude of the data signal is positive or negative. Therefore, in the data line driving circuit for supplying a data signal to the data line, a breakdown voltage corresponding to the voltage amplitude is required for the constituent elements. For this reason, a storage capacitor is provided in parallel with the pixel capacitor, and a capacitor line commonly connected to the storage capacitor in each row is driven in binary in synchronization with the selection of the scanning line, thereby suppressing the voltage amplitude of the data signal. A technique has been proposed (see Patent Document 1).
JP 2001-83943 A

By the way, in this technique, the circuit for driving the capacitance line is equivalent to the scanning line driving circuit (substantially a shift register) for driving the scanning line, so that the circuit configuration for driving the capacitance line is complicated. End up.
SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device, a driving circuit, and an electronic apparatus that can suppress the voltage amplitude of a data line with a simple configuration. There is to do.

  In order to achieve the above object, a drive circuit for an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of capacitors provided corresponding to the plurality of scanning lines. Each of the scanning lines of the plurality of rows and the data lines of the plurality of columns is provided corresponding to an intersection, and each of the scanning lines is connected to a data line corresponding to itself and a scanning line corresponding to itself is provided. A pixel switching element that becomes conductive when selected, a pixel capacitor interposed between the pixel switching element and a common electrode, and a capacitor provided corresponding to one end of the pixel capacitor and the scanning line A scanning line driving circuit for selecting the scanning lines in a predetermined order; and a single scanning line, comprising: a pixel including a storage capacitor interposed between the scanning line and a pixel; For the capacitance line provided corresponding to When the inspection line is selected, the first power supply line is selected, and a scanning line that is separated from the one scanning line by a predetermined line and selected after the one scanning line is selected, and then again. The second power supply line is selected until the one scanning line is selected, and the capacitor line driving circuit for applying the voltage of the selected power supply line and the pixel corresponding to the selected scanning line are And a data line driver circuit for supplying a data signal corresponding to a gray scale through a data line. According to the present invention, it is possible to suppress the voltage amplitude of the data line and to prevent the display quality from being lowered with a simple configuration.

Here, in the drive circuit of the electro-optical device according to the present invention, when a scanning line separated by a predetermined row from the scanning line corresponding to one capacitance line is selected, the voltage of the one capacitance line changes. The voltage of the first and second power supply lines is preferably set, and the voltage of the first power supply line is switched between two different voltages at a predetermined cycle, and the voltage of the second power supply line is The voltage of the second power supply line may be constant, or the intermediate value of the two voltages of the first power supply line may be used. Further, the first and second power supply lines may be switched such that two different voltages are complementarily and each time the scanning line is selected.
In the drive circuit of the electro-optical device according to the invention, the capacitor line drive circuit includes first to fourth transistors corresponding to each of the capacitor lines, and the first corresponding to one capacitor line. One transistor is connected to a scanning line whose gate electrode is separated from the scanning line corresponding to the one capacitance line by a predetermined number of rows, and a source electrode is an on-voltage power supply line that supplies an on-voltage for turning on the fourth transistor. The second transistor has a gate electrode connected to a scanning line corresponding to the one capacitor line, and a source electrode connected to an off-voltage supply line that supplies an off-voltage for turning off the fourth transistor. The third transistor has a gate electrode connected to the scanning line corresponding to the one capacitance line, a source electrode connected to the first power supply line, and the fourth transistor having a gate The pole is commonly connected to the drain electrodes of the first and second transistors, the source electrode is connected to the second feeder, and the drain electrodes of the third and fourth transistors are connected to the one capacitance line. It is good also as a structure. In such a configuration, a plurality of sets of the first, second, and fourth transistors are provided for one capacitor line, and a fourth transistor that connects the one capacitor line to the second feeder line is provided, Switching from a plurality of sets may be performed in a predetermined order. Also, in this configuration, each of the capacitance lines has an auxiliary capacitance, and one end of the auxiliary capacitance corresponding to one capacitance line is connected to the gate electrode of the fourth transistor, and the other end is A configuration in which the potential is kept constant at least in a period from when a scanning line separated by a predetermined row from the scanning line corresponding to the one capacitor line is selected until the one scanning line is selected again may be employed. Here, the other end of the auxiliary capacitor corresponding to the one capacitor line may be connected to the scanning line corresponding to the one capacitor line.
On the other hand, in the drive circuit of the electro-optical device according to the present invention, the first feeder line is divided into an odd row and an even row, and the source electrode of the third transistor of the capacitor line corresponding to the odd row is an odd row. The source electrode of the third transistor of the capacitor line corresponding to the even row is connected to the first feed line for the even row, and one of the two different voltages corresponds to the odd row. The other two voltages are applied to the first power supply line corresponding to the even-numbered row, and the two different voltages are complementarily replaced with each other at a predetermined cycle. It is also good.
The present invention can be conceptualized not only as a drive circuit for an electro-optical device, but also as an electro-optical device, and further as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, the electro-optical device 10 has a display area 100, and a control circuit 20, a scanning line driving circuit 140, a capacitor line driving circuit 150, and a data line driving circuit 190 are arranged around the display area 100. The arrangement is arranged. Among these, the display area 100 is an area where the pixels 110 are arranged. In this embodiment, 321 rows of scanning lines 112 extend in the row (X) direction, while 240 columns of data lines 114 are columns (Y ) Of the pixels corresponding to the intersection of the scanning lines 112 in the 1st to 320th rows other than the final 321st row and the data lines 114 in the 1st to 240th columns. 110 are arranged. Therefore, in the present embodiment, the scanning line 112 in the 321st row does not contribute to the vertical scanning of the display area 100 (operation for sequentially selecting scanning lines for voltage writing to the pixels 110).
In the present embodiment, the pixels 110 are arranged in a matrix of 320 rows × 240 columns in the display region 100, but the present invention is not limited to this arrangement.
In addition, corresponding to the scanning lines 112 in the first to 320th rows, capacitance lines 132 are provided extending in the X direction, respectively. For this reason, in the present embodiment, the capacity lines 132 are provided for 1 to 320 rows excluding the dummy 321st scanning line 112.

Here, a detailed configuration of the pixel 110 will be described.
FIG. 2 is a diagram illustrating the configuration of the pixel 110, and 2 × 2 total 4 corresponding to the intersections of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto. A configuration for pixels is shown.
Note that i is a symbol generally indicating a row in which the pixels 110 are arranged, and is an integer of 1 to 320, and j and (j + 1) generally indicate a column in which the pixels 110 are arranged. The symbol of the case, which is an integer from 1 to 240. Here, (i + 1) is an integer of 1 or more and 320 or less when generally indicating the row in which the pixels 110 are arranged, but is a dummy 321 when describing the row of the scanning line 112. Since it is necessary to include the line, it is an integer between 1 and 321 inclusive.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, And a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in the i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 that is one end of the pixel capacitor 120.
The other end of the pixel capacitor 120 is connected to the common electrode 108. The common electrode 108 is common to all the pixels 110 as shown in FIG. 1 and is supplied with a common signal Vcom. In the present embodiment, the common signal Vcom is constant at the voltage LCcom in terms of time as will be described later.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the i and (i + 1) th scanning lines 112, respectively, and Ci and C (i + 1) indicate i and (i + 1), respectively. ) The voltage of the capacitor line 132 in the row is shown.

  In the display region 100, a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, are bonded to each other with a certain gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in the gap. For this reason, the pixel capacitor 120 has a configuration in which the liquid crystal 105 which is a kind of dielectric is sandwiched between the pixel electrode 118 and the common electrode 108, and holds a differential voltage between the pixel electrode 118 and the common electrode 108. . In this configuration, in the pixel capacitor 120, the amount of transmitted light changes according to the effective value of the holding voltage. In the present embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value is increased. The normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is set.

  The storage capacitor 130 in the pixel 110 in the i row and j column has one end connected to the pixel electrode 118 (the drain electrode of the TFT 116) and the other end connected to the i-th capacitor line 132. Here, the capacitance values in the pixel capacitor 120 and the storage capacitor 130 are Cpix and Cs, respectively.

Returning again to FIG. 1, the control circuit 20 outputs various control signals to control each part in the electro-optical device 10, and the second capacitance signal Vc <b> 1 is supplied to the first power supply line 165. The capacitance signal Vc2 is supplied to the second power supply line 167, respectively. In addition, the control circuit 20 supplies an on-voltage Von, which will be described later, to the on-voltage power supply line 161 and the off-voltage Voff to the off-voltage power supply line 16.
3, and a common signal Vcom is supplied to the common electrode 108.
As described above, peripheral circuits such as the scanning line driving circuit 140, the capacitor line driving circuit 150, and the data line driving circuit 190 are provided around the display region 100. Among these, the scanning line driving circuit 140 sends the scanning signals Y1, Y2, Y3,..., Y320, Y321 to 1, 2, 3,. This is supplied to the scanning line 112 in the row. That is, the scanning line driving circuit 140 selects the scanning lines in the order of the first, second, third,..., 320, and 321st rows, and sets the scanning signal to the selected scanning line to the H level corresponding to the selection voltage Vdd. The scanning signals for the other scanning lines are set to the L level corresponding to the non-selection voltage (ground potential Gnd).

In detail, as shown in FIG. 4, the scanning line driving circuit 140 sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly, etc., so that the scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 are output.
In the present embodiment, as shown in FIG. 4, the period of one frame is an effective scanning period Fa from when the scanning signal Y1 becomes H level until the scanning signal Y320 becomes L level,
And a blanking period Fb from when the dummy scanning signal Y321 becomes H level to when the scanning signal Y1 becomes H level again. A period during which one row of scanning lines 112 is selected is a horizontal scanning period (H).

In the present embodiment, the capacitor line driving circuit 150 includes a set of TFTs 152, 154, 156, and 158 provided corresponding to the capacitor lines 132 in the first to 320th rows. Here, the TFTs 152, 154, 156, 158 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 152 (first transistor) is selected next to the i-th row (i + 1) -th row. The source electrode is connected to the on-voltage power supply line 161. The gate electrode of the i-th TFT 154 (second transistor) is connected to the i-th scanning line 112, the source electrode is connected to the off-voltage power supply line 163, and the TFTs 152 and 154 in the i-th row are connected. The drain electrodes are connected to the gate electrode of the TFT 158 in the i-th row.
On the other hand, the gate electrode of the i-th TFT 156 (third transistor) is connected to the i-th scanning line 112, and the source electrode thereof is connected to the first power supply line 165. The source electrode of the i-th TFT 158 (fourth transistor) is connected to the second feed line 167, and the drain electrodes of the TFTs 156 and 158 are connected to the i-th capacitor line 132.
Here, the on-voltage Von supplied to the on-voltage power supply line 161 is a voltage that, when applied to the gate electrode of the TFT 158, turns the TFT 158 on (the source-drain electrode is conductive). For example, the voltage Vdd. Further, the off-voltage Voff supplied to the off-voltage power supply line 163 corresponds to the T voltage when it is applied to the gate electrode of the TFT 158.
This is a voltage that causes the FT 158 to be in an off state (non-conducting state between the source and drain electrodes), for example, a zero voltage (ground potential Gnd).

The data line driving circuit 190 is a voltage corresponding to the gray level of the pixel 110 located on the scanning line 112 selected by the scanning line driving circuit 140, and has a polarity voltage data signal X1 designated by the polarity instruction signal Pol. , X2, X3,..., X240 are supplied to the data lines 114 in the 1, 2, 3,.
Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation value (brightness) of the corresponding pixel 110. Display data Da for designating the data is stored. The display data Da stored in each storage area is rewritten by the display circuit Da after the change together with the address by the control circuit 20 when the display contents are changed.
The data line driving circuit 190 reads out the display data Da of the pixel 110 located on the selected scanning line 112 from the storage area, and converts it into a data signal having a voltage corresponding to the gradation value and having a specified polarity. The operation of converting and supplying to the data line 114 is executed for each of the 1 to 240 columns positioned on the selected scanning line 112.

Here, the polarity instruction signal Pol is a signal for designating positive polarity writing when it is at the H level, and for designating negative polarity writing when it is at the L level. In this embodiment, as shown in FIG. The polarity is inverted every frame period. That is, in this embodiment, the surface inversion method is used in which all the polarities to be written to the pixels in the period of one frame are the same, and the writing polarity is inverted every period of one frame. The reason for polarity inversion is to prevent deterioration of the liquid crystal due to application of a direct current component.
As for the writing polarity in the present embodiment, when the voltage corresponding to the gradation is held in the pixel capacitor 120, the potential of the pixel electrode 118 is higher than the voltage LCcom of the common electrode 108. It is called positive polarity, and the case of the lower side is called negative polarity. On the other hand, the voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

The control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at the timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 outputs the scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 by sequentially shifting the start pulse Dy according to the clock signal Cly. The start timing of the period in which is selected is the timing at which the logic level of the clock signal Cly transitions. Therefore, the data line driving circuit 190 starts the selection depending on, for example, which row scanning line is selected by continuously counting the latch pulse Lp over a period of one frame and the supply timing of the latch pulse Lp. You can know the timing.

  In this embodiment, in addition to the scanning lines 112, the data lines 114, the TFTs 116, the pixel electrodes 118, and the storage capacitors 130 in the display region 100, the element substrate includes the TFTs 152, 154, 156 in the capacitor line driving circuit 150. 158, an on-voltage feed line 161, an off-voltage feed line 163, a first feed line 165, a second feed line 167, and the like are also formed.

FIG. 3 is a plan view showing a configuration in the vicinity of the boundary between the capacitive line driving circuit 150 and the display region 100 in such an element substrate.
As shown in this figure, in the present embodiment, the TFTs 116, 152, 154, 156, 158 are of the amorphous silicon type and the bottom gate type in which the gate electrode is located below the semiconductor layer. Specifically, the scanning electrode 112, the capacitor line 132, and the gate electrode of the TFT 158 are formed by patterning the gate electrode layer serving as the first conductive layer, a gate insulating film (not shown) is formed thereon, and the TFT 116 is further formed. , 152, 154, 156, and 158 are formed in an island shape. On the semiconductor layer, a rectangular pixel electrode 118 is formed by patterning an ITO (indium tin oxide) layer serving as a second conductive layer via a protective layer, and further aluminum or the like serving as a third conductive layer. By patterning the metal layer, the data line 114, the on-voltage power supply line 161, the off-voltage power supply line 163, the first power supply line 165, and the second power supply line 167 that are the source electrodes of the TFTs 116, 152, 154, 156, and 158 are formed. At the same time, the drain electrodes of these TFTs are formed.

Here, the gate electrodes of the TFTs 154 and 156 are portions branched from the scanning line 112 in the Y (downward) direction in a T shape, and the gate electrode of the TFT 152 is a T shape from the scanning line 112 in the Y (upward) direction. It is the part which branched in the shape. The storage capacitor 130 has a structure in which the gate insulating film is sandwiched between the pixel electrode 118 and a portion of the capacitor line 132 formed so as to be wide in the lower layer of the pixel electrode 118.
In addition, the common drain electrode of the TFTs 152 and 154 and the gate electrode of the TFT 158 are electrically connected via a contact hole (indicated by X in the drawing) penetrating the gate insulating film. Similarly, the common drain electrodes of the TFTs 156 and 158 and the capacitor line 132 are electrically connected via contact holes (indicated by X in the figure).
Note that the common electrode 108 facing the pixel electrode 118 is formed on the counter substrate, and thus does not appear in FIG. 3 showing a plan view of the element substrate.

FIG. 3 is merely an example, and the TFT type may be another structure, for example, the top gate type in terms of the arrangement of the gate electrodes, or the polysilicon type in terms of the process. Further, instead of building the element of the capacitor line driving circuit 150 in the display region 100, an IC chip may be mounted on the element substrate side.
When the IC chip is mounted on the element substrate side, the scanning line driving circuit 140 and the capacitor line driving circuit 150 may be integrated as a semiconductor chip together with the data line driving circuit 190, or may be separate chips. The control circuit 20 is FPC (flexible printed
circuit) may be connected via a substrate or the like, or may be configured to be mounted on an element substrate as a semiconductor chip.
When the present embodiment is a reflective type instead of a transmissive type, the reflective conductive layer may be patterned for the pixel electrode 118, or a separate reflective metal layer may be provided. Furthermore, a so-called transflective type in which both a transmissive type and a reflective type are combined may be used.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
As described above, in this embodiment, the surface inversion method is used. Therefore, the control circuit 20 designates the positive polarity writing as the H level in the period of a certain frame (denoted as “n frame”) for the polarity instruction signal Pol, as shown in FIG. The negative polarity writing is designated as the L level during the period of (n + 1) frames, and the writing polarity is similarly reversed every frame period thereafter.
Further, the control circuit 20 sets the first capacitance signal Vc1 and the second capacitance signal Vc2 to the same potential in the n frame, while the first capacitance signal Vc1 is set to be higher than the second capacitance signal Vc2 in the (n + 1) frame. The voltage is relatively increased by ΔV. Therefore, as shown in FIG. 4, if the second capacitance signal Vc2 is constant regardless of the writing polarity at the voltage Vs1, the first capacitance signal Vc1 is the same voltage Vsl in the n frames, and (n + 1) ) The voltage Vsh is higher than the voltage Vsl by ΔV in the frame.

In the n frame, the scanning signal driving circuit 140 first sets the scanning signal Y1 to the H level.
On the other hand, when the latch pulse Lp is output at the timing when the scanning signal Y1 becomes H level, the data line driving circuit 190 displays the pixels in the first row and the columns 1, 2, 3,. The data Da is read and converted into data signals X1, X2, X3,..., X240 having a voltage specified by the display data Da as a high-order side with respect to the voltage LCcom. ..., supplied to the 240 data lines 114.
Thus, for example, a positive voltage that is higher than the voltage LCcom by the voltage specified by the display data Da of the pixel 110 in the first row and j column is applied to the jth data line 114 as the data signal Xj. .
Now, when the scanning signal Y1 becomes the H level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned on. Is done. For this reason, a positive voltage corresponding to each gradation is written in the pixel capacitors 120 in the first row and the first column to the first row and the 240th column.
On the other hand, if the scanning signal Y1 is at the H level, in the capacitor line driving circuit 150, the TFTs 154 and 156 corresponding to the capacitor line 132 in the first row are turned on, but the TFT 152 is off (the scanning signal Y2 is at the L level). Therefore, the off voltage Voff is applied to the gate electrode of the TFT 158 and the TFT 158 is turned off. As a result, the capacitor line 132 in the first row is connected to the first power supply line 165, and the voltage Vsl It becomes. For this reason, the differential voltage between the positive voltage and the voltage Vsl corresponding to each gradation is written in the storage capacitor 130 in the first row and the first column to the first row and the 240th column.

Next, the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level.
When the scanning signal Y1 becomes L level, the TFTs 116 in the pixels in the first row and first column to the first row and 240th column are turned off. If the scanning signal Y1 is at the L level and the scanning signal Y2 is at the H level, in the capacitor line driving circuit 150, the TFTs 154 and 156 corresponding to the capacitor line 132 in the first row are turned off and the TFT 152 in the first row is turned on. Therefore, the on-voltage Von is applied to the gate electrode of the TFT 158 in the first row and the TFT 158 is turned on. As a result, the capacitor line 132 in the first row is connected to the second power feed line 167. In the n frame designating positive polarity writing, the second power supply line 167 is at the same voltage Vsl as the first power supply line 165, so that the potential does not fluctuate.
Therefore, if the polarity instruction signal Pol is at the H level and the positive polarity writing is instructed, even if the scanning signal Y2 becomes the H level, the pixel capacitors 120 and the storage capacitors of the first row and the first column to the first row and the 240th column are stored. There is no change in the voltage held at 130.

On the other hand, when the latch pulse Lp is output at the timing when the scanning signal Y2 becomes H level, the data line driving circuit 190 is the gray level of the pixels in the second row and the first, second, third,. .., X240 are supplied to the data lines 114 of 1, 2, 3,..., 240 columns, respectively. When the scanning signal Y2 becomes the H level, the TFTs 116 in the pixels of the 2nd row and the 1st column to the 2nd row and the 240th column are turned on, so that the data signals X1, X2, X3,. As a result, the positive voltage corresponding to the gradation is written in each of the pixel capacitors 120 in the first row and the first column to the first row and the 240th column.
If the scanning signal Y2 is at the H level, in the capacitor line driving circuit 150, the TFTs 154 and 156 corresponding to the capacitor line 132 in the second row are turned on, but the TFT 152 in the second row is off (scanning signal). Since Y3 is at the L level, the TFT 158 in the second row is also off. For this reason, since the capacitor line 132 in the second row is at the voltage Vsl, the difference voltage between the positive voltage and the voltage Vsl corresponding to the gradation is respectively stored in the storage capacitor 130 in the second row and first column to the second row and 240th column. Will be written.

Next, the scanning signal Y2 becomes L level and the scanning signal Y3 becomes H level.
When the scanning signal Y2 becomes L level, in the capacitor line driving circuit 150, the TFT 152 corresponding to the capacitor line 132 in the first row is turned off. For this reason, the gate electrode of the TFT 158 corresponding to the capacitor line 132 in the first row is in a high impedance state that is not electrically connected anywhere, but because of the capacitance parasitic on the gate electrode itself, the first row The on-voltage Von which is the state immediately before the TFT 152 is turned off is maintained. For this reason, since the TFT 158 corresponding to the capacitor line 132 in the first row continues to be in the on state, the capacitor line 132 in the first row maintains the voltage Vsl. Note that the operation in which the capacitor line 132 in the first row maintains the voltage Vsl is continued until the scanning signal Y1 becomes H level again.
Since the capacitor line 132 in the first row is maintained at the voltage Vsl, the voltage held in the pixel capacitor 120 and the storage capacitor 130 in the first row and first column to the first row and 240 columns is again until the scanning signal Y1 becomes the H level. There will be no change. After all, the pixel capacitance 120 in the first row and first column to the first row and 240th column has a difference between the voltage of the data signal applied to the pixel electrode 118 and the voltage LCcom of the common electrode 108 when the scanning signal Y1 becomes H level. The voltage, that is, the voltage corresponding to the gradation is continuously held.
Further, when the latch pulse Lp is output at the timing when the scanning signal Y3 becomes H level, the data line driving circuit 190 is the gradation of the pixels in the third row and in the first, second, third,. .., X240 are supplied to the data lines 114 of 1, 2, 3,..., 240 columns, respectively, whereby 3 rows 1 columns to 3 rows 240 are supplied. A positive voltage corresponding to each gradation is written in the pixel capacitors 120 in the column.
If the scanning signal Y3 is at the H level, in the capacitor line driving circuit 150, the TFTs 154 and 156 corresponding to the capacitor line 132 in the third row are turned on, but the TFT 152 in the third row is turned off (scanning signal). Since Y4 is at L level), the TFT 158 in the third row is also turned off. For this reason, since the capacitor line 132 in the third row has the voltage Vsl, the storage capacitor 130 in the third row and first column to the third row and 240th column has a difference voltage between the positive voltage and the voltage Vsl corresponding to each gradation. Will be written.

In the n-frame period in which the polarity instruction signal Pol is at the H level, the same operation is repeated until the scanning signal Y321 becomes the H level. Thereby, the voltage of the data signal applied to the pixel electrode 118, that is, the difference voltage between the positive voltage corresponding to the gradation and the voltage LCcom of the common electrode 108 is held in all the pixel capacitors 120. All storage capacity 13
At 0, the difference voltage between the positive voltage corresponding to the gradation and the voltage Vsl is held.

Next, the control circuit 20 will describe the operation of (n + 1) frames in which the polarity signal Pol becomes L level.
The operation of the (n + 1) frame is different from the operation of the n frame mainly in the following two points. That is, first, the control circuit 20 sets the first capacitance signal Vc1 to a voltage Vsh higher by ΔV than the voltage Vsl as shown in FIG. 4, and secondly, the scanning signal Yi is at the H level. When the latch pulse Lp is output at the timing, the data line driving circuit 190 performs n frames until the point at which the display data Da of the pixels in the 1, 2, 3,. However, the data signals X1, X2, X3,..., X240 are n frames in that they correspond to the display data Da and have a voltage corresponding to the negative polarity (this meaning will be described later). The operation is different.
Therefore, with respect to the operation in the (n + 1) frame, the voltage written in the pixel capacitor 120 in the i row and j column when the scanning signal Yi becomes H level is the scanning signal Y (i + 1), centering on this difference. It will be explained from the viewpoint of how it changes when the value becomes H level.

FIG. 5 is a diagram for explaining a voltage change of the pixel capacitor 120 of i rows and j columns in the (n + 1) frame.
First, when the scanning signal Yi becomes H level, as shown in FIG. 5A, the TFTs 116 in i rows and j columns are turned on, so that the data signal Xj is connected to one end (pixel electrode 118) of the pixel capacitor 120 and the storage capacitor. The voltage is applied to one end of 130. On the other hand, if the scanning signal Yi is at the H level, the TFTs 154 and 156 corresponding to the i-th capacitor line 132 are turned on and the TFTs 152 and 158 are turned off in the capacitor line driving circuit 150. The voltage Ci becomes the voltage Vsh of the first feeder 165. The common electrode 108 is constant at the voltage LCcom.
Therefore, if the voltage of the data signal Xj at this time is Vj, the pixel capacitor 120 in the i row and j column is charged with the voltage (Vj−LCcom), and the storage capacitor 130 is charged with the voltage (Vj−Vsh). The

Next, when the scanning signal Yi becomes L level, as shown in FIG. 5B, the TFTs 116 in the i rows and j columns are turned off. Further, when the scanning signal Yi becomes the L level, the next scanning signal Y (i + 1) becomes the H level ((i + 1) rows are not shown in FIG. 5B). The TFTs 154 and 156 corresponding to the capacitor line 132 of the eye are turned off, the TFT 152 of the i-th row is turned on, and the on-voltage Von is applied to the gate electrode of the TFT 158 of the i-th row. For this reason, since the TFT 158 in the i-th row is turned on, the voltage Ci of the capacitor line 132 in the i-th row becomes the voltage Vsl of the second power supply line 167, which is a voltage compared to when the scanning signal Yi is at the H level. Decrease by ΔV. On the other hand, the common electrode 108 is constant at the voltage LCcom. Therefore, the charge stored in the pixel capacitor 120 moves to the storage capacitor 130, so that the voltage of the pixel electrode 118 decreases.
Specifically, in the serial connection of the pixel capacitor 120 and the storage capacitor 130, the other end (common electrode) of the pixel capacitor 120 is maintained at a constant voltage, and the other end of the storage capacitor 130 is reduced by the voltage ΔV. The voltage of the pixel electrode 118 also decreases.
For this reason, the voltage of the pixel electrode 118 which is the series connection point is
Vj− {Cs / (Cs + Cpix)} · ΔV
Therefore, the capacitance ratio {Cs / (Cs + Cpix) of the pixel capacitor 120 and the storage capacitor 130 is more than the voltage change ΔV of the capacitor line 132 in the i-th row than the voltage Vj of the data signal when the scanning signal Yi is at the H level. )}. That is, the i-th capacitance line 1
When the voltage Ci of 32 is reduced by ΔV, the voltage of the pixel electrode 118 becomes {Cs / (Cs + Cpix)} · ΔV (= Δ) rather than the voltage Vj of the data signal when the scanning signal Yi is at the H level.
Vpix). However, the parasitic capacitance of each part is ignored.

Here, the data signal Xj when the scanning signal Yi is at the H level is set to the voltage Vj in anticipation that the pixel electrode 118 is lowered by the voltage ΔVpix. That is, the voltage of the pixel electrode 118 after being lowered is set to be lower than the voltage LCcom of the common electrode 108, and the difference voltage between the two is set to a value corresponding to the gradation of i rows and j columns.
Specifically, in the present embodiment, as shown in FIG. 7, in the n frame for positive polarity writing, the data signal has a voltage Vb (+) corresponding to black b from a voltage Vw (+) corresponding to white w. ), And when the voltage becomes higher than the voltage LCcom as the gradation becomes lower (darker), the voltage Vb ( In the case where the pixel is black b, the voltage Vw (+) is set to be the same as the positive voltage range and the gradation relationship is reversed. Second, after the voltage of the data signal is written in the (n + 1) frame, when the pixel electrode 118 is lowered by the voltage ΔVpix, the voltage of the pixel electrode 118 is changed from the voltage Vw (−) corresponding to negative white to black. And a decrease (Vsh−Vsl) of the voltage ΔV of the capacitor line 132 is set so as to be symmetrical to the positive voltage with reference to the voltage LCcom.
As a result, in the (n + 1) frame designating negative polarity writing, the voltage of the pixel electrode 118 when lowered by the voltage ΔVpix is a negative polarity voltage corresponding to the gradation, that is, the voltage Vw ( In the range from-) to the voltage Vb (-) corresponding to black b, the voltage shifts to a voltage lower than the voltage LCcom as the gradation becomes lower (darker).
In FIG. 5, the pixel capacitor 120 and the storage capacitor 130 in the i row and j column are described, but the same operation is similarly performed for the i row that also functions as the scanning line 112 and the capacitor line 132. In the (n + 1) frame, as in the n frame, the scanning signals Y1, Y2, Y3,..., Y320, Y321 are sequentially at the H level, so that the operation in each row is 1, 2, 3,. The processing is also performed in order for the 320 rows of pixels.

As described above, in this embodiment, the voltage range a of the data line in the (n + 1) frame designating the negative polarity write is the same as the n frame designating the positive polarity write, but the pixel electrode 118 after the shift. Is a negative voltage corresponding to the gradation. Thus, according to the present embodiment, not only the withstand voltage of the elements constituting the data line driving circuit 190 is reduced, but also the voltage amplitude in the data line 114 where the capacitance is parasitic is reduced, so that the parasitic capacitance is wasteful. Power is not consumed.
That is, when the pixel capacitor 120 is AC-driven in a configuration in which the common electrode 108 is maintained at the voltage LCcom and the voltage of the capacitor line 132 is constant over each frame, the pixel electrode 118 has a gradation in a certain frame. Accordingly, when writing is performed with a voltage in the range from the positive voltage Vw (+) to the voltage Vb (+), if there is no change in gradation, the voltage from the voltage Vw (−) corresponding to the negative polarity will be applied in the next frame. A voltage up to Vb (−) and inverted with respect to the voltage LCcom must be written. For this reason, in the configuration in which the voltage of the common electrode 108 is constant, when the voltage of the capacitor line 132 is constant, the voltage of the data signal covers the range b in the figure, so that the breakdown voltage of the elements constituting the data line driving circuit 190 is also in the range. In addition to the need to correspond to b, if the voltage changes in the range b in the data line 114 where the capacitance is parasitic, there is a disadvantage that power is wasted due to the parasitic capacitance. On the other hand, in the present embodiment, the voltage range a of the data line is approximately halved compared to the range b, so that such inconvenience is solved.

Furthermore, according to the present embodiment, as shown in FIG. 6, in the frame instructing positive polarity writing, the voltage Ci of the capacitance line 132 in the i-th row is the second when the scanning signal Yi becomes H level. The voltage Vsl of the first power supply line 165 becomes the voltage Vsl of the second power supply line 167 when the next scanning signal Y (i + 1) becomes the H level. For this reason, the voltage Ci of the capacitance line 132 in the i-th row does not change at the timing when the scanning signal Y (i + 1) becomes the H level in the frame instructing the positive writing.
On the other hand, in the frame instructing negative polarity writing, the voltage Ci of the capacitor line 132 in the i-th row becomes the voltage Vsh when the scanning signal Yi becomes H level, and the next scanning signal Y (i + 1) becomes H level. Becomes the voltage Vsl of the second feeder 167. For this reason, the voltage Ci of the capacitance line 132 in the i-th row decreases by the voltage ΔV at the timing when the scanning signal Y (i + 1) becomes the H level in the frame instructing negative polarity writing.
In the present embodiment, four TFTs 152, 154, 156, and 158 are sufficient to drive the capacitor line 132 for one row in this way, and no additional control signal or control voltage is required. For this reason, the configuration of the capacitor line driving circuit 150 that drives the capacitor line 132 corresponding to each row can be prevented from becoming complicated.
FIG. 6 is a diagram showing the voltage relationship among the scanning signal, the capacitor line, and the pixel electrode, and the voltage change of the pixel electrode 118 in i row and j column is indicated by Pix (i, j).

In addition, according to the present embodiment, even after the scanning signal Y (i + 1) changes to the L level, the gate electrode of the TFT 158 corresponding to the i-th capacitance line 132 is turned on by the parasitic capacitance. Therefore, as a result of the TFT 158 being kept on, the i-th capacitor line 132 is stabilized at the voltage of the second capacitor signal Vc2 without being in a high impedance state. Since the capacitor line 132 intersects with the data lines 114 of 1 to 240 columns, the capacitor line 132 is not only easily affected by the voltage change of the data signals X1 to X240, but is also parallel to the scan line 112, so the voltage change of the scan signal Also susceptible to If the capacitance line 132 is not stabilized by the voltage of the second capacitance signal Vc2, the voltage fluctuates under the influence of these voltage changes. When the voltage of the capacitor line 132 fluctuates, the voltage held in the pixel capacitor 120 is deviated from the voltage corresponding to the target gradation value, which adversely affects the display quality. Since the capacitance line 132 does not fluctuate, such display quality is hardly affected.
In addition, although the voltage range of the data signal when the positive polarity writing is specified and the voltage range of the data signal when the negative polarity writing is specified are matched, The voltage amplitude of the data signal can be suppressed by the voltage change of the capacitor line 132.

In this description, by setting the second capacitance signal Vc2 to be constant at the voltage Vsl, when the scanning signal Y (i + 1) becomes H level in the n frame designating the positive writing, the i-th row While the voltage of the capacitor line 132 is not changed, when the scanning signal Y (i + 1) becomes H level in the (n + 1) frame designating negative polarity writing, the capacitor line 132 in the i-th row is lowered by the voltage ΔV. Thus, the pixel electrode 118 written when the scanning signal Yi is at the H level is decreased by the voltage ΔVpix, but this may be reversed.
That is, as shown in FIG. 8, by making the second capacitance signal constant at the voltage Vsh, when the scanning signal Y (i + 1) becomes H level in the frame designating negative polarity writing, i rows While the voltage of the capacitive line 132 of the eye is not changed, when the scanning signal Y (i + 1) becomes the H level in the frame designating the positive writing, the capacitive line 132 of the i-th row is raised by the voltage ΔV. The pixel electrode 118 written when the scanning signal Yi is at the H level may be raised by the voltage ΔVpix.
In this configuration, the voltage relationship of the data signal is as shown in FIG. 7 (a) and FIG.
Inversion is performed with reference to Ccom, and positive writing is replaced with negative writing, and negative writing is replaced with positive writing.

Furthermore, in this explanation, the polarity to be written to the pixels in the period of one frame is all the same, and the surface inversion method is used in which the writing polarity is inverted every period of one frame, but the writing polarity is inverted every row. A scanning line (line) inversion method may be used.
When the scanning line inversion method is used, the polarity instruction signal Pol is inverted every horizontal scanning period (H) as shown in FIG. 9, and the same scanning signal becomes H level in adjacent frames. This relationship is also reversed when viewed in the period (the same scanning line is selected).
The first capacitance signal Vc1 becomes the voltage Vsl when the polarity instruction signal Pol is at the H level, and becomes the voltage Vsh when the polarity instruction signal Pol is at the L level.
Accordingly, in the n frame of FIG. 9, the odd-numbered (1, 3, 5,..., 319) rows of capacitor lines 132 are transferred to the next even (2, 4, 6,..., 320) rows of scanning lines 112. Even if the scanning signal becomes H level, the voltage does not change, but the capacitor line 132 in the even-numbered row decreases by the voltage ΔV when the scanning signal to the next odd-numbered scanning line 112 becomes H level. Therefore, in the n frame of FIG. 9, the positive polarity writing similar to that in FIG. 7A is executed in the odd-numbered rows, while the negative polarity writing similar to that in FIG. 7B is executed in the even-numbered rows.
On the other hand, in the (n + 1) frame in FIG. 9, the odd-numbered capacitor lines 132 decrease by the voltage ΔV when the scanning signal to the next even-numbered scanning line 112 becomes H level, The voltage of the capacitor line 132 does not change even when the scanning signal to the next odd-numbered scanning line 112 becomes H level. Therefore, in the (n + 1) frame of FIG. 9, the negative polarity writing similar to FIG. 7B is executed in the odd-numbered rows, while the positive polarity writing similar to FIG. 7A is executed in the even-numbered rows. .
In FIG. 9, the second capacitance signal Vc2 is the voltage Vsl. However, the voltage Vsh may be used to increase the voltage of the capacitance line 132 by ΔV.

Further, when the scanning line inversion method is used in this way, the second capacitance signal Vc2 may be constant at the voltage LCcom as shown in FIG.
When the second capacitance signal Vc2 is constant at the voltage LCcom, in the n frame of FIG. 10, when the scanning signal to the next even-numbered scanning line 112 becomes H level, The voltage Vsl rises to the voltage LCcom, and the capacitance line 132 in the even-numbered row falls from the voltage Vsh to the voltage LCcom when the scanning signal to the next odd-numbered scanning line 112 becomes H level, while (n + 1) ) In the frame, the odd-numbered capacitive lines 132 drop from the voltage Vsh to the voltage LCcom when the scanning signal to the next even-numbered scanning line 112 becomes H level. When the scanning signal to the next odd-numbered scanning line 112 becomes H level, the voltage rises from the voltage Vsl to the voltage LCcom.
Here, when the amount of increase from the voltage Vsl to the voltage LCcom and the amount of change from the voltage LCcom to the voltage Vsl are equally ΔV, as shown in FIG. The operation of shifting the voltage written when the signal becomes H level by the voltage ΔVpix by changing the capacitance line 132 of the i-th row by the voltage ΔV when the scanning signal Y (i + 1) becomes the H level. The positive polarity writing and the negative polarity writing are alternately executed every one frame period.

If the voltage range when the negative polarity writing is designated matches the voltage range a when the positive polarity writing is designated, the data signal has the same effect as FIG. That is, as shown in FIG. 12, when the center of the voltage range a is set to coincide with the voltage LCcom in the n frame for positive polarity writing, and the voltage Vw (+) increases when the voltage ΔVpix increases. To the voltage Vb (+), and when the voltage ΔVpix falls, the voltage ΔV (= Vsh−LCcom = LCcom−) so as to shift to the range from the voltage Vw (−) to the voltage Vb (−). Vsl) may be set. However, in the voltage range a in FIG. 12, when positive polarity writing is specified, the white w side is low and the black b side is high, but when negative polarity writing is specified, the white w side is high and black b The side becomes low, and the relationship of gradation is reversed.
Note that even if the voltage range of the data signal when the positive polarity writing is designated and the voltage range of the data signal when the negative polarity writing is designated do not coincide with each other, the data changes due to the voltage change of the capacitor line 132. The voltage amplitude of the signal can be suppressed.

<Application example of the first embodiment>
In the i-th row of the capacitor line driving circuit 150, the period during which the TFTs 152, 154, and 156 are turned on is at most the horizontal scanning period (H), but the period during which the TFT 158 is turned on is the non-selection period (scanning signal in the i-th row). The period over which Yi is at the L level). For this reason, the TFT 158 is in an environment where the transistor characteristics are likely to change because the period during which the TFT 158 is in the on state is significantly longer than that of the TFTs 152, 154, and 156. Note that the change in transistor characteristics here means that the gate voltage (threshold voltage) for turning on as a switch increases with time. For this reason, the possibility of a malfunction that the TFT 158 does not turn on in the non-selection period increases as it is used for a long time.
Therefore, an application example for the purpose of suppressing the possibility of such a malfunction will be described.

FIG. 13 is a block diagram illustrating a configuration of an electro-optical device according to this application example.
As shown in this figure, in the application example, the TFT 158 is divided into two systems of TFTs 158a and 158b and is used alternately.
In detail, the capacitor line driving circuit 150 according to the application example is divided into a system and b system in each row. Of these, the system a has TFTs 152a, 154a and 158a, and the source electrode of the TFT 152a is supplied. The b system has TFTs 152b, 154b, and 158b connected to the electric wire 161a, and the source electrode of the TFT 152b is connected to the feeder line 161b.
In this application example, the control circuit 20 supplies the signal Von-a to the power supply line 161a and the signal Von-b to the power supply line 161b. As an example of the voltage waveforms of the signals Von-a and Von-b, as shown in FIG. 15, for example, in the n frame, the signal Von-a becomes the on voltage Von, the signal Von-b becomes the off voltage Voff, In the (n + 1) frame, the signal Von-a becomes the off voltage Voff, and the signal Von-b becomes the on voltage Von.

In this application example, the capacitor line 132 is connected to the second power supply line 167 after selection in the TFT 152a in the n frame where the signal Von-a becomes the on voltage Von, and the signal Von-b becomes the on voltage Von ( In the (n + 1) frame, the TFT 152b. For this reason, according to the application example, the period during which the TFTs 152a and 152b are turned on is halved compared to the first embodiment, so that the possibility of malfunction due to long-term use can be kept low.
In the application example, any of FIGS. 4, 8, 9, and 10 can be applied as the first capacitance signal Vc1, the second capacitance signal Vc2, and the polarity instruction signal Pol.

  FIG. 14 is a plan view showing a configuration near the boundary between the capacitive line driving circuit 150 and the display region 100 in the element substrate in the application example. As described above, the TFT 152, the TFT 154, and the TFT 158 are each composed of the TFT 152a. 152b, TFTs 154a and 154b, and TFTs 158a and 158b.

In this figure, the gate electrode of the TFT 154a in the i-th row is a portion branched in a T shape in the Y (downward) direction from the scanning line 112 in the i-th row, but the gate electrode of the TFT 154b in the i-th row is , A portion branched from the gate electrode of the TFT 156 in the i-th row.
In this application example, the voltages of the signals Von-a and Von-b are switched every frame period, but the present invention is not limited to this. Further, it is not necessary to periodically switch the voltages of the signals Von-a and Von-b. For example, a configuration may be adopted in which the voltage is switched each time the power is turned on (off).
Further, in this application example, the configuration in which the TFT 158 is divided into the two TFTs 158a and 158b is shown, but the configuration may be such that three or more are used while being switched in a predetermined order.
That is, the purpose of the application example is to shorten the period during which any one of the TFTs 158 is turned on (longen the period during which the TFTs 158 are turned off) to reduce the change in transistor characteristics. Of these, at least one or more may be off and one or more may be on.

Second Embodiment
Next, a second embodiment of the present invention will be described. FIG. 16 is a block diagram illustrating a configuration of an electro-optical device according to the second embodiment of the invention.
The configuration shown in this figure is different from that of the first embodiment (see FIG. 1) in that auxiliary capacitors 184 are provided corresponding to the capacitor lines 132 of 1 to 320 rows. Therefore, this point will be described. The auxiliary capacitor 184 corresponding to the i-th capacitor line 132 has one end connected to the gate electrode of the TFT 158 corresponding to the i-th capacitor line 132 and the other end connected to the i-th capacitor line 132. It is connected to the scanning line 112.

FIG. 17 is a plan view showing a configuration in the vicinity of the boundary between the capacitive line driving circuit 150 and the display region 100 in the element substrate in the second embodiment.
In this figure, the part different from the first embodiment (see FIG. 3) is that the scanning line 112 has a wide part facing in the Y (down) direction, and the third conductive layer is overlapped with the wide part. The patterned electrode portion of the metal layer is provided. Therefore, the auxiliary capacitor 184 has a configuration in which the gate insulating film is sandwiched between the wide portion of the scanning line 112 and the electrode portion patterned so as to overlap the wide portion.
This electrode portion is connected to the gate electrode of the TFT 158 via a contact hole.

When the auxiliary capacitor 184 is provided in this manner, the gate electrode of the TFT 158 can be held more stably, so that the deterioration of display quality can be further suppressed.
Note that the purpose of the auxiliary capacitor 184 is that in the i-th row, the gate electrode of the TFT 158 corresponding to the i-th capacitor line 132 is used even if the scanning signals Yi and Y (i + 1) are both at the L level. Since the state immediately before the TFT 158 is turned off is maintained without depending on the parasitic capacitance, the other end of the auxiliary capacitor 184 may be grounded to the potential Gnd, for example.

<Third Embodiment>
When the scanning line inversion method is used (see FIGS. 9 and 10), the first capacitance signal Vc1 needs to be switched between the voltages Vsl and Vsh every horizontal scanning period (H). For this reason, if a capacitance is parasitic on the first power supply line 165 that supplies the first capacitance signal Vc1, power is wasted due to this voltage switching. A third embodiment that eliminates this point will be described.

FIG. 18 is a block diagram illustrating a configuration of an electro-optical device according to the third embodiment of the invention. The difference between the configuration shown in this figure and the first embodiment (see FIG. 1) is that, first, the control circuit 20 outputs two types of first capacitance signals, and second, the capacitance lines In the drive circuit 150, the source electrode of the TFT 156 corresponding to the odd-numbered capacitance line 132 is connected to the power supply line that supplies one of the two types of first capacitance signals, while the TFT 156 corresponding to the even-numbered capacitance line 132. The source electrode is connected to a power supply line that supplies the other.
Since the others are the same, the description thereof will be omitted, and in the following, this difference will be mainly described.

Specifically, the control circuit 20 uses the first capacitance signals Vc1a and Vc1b instead of the first capacitance signal Vc1.
Are supplied to the first feeders 165a and 165b, respectively.
Here, as shown in FIG. 20, the first capacitance signal Vc1a is constant in voltage over each frame, is the voltage Vsl in the n frame, and switches to the voltage Vsh in the next (n + 1) frame. That is, in the first capacitance signal Vc1a, the voltages Vsl and Vsh are alternately switched every frame period.
On the other hand, the first capacitance signal Vc1b has a relationship in which the voltages Vsl and Vsh are interchanged with respect to the first capacitance signal Vc1a. That is, the first capacitance signal Vc1b becomes the voltage Vsh when the first capacitance signal Vc1a is the voltage Vsl in the n frame, and becomes the voltage Vsl when the first capacitance signal Vc1a is the voltage Vsh in the (n + 1) frame. The second capacitance signal Vc2 is constant at the voltage LCcom.
In the capacitor line driving circuit 150, the source electrode of the TFT 156 corresponding to the odd-numbered capacitor line 132 is connected to the first feeder line 165a, and the source electrode of the TFT 156 corresponding to the even-numbered capacitor line 132 is the first feeder line. 165b.

FIG. 19 is a plan view showing a configuration near the boundary between the capacitive line driving circuit 150 and the display region 100 in the element substrate in the third embodiment.
As shown in this figure, the second feed line 167 is positioned closer to the first feed line 165b in the odd-numbered i rows between the first feed lines 165a and 165b, and the first feed line in the even-numbered (i + 1) rows. Each line is folded so as to be positioned closer to the electric wire 165a.
The common semiconductor layers of the TFTs 156 and 158 cover the region from the second feed line 167 to the first feed line 165a with respect to the X direction in the odd-numbered i rows, and the number of the common semiconductor layers in the even-numbered (i + 1) rows with respect to the X direction. It is provided over a region from the first power supply line 165b to the second power supply line 167. For this reason, the TFTs 156 and 158 corresponding to the odd-numbered i-th row and the TFTs 156 and 158 corresponding to the even-numbered (i + 1) -th row are in opposite relations to each other.
In the third embodiment, i is an odd number and (i + 1) is an even number for convenience.

In the third embodiment, in the n frame, the capacitance line 132 corresponding to the odd-numbered row becomes the voltage Vsl of the first capacitance signal Vc1a when the scanning signal of the same row becomes H level, and the scanning signal of the next row is H. Since the voltage LCcom of the second capacitance signal Vc2 is reached when the level is reached, the voltage rises by the voltage (LCcom−Vsl), while the scanning signal of the same row is at the H level in the capacitance line 132 corresponding to the even-numbered row. The voltage Vsh of the first capacitance signal Vc1b at this time, and the voltage LCcom of the second capacitance signal Vc2 when the scanning signal of the next row becomes the H level, so that the voltage (Vsh−LCcom) drops.
On the other hand, in the next (n + 1) frame, the capacity line 132 in the odd-numbered row drops by the voltage (Vsh−LCcom) when the scanning signal in the next row becomes H level, and the capacity line 132 in the even-numbered row. Increases by a voltage (LCcom−Vsl) when the scanning signal of the next row becomes H level.
Therefore, in the third embodiment, since the voltage of the capacitor line 132 in each row changes in the same manner as in the examples shown in FIGS. 9 and 10, by supplying the data signal in the voltage range as shown in FIG. The voltage to the pixel can be written by the scanning line inversion method.
In particular, according to the third embodiment, two first capacitance signals Vc1a and Vc1b are required. The voltage switching between the two first capacitance signals Vc1a and Vc1b is not a horizontal scanning period (H) but a frame. Therefore, it is possible to suppress power that is wasted due to parasitic capacitance due to voltage switching.

In the above-described embodiment, the data line 114 is configured to supply a data signal having a voltage corresponding to the gradation of the pixel located on the selected scanning line. However, the present invention is not limited to this. For example, as shown in FIG. 21, the data signals X1, X2, X3,..., X240 having pulse widths corresponding to the gradations of the pixels located on the selected scanning line are displayed in the first, second, third,. The data line may be supplied to the data line.
In this configuration, as shown in FIG. 21, the data lines 11 in the 1, 2, 3,.
4 are provided corresponding to each of the four, and each switch 192 is turned on when the data signals X1, X2, X3,..., X240 are at the H level (a period in which a pulse is output). One end of each switch 192 is connected to the data line 114 corresponding to itself, and the other end is commonly connected to the common electrode 108.
Here, the data line driving circuit 190 generates a data signal having a pulse width (H level) corresponding to the gradation of the pixel located on the selected scanning line, and the start of the pulse is the scanning line selection start timing. Output as follows. For this reason, the data signal Xj has a pulse width (H level) so that the gradation of the pixels in the i-th row and j-th column should be brightened during the period when the i-th row scanning line 112 is selected. (In case of normally white mode).
Further, as shown in FIG. 22, the first capacitance signal Vc1 has a voltage LCcom at the scanning line selection start timing when the polarity instruction signal Pol is at the H level and the positive polarity writing is designated. When the polarity instruction signal Pol is at the L level and negative polarity writing is specified, the voltage LCcom is changed from the voltage LCcom to the selection end timing. Is supplied from the control circuit 20 as a ramp signal that rises to the voltage Vsh.

In the period when the i-th scanning line 112 is selected, the switch 192 corresponding to the j-th data line 114 changes the gradation of the pixels in the i-th row and j-th column from the selection start timing of the i-th scanning line. Turns on only for a period of time In this ON period, the data line 114 has the same voltage LCcom as that of the common electrode 108, so that the voltage is not charged in the pixel capacitor 120 in the i row and j column.
Since the ramp signal is supplied to the capacitor line 132 which is the other end of the storage capacitor 130 in the row j column, the storage capacitor 130 is charged with a differential voltage between the voltage of the ramp signal and the voltage LCcom.
When a period corresponding to the gray level of the pixel in the i-th row and j-th column elapses from the selection start timing of the scanning line in the i-th row, the pulse output of the data signal Xj ends and the switch 192 is turned off. Although the data line 114 is in a high impedance state that is not electrically connected anywhere, the voltage of the ramp signal continues to change, so the pixel electrode 118 that is a connection point of the pixel capacitor 120 and the storage capacitor 130 connected in series is The voltage change of the ramp signal follows from the time when the switch 192 is turned off.
Therefore, at the selection end timing of the i-th scanning line, the pixel capacitor 120 in the i-th row and j-th column is charged with a voltage that increases as the absolute value of the switch 192 increases.
When the next (i + 1) th scanning line selection start timing comes, the i-th capacitance line 132 becomes the voltage LCcom, so that the positive polarity writing is designated when the scanning signal Yi is at the H level. If the negative polarity writing is specified, the voltage (Vsh
-LCcom). Therefore, similarly to the example shown in FIG. 10, the voltage of the pixel electrode 118 is shifted, so that the holding voltage of the pixel capacitor 120 can be made a voltage corresponding to the gradation.

In each of the embodiments described above, in the capacitor line driving circuit 150, the gate electrode of the TFT 152 corresponding to the i-th capacitor line 132 is connected to the next (i + 1) -th scanning line 112. Any structure that connects to the scanning lines 112 separated by several m (m is an integer of 2 or more) is sufficient. However, when m increases, it is necessary to connect the gate electrode of the TFT 152 corresponding to the capacitance line 132 in the i-th row to the scanning line 112 in the (i + m) -th row, and the wiring becomes complicated.
Further, in order to drive up to the TFT 152 corresponding to the last 320th capacity line 132, m dummy scanning lines 112 are required. However, if m is “1” as in each embodiment, the blanking period Fb is eliminated and the gate electrode of the TFT 152 corresponding to the 320th capacitor line 132 is connected to the first scan line 112. For example, if m is “2”, the return period Fb is also eliminated, and the T corresponding to the capacitance line 132 in the 319th and 320th rows is also obtained.
If the gate electrode of the FT 152 is connected to the scanning lines 112 in the first and second rows, there is no need to provide a dummy scanning line.
Furthermore, the voltage Vcom of the common electrode 108 is set to a low level when the positive polarity writing is designated,
A configuration may be adopted in which high-order switching is performed when negative polarity writing is designated.

Further, in each embodiment, the liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108 as the pixel capacitor 120, and the electric field direction applied to the liquid crystal is set to be the direction perpendicular to the substrate surface. A common electrode may be stacked so that the direction of the electric field applied to the liquid crystal is the horizontal direction of the substrate surface.
On the other hand, in each embodiment, since the vertical scanning direction is a direction from the top to the bottom in FIG. 1, the gate electrode of the TFT 152 corresponding to the i-th capacitor line 132 is used as the (i + 1) -th scanning line. In the case where the vertical scanning direction is the direction from the bottom to the top, the connection may be made to the scanning line 112 in the (i-1) th row. That is, the gate electrode of the TFT 152 corresponding to the i-th capacitance line 132 is a scanning line other than the i-th scanning line, and is selected after the i-th scanning line is selected. Any configuration may be used as long as it is connected to.

Further, in each of the above-described embodiments, when the pixel capacitor 120 is taken as a unit, the writing polarity is reversed for each frame period, because the pixel capacitor 120 is only for AC driving. The inversion period may be a period of two frames or more.
Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed, and another color (for example, cyan (C)) may be used. In addition, one dot may be configured with these four color pixels to improve the color reproducibility.

In the above description, the reference of the writing polarity is the voltage LCcom applied to the common electrode 108. This is a case where the TFT 116 in the pixel 110 functions as an ideal switch. -Due to the parasitic capacitance between the drains, a phenomenon in which the potential of the drain (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, penetration, field-through, etc.) occurs. In order to prevent the deterioration of the liquid crystal, the pixel capacitor 120 must be AC driven. However, when AC driving is performed with the applied voltage LCcom applied to the common electrode 108 as a reference for the writing polarity, negative writing is performed for pushdown. The effective voltage value of the pixel capacitor 120 is slightly larger than the effective value of the positive polarity writing (when the TFT 116 is n-channel). For this reason, in actuality, the reference voltage of the write polarity and the voltage LCcom of the common electrode 108 are separated, and more specifically, the reference voltage of the write polarity is set to the voltage LCcom so that the influence of pushdown is offset. Alternatively, the offset may be set to a higher position.
Further, since the storage capacitor 130 is insulated in terms of direct current, it is sufficient that only the potential difference applied to the first feeder 165 and the second feeder 167 has the above-described relationship, for example, the voltage LCcom and The potential difference may be any number of volts.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 23 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to any of the embodiments.
As shown in this figure, a mobile phone 1200 includes the electro-optical device 10 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that the components of the electro-optical device 10 corresponding to the display region 100 do not appear as appearance.

As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 23, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. , Car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a configuration of a boundary between a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the negative polarity writing of the same electro-optical apparatus. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. It is a figure which shows the relationship between the data signal and holding voltage of the same electro-optical device. FIG. 6 is a diagram for explaining another operation (part 1) of the electro-optical device. FIG. 10 is a diagram for explaining another operation (part 2) of the same electro-optical device. FIG. 11 is a diagram for explaining another operation (part 3) of the same electro-optical device. It is a voltage waveform diagram for demonstrating another operation | movement (the 3). It is a figure which shows the relationship between the data signal and holding voltage in another operation | movement (the 3). It is a figure which shows the application example of the same electro-optical apparatus. It is a figure which shows the structure of the boundary of a display area and a capacitive line drive circuit in the application example. It is a figure which shows an example of the waveform of signals Von-a and Von-b in the same application example. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a diagram illustrating a configuration of a boundary between a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. FIG. 3 is a diagram illustrating a configuration of a boundary between a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the structure of the electro-optical apparatus which concerns on the modification of this invention. FIG. 10 is a diagram for explaining the operation of the electro-optical device according to the modification. It is a figure which shows the structure of the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 120 ... Pixel capacity, 130 ... Storage capacity, 132 DESCRIPTION OF SYMBOLS ... Capacitance line, 140 ... Scanning line drive circuit, 150 ... Capacitance line drive circuit, 156, 158 ... TFT, 161 ... On-voltage feed line, 163 ... Off-voltage feed line, 165, 165a, 165b ... First feed line, 167 ... second feeder, 184 ... auxiliary capacity, 1200 ... mobile phone

Claims (11)

Multiple rows of scanning lines;
Multiple columns of data lines;
A plurality of capacitance lines provided corresponding to the plurality of rows of scanning lines;
Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines,
Each is
A pixel switching element that has one end connected to a data line corresponding to itself and is turned on when a scanning line corresponding to the data line is selected;
A pixel capacitor interposed between the pixel switching element and the common electrode;
A storage capacitor interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line;
A pixel containing
A drive circuit for an electro-optical device having:
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A scanning line that is selected from the first feeding line when the scanning line is selected with respect to the capacitance line provided corresponding to the scanning line and is separated from the scanning line by a predetermined line. Capacitor lines that select the second power supply line until the one scan line is selected again after the scan line selected after the one scan line is selected, and apply the voltage of the selected power supply line, respectively. A drive circuit;
A data line driving circuit for supplying a data signal corresponding to the gradation of the pixel to the pixel corresponding to the selected scanning line via the data line;
Equipped with,
The capacitor line driving circuit includes:
Corresponding to each of the capacitance lines, there are first to fourth transistors,
In the first transistor corresponding to one capacitance line, the gate electrode is connected to a scanning line separated from the scanning line corresponding to the one capacitance line by a predetermined row, and the source electrode is turned on to turn on the fourth transistor. Connected to the on-voltage feeder that feeds the voltage,
The second transistor has a gate electrode connected to a scanning line corresponding to the one capacitor line, and a source electrode connected to an off-voltage power supply line that supplies an off-voltage for turning off the fourth transistor,
The third transistor has a gate electrode connected to a scanning line corresponding to the one capacitance line, a source electrode connected to the first power supply line,
The fourth transistor has a gate electrode commonly connected to the drain electrodes of the first and second transistors, and a source electrode connected to the second feeder.
A drive circuit for an electro-optical device, wherein drain electrodes of the third and fourth transistors are connected to the one capacitor line . A plurality of sets of the first, second and fourth transistors for one capacitance line;
A fourth transistor for connecting the one capacitive line to the second power supply line, the driving circuit for an electro-optical device according to claim 1 from the multiple sets, and switches in a predetermined order. Auxiliary capacitance corresponding to each of the capacitance lines,
The auxiliary capacitor corresponding to one capacitor line has one end connected to the gate electrode of the fourth transistor and the other end selected at least from the scan line corresponding to the one capacitor line. 2. The drive circuit for an electro-optical device according to claim 1 , wherein the drive circuit is maintained at a constant potential during a period from when the first scanning line is selected again. The drive circuit of the electro-optical device according to claim 3 , wherein the other end of the auxiliary capacitor corresponding to the one capacitance line is connected to a scanning line corresponding to the one capacitance line. The first feeder line is divided into an odd line and an even line,
The source electrode of the third transistor of the capacitor line corresponding to the odd row is connected to the first feeder line for the odd row, and the source electrode of the third transistor of the capacitor line corresponding to the even row is the first electrode for the even row. Connected to the feeder,
One of the two different voltages is applied to the first feed line corresponding to the odd-numbered row, the other of the two different voltages is applied to the first feed line corresponding to the even-numbered row, and the two different voltages The drive circuit of the electro-optical device according to claim 1 , wherein the two are replaced in a complementary manner with a predetermined period. The voltages of the first and second feeder lines are set so that the voltage of the one capacitor line changes when a scan line separated from the scan line corresponding to the one capacitor line by a predetermined row is selected. The drive circuit of the electro-optical device according to claim 1. As for the voltage of the first power supply line, two different voltages are switched at a predetermined cycle,
The drive circuit of the electro-optical device according to claim 6 , wherein the voltage of the second feeder line is constant. The drive circuit for the electro-optical device according to claim 7 , wherein the voltage of the second power supply line is an intermediate value of two voltages in the first power supply line. The drive circuit of the electro-optical device according to claim 6 , wherein the first and second feeder lines have two different voltages that are complementarily switched every time the scanning line is selected. Multiple rows of scanning lines;
Multiple columns of data lines;
A plurality of capacitance lines provided corresponding to the plurality of rows of scanning lines;
Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines,
Each is
A pixel switching element that has one end connected to a data line corresponding to itself and is turned on when a scanning line corresponding to the data line is selected;
A pixel capacitor interposed between the pixel switching element and the common electrode;
A storage capacitor interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line;
A pixel containing
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
A scanning line that is selected from the first feeding line when the scanning line is selected with respect to the capacitance line provided corresponding to the scanning line and is separated from the scanning line by a predetermined line. Capacitor lines that select the second power supply line until the one scan line is selected again after the scan line selected after the one scan line is selected, and apply the voltage of the selected power supply line, respectively. A drive circuit;
A data line driving circuit for supplying a data signal corresponding to the gradation of the pixel to the pixel corresponding to the selected scanning line via the data line;
Equipped with,
The capacitor line driving circuit includes:
Corresponding to each of the capacitance lines, there are first to fourth transistors,
In the first transistor corresponding to one capacitance line, the gate electrode is connected to a scanning line separated from the scanning line corresponding to the one capacitance line by a predetermined row, and the source electrode is turned on to turn on the fourth transistor. Connected to the on-voltage feeder that feeds the voltage,
The second transistor has a gate electrode connected to a scanning line corresponding to the one capacitor line, and a source electrode connected to an off-voltage power supply line that supplies an off-voltage for turning off the fourth transistor,
The third transistor has a gate electrode connected to a scanning line corresponding to the one capacitance line, a source electrode connected to the first power supply line,
The fourth transistor has a gate electrode commonly connected to the drain electrodes of the first and second transistors, and a source electrode connected to the second feeder.
An electro-optical device, wherein drain electrodes of the third and fourth transistors are connected to the one capacitor line . An electronic apparatus comprising the electro-optical device according to claim 10 .

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