JP4957169B2 - Electro-optical device, scanning line driving circuit, and electronic apparatus - Google Patents

Description

  The present invention relates to a technique for driving a scanning line using a demultiplexer.

  In an electro-optical device such as a liquid crystal, pixels are provided corresponding to intersections of a plurality of scanning lines and a plurality of columns of data lines. This pixel has a gradation corresponding to the voltage (or current) of the data line corresponding to itself when the scanning line corresponding to itself becomes an active level, and even if the scanning line becomes a non-active level. The gradation is maintained. Accordingly, the scanning lines of a plurality of rows are set to the active level in a predetermined order, and a voltage (or current) corresponding to the gradation is supplied to the pixels located on the scanning line having the active level through the data line. By doing so, the target image can be displayed.

Here, a circuit that sets the scanning lines of a plurality of rows to an active level in a predetermined order is called a scanning line driving circuit, and a shift register is generally used. With respect to such a scanning line driving circuit, the so-called peripheral circuit built-in type constituted by the same switching element as the pixel, rather than mounting an external integrated circuit, improves the manufacturing efficiency by sharing the process. It is advantageous in terms of the aspect.
By the way, the shift register has a complementary logic circuit (an inverter or a clocked inverter) in which a p-channel transistor and an n-channel transistor are combined. If not, inconveniences such as through current flow occur.
Therefore, the scanning lines are divided into a plurality of rows (for example, 3 rows), and a transistor (TFT) is provided as a switch for each scanning line, and these blocks are selected one by one by an address signal and selected. A so-called demultiplexer method has been proposed in which the switches of a plurality of rows of scanning lines in one block are turned on one by one in order by a select signal, and the scanning lines are sequentially brought to an active level (see, for example, Patent Document 1). .
Japanese Patent Laid-Open No. 2002-169518 (refer to FIG. 1 in particular)

However, in this technique, in order to turn on the transistor provided in the scanning line, a voltage higher than the threshold level of the transistor by the threshold level must be applied to the gate electrode. Therefore, in the above technique, since it is necessary to separately generate voltages higher than the active level, there arises a problem that a high withstand voltage of a power supply circuit that generates these voltages and a complicated configuration are caused.
The present invention has been made in view of the above-described circumstances, and an object thereof is to generate a voltage higher than the active level when driving a scanning line using a demultiplexer method. An object is to provide an electro-optical device, a scanning line driving circuit, and an electronic apparatus.

In order to achieve the above object, in the scanning line driving circuit according to the present invention, a plurality of scanning lines that are blocked every p (p is an integer of 2 or more) rows, a plurality of columns of data lines, , Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines, and according to the data signal supplied to the data lines when the logic level of the scanning lines becomes an active level. A scanning line driving circuit that selects the plurality of rows of scanning lines in a predetermined order and sets the selected scanning lines to an active level with respect to an electro-optical device having a pixel having a predetermined gradation. The scanning line driving circuit has a unit circuit corresponding to each of the plurality of scanning lines, and p unit circuits corresponding to the blocked p rows of scanning lines correspond to the p rows. Active during the period indicating each selection of scan lines A logic signal for level is supplied in common, each unit circuit includes first and second transistors, the first transistor is supplied with the logic signal to the source electrode, and the drain electrode is connected to itself. The second transistor is connected to a corresponding scanning line, and the second transistor becomes active at the gate electrode before and after the logic signal becomes an active level and when the logic signal is at a non-active level. Ri, when the logic signal changes from non-active level to an active level, the first control signal ing the non-active level from the active level is supplied to the source electrode, before the logic signal becomes active level , A second control signal having an active level is provided so as to overlap with the first control signal. In the electrode, characterized in that connected to the gate electrode of the first transistor. According to this configuration, the voltage of the gate electrode of the first transistor is self-generated using the active level and non-active, and therefore, when driving the scanning line, a voltage other than the active level and non-active is generated. It becomes possible to eliminate the necessity.

In the present invention, an auxiliary capacitor may be interposed between the gate electrode and the drain electrode of the second transistor . In the present invention, the second control signal may be commonly supplied to a plurality of the unit circuits provided corresponding to a plurality of scanning lines having different blocks .
The present invention can be conceptualized not only as a scanning line driving circuit but also as an electro-optical device driven by the scanning line driving circuit, and also as an electronic apparatus having the electro-optical device. Here, in the case of a concept as an electro-optical device, a switch is provided corresponding to each of the scanning lines of the plurality of rows, and one end of the switch is commonly grounded to the non-active level, and the other end of the switch May be connected to a scanning line corresponding to itself, and may be turned on all at once during a period in which none of the plurality of scanning lines is selected. According to this configuration, it is possible to shorten the state where the scanning lines are not electrically connected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram illustrating an overall configuration of an electro-optical device to which the scanning line driving circuit according to the first embodiment is applied.
As shown in this figure, the electro-optical device 1 is roughly divided into a display panel 10, a control circuit 20, a Y driver 30, and a data line driving circuit 50. Among them, in the display panel 10, although not particularly illustrated, the element substrate and the counter substrate are bonded together with a certain gap so that the electrode forming surfaces face each other, and for example, TN (twisted nematic) is put in this gap. ) Type liquid crystal.
On the element substrate of the display panel 10, the constituent elements of the unit circuit 40 are formed by a common process together with the pixel switching elements described later, and the Y driver 30 and the data line driving circuit 50, which are semiconductor chips, include COG technology and the like. It is implemented by. Various control signals are supplied from the control circuit 20 to the Y driver 30, the unit circuit 40, and the data line driving circuit 50 via an FPC (Flexible Printed Circuit) substrate or the like.

  The display panel 10 has a display area 100. In the present embodiment, 240 display lines 112 are provided in the display area 100 so as to extend in the row (X) direction, and 320 data lines 114 extend in the column (Y) direction. In addition, each scanning line 112 is provided so as to be electrically insulated from each other. In the present embodiment, 240 scanning lines 112 are divided into blocks every three rows. Therefore, the number of scanning line blocks is “80”.

The pixels 110 are arranged corresponding to the intersections of the 240 rows of scanning lines 112 and the 320 columns of data lines 114, respectively. Therefore, in the present embodiment, the pixels 110 are arranged in a matrix of 240 rows × 320 columns in the display area 100.
For convenience, in order to generalize and describe the rows (blocks) in the display area, if an integer m of 1 to 80 is used, the (3m-2) th row (3m-1) from the top in FIG. The scanning lines 112 in the) th and (3m) th lines belong to the mth scanning line block.

  Here, for convenience of description, the configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating a configuration of the pixel 110, and includes the (3m-2) th, (3m-1) th, and (3m) th scanning lines 112 belonging to the mth scanning line block. A configuration of a total of 6 pixels of 3 × 2 corresponding to the intersection of a column and a column adjacent to the column is shown.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116, a pixel capacitor (liquid crystal capacitor) 120, and a storage. And a capacitor 130. Each pixel 110 has the same configuration. Therefore, when focusing on one pixel, in the target pixel 110, the gate electrode of the TFT 116 is connected to the scanning line 112 corresponding to itself, while the source electrode is connected to the data line 114 corresponding to itself, The drain electrode is connected to the pixel electrode 118 that is one end of the pixel capacitor 120 and one end of the storage capacitor 130.
The other end of the pixel capacitor 120 is a common electrode 108. The common electrode 108 is common to all the pixels 110 as shown in FIG. 1, and is maintained at a constant voltage LCcom with respect to time in this embodiment.
On the other hand, the other end of the storage capacitor 130 is a capacitor line 132. Although not shown in FIG. 1, the capacitor line 132 is maintained at the same voltage LCcom as the common electrode 108, for example. Note that the capacitor line 132 may be configured to be maintained at a voltage other than the voltage LCcom.

  In the display region 100, a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, are bonded to each other with a certain gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in the gap. For this reason, the pixel capacitor 120 has a structure in which the liquid crystal 105 which is a kind of dielectric is sandwiched between the pixel electrode 118 and the common electrode 108 and holds a differential voltage between the pixel electrode 118 and the common electrode 108. ing. In this configuration, the amount of light transmitted through the pixel capacitor 120 changes according to the effective value of the holding voltage. In the present embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value is increased. Assume that it is a normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

  In FIG. 1, the Y driver 30 is an address signal (logic signal) for sequentially selecting three scanning lines belonging to the first, second, third,..., 80th scanning line blocks in accordance with control by the control circuit 20. Ad-1, Ad-2, Ad-3,..., Ad-80 are generated. Here, for convenience of explanation, an address signal supplied corresponding to the mth scanning line block is denoted as Ad-m.

In the present embodiment, the scanning line driving circuit is an aggregate of unit circuits 40 provided so as to correspond to the scanning lines 112 in the 1st to 240th rows on a one-to-one basis. The output terminal of each unit circuit 40 is connected to the scanning line 112 corresponding to itself. For this reason, the unit circuit 40 corresponding to the 1st, 2nd, 3rd,..., 240th rows sends the scanning signals G1, G2, G3,. Supply each.
Here, at the input ends of the three unit circuits 40 corresponding to the (3m-2) th, (3m-1) th and (3m) th scanning lines 112 belonging to the mth scanning line block, The address signal Ad-m output corresponding to the scanning line block is supplied in common. For example, the address signal Ad-80 is commonly supplied to the input ends of the three unit circuits 40 corresponding to the scanning lines 112 in the 238th, 239th, and 240th rows belonging to the 80th scanning line block. .

All the unit circuits 40 are commonly supplied with a clock signal (first control signal) Clk. On the other hand, different select signals (second control signals) are supplied to the three rows of unit circuits belonging to the m-th scanning line block. Specifically, the select signal Sel-1 is supplied to the unit circuit 40 corresponding to the (3m-2) th row, and the select signal Sel-2 is supplied to the unit circuit 40 corresponding to the (3m-1) th row (3m-2). ) A select signal Sel-3 is supplied to each unit circuit 40 corresponding to the row. In other words, in the case of one scanning line block, in the unit circuits of three rows, the selection signals Sel-1, Sel-2, and Sel-3 are supplied in order from the top. Here, when the select signals Sel-1, Sel-2, and Sel-3 are generally expressed using n, they are expressed as Sel-n. Note that n is one of 1, 2, and 3.
The select signals Sel-1, Sel-2, Sel-3 and the clock signal Clk are output from the control circuit 20, respectively.

Here, the address signal Ad-m, the select signal Sel-n, and the clock signal Clk will be described with reference to FIG.
As shown in this figure, the address signals Ad-1, Ad-2, Ad-3,..., Ad-80 are pulse trains in which three pulses each having a pulse width of H are continuous, and from the start of the pulse train. Outputs are made in order so as not to overlap each other.
The select signal Sel-1 is the address signal Ad immediately before the first shot is output in each pulse train of the address signals Ad-1, Ad-2, Ad-3,..., Ad-80. −1, Ad-2, Ad-3,..., Ad-80 are pulses that are output during a period in which all are at the L level. The select signal Sel-2 is a pulse output between the first shot and the second shot in each pulse train of the address signals Ad-1, Ad-2, Ad-3,..., Ad-80. . The select signal Sel-3 is a pulse output between the second shot and the third shot in each pulse train of the address signals Ad-1, Ad-2, Ad-3, ..., Ad-80. .
In the present embodiment, the falling edge of the select signal Sel-1 is generated so as to coincide with the rising edge of the first shot pulse in the address signals Ad-1, Ad-2, Ad-3,. The Similarly, the fall of the select signal Sel-2 and the rise of the second shot pulse in the address signals Ad-1, Ad-2, Ad-3,. The falling edge of the signal Sel-3 and the rising edge of the third shot pulse in the address signals Ad-1, Ad-2, Ad-3,.
The clock signal Clk is output at the timing when any one of the select signals Sel-1, Sel-2, and Sel-3 is output. That is, the clock signal Clk is a signal corresponding to the logical sum of the select signals Sel-1, Sel-2, and Sel-3.

The data line driving circuit 50 outputs data signals d1, d2, d3,..., D320 of voltages corresponding to the gradations of the pixels 110 located on the scanning line 112 that has become the active level of H level 1, 2, 3, ..., supplied to the data lines 114 in the 320th column.
Here, the data line driving circuit 50 has a storage area (not shown) corresponding to a matrix arrangement of 240 rows × 320 columns, and each storage area has a gradation value (pixel value) of the corresponding pixel 110. Display data Da for designating (brightness) is stored. The display data Da stored in each storage area is rewritten by the display circuit Da after the change together with the address by the control circuit 20 when the display contents are changed.
The data line driving circuit 50 reads the display data Da of the pixels 110 located on the scanning line 112 that is at the H level from the storage area, converts the data into a data signal having a voltage corresponding to the gradation value, and supplies the data signal to the data line 114. This operation is executed for each of the 1st to 320th columns positioned on the scanning line 112.

Note that the number of rows of the scanning line 112 that is at the H level and the timing at which the scanning line 112 is at the H level are controlled by the control circuit 20 to the Y driver 30 (addresses) as described later. , Ad-80) and control to the unit circuit 40 (select signals Sel-1, Sel-2, Sel-3).
For this reason, the data line driving circuit 50 receives the notification of the control contents from the control circuit 20, for example, which row of the display data Da should be read out, and at what timing the data signals d1, d2, d3,. , D320 should be output.
The voltage corresponding to the gradation value here has two types of positive polarity on the higher side than the voltage LCcom applied to the common electrode 108 and negative polarity on the lower side, and the data line For example, the drive circuit 50 switches alternately between positive polarity and negative polarity for each frame period for the same pixel. Note that the write polarity is based on the voltage LCcom, but unless otherwise specified, the voltage is based on the ground potential Gnd of the power source, the L level of the logic level is the ground potential Gnd, and the logic level H The level is set to voltage Vdd.

Next, the unit circuit 40 which is a characteristic part of the present invention will be described.
The unit circuits 40 corresponding to the scanning lines 112 in the 1st to 240th rows are structurally identical to each other, but the scanning line 112 corresponding to the address line and select signal supplied is the scanning line block. Depending on the number of rows in the scanning line block. Here, as described above, m indicates the number of the scanning line block, and n indicates the row of the three scanning lines belonging to each scanning line block. Therefore, the three lines belonging to the mth scanning line block. Among these scanning lines, the n-th scanning line 112 is the {3 (m−1) + n} row among the 1st to 240th rows in the display panel 10, and the unit circuit corresponding to this scanning line includes It can be expressed that the address signal Ad-m and the select signal Sel-n are supplied.

FIG. 3 is a diagram showing a configuration of the unit circuit 40 corresponding to the scanning line 112 in the {3 (m−1) + n} row.
As shown in this figure, the unit circuit 40 includes two TFTs 42 and 44. Among these, the source electrode of the TFT 42 (first transistor) is connected to the input terminal In to which the address signal Ad-m is supplied, and the drain electrode thereof is the scanning line 112 in the {3 (m−1) + n} row. Is connected to an output end Out which is one end of the.
A clock signal Clk is supplied to the gate electrode of the TFT 44 (second transistor), a select signal Sel-n is supplied to the source electrode, and its drain electrode is connected to the gate electrode of the TFT 42.
C1 is a capacitance parasitic between the source and gate electrodes in the TFT 42, and similarly, the capacitance C2 is a capacitance parasitic between the source and gate electrodes in the TFT 44. The auxiliary capacitor Ca is a capacitor inserted between the source and gate electrodes in the TFT 44. Therefore, the capacitors C2 and Ca are connected in parallel between the source and gate electrodes of the TFT 44. The TFTs 42 and 44 are formed by a common process with the TFT 116 in the pixel 110, and the auxiliary capacitance is configured by, for example, sandwiching a gate insulating film between the gate electrode of the TFT and the wiring layer.

  In the unit circuit 40 corresponding to the scanning line 112 in the {3 (m−1) + n} row, as shown in FIG. 5 (FIG. 4), the select signal Sel-n and the clock signal Clk are at the H level over the period S. Thereafter, both signals fall to the L level and the address signal Ad-m rises to the H level. When the period H elapses from this rise, the address signal Ad-m falls to the L level. If the state in which the select signal Sel-n is in the L level and the clock signal Clk is in the H level for the period S passes twice, the select signal Sel-n and the clock signal Clk are in the H level for the period S again.

When the select signal Sel-n and the clock signal Clk attain the H level in the output of the select signal Sel-n, the clock signal Clk, and the address signal Ad-m, scanning of the {3 (m−1) + n} row. In the unit circuit 40 corresponding to the line 112, the gate electrode of the TFT 44 has a voltage Vdd corresponding to the H level, so that the source and drain electrodes are in a conductive (ON) state.
On the other hand, since the address signal Ad-m is at the L level, the gate electrode Vg of the TFT 42 is charged by the voltage drop due to the ON resistance of the TFT 44 from the voltage Vdd at the H level of the select signal Sel-n while charging the capacitor C1. The voltage Va is decreased while increasing.
Since the TFT 42 is also turned on by this voltage Va, the output terminal Out becomes conductive with the input terminal In. Therefore, the L level of the address signal Ad-m becomes the scanning signal G [3 (m−1) + n] as it is.

Next, when the select signal Sel-n and the clock signal Clk fall to the L level while the address signal Ad-m rises to the H level, the source / drain electrodes of the TFT 44 become non-conductive (off). Therefore, the gate electrode of the TFT 42 is in a high impedance state which is not electrically connected to any part, but the input terminal In which is the other end of the capacitor C1 charged with the voltage Vdd is at the H level of the address signal Ad-m. Therefore, the gate electrode Vg of the TFT 42, which is one end of the capacitor C1, also rises to the voltage (Va + Vdd) obtained by adding the voltage Vdd to the voltage Va immediately before the voltage Vdd.
For this reason, since the TFT 42 is continuously turned on, the H level of the address signal Ad-m appears as it is as the scanning signal G [3 (m−1) + n].

  Subsequently, the address signal Ad-m falls to the L level. For this reason, since the input terminal In which is the other end of the capacitor C1 also falls to the L level, the gate electrode Vg of the TFT 42 returns to the voltage Va. Therefore, since the TFT 42 is still in the ON state, the L level of the address signal Ad-m appears as it is as the scanning signal G [3 (m−1) + n].

When the select signal Sel-n and the address signal Ad-m are at the L level and the clock signal Clk is at the H level, the TFT 44 is turned on. For this reason, since the gate electrode Vg becomes L level of the select signal Sel-n, the TFT 42 is turned off. As a result, the output terminal Out is in a high impedance state, but the scanning signal G [3 (m−1) + n] is indicated by a broken line in FIG. 5 due to various capacitances parasitic on the scanning line 112. It is maintained at the previous L level.
On the other hand, since the address signal Ad-m is also at the L level, both ends of the capacitor C1 are at the same level, whereby the charged voltage is reset to zero. Therefore, the level of the address signal Ad-m should not directly affect the on / off state of the TFT 42 of the unit circuit 40 corresponding to the {3 (m−1) + n} row. Will be described later).

By the way, after the three scanning lines 112 belonging to the mth scanning line block are sequentially set to the H level, the address signal Ad-m maintains the L level until the period F of one frame elapses. The select signal Sel-n becomes H level for each period U in order to sequentially select the three scanning lines 112 belonging to other scanning line blocks. Since the clock signal Clk has such a characteristic that it is the logical sum of the select signals Sel-1, Sel-2, and Sel-3, it becomes the H level together with any one of the select signals every period U / 3.
Here, when the address signal Ad-m is at the L level and the select signal Sel-n and the clock signal Clk are at the H level, the gate electrode of the TFT 42 is at the H level, so that the output terminal Out is at the address signal L level. To confirm. For this reason, since the output terminal Out is in a high impedance state and periodically refreshed to the L level in the period U, voltage changes due to noise and various parasitic capacitances are suppressed. .
When the address signal Ad-m is at the L level and the gate electrode Vg is at the H level and the TFT 42 is turned on, the voltage Va is charged to the capacitor C1 (TFT 42 is turned on). When only the clock signal Clk becomes H level, the charging voltage is reset to zero.

Here, in general, the unit circuit 40 corresponding to the {3 (m−1) + n} row has been described. However, since m is 1 to 80 and n is 1, 2, and 3, it is shown in FIG. In response to the address signals Ad-1, Ad-2, Ad-3,..., Ad-80, select signals Sel-1, Sel-2, Sel-3 are output as shown in FIG. Scan signals G1, G2, G3,..., G240 are extracted from the three pulse trains in the address signals corresponding to the scan signals G1, G2, G3,. It will be a thing.
Further, in the period corresponding to the L level of the scanning signal, the output terminal Out temporarily becomes a high impedance state, so that the voltage is likely to be uncertain. However, in this embodiment, the potential Gnd is changed to the L level for each period U. Since it is periodically refreshed, in practice, it is almost stable at the L level.
In FIG. 4, among the periods when the scanning signal is at the L level, the thin line indicates a period in which the thin line is held at the L level although it is unstable due to the parasitic capacitance of the scanning line because it is in a high impedance state. A thick line indicates a period in which the L level is established by refresh.

As described above, in the unit circuit 40 corresponding to the {3 (m−1) + n} row, the TFT 42 is turned on before the scanning line 112 of the row is set to the H level, thereby the L level address signal Ad−. When m is used as it is as the scanning signal G [G3 (m-1) + n], the voltage Va is charged in the capacitor C1, and then the address signal Ad-m is changed to the H level. Is added to the voltage Va to continuously turn on the TFT 42, and the H-level address signal Ad-m is output as the scanning signal G [G3 (m-1) + n].
For this reason, the gate voltage of the TFT 42 constituting the demultiplexer is self-generated using the logic levels of H and L, so that the ON voltage to be applied to the gate electrode of the TFT 42 when the scanning line is set to the H level. As a result, it becomes unnecessary to separately generate a voltage higher than the H level by the threshold voltage of the TFT. Therefore, when driving the scanning line, it is only necessary to generate the voltage Vdd corresponding to the H level in addition to the potential Gnd corresponding to the L level, so that it is not necessary to increase the breakdown voltage of the constituent elements of the power supply circuit. Thus, the configuration can be simplified.

Here, the reason why the auxiliary capacitance Ca is positively provided in addition to the parasitic capacitance C2 between the source and drain electrodes of the TFT 44 is as follows. That is, when the auxiliary capacitor Ca is not provided, when the select signal Sel-n is at the L level and the address signal Ad-m rises from the L level to the H level, the capacitors C1, C2, other capacitors, etc. As a result, the gate electrode voltage of the TFT 42 changes in the rising direction, which is the voltage change direction of the address signal Ad-m, and thus the off-resistance of the TFT 42 becomes so small that it cannot be ignored (half-on state). This is because there is a possibility of being lost. When the TFT 42 is in a half-on state, the scanning line that is the output end Out rises from the L level, and the off-leak of the TFT 116 in the pixel increases.
In order to prevent this half-on state, in the present embodiment, the clock signal Clk is set to fall at the rising timing of the address signal Ad-m, and the auxiliary capacitor Ca is parallelized in addition to the capacitor C2. The capacitance between the gate electrode and the drain electrode of the TFT 44 is increased, and the rise in the voltage of the gate electrode of the TFT 42 is canceled by the fall of the clock signal Clk via the increased capacitance.
The auxiliary capacitance Ca is preferably about 300 to 500 fF (Famto Farad), although it cannot be said unconditionally depending on various conditions.

The operation of the electro-optical device will be briefly described. At the beginning of a certain frame, the scanning signal G1 becomes H level. When the scanning signal G1 becomes H level, the data line driving circuit 50 reads out the display data Da of the pixels in the first row and the first, second, third,..., 320th column, and designates it by the read display data Da. The converted voltage is converted into a high or low voltage with reference to the voltage LCcom and supplied as data signals d1, d2, d3,..., D320 to the data lines 114 of 1, 2, 3,. .
On the other hand, when the scanning signal G1 becomes the H level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 320th column are turned on, so that the data signals d1, d2, d3,. Is done. For this reason, the differential voltage between the data signals d1 to d320 and the voltage LCcom is written into the pixel capacitor 120 in the first row and first column to the first row and 320 columns.
Immediately before the scanning signal G2 becomes H level, the scanning signal G1 becomes L level, thereby turning off the TFTs 116 in the pixels of the first row and the first column to the first row and the 320th column, but the voltage written in the pixel capacitor 120 is The pixel capacitors 120 in the 1st row and 1st column to the 1st row and 320th column maintain the gradation corresponding to the written voltage because they are held in the storage capacitor 130 connected in parallel with the capacity.

Next, the scanning signal G2 becomes H level. When the scanning signal G2 becomes H level, the data line driving circuit 50 reads the display data Da of the pixels in the second row and the columns 1, 2, 3,. The converted voltage is converted into a high or low voltage with reference to the voltage LCcom and supplied as data signals d1, d2, d3,..., D320 to the data lines 114 of 1, 2, 3,. .
On the other hand, when the scanning signal G2 becomes the H level, the TFTs 116 in the pixels of the 2nd row and the 1st column to the 2nd row and the 320th column are turned on, so that the data signals d1, d2, d3,. Is done. For this reason, the differential voltage between the data signals d1 to d320 and the voltage LCcom is written into the pixel capacitor 120 in the 2nd row and the 1st column to the 2nd row and the 320th column.

Similarly, the writing of the voltage via the data signal is repeated until the scanning signals G3, G4,..., G240 become the H level, whereby the voltage corresponding to the gradation value is applied to all the pixels. Written. In the next frame, the voltage writing is executed in the same manner with the writing polarity reversed. That is, when attention is paid to a certain pixel, if the voltage corresponding to the gradation value is higher or lower than the voltage LCcom in a certain frame, it is higher or lower than the voltage LCcom in the next frame. The other lower polarity is assumed. By such polarity reversal, application of a direct current component to the liquid crystal 105 is avoided, and deterioration is prevented.
FIG. 6 is a diagram illustrating the voltage of the pixel electrode 118 in a certain column in the {3 (m−1) + n} row in relation to the scanning signal G [3 (m−1) + n]. In this figure, when the scanning signal G [3 (m−1) + n] becomes H level, the voltage LCcom is higher or lower than the voltage LCcom by the amount corresponding to the gradation value for the pixel (in the figure). A data signal (shown by ↑ or ↓) is supplied to the data line 114 in the column and written to the pixel electrode 118. In the scanning signal G [3 (m−1) + n], the L level is assumed to be stabilized.

Second Embodiment
Next, a scanning line driving circuit according to a second embodiment of the present invention will be described. FIG. 7 is a diagram illustrating an overall configuration of an electro-optical device to which the scanning line driving circuit is applied.
As shown in FIG. 7, in the second embodiment, the signals supplied to the unit circuits 40 constituting the scanning line driving circuit are the select signals Sel-1, Sel-2 in the first embodiment (see FIG. 1). , Sel-3 and the clock signal Clk are interchanged. Each unit circuit 40 is structurally the same as in FIG. 3, but corresponds to the nth row among the three scanning lines belonging to the mth scanning line block, as shown in parentheses in FIG. In the unit circuit 40, the select signal Sel-n as the first control signal is supplied to the gate electrode of the TFT 44, and the clock signal Clk as the second control signal is supplied to the source electrode of the TFT 44.

FIG. 8 shows waveforms of the address signal Ad-m, the select signal Sel-n, and the clock signal Clk according to the second embodiment. As shown in this figure and FIG. 9, the address signals Ad-1 to Ad-80 are the same as those in the first embodiment.
However, the select signals Sel-1, Sel-2, and Sel-3 are different from the first embodiment. That is, as shown in FIG. 8, the first shot of the select signal Sel-1 is output in each of the pulse trains of the address signals Ad-1, Ad-2, Ad-3,. , Ad-80 includes the first pulse that is output during a period in which all of the address signals Ad-1, Ad-2, Ad-3,..., Ad-80 are at the L level. Although common, in the second embodiment, after the first shot of the address signal is output until the next second shot is output, the address signal and the clock signal Clk are at the L level. The second pulse output during a certain period is included.
Similarly, the select signal Sel-2 is from the output of the second shot of the address signal to the output of the next third shot in addition to the pulses of the first embodiment. The select signal Sel-3 includes the second pulse output during a period in which the signal Clk is at the L level, and the select signal Sel-3 includes the next address after the third shot in the address signal is output in addition to the pulse of the first embodiment. This includes a second pulse that is output until the first shot of the signal is output and the address signal and the clock signal Clk are at the L level.
For this reason, in the second embodiment, the clock signal Clk is the same as in the first embodiment, but is not the logical sum of the select signals Sel-1, Sel-2, and Sel-3.

Also in the second embodiment, in the unit circuit 40 corresponding to the {3 (m−1) + n} row, as shown in FIG. 9, before the scanning line 112 of the row is set to the H level, the select signal When Sel-n and the clock signal Clk become H level, the L-level address signal Ad-m is used as it is as the scanning signal G [G3 (m-1) + n], and the capacitor Va is charged with the voltage Va. Thereafter, when the address signal Ad-m is changed to the H level, the TFT 42 is continuously turned on by adding the change amount to the gate voltage of the TFT 42 to the voltage Va, so that the address signal Ad-m of the H level is supplied. The scanning signal G [G3 (m−1) + n] is output. Thereafter, when the address signal Ad-m becomes L level, the voltage Va is reset to zero by the second pulse of the select signal Sel-n, and the L level is maintained as the scanning signal G [G3 (m−1) + n]. It has a configuration.
Accordingly, also in the second embodiment, as in the first embodiment, the gate voltage of the TFT 42 is self-generated using the logic levels H and L, so that the breakdown voltage of the constituent elements of the power supply circuit is increased. This eliminates the necessity and simplifies the configuration.

By the way, in the first and second embodiments described above, after each scanning line 112 changes from H to L level, the scanning line 112 is periodically set to L level every period U (a period during which scanning lines for three rows are at H level). Although refreshing is performed periodically, the shorter the refresh cycle, the better.
For this reason, for example, as shown in FIG. 10, each scanning line 112 may be provided with a TFT 140 (switch). Here, the source electrode of each TFT 140 is commonly grounded to the potential Gnd which is L level, the drain electrode is connected to the scanning line 112, and the signal Set is commonly supplied to the gate electrode. For this reason, when the signal Set becomes H level, all the scanning lines 112 are fixed at L level.
Here, the signal Set is a period in which any one of the address signals Ad-1, Ad-2, Ad-3,..., Ad-80 is not at the H level, that is, a period in which all the address signals are at the L level. Any signal can be used as long as it is at the H level, and for example, the clock signal Clk described above can be used as it is.

According to such a configuration, as shown in FIG. 11, each scanning line 112 has an interval for determining the L level to be short, so that a voltage unstable state due to a long continuous high impedance state is reduced. At the same time, L level homogenization between the scanning lines 112 is achieved.
If the voltage between the scanning lines 112 is different due to voltage fluctuation in the high impedance state, the influence of the off-leak of the TFT 116 in the pixel is different for each row and appears as uneven display in the row direction. Therefore, as compared with FIG. 4 and the case, since the L-level determination cycle is short and common to all the scanning lines 112, display unevenness hardly occurs.

  In the embodiment, the number p of scanning lines constituting the scanning line block has been described as “3”, but may be “2” or an integer greater than or equal to “4”. In the embodiment, since the TFT 116 is an n-channel type, the active level is an H level and the non-active level is an L level. However, when the TFT 116 is a p-channel type, the active level is an L level. The non-active level becomes H level. When the TFT 116 is a p-channel type, it may be negative logic, so that the configuration thereof will not be required.

In each of the above-described embodiments, when the pixel capacitor 120 is taken as a unit, the writing polarity is inverted every frame period, because the pixel capacitor 120 is only for AC driving. The inversion may be performed every period of two frames or more.
Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed, and another color (for example, cyan (C)) may be used. In addition, one dot may be configured with these four color pixels to improve the color reproducibility.

In the above description, the reference of the writing polarity is the voltage of the common electrode 108. This is a case where the TFT 116 in the pixel 110 functions as an ideal switch. Due to the parasitic capacitance, a phenomenon in which the potential of the drain electrode (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, punch-through, or field-through) occurs. In order to prevent the deterioration of the liquid crystal, the pixel capacitor 120 must be AC driven. However, when AC driving is performed using the voltage applied to the common electrode 108 as a reference for the writing polarity, negative writing is used for pushdown. The effective voltage value of the pixel capacitor 120 is slightly larger than the effective value by the positive polarity writing (in the case where the TFT 116 is an n-channel). Therefore, in practice, the reference voltage of the write polarity is divided from the voltage of the common electrode 108. Specifically, the reference voltage of the write polarity is changed to the voltage of the common electrode so that the influence of pushdown is offset. Alternatively, the offset may be set to a higher position.
Furthermore, the other end of the storage capacitor 130 is not constant, and may be configured such that it is switched to the lower side during positive polarity writing, then switched to the higher level, switched to the higher level during polarity writing, and then switched to the lower side.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 1 according to the above-described embodiment as a display device will be described. FIG. 12 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 1 according to the embodiment.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 1 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that components of the electro-optical device 1 other than the portion corresponding to the display region 100 do not appear as an appearance.

  As an electronic apparatus to which the electro-optical device 1 is applied, in addition to the mobile phone shown in FIG. 12, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder type (or monitor direct view type) video recorder. , Car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices.

1 is a diagram illustrating an electro-optical device using a scanning line driving circuit according to a first embodiment. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the unit circuit in the scanning line drive circuit. It is a figure which shows operation | movement of the scanning line drive circuit. It is a figure for demonstrating operation | movement of the unit circuit. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the electro-optical apparatus using the scanning line drive circuit which concerns on 2nd Embodiment. It is a figure which shows operation | movement of the scanning line drive circuit. It is a figure for demonstrating operation | movement of the unit circuit. It is a figure which shows the application example of the same electro-optical apparatus. It is a figure for demonstrating operation | movement of the scanning-line drive circuit which concerns on the same application example. It is a figure which shows the structure of the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Display panel, 20 ... Control circuit, 30 ... Y driver, 40 ... Unit circuit, 42, 44 ... TFT, 50 ... Data line drive circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scanning line, 114 ... Data line, 116 ... TFT, 120 ... Pixel capacity, 140 ... TFT, 1200 ... Mobile phone

Claims (6)

a plurality of scanning lines blocked for each p (p is an integer of 2 or more) rows;
Multiple columns of data lines;
Provided corresponding to the intersections of the plurality of rows of scanning lines and the plurality of columns of data lines, and according to the data signal supplied to the data lines when the logic level of the scanning lines becomes an active level. A pixel for gradation,
For an electro-optical device having
A scanning line driving circuit that selects the plurality of scanning lines in a predetermined order and sets the selected scanning lines to an active level;
The scanning line driving circuit has a unit circuit corresponding to each of the scanning lines of the plurality of rows,
The p unit circuits corresponding to the blocked p rows of scanning lines are commonly supplied with a logic signal that becomes an active level in a period indicating selection of the scanning lines corresponding to the p rows,
Each of the unit circuits includes first and second transistors,
The first transistor includes:
The logic signal is supplied to the source electrode, the drain electrode is connected to the scanning line corresponding to itself,
The second transistor is
A gate electrode, a back and forth the logic signal becomes active level and, when the logical signal is non-active level, becomes active level, the active level the logic signal from the non-active level when changing the first control signal ing from the active level to the non-active level is supplied,
Before the logic signal becomes active level, the source electrode is supplied with a second control signal that becomes active level so as to overlap with the first control signal,
A drain electrode is connected to a gate electrode of the first transistor. A scanning line driving circuit, wherein: The scanning line driving circuit according to claim 1, wherein an auxiliary capacitor is interposed between the gate electrode and the drain electrode of the second transistor. 2. The scanning line driving circuit according to claim 1 , wherein the second control signal is commonly supplied to a plurality of the unit circuits provided corresponding to a plurality of scanning lines having different blocks . a plurality of scanning lines blocked for each p (p is an integer of 2 or more) rows;
Multiple columns of data lines;
Provided corresponding to the intersections of the plurality of rows of scanning lines and the plurality of columns of data lines, and according to the data signal supplied to the data lines when the logic level of the scanning lines becomes an active level. A pixel for gradation,
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and setting the selected scanning lines to an active level;
A data line driving circuit for supplying a data signal corresponding to a gradation of a pixel corresponding to the scanning line having the active level through the data line;
Comprising
The scanning line driving circuit includes:
A unit circuit corresponding to each of the plurality of rows of scanning lines;
The p unit circuits corresponding to the blocked p rows of scanning lines are commonly supplied with a logic signal that becomes an active level during a period indicating the selection of the scanning lines corresponding to the p rows.
Each of the unit circuits includes first and second transistors,
The first transistor includes:
The logic signal is supplied to the source electrode,
The drain electrode is connected to the scanning line corresponding to itself,
The second transistor is
A gate electrode, a back and forth the logic signal becomes active level and, when the logical signal is non-active level, becomes active level, the active level the logic signal from the non-active level when changing the first control signal ing from the active level to the non-active level is supplied,
Before the logic signal becomes active level, the source electrode is supplied with a second control signal that becomes active level so as to overlap with the first control signal,
An electro-optical device, wherein a drain electrode is connected to a gate electrode of the first transistor. A switch is provided corresponding to each of the plurality of rows of scanning lines,
One end of the switch is commonly grounded to the non-active level,
The other end of the switch is connected to a scanning line corresponding to itself,
The electro-optical device according to claim 4, wherein the electro-optical device is turned on all at once in a period in which none of the plurality of scanning lines is selected. An electronic apparatus comprising the electro-optical device according to claim 4.

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