JP4349446B2 - Electro-optical device, drive circuit, and electronic device - Google Patents

Description

  The present invention relates to a technique for suppressing display unevenness in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. In order to suppress the voltage amplitude of the data line when the pixel capacitor is AC driven, The electrodes are individualized for each scanning line (for each row), and when a selection voltage is applied to the scanning line, a common electrode corresponding to the scanning line is connected to a power supply line having a voltage corresponding to the writing polarity. There is known a technique of connecting via a cable (see Patent Document 1).
See Japanese Patent Application Laid-Open No. 2005-3000948

However, in this technique, since the transistor is turned off in a non-selection period in which the selection voltage is not applied to the scanning line, the common electrode enters a voltage indeterminate state (high impedance state) in which the common electrode is not electrically connected. For this reason, the common electrode is subject to a change in the voltage of the data line and the influence of noise through the parasitic capacitance, and therefore the voltage is likely to fluctuate. When the voltage of the common electrode fluctuates, the effect appears for each row, causing stripe-like display unevenness in the horizontal direction, resulting in a problem that the display quality is remarkably lowered.
The present invention has been made in view of such circumstances, and one of its purposes is an electro-optical device, a driving circuit, and a driving circuit capable of suppressing the occurrence of display unevenness in a configuration in which common electrodes are individually driven. To provide electronic equipment.

  In order to achieve the above object, a drive circuit for an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, a plurality of common electrodes provided on each of the plurality of scanning lines, A pixel switching element provided corresponding to the intersection of the scanning line and the data line, each of which is connected to the data line and is turned on when a selection voltage is applied to the scanning line; A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode, and a pixel having a gradation according to a holding voltage of the pixel capacitor, A driving circuit for the electro-optical device, the scanning line driving circuit for applying the selection voltage to the plurality of scanning lines in a predetermined order; the common electrode driving circuit for individually driving the plurality of common electrodes; A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation of the pixel to a pixel corresponding to the scanning line to which the selection voltage is applied via the data line, and the common electrode The drive circuit is set to the on or off state for each common electrode according to the voltage held in the gate electrode, and when set to the on state, either the low side voltage or the high side voltage is set. When the selection voltage is applied to a scanning circuit that makes a pair with the common electrode and a scanning line that is paired with the common electrode, an ON voltage that sets the switching circuit to an ON state is applied to the gate electrode of the switching circuit. When there is an instruction through a predetermined control line after the application of the selection voltage to the first application circuit and the scanning line is completed, the lower level is applied to each of the common electrodes. Or and having a second application circuit for applying one of the voltage of the high-side again, the. According to the present invention, even after the application of the selection voltage to the scanning line is completed, the switch circuit sets the common electrode in a voltage-determined state, thereby preventing the common electrode from fluctuating in potential.

  In the present invention, the first application circuit has first and second transistors, the switch circuit has third and fourth transistors, and the second application circuit has fifth transistors, In the first transistor, a gate electrode is connected to the scanning line, a source electrode is connected to a first power supply line to which a voltage for turning the third transistor on or off is supplied, and the second transistor In the third transistor, the gate electrode is connected to the scanning line, the source electrode is connected to a second feeding line to which a voltage for turning the fourth transistor on or off is supplied, Is connected to the drain electrode of the first transistor, and the source electrode is connected to a third feeder line to which one of the low-side and high-side voltages is fed. In the fourth transistor, the gate electrode is connected to the drain electrode of the second transistor, the source electrode is connected to the fourth power supply line to which the other voltage on the lower side or the higher side is supplied, and the third transistor And the drain electrodes of the fourth transistor are connected to the common electrode, and in the fifth transistor, the gate electrode is connected to the control line, and the source electrode is supplied with a voltage on either the lower side or the higher side. The drain electrode may be connected to the signal electrode and the drain electrode may be connected to the common electrode. According to this configuration, the constituent elements of the common electrode driving circuit can be formed in the same manner as the pixel switching elements.

  Here, in the above configuration, the source electrode of the fifth transistor may be connected to a common signal line in each row of the scanning line and the common electrode. In addition, the first mode in which effective display is performed using all the pixels and the second mode in which effective display is performed using only pixels corresponding to a part of the scanning lines. The scanning line driving circuit performs an operation of sequentially applying the selection voltage to the plurality of scanning lines in a predetermined cycle, and the first power supply line includes the third transistor in an on state and an off state. Each time a selection voltage is applied to the scanning line, the voltage to be inverted is supplied in an inverted manner, and one of the low-side and high-side voltages is supplied to the third power supply line over a period of at least one frame. The control line is supplied with a voltage for turning off the fifth transistor. In the second mode, the scanning line driving circuit applies the selection voltage to the plurality of scanning lines in order. 1 movement And a second operation of sequentially applying the selection voltage to the partial scanning lines in a cycle longer than the predetermined cycle, and the first feeder line includes the first operation. Sometimes, one of a voltage for turning on the third transistor or a voltage for turning off the third transistor is applied, and the other of the voltage for turning on or off the third transistor during the second operation is The selection voltage is applied to a part of the scanning lines over a period of time, and the low voltage side or the high voltage side is supplied to the third feeder line for a period of at least one frame, and the control is performed. The line is supplied with a voltage that turns on the fifth transistor for a part or all of the period from the end of the first operation to the start of the second operation. Configuration voltage for the fifth transistor turned off over the course is supplied is preferable. According to this configuration, when attention is paid to one column of pixels in the first mode, the writing polarity is inverted for each row, so that the display quality is improved. In the present invention, odd numbers and even numbers are merely relative concepts for specifying alternately arranged rows.

Of the scanning lines and common electrodes, the source electrode of the fifth transistor in the odd-numbered row is connected to the first signal line to which one of the low-side and high-side voltages is fed, and the fifth row in the even-numbered row. The source electrode of the transistor may be connected to a second signal line to which the other voltage on the lower side or the higher side is supplied. In addition, the first mode in which effective display is performed using all the pixels and the second mode in which effective display is performed using only pixels corresponding to a part of the scanning lines. The scanning line driving circuit performs an operation of sequentially applying the selection voltage to the plurality of scanning lines in a predetermined cycle, and the first power supply line includes the third transistor in an on state and an off state. Each time a selection voltage is applied to the scanning line, the voltage to be inverted is supplied in an inverted manner, and one of the low-side and high-side voltages is supplied to the third power supply line over a period of at least one frame. The control line is supplied with a voltage for turning off the fifth transistor. In the second mode, the scanning line driving circuit applies the selection voltage to the plurality of scanning lines in order. 1 movement And a second operation of sequentially applying the selection voltage to the partial scanning lines in a cycle longer than the predetermined cycle, and the first feeder line includes the first and first In the second operation, a voltage for turning on and off the third transistor is supplied by being inverted every time a selection voltage is applied to the scanning line. One of the high-side voltages is supplied for a period of at least one frame, and the control line is supplied with the first voltage over a part or all of the period from the end of the first operation to the start of the second operation. It is preferable that a voltage for turning on the fifth transistor is supplied, and a voltage for turning off the fifth transistor is supplied over the other period. According to this configuration, even in the second mode, when attention is paid to one column of pixels that perform effective display, the writing polarity is inverted for each row as in the first mode, so that the display quality is further improved.
The present invention can be conceptualized not only as a drive circuit for an electro-optical device but also as an electro-optical device. Furthermore, the present invention can be conceptualized not only as an electro-optical device but also as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, the electro-optical device 10 has a display area 100, and a scanning line driving circuit 140, common electrode driving circuits 170 a and 170 b, and a data line driving circuit 190 are arranged around the display area 100. The peripheral circuit built-in panel configuration. The control circuit 20 is connected to the peripheral circuit built-in panel by, for example, an FPC (flexible printed circuit) substrate.

The display area 100 is an area where the pixels 110 are arranged. In the present embodiment, the display lines 100 are arranged so that the scanning lines 112 from the first line to the 320th line extend in the row (X) direction, and 240 columns of data. Each of the lines 114 is provided so as to extend in the column (Y) direction. The pixels 110 are arranged corresponding to the intersections between the scanning lines 112 in the first to 320th rows and the data lines 114 in the first to 240th columns. Accordingly, in the present embodiment, the pixels 110 are arranged in a matrix of 320 rows × 240 columns in the display area 100, but the present invention is not limited to this arrangement.
In the present embodiment, the common electrode 108 is provided extending in the X direction for each of the scanning lines 112 in the first to 320th rows. For this reason, the common electrode 108 is provided corresponding to each scanning line 112 in the first to 320th rows.

Here, a detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating the configuration of the pixel 110, and corresponds to the intersection of the i row and the (i + 1) row adjacent thereto in the downward direction and the j column and the (j + 1) column adjacent thereto in the right direction. A configuration of a total of 4 pixels of 2 × 2 is shown.
I and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and i is an odd number of 1, 3, 5,..., 319, and (i + 1) Is an even number consecutive to i and is any one of 2, 4, 6,. J and (j + 1) are symbols for generally indicating the column in which the pixels 110 are arranged, and j is an odd number of 1, 3, 5,..., 239, and (j + 1) Is an even number consecutive to j and is any one of 2, 4, 6,.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel switching element, a liquid crystal capacitor (pixel capacitor) 120, And a storage capacitor 130. Since each pixel 110 has the same configuration in this embodiment, a description will be given by representatively assuming that it is located in i row and j column. In the pixel 110 in i row and j column, the gate electrode of the TFT 116 scans the i row. While being connected to the line 112, its source electrode is connected to the data line 114 in the j-th column, and its drain electrode is connected to the pixel electrode 118 as one end of the liquid crystal capacitor 120 and one end of the storage capacitor 130. Yes. The other end of the liquid crystal capacitor 120 and the other end of the storage capacitor 130 are connected to the common electrode 108, respectively.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the i and (i + 1) th scanning lines 112, respectively, and Ci and C (i + 1) indicate i and (i + 1), respectively. ) The voltage of the common electrode 108 in the row is shown. The optical characteristics of the liquid crystal capacitor 120 will be described later.

Returning to FIG. 1 again, the control circuit 20 outputs various control signals to control each part in the electro-optical device 10. Various control signals will be described later as appropriate.
In addition, the electro-optical device 10 includes a full-screen mode (first mode) in which an image is displayed using all of the pixels 110 arranged in 320 vertical rows × 240 horizontal rows, and a part of the scanning lines in the arrangement. The operation is performed in two modes, that is, a partial mode (second mode) in which an effective image is displayed using only the pixels 110 corresponding to, and the other pixels are disabled by being displayed off. In the following description, the partial mode is treated as an exception, and the full screen mode is described as a rule.

As described above, peripheral circuits such as the scanning line driving circuit 140, the common electrode driving circuits 170a and 170b, and the data line driving circuit 190 are provided around the display region 100.
Among these, the scanning line driving circuit 140 applies the scanning signals Y1, Y2, Y3,..., Y320 to the scanning lines in the first, second, third,. 112 is supplied. More specifically, as shown in FIG. 5, the scanning line driving circuit 140 counts the scanning lines 112 row by row from the top in FIG. The scanning signals to the selected scanning lines are selected in order, the selection voltage Vdd corresponding to the H level is set, and the scanning signals to the other scanning lines are set to the non-selection voltage (ground potential Gnd) corresponding to the L level. To do.

Here, the scanning line driving circuit 140, for example, sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly, etc., to thereby generate the scanning signals Y1, Y2, Y3, Y4,. The H level is set in this order. In FIG. 5, the timing at which the scanning signal to a certain scanning line changes from H to L level is substantially the same as the timing at which the scanning signal to the next scanning line changes from L to H level. However, the period during which the signal is at the H level may be narrowed.
In this embodiment, one frame means a period required to display one image in the full screen mode, which is 16.7 milliseconds. As shown in FIG. 5, the scanning signal Y1 is at the H level. In addition to the effective scanning period Fa from when the scanning signal Y320 becomes L level, other blanking periods are included. It is not necessary to provide a return period. A period during which one row of scanning lines 112 is selected is a horizontal scanning period (H).
Here, in the partial mode, since one image may not be displayed in one frame as will be described later, a period of 16.7 milliseconds may be set for convenience.
On the other hand, if the scanning line driving circuit 140 is in the partial mode, for example, as shown in FIGS. 8 to 10 to be described later, all or some of the waveforms of the scanning signals Y1 to Y320 in the full screen mode are displayed in some frames. A scanning signal that is at H level for only a part is output.

The common electrode drive circuits 170a and 170b drive the common electrodes 108 in the first to 320th rows, and are divided into 170a and 170b for convenience.
Among these, the common electrode driving circuit 170a is provided between the scanning line driving circuit 140 and the display region 100 in the present embodiment, and is an n-channel type provided corresponding to the common electrode 108 in the first to 320th rows. It is comprised from the group of TFT171-174.
Since the connections of the TFTs 171 to 174 are common across the rows, the gate electrode of the TFT 171 (first transistor) in the i-th row is connected to the scanning line 112 in the i-th row. The drain electrode is connected to the first power supply line 161 and the gate electrode of the TFT 173 is connected. The gate electrode of the same i-th row TFT 172 (second transistor) is connected to the i-th row scanning line 112, its source electrode is connected to the second power feed line 162, and its drain electrode is connected to the gate electrode of the TFT 174. ing.
The source electrode of the i-th TFT 173 (third transistor) is connected to the third power supply line 163, and the source electrode of the same i-th TFT 174 (fourth transistor) is connected to the fourth power supply line 164. The drain electrodes of the TFTs 173 and 174 are connected to the i-th common electrode 108.

  The common electrode driving circuit 170b is provided on the side opposite to the common electrode driving circuit 170a with respect to the display region 100, and includes an n-channel TFT 175 provided corresponding to the common electrodes 108 in the first to 320th rows. The Here, the gate electrode of the TFT 175 (fifth transistor) in each row is connected to the control line 165, its source electrode is connected to the signal line 167, and its drain electrode is connected to the common electrode 108.

The data line driving circuit 190 is a voltage corresponding to the gray level of the pixel 110 positioned on the scanning line 112 to which the selection voltage is applied by the scanning line driving circuit 140 and is designated by the polarity designation signal Pol. A data signal having a voltage corresponding to the writing polarity is supplied to the data line 114.
The data line driving circuit 190 has a storage area (not shown) corresponding to a pixel matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation (brightness) of the corresponding pixel 110. Is stored. Here, immediately before the selection voltage is applied to a certain scanning line 112, the data line driving circuit 190 reads the display data Da of the pixel 110 located on the scanning line 112 from the storage area, and uses the read display data. The voltage is converted into a voltage according to the designated gradation and writing polarity, and supplied to the data line 114 as a data signal in accordance with the timing at which the selection voltage is applied. The data line driving circuit 190 executes this supply operation for each of the 1st to 240th columns positioned on the selected scanning line 112.
The display data Da stored in the storage area is rewritten when the display content is changed and the display data Da after the change is supplied from the control circuit 20 together with the address. Further, the data line driving circuit 190 operates as described later in the partial mode.

Further, the control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at the timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 sequentially sets the scanning signals Y1, Y2, Y3, Y4,..., Y320 to the H level by sequentially shifting the start pulse Dy according to the clock signal Cly. The start timing of the period during which the scanning line is selected is the timing at which the logic level of the clock signal Cly transitions. Therefore, the data line driving circuit 190 knows which row scanning line is selected, for example, by continuously counting the latch pulse Lp from the start of the period of one frame, and further, according to the supply timing of the latch pulse Lp, The start timing of the selection can be known.
Note that, even in the partial mode, the scanning line driving circuit 140 executes the shift operation of the start pulse Dy and the like, and only partially restricts the scanning signal to be set to the H level.

In this embodiment, the polarity designation signal Pol designates positive polarity writing for the pixel of the scanning line to which the selection voltage is applied if it is H level in the full screen mode, and if it is L level, the pixel concerned. Is a signal designating negative polarity writing, and actually has a waveform as shown in FIG. Specifically, as shown in the figure, in a period of a certain frame (denoted as “n frame”), the selection voltage is applied to the scanning signal to the scanning line of the odd (1, 3, 5,..., 319) rows. Is applied to the H level, and is applied to the scanning signal to the scanning line of the even (2, 4, 6,..., 320) th row, and becomes the L level. Therefore, in the present embodiment, in the full screen mode, a row inversion (also referred to as line inversion or scanning line inversion) method in which the polarity of writing to the pixels is inverted for each row is used.
In the full-screen mode, the polarity designation signal Pol is logically inverted when compared in the same row in the next frame (indicated as “(n + 1) frame”), but the write polarity is thus inverted. The reason for this is to prevent deterioration of the liquid crystal due to application of a direct current component.
In the partial mode, the polarity designation signal Pol becomes L level over the entire first frame, H level over a partial period of the fourth frame, as shown in FIGS. It is at the H level over the entire 7 frames and at the L level over a partial period of the 10th frame.

  Here, regarding the writing polarity in the present embodiment, when the voltage corresponding to the gradation is held in the liquid crystal capacitor 120, the potential of the pixel electrode 118 is set higher than the potential of the common electrode 108. It is called positive polarity, and the case of the lower side is called negative polarity. As for the voltage, unless otherwise specified, the ground potential Gnd corresponds to the L level of the logic level and is used as a reference for the voltage zero.

The control circuit 20 supplies signals Vg-a and Vg-b to the first power supply line 161 and the second power supply line 162, respectively. In this embodiment, in the full screen mode, the signal Vg-a has the same waveform as the polarity designation signal Pol, and the signal Vg-b has a waveform obtained by logically inverting the polarity designation signal Pol.
When applied to the gate electrodes of the TFTs 173 and 174, the voltage Vdd corresponding to the logic level H level is an on-voltage that causes the source and drain electrodes of the TFTs 173 and 174 to be in a conductive (on) state. Further, the L level is the ground potential Gnd, which is an off voltage that causes the source / drain electrodes of the TFTs 173 and 174 to become non-conductive (off) even when applied to the gate electrodes of the TFTs 173 and 174.

Common signals Vc-a and Vc-b are supplied to the third feeder line 163 and the fourth feeder line 164 by the control circuit 20, respectively. In the present embodiment, the common signal Vc-a is constant at the voltage Vsl and the common signal Vc-b is constant at the voltage Vsh in both the full screen mode and the partial mode. The voltages Vsl and Vsh have a relationship of (Gnd ≦) Vsl <Vsh (≦ Vdd), and the voltage Vsl is relatively lower than the voltage Vsh (the voltage Vsh is relative to the voltage Vsl). Is a high voltage).
Further, the control signal Vg-c is supplied to the control line 165 by the control circuit 20. The control signal Vg-c is at L level in the full screen mode, and only in the second, third, eighth and ninth frames as shown in FIGS. 8 to 10 described later in the partial mode. At H level. Further, a common signal Vc is supplied to the signal line 167 by the control circuit 20. The common signal Vc becomes the voltage Vsh in the second and third frames in the partial mode, and becomes the voltage Vsl in the eighth and ninth frames.

  Now, the panel in the electro-optical device has a configuration in which a pair of substrates of an element substrate and a counter substrate are bonded together with a certain gap therebetween, and liquid crystal is sealed in this gap. In addition, the scanning line 112, the data line 114, the common electrode 108, the pixel electrode 118, and the TFTs 116 and 171 to 175 are formed on the element substrate, and are bonded so that the electrode formation surface faces the counter substrate. . FIG. 3 is a plan view showing the vicinity of the boundary between the display region 100 and the common electrode driving circuit 170a, and FIG. 3 is a plan view showing the vicinity of the boundary between the display region 100 and the common electrode driving circuit 170b. The thing is FIG.

As can be seen from FIGS. 3 and 4, the display region 100 is an FFS (fringe field switching) mode, which is a modification of the IPS mode in which the electric field direction applied to the liquid crystal is the substrate surface direction. In the present embodiment, the TFTs 116 and 171 to 175 are amorphous silicon types, and are bottom gate types in which the gate electrodes are located below the semiconductor layer (the back side in the drawing).
Specifically, a rectangular electrode 108f is formed by patterning a (first) ITO (indium tin oxide) layer to be a first conductive layer, and scanning is also performed by patterning a gate electrode layer to be a second conductive layer. Gate wirings such as the line 112, the control line 165, and the common line 108e are formed, a gate insulating film (not shown) is formed thereon, and a semiconductor layer of the TFT is formed in an island shape. Subsequently, after forming a protective insulating layer (not shown), the pixel electrode 118 having a comb-like shape is formed by patterning the (second) ITO layer that becomes the third conductive layer, and further becomes the fourth conductive layer. By patterning the metal layer, along with the source electrode and drain electrode of the TFT, in addition to the data line 114, the first power supply line 161, the second power supply line 162, the third power supply line 163, the fourth power supply line 164, the signal line 167, Various connection electrodes are formed.
In FIG. 3 and FIG. 4, a mark X is a contact hole for connecting a wiring made of the gate electrode layer and a wiring layer made of the fourth conductive layer.

  1 and 2, the common electrode 108 in FIG. 3 and FIG. 4 is a rectangular electrode in which a common line 108e extending in parallel with the scanning line 112 and a pixel electrode 118 are stacked via a protective insulating layer. 108f. Here, the common line 108e and the electrodes 108f located in the same row have portions that partially overlap each other, and are electrically connected. For this reason, the common line 108e and the electrode 108f located in the same row are electrically the same and do not need to be distinguished from each other. Therefore, unless they are structurally explained, the common line 108e and the electrode 108f are simply used as the common electrode 108 without being distinguished from each other.

In the present embodiment, the storage capacitor 130 is a capacitance component generated by a stacked structure in which the electrode 108f and the pixel electrode 118 are interposed via a protective insulating layer. In addition, since a liquid crystal is also sealed in the gap between the element substrate and the counter substrate, a capacitance component is generated between the pixel electrode 118 and the electrode 108f due to the structure through the liquid crystal serving as a dielectric. In this embodiment, the capacitive component due to the liquid crystal is used as the liquid crystal capacitor 120.
In this configuration, an electric field according to the holding voltage of the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 is generated along the element substrate surface and in a direction orthogonal to the comb teeth of the pixel electrode 118, The orientation state is changed. Thereby, the amount of light passing through the polarizer (not shown) becomes a value corresponding to the effective value of the holding voltage.
In this embodiment, the FFS mode is used. However, the IPS mode may be used, and other modes may be used as long as the electrical equivalent circuit is a circuit as shown in FIG.

Here, since the holding voltage of the parallel capacitor is a difference voltage between the pixel electrode 118 and the common electrode 108 (electrode 108f), in order to set the pixel in i row and j column to the target gradation, the scan in the i row is performed. A selection voltage Vdd is applied to the line 112 to turn on the TFT 116, and a data signal Xj having a voltage such that the difference voltage corresponds to the gradation of the pixel is supplied to the data line 114 in the jth column. And the TFT 116 turned on in the i row and the j column may be supplied to the pixel electrode 118.
In this embodiment, for convenience of explanation, if the voltage effective value is close to zero, the light transmittance is minimized and black display is obtained, while the amount of transmitted light increases as the voltage effective value increases, Finally, the normally black mode in which the white display with the maximum transmittance is achieved.
Further, since the common electrode 108 in each row intersects with the data line 114 in the first to 240th columns via a gate insulating film or the like, it is capacitively coupled to each other via a parasitic capacitance as shown by a broken line in FIG. It will be.

The configuration shown in FIGS. 3 and 4 is merely an example, and the TFT type may be another structure, for example, the top gate type in terms of the arrangement of the gate electrode, or the polysilicon type in terms of the process. good. In addition, the TFTs 171 to T75 which are the constituent elements of the common electrode driving circuits 170a and 170b may be mounted on the element substrate instead of being built on the substrate by the same process as the display region 100.
When the IC chip is mounted on the element substrate, the scanning line driving circuit 140 and the common electrode driving circuits 170a and 107b may be integrated as a semiconductor chip together with the data line driving circuit 190, or may be separate chips. On the other hand, the control circuit 20 may be configured to be built in the element substrate.
Further, the common electrode driving circuit 170 a is provided on the scanning line driving circuit 140 side and the common electrode driving circuit 170 b is provided on the opposite side of the scanning line driving circuit 140 with respect to the extending direction of the scanning line 112. However, the relationship may be reversed, and both the common electrode driving circuits 170a and 170b may be provided in the same region.
The present embodiment may be a transmissive type, a reflective type, or a so-called transflective type that combines both a transmissive type and a reflective type. For this reason, no particular reference is made to the reflective layer and the like.

Next, the case of the full screen mode among the operations of the electro-optical device 10 according to the present embodiment will be described.
As described above, in this embodiment, when the full screen mode is set, the control circuit 20 outputs the polarity designation signal Pol, the signals Vg-a and Vg-b in n frames, as shown in FIG. The common signal Vc-a is set to the voltage Vsl, and the common signal Vc-b is set to the voltage Vsh.
In the n-th frame, the scanning signal Y1 to the first scanning line 112 is first set to the H level by the scanning line driving circuit 140. In addition, since the positive polarity writing is designated in the odd-numbered row in the n frame, when the latch pulse Lp is output at the timing when the scanning signal Y1 becomes the H level, the data line driving circuit 190 is in the first row. The data signals X1, X2, X3,..., X240 having voltages higher than the voltage Vsl by the voltage specified by the display data Da of the pixels in the 1, 2, 3,. , 240, to the data lines 114 in 240 columns. Thereby, for example, the data signal Xj supplied to the data line 114 in the j-th column becomes a voltage higher than the voltage Vsl by the voltage specified by the display data Da of the pixel 110 in the first row and j-th column.
When the scanning signal Y1 becomes the H level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned on, so that the data signals X1, X2, X3,. .

On the other hand, in the period when the scanning signal Y1 is at the H level, the TFTs 171 and 172 in the first row are turned on in the common electrode driving circuit 170a. Here, during the period in which the scanning signal Y1 is at the H level, the signal Vg-a supplied to the first power supply line 161 is at the H level, and the signal Vg-b supplied to the second power supply line 162 is at the L level. Therefore, the TFTs 171 and 172 in the first row are turned on, whereby an H level on voltage is applied to the gate electrode of the TFT 173 in the first row and an L level off voltage is applied to the gate electrode of the TFT 174. The Therefore, the TFTs 173 and 174 in the first row are turned on and off, respectively, so that the common electrode 108 in the first row is connected to the third power supply line 163 and becomes the voltage Vsl.
Therefore, a positive voltage corresponding to the gradation is written in the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 in the first row and the first column to the first row and the 240th column.
In the full screen mode, the control signal Vg-c is at the L level, and in the common electrode driving circuit 170b, all the TFTs 175 are off, so that the voltage of the common electrode 108 is not determined.

Next, the scanning signal Y1 becomes L level, while the scanning signal Y2 becomes H level.
Here, when the scanning signal Y1 becomes L level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned off. For this reason, in each of the pixels 110 in the first row and the first column to the first row and the 240th column, the pixel electrode 118 is in a high impedance state.
On the other hand, in the common electrode driving circuit 170a, when the scanning signal Y1 becomes L level, the TFTs 171 and 172 in the first row are turned off, so that the gate electrodes of the TFTs 173 and 174 are in a high impedance state. However, since the gate electrodes of the TFTs 173 and 174 are held in a state just before the high impedance state due to the parasitic capacitance, that is, in the H and L level states, the TFTs 173 and 174 continue to maintain the on and off states. To do. For this reason, the common electrode 108 in the first row is continuously connected to the third power supply line 163 even when the scanning signal Y1 becomes the L level, so that the voltage Vsl is maintained. Therefore, since the other end of the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 in the 1st row and the 1st column to the 1st row and 240th column is maintained at the voltage Vsl, the written voltage state is continued without being changed. become.

In addition, since even-numbered writing is designated in the even-numbered row in the n frame, when the latch pulse Lp is output at the timing when the scanning signal Y2 becomes H level, the data line driving circuit 190 is in the second row. The data signals X1, X2, X3,..., X240 are output with the voltage specified by the display data Da of the pixels in the first, second, third,. Thereby, for example, the data signal Xj supplied to the data line 114 in the j-th column becomes a voltage lower than the voltage Vsh by the voltage specified by the display data Da of the pixel 110 in the second row and j-th column.
When the scanning signal Y2 becomes H level, the TFTs 116 in the pixels in the 2nd row and the 1st column to the 2nd row and the 240th column are turned on, so that the data signals X1, X2, X3,. .
On the other hand, in the period during which the scanning signal Y2 is at the H level, the TFTs 171 and 172 in the second row are turned on in the common electrode driving circuit 170a. Here, in the period when the scanning signal Y2 is at the H level, the signal Vg-a supplied to the first power supply line 161 is at the L level, and the signal Vg-b supplied to the second power supply line 162 is at the H level. Since they are switched, the TFTs 173 and 174 in the second row are turned off and on, respectively, contrary to the first row. For this reason, the common electrode 108 in the second row is connected to the fourth feeder line 164 and becomes the voltage Vsh.
Therefore, a negative voltage corresponding to the gradation is written in the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 of 2 rows and 1 column to 2 rows and 240 columns.

Subsequently, the scanning signal Y2 becomes L level, while the scanning signal Y3 becomes H level. Here, when the scanning signal Y2 becomes the L level, the TFTs 116 in the pixels of the 2nd row and the 1st column to the 2nd row and the 240th column are turned off. The pixel electrode 118 enters a high impedance state.
On the other hand, in the common electrode driving circuit 170a, when the scanning signal Y2 becomes L level, the TFTs 171 and 172 in the second row are also turned off, so that the gate electrodes of the TFTs 173 and 174 are in a high impedance state. Since the parasitic capacitances hold the L and H levels, respectively, the TFTs 173 and 174 in the second row continue to be kept off and on. For this reason, the common electrode 108 in the second row is continuously connected to the fourth power supply line 164 even when the scanning signal Y2 becomes L level, so that the voltage Vsh is maintained.
Therefore, since the other end of the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 in the 2nd row and the 1st column to the 2nd row and 240th column is maintained at the voltage Vsh, the written voltage state is continued without being changed. become.

When the scanning signal Y3 becomes H level, a positive voltage corresponding to the gradation is written in the parallel capacitance of the liquid crystal capacitor 120 and the storage capacitor 130 in the third row. Next, the scanning signal When Y4 becomes H level, a negative voltage corresponding to the gradation is written in the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 in the fourth row.
Thereafter, the same operation is repeated up to the 320th row, and in this way, in the n frame, the positive voltage corresponding to the gradation is written in the parallel capacitance of the liquid crystal capacitor 120 and the storage capacitor 130 in the odd row. In addition, a negative voltage corresponding to each gradation is written in the parallel capacitors of the liquid crystal capacitors 120 and the storage capacitors 130 in even-numbered rows. As described above, since voltages corresponding to gradations are written in the parallel capacitors in all the pixels, one image (frame) is displayed in the display region 100.

In the next (n + 1) frame, the polarity designation signal Pol and the signals Vg-a and Vg-b are in a relationship in which the logic level of the previous n frame is inverted. Therefore, when the odd-numbered scanning lines 112 are selected, The common electrode 108 corresponding to the selected odd-numbered scanning line is connected to the fourth power supply line 164 to become the voltage Vsh, and even if the scanning line is not selected (the scanning signal is L level), While the connection state is maintained, when the even-numbered scanning line 112 is selected, the common electrode 108 corresponding to the selected even-numbered scanning line is connected to the third feeding line 163 to the voltage Vsl. In addition, even when the scanning line is not selected, the connection state is maintained.
For this reason, in the (n + 1) frame, a negative voltage corresponding to the gray level is written in each of the parallel capacitors of the odd-numbered liquid crystal capacitors 120 and the storage capacitors 130, and The positive voltage corresponding to the gradation is written, and the written voltage state is maintained.

Here, voltage writing in the present embodiment will be described with reference to FIG. In FIG. 6, the voltage Pix (i, j) at the pixel electrode 118 in the i row and j column and the voltage Pix (i + 1, j) at the pixel electrode 118 in the (i + 1) row and j column are respectively represented by the scanning signals Yi, It is a figure shown in relation to Y (i + 1). Note that the vertical scale indicating the voltage in FIG. 6 is enlarged from the vertical scale in FIG. 5 for convenience.
In the n frame, since positive polarity writing is designated for the odd-numbered i-th row pixels, the j-th data line 114 has a higher voltage Vsl than the voltage Vsl during the period when the scanning signal Yi is at the H level. A data signal Xj having a higher voltage (indicated by ↑ in FIG. 6) corresponding to the gray level of the pixel in the i row and j column is supplied. Thus, in the parallel capacitance of the liquid crystal capacitor 120 and the storage capacitor 130 in the i row and j column, the voltage difference between the voltage of the data signal Xj and the voltage Vsl of the common electrode 108, that is, the positive voltage corresponding to the gradation is written. Will be.
Here, when the scanning signal Yi becomes L level, the pixel electrode 118 in i row and j column is in a high impedance state. On the other hand, the odd-numbered i-th common electrode 108 is connected to the third power supply line 163 when the scanning signal Yi becomes H level in the n frame, and thus becomes the voltage Vsl. It continues until the scanning signal Yi becomes H level again in the (n + 1) frame. Therefore, the voltage Pix (i, j) of the pixel electrode 118 in the i row and j column does not vary from the voltage (the voltage of the data signal Xj) when the scanning signal Yi becomes the H level, and the liquid crystal capacitance 120 The effective voltage value (hatched portion) held in the parallel capacitor of the storage capacitor 130 is not affected.

In the n frame, since negative polarity writing is designated for even-numbered (i + 1) -th row pixels, in the period when the scanning signal Y (i + 1) is at the H level, Thus, a data signal Xj having a lower voltage (indicated by ↓ in FIG. 6) by a voltage corresponding to the gradation of the pixel in (i + 1) rows and j columns from the voltage Vsh is supplied. As a result, in the parallel capacitor of the liquid crystal capacitor 120 and the storage capacitor 130 in (i + 1) rows and j columns, a negative voltage corresponding to the gradation is written. Further, the common electrode 108 in the even (i + 1) -th row is connected to the fourth power supply line 164 when the scanning signal Y (i + 1) becomes the H level in the n frame, and thus becomes the voltage Vsh. Since it continues until the scanning signal Y (i + 1) becomes H level again in the next (n + 1) frame, the voltage Pix (i + 1, j) is the voltage when the scanning signal Y (i + 1) becomes H level. (The voltage of the data signal Xj) does not fluctuate, and the effective voltage value (hatched portion) held in the parallel capacitance of the liquid crystal capacitor 120 and the storage capacitor 130 is not affected.
Further, in the next (n + 1) frame, since the writing polarity is inverted, negative polarity writing is performed on the odd-numbered i-th row pixels, and positive polarity writing is performed on the even-numbered (i + 1) -th row pixels. Each is executed.
In this way, in the present embodiment, the writing polarity is reversed for each scanning line in the full screen mode.

According to such an embodiment, the common electrode 108 in the row in which the positive polarity writing is designated becomes the relatively low voltage Vsl when the scanning line 112 in the row is selected, and is higher than this voltage. While the higher voltage corresponding to the gray scale is supplied as the data signal, the common electrode 108 in the row in which the negative polarity writing is designated is relatively set when the scanning line 112 in the row is selected. The voltage Vsh becomes high, and a voltage lower than this voltage by a voltage corresponding to the gradation is supplied as a data signal.
Therefore, the voltage amplitude of the data signal is narrower than that in the case where the voltage of the common electrode 108 is constant, so that the withstand voltage required for the constituent elements of the data line driving circuit 190 is suppressed to a low level. Can be simplified, and it is also possible to suppress the wasteful power consumption due to the voltage change.

By the way, since the common electrode 108 (common line 108e) in each row intersects with the data lines 114 of 1 to 240 columns via the gate insulating film as described above, the voltage change of these data lines 114, that is, The change of the data signals X1 to X240 propagates to the common electrode 108 through the parasitic capacitance.
Therefore, if the common electrode 108 is not electrically connected to any part, the potential fluctuates due to the influence of the voltage change of each data line (voltage change of the data signals X1 to X240). Since the common electrode 108 is independent for each row in this embodiment, there is a high possibility that the potential of the common electrode fluctuates by a different amount for each row and adversely affects display quality.

  In contrast, in the present embodiment, in the odd-numbered i-th row, for example, when the scanning signal Yi becomes H level in the n-th frame, the TFTs 171 and 172 in the i-th row are turned on, so that the TFTs 173 and 174 are turned on. Are turned on and off, and H and L levels are written to the capacitances parasitic on the gate electrodes of the TFTs 173 and 174, respectively, so that even if the scanning signal Yi becomes the L level, the TFTs 173 and 174 in the i-th row The ON / OFF state is maintained, and eventually, the odd-numbered i-th common electrode 108 continues to be connected to the third feeder line 163. On the other hand, in the nth frame, the common electrode in the even (i + 1) th row continues to be connected to the fourth feeder line 164. Accordingly, in the present embodiment, in the full screen mode, the common electrode 108 in each row is always in a state where the voltage Vsl or Vsh is applied, and does not become a high impedance state, which is caused by the voltage variation of the common electrode. It is possible to prevent deterioration in display quality.

Next, the operation in the partial mode will be described. FIG. 7 is a diagram showing an example of the operation of each frame in the partial mode. In the present embodiment, in the partial mode, an operation with 12 frames from 1st to 12th as one unit is executed.
In this example, the 1st to 80th lines and the 161st to 320th lines are set as non-display lines, the pixels corresponding to the non-display lines are invalidated, and the 81st to 160th lines are set as display lines, and the pixels corresponding to the display lines are displayed. In the case where effective display is performed using only the pixel, it is shown in what polarity voltage writing is performed on the pixels located on the scanning lines in the first to 320th rows.
Note that in the partial mode, the pixels located in the display row may be simply binary display that is either on-white or off-black, but here, description is made assuming that gradation display is performed.

In the figure, + indicates positive polarity, − indicates negative polarity, and each indicates a case where voltage writing is performed, while × indicates a state where voltage writing is not performed.
Here, in the first and seventh frames of the partial mode, negative voltage writing and positive voltage writing are performed on the 1st to 80th lines and the 161st to 320th lines of the non-display lines, respectively. Is for forcibly writing a voltage corresponding to black (off) in order to invalidate the pixels in the non-display row. On the other hand, in the first, fourth, seventh, and tenth frames of the partial mode, voltage writing is performed in the order of negative polarity, positive polarity, positive polarity, and negative polarity in the 81st to 160th display rows. . For this reason, in this embodiment, in the partial mode, the writing polarities of adjacent rows are the same.

Waveforms of the scanning signal and the like in the partial mode according to FIG. 7 will be described with reference to FIGS. Here, FIG. 8 shows the waveforms and the like of the scanning signals Y1 to Y320 of the first to fourth frames, FIG. 9 shows the waveforms and the like of the scanning signals Y1 to Y320 of the fifth to eighth frames, and FIG. FIG. 10 is a diagram illustrating waveforms and the like of scanning signals Y1 to Y320 in the ninth to twelfth frames.
As shown in FIG. 8, in the first frame of the partial mode, the scanning signals Y1 to Y320 are the same as in the full screen mode. However, in the present embodiment, since the polarity designation signal Pol is constant at the L level in the first frame, it corresponds to negative black (off) in the 1st to 80th lines and the 161 to 320th non-display lines. In the 81st to 160th display rows, a voltage corresponding to the negative polarity gradation is written.
In the second and third frames in the partial mode, the scanning signals Y1 to Y320 do not become the H level, and therefore no writing operation is executed.
In the fourth frame in the partial mode, only the scanning signals Y81 to Y160 applied to the display row are sequentially set to the H level. Since the polarity designation signal Pol is at the H level during the period in which the scanning signals Y81 to Y160 are at the H level in the fourth frame, the voltage corresponding to the positive tone is written in the 81st to 160th display lines. It is.

Next, as shown in FIG. 9, in the fifth and sixth frames in the partial mode, the scanning signals Y1 to Y320 do not become the H level as in the second and third frames. The action is not performed.
In the seventh frame, the scanning signals Y1 to Y320 are the same as in the full screen mode. However, in the present embodiment, since the polarity designation signal Pol is constant at the H level in the seventh frame, it corresponds to positive black (off) in the 1st to 80th lines and the 161st to 320th non-display lines. The voltage corresponding to the positive polarity gradation is written in the 81st to 160th display rows.
In the eighth frame and the ninth frame shown in FIG. 10, the scanning signals Y1 to Y320 do not become H level, and therefore no writing operation is executed. In the tenth frame in the partial mode, only the scanning signals Y81 to Y160 applied to the display row sequentially become H level. Since the polarity designation signal Pol is at the L level during the period in which the scanning signals Y81 to Y160 are at the H level in the tenth frame, a voltage corresponding to the negative gradation is written in the 81st to 160th display rows. It is. In the eleventh and twelfth frames, the scanning signals Y1 to Y320 do not become H level, and therefore no writing operation is executed.
Thereafter, in the partial mode, the operations of the first to twelfth frames are repeated.

  In the full screen mode, the voltage writing is performed for each frame. In the partial mode, the off-voltage writing for the pixels in the non-display row is executed once every six frames, and the voltage for the pixels in the display row is performed. Since the writing cycle is executed once every three frames, the power consumed by the voltage writing can be suppressed.

By the way, in the full screen mode, in the common electrode driving circuit 170a, for example, the TFTs 173 and 174 in the i-th row hold the on or off voltage applied to the gate electrode with the parasitic capacitance when the scanning signal Yi is at the H level. Thus, the potential of the i-th common electrode 108 is determined even when the scanning signal Yi becomes L level.
However, in such a partial mode, the frequency of voltage writing executed when the scanning signal becomes H level is lower than in the full screen mode. For this reason, there is a possibility that the on-voltage held in either the gate electrode of the TFT 173 or 174 gradually decreases due to leakage or the like and eventually becomes lower than the threshold value, and the on-state cannot be maintained. is there.
In order to avoid this, a configuration in which a capacitive element is added to the gate electrodes of the TFTs 173 and 174 to reduce the influence of leakage is conceivable. However, an extra space is required to form the capacitive element. Accordingly, a so-called frame area outside the display area becomes wider.

Therefore, in the partial mode in the present embodiment, the control circuit 20 supplies the control signal Vg-c and the common signal Vc as described above. That is, the control circuit 20 sets the control signal Vg-c to the H level only in the second, third, eighth and ninth frames, sets the common signal Vc to the voltage Vsh in the second and third frames, and sets the eighth and eighth frames. The voltage is Vsl in 9 frames.
Since the polarity designation signal Pol is at the L level in the first frame before that, the signal Vg-a is the same L level, and the signal Vg-b is the inverted H level. Therefore, in the common electrode driving circuit 170a, in the odd-numbered i-th row, when the scanning signal Yi becomes H level and the TFTs 171 and 172 are turned on, the off and on voltages are applied to the gate electrodes of the TFTs 173 and 174, respectively. Therefore, the common electrode 108 in the i-th row becomes the higher voltage Vsh in accordance with the negative polarity writing. Similarly, in the even (i + 1) -th row, the gate electrodes of the TFTs 173 and 174 are turned off. Since the ON voltage is applied, the common electrode 108 in the (i + 1) th row becomes the voltage Vsh.
In the second and third frames, since the scanning signal does not become H level, the gate voltages of the TFTs 173 and 174 in each row may be reduced due to leakage or the like, and the on state may not be maintained. However, in the common electrode driving circuit 170b, Since the TFTs 175 in each row are turned on all at once when the control signal Vg-c becomes H level, all the common electrodes 108 are not affected by the gate voltages of the TFTs 173 and 174, that is, regardless of whether they are turned on or off. As in the case of one frame, the voltage Vsh of the common signal Vc is determined.

In the fourth frame, since the polarity designation signal Pol is at the H level during the period when the scanning signals Y80 to Y161 are sequentially at the H level, the signal Vg-a is at the H level and the signal Vg-b is inverted. L level.
In the common electrode driving circuit 170a, when the scanning signal applied to the display row becomes H level and the TFTs 171 and 172 are turned on, on and off voltages are applied to the gate electrodes of the TFTs 173 and 174, respectively. Since the TFTs 173 and 174 are turned on and off, respectively, the common electrode 108 in the display row is switched to the lower voltage Vsl in accordance with the positive polarity writing.
On the other hand, in the seventh to tenth frames, the operation of the relationship in which the polarities in the first to fourth frames are reversed is executed.

  As described above, according to the present embodiment, in the partial mode, the common electrode 108 of the second, third, eighth, and ninth frames is used in the second, third, eighth, and ninth frames in addition to the first and seventh frames in which voltage writing is performed for all rows. Since the potential is fixed, it is possible to suppress the degradation of display quality by that amount.

  In the present embodiment, the control signal Vg-c is set to H level in the second, third, eighth, and ninth frames to determine the potential of the common electrode 108, but voltage writing is performed for all rows. It may be all or part of the frame after the first (seventh) frame and before the fourth (tenth) frame in which voltage writing is performed only on the display row. The control signal Vg-c may be set to the H level only in the ninth frame.

Second Embodiment
In the first embodiment described above, in the full screen mode, the pixel inversion polarity is reversed for each row. However, in the partial mode, the display row has a common writing polarity. It cannot be denied that the display quality of the image displayed by the pixels in the display row is inferior to that in the full screen mode.
Therefore, a second embodiment in which the writing polarity is reversed for each scanning line in the display rows even in the partial mode will be described.

FIG. 11 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment.
The configuration shown in this figure is different from that in FIG. 1 in that the connection destination of the source electrode of the TFT 175 is divided into an odd row and an even row in the common electrode driving circuit 170b. Specifically, the source electrodes of the odd-numbered TFTs 175 are connected to the first signal line 167c to which the common signal Vc-c is supplied, and the source electrodes of the even-numbered TFTs 175 are supplied with the common signal Vc-d. It is connected to the two signal lines 167d.

FIG. 12 is a plan view showing the vicinity of the boundary between the display region 100 and the common electrode driving circuit 170b in the element substrate of the second embodiment.
As shown in this figure, the source electrode of the TFT 175 in the odd-numbered i-th row uses a portion branched from the signal line 167, but the source electrode of the TFT 175 in the even-numbered (i + 1) -th row uses the first signal line 167c. It is connected to the second signal line 167d through an undercrossing wiring.

In the second embodiment, the operation in the full screen mode is the same as that in the first embodiment. Therefore, the operation of the second embodiment will be described focusing on the differences in the partial mode.
FIG. 13 is a diagram illustrating an example of the operation of each frame in the partial mode.
Also in the second embodiment, in the partial mode, an operation with 12 frames from 1st to 12th as one unit is executed, and the 1st to 80th lines and the 161st to 320th lines are set as non-display lines, and 81 About the 160th line as a display line, it is the same as that of 1st Embodiment (refer FIG. 6).
As shown in FIG. 13, the writing polarity in the first frame in the partial mode is obtained by inverting the writing polarity in the previous full-screen mode for both the display row and the non-displaying row. Assume that positive polarity writing and negative polarity writing are specified for even-numbered rows, respectively. Further, the writing polarity in the seventh frame is obtained by inverting the writing polarity in the first frame. Both the first and seventh frames are row inversion methods.
On the other hand, the writing polarity in the fourth frame of the display row is the reverse of the writing polarity of the first frame, and the writing polarity in the tenth frame of the display row is the reverse of the writing polarity of the seventh frame. Both are row inversion methods.
The control circuit 20 sets the common signal Vc-c to the voltage Vsl and the common signal Vc-d to the voltage Vsh in the second and third frames, and sets the common signal Vc-c to the voltage in the eighth and ninth frames. Let Vsh be the common signal Vc-d.

Waveforms of the scanning signal and the like in the partial mode according to FIG. 13 are shown in FIGS. 13 shows the waveforms and the like of the scanning signals Y1 to Y320 of the first to fourth frames, FIG. 14 shows the waveforms and the like of the scanning signals Y1 to Y320 of the fifth to eighth frames, and FIG. It is a figure which shows the waveform etc. of the scanning signals Y1-Y320 of the 9th-12th frame.
As shown in these drawings, the scanning signals Y1 to Y320 in the partial mode are the same as those in the partial mode of the first embodiment.

  In the second embodiment, the operation of the first frame is the same as that in the full screen mode except that a voltage corresponding to black (off) is forcibly written for a non-display row. For this reason, the odd-numbered i-th common electrode 108 becomes the low-order side voltage Vsl in accordance with the positive polarity writing, and the even-numbered (i + 1) -th common electrode 108 has the high-order side voltage in response to the negative polarity writing. Vsh.

Next, when the signal Vg-c becomes H level in the second and third frames of the partial mode, the TFTs 175 in the 1st to 320th rows are all turned on in the common electrode driving circuit 170b. Becomes the voltage Vsl of the common signal Vc-c, and the common electrode 108 in the even-numbered row becomes the voltage Vsh of the common signal Vc-d, which is fixed and maintained at the same voltage as the first frame.
In the fourth frame, among the periods in which the scanning signals Y80 to Y161 are sequentially at the H level, the polarity designation signal Pol is at the L level in the period in which the scanning signal in the odd-numbered row is at the H level. By the electrode drive circuit 170a, the odd-numbered common electrodes 108 applied to the display rows are fixed to the higher voltage Vsh according to the negative polarity writing, while the even-numbered common electrodes 108 applied to the display rows are set to the positive polarity writing. Accordingly, the lower voltage Vsl is determined.
In each row in the seventh to tenth frames, the operation of the relationship in which the writing polarity in the first to fourth frames is inverted is executed.

  As described above, according to the second embodiment, in the partial mode, the common electrode 108 is used in the second, third, eighth, and ninth frames other than the first and seventh frames in which voltage writing is performed for all rows. Therefore, it is possible to suppress the deterioration of display quality by that amount. Further, according to the second embodiment, since the writing polarity of the display line in the partial mode is the row inversion method in which the scanning polarity is reversed for each scanning line as in the full screen mode, the display quality of the partial mode is changed to the full screen mode. It is possible to keep it at the same level.

<Application and modification>
In the first and second embodiments described above, if both are full-screen modes, the row inversion method for inverting the pixel writing polarity for each row is used, but the column inversion method for inverting each column, A dot inversion method in which each pixel is inverted every row and every column may be adopted.
In order to use the column inversion method or the dot inversion method, for example, as shown in FIG. 17, two common electrodes 108a and 108b are provided per row, and as shown in FIG. 110 may correspond to the common electrode 108a, and the pixel 110 in the even (j + 1) th column may correspond to the common electrode 108b.
Further, in the common electrode driving circuit 170a, the TFTs 173 and 174 in each row are divided into two series of TFTs 173a and 173b and TFTs 174a and 174b, respectively, and one of the series is determined as one of the voltages Vsl and Vsh at the common electrode 108a. In this case, any one of the other series may be determined as the other of the voltages Vsl and Vsh at the common electrode 108b.
In the common electrode driving circuit 170b, the TFTs 175 are divided into two series of TFTs 175a and 175b so as to correspond to the two common electrodes 108a and 108b, respectively. Specifically, the source electrode of the TFT 175a is connected to the common electrode 108a, the drain electrode is connected to the first signal line 167c, the source electrode of the TFT 175b is connected to the common electrode 108b, and the drain electrode is connected to the second signal line 167d. Is done.

Here, in order to use the column inversion method, for example, when the odd number column is positive, the even number column may be negative. Therefore, when the scanning signal of each row becomes H level, it corresponds to the odd number column. The common electrode 108a may be fixed to the lower voltage Vsl according to the positive polarity, and the common electrode 108b corresponding to the even number column may be fixed to the higher voltage Vsh according to the negative polarity.
On the other hand, in order to use the dot inversion method, the row inversion method may be combined with the column inversion method. For example, when the odd-numbered odd-numbered column is positive, the odd-numbered even-numbered column is negative and the next even-numbered odd-numbered Columns are negative and even rows and even columns are positive. For this purpose, when the scanning signal in the odd-numbered row becomes the H level, the common electrode 108a corresponding to the odd-numbered column is fixed to the lower voltage Vsl according to the positive polarity, and the common electrode corresponding to the even-numbered column is determined. While 108b is fixed to the higher voltage Vsh according to the negative polarity, when the scanning signal of the next even-numbered row becomes the H level, the common electrode 108a corresponding to the odd column is set to the voltage Vsh according to the negative polarity. And the common electrode 108b corresponding to the even-numbered column may be fixed to the voltage Vsl according to the positive polarity.
Note that, in both the column inversion method and the dot inversion method, the data signal to the odd-numbered column and the data signal to the even-numbered column are inverted from each other during the period in which the selection voltage is applied to the scanning line of one row. It is related. Furthermore, in order to prevent a DC component from being applied to the liquid crystal capacitor 120, it is necessary to reverse the polarity at a predetermined frame period.

In the embodiment described above, the common signals Vc-a and Vc-b and the signals Vg-a and Vg-b have waveforms as shown in FIG. May be inverted (replaced), for example, every frame period or every horizontal scanning period (H), and the logic of the signals Vg-a and Vg-b may be defined in accordance with this inversion.
That is, when the scanning signal to a certain scanning line becomes H level, the common electrode is set to a voltage corresponding to the writing polarity to the row, and the scanning signal becomes L level. Any configuration may be used as long as the common electrode of the row is continuously maintained at the same voltage.

In the above-described embodiment, the i-th TFTs 171 and 172 are turned on when the i-th scanning line is selected and the scanning signal Yi becomes H level. Here, the TFTs 171 and 172 in the i-th row are connected to the gate electrodes of the TFTs 173 and 174 with the first power supply line 161 and the second power supply line 162, and either one of the TFTs 173 and 174 is turned on. It is important to determine that the other is turned off. When the common electrode 108 in the i-th row is determined to have a potential corresponding to the writing polarity, when the TFTs 171 and 172 are turned on. , Not so important.
In addition, since it is meaningless to specify the writing polarity in the vertical blanking period, the logic signals such as the polarity specifying signal Pol and the common signals Vc-a and Vc-b are fixed to a certain level, or These signal lines may be in a high impedance state.
Furthermore, in the embodiment, the liquid crystal capacitor 120 is set to the normally black mode, but may be set to a normally white mode in which a bright state is obtained when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed, and another color (for example, cyan (C)) may be used. In addition, one dot may be configured with these four color pixels to improve the color reproducibility.

<Electronic equipment>
Next, an example of an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described.
FIG. 19 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment. As shown in this figure, the mobile phone 1200 includes the electro-optical device 10 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206.
Electronic devices to which the electro-optical device 10 is applied include a digital still camera, a notebook computer, a liquid crystal television, a video recorder, a car navigation device, a pager, an electronic notebook, and a calculator in addition to the mobile phone shown in FIG. , A word processor, a workstation, a video phone, a POS terminal, a touch panel, and the like. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a plan view showing a main part configuration of an element substrate of the electro-optical device. FIG. 3 is a plan view showing a main part configuration of an element substrate of the electro-optical device. FIG. 6 is a diagram for explaining an operation in a full screen mode of the electro-optical device. It is a figure which shows the voltage waveform of the pixel electrode in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining a partial mode operation of the electro-optical device. FIG. 6 is a diagram for explaining a partial mode operation of the electro-optical device. FIG. 6 is a diagram for explaining a partial mode operation of the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a plan view showing a main part configuration of an element substrate of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a diagram for explaining a partial mode operation of the electro-optical device. FIG. 6 is a diagram for explaining a partial mode operation of the electro-optical device. FIG. 6 is a diagram for explaining a partial mode operation of the electro-optical device. It is a figure which shows the structure of the electro-optical apparatus which concerns on an application example. It is a figure which shows the structure of the pixel of the electro-optical apparatus which concerns on an application example. It is a figure which shows the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scanning line, 114 ... Data line, 116 ... TFT, 120 ... Liquid crystal capacity, 130 ... Storage capacity, 140 ... Scanning line driving circuit 161 ... first feeding line 162 ... second feeding line 163 ... third feeding line 164 ... fourth feeding line 165 ... control line 167 ... signal line 170a, 170b ... common electrode Drive circuit, 171-175 ... TFT, 190 ... Data line drive circuit, 1200 ... Mobile phone

Claims (8)

A plurality of scanning lines, a plurality of data lines, a plurality of common electrodes provided on each of the plurality of scanning lines,
Provided corresponding to the intersection of the scan line and the data line,
One end of the pixel switching element is connected to the data line and becomes conductive when a selection voltage is applied to the scanning line;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode;
A pixel having a gradation according to the holding voltage of the pixel capacitor,
A drive circuit for an electro-optical device having:
A scanning line driving circuit for applying the selection voltage to the plurality of scanning lines in a predetermined order;
A common electrode driving circuit for individually driving the plurality of common electrodes;
A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the selection voltage is applied via the data line;
Comprising
The common electrode driving circuit is provided for each common electrode.
A switch circuit that is set to an on or off state according to a voltage held in the gate electrode, and that applies either a low-side voltage or a high-side voltage to the common electrode when the on-state is set. ,
A first application circuit that applies an on-voltage that sets the switch circuit to an on state to the gate electrode of the switch circuit when the selection voltage is applied to a scanning line that is paired with the common electrode;
When there is an instruction through a predetermined control line after the application of the selection voltage to the scanning line is completed, a second voltage is applied to either the low-side or the high-side for each of the common electrodes. Two application circuits;
A drive circuit for an electro-optical device, comprising: The first application circuit includes first and second transistors,
The switch circuit includes third and fourth transistors,
The second application circuit includes a fifth transistor;
In the first transistor, a gate electrode is connected to the scanning line, and a source electrode is connected to a first power supply line to which a voltage for turning the third transistor on or off is supplied.
In the second transistor, a gate electrode is connected to the scanning line, and a source electrode is connected to a second power supply line to which a voltage for turning the fourth transistor on or off is supplied.
In the third transistor, a gate electrode is connected to a drain electrode of the first transistor, and a source electrode is connected to a third feeder line to which one of a low-side voltage and a high-side voltage is fed,
In the fourth transistor, a gate electrode is connected to a drain electrode of the second transistor, and a source electrode is connected to a fourth power supply line to which the other voltage on the lower side or the higher side is supplied,
The drain electrodes of the third and fourth transistors are connected to the common electrode,
In the fifth transistor, a gate electrode is connected to the control line, a source electrode is connected to a signal line to which either a low voltage or a high voltage is supplied, and a drain electrode is connected to the common electrode. The drive circuit of the electro-optical device according to claim 1. The drive circuit of the electro-optical device according to claim 2, wherein the source electrode of the fifth transistor is connected to a common signal line in each row of the scanning line and the common electrode. A first mode for performing effective display using all pixels;
A second mode for performing effective display using only pixels corresponding to some scanning lines,
In the first mode,
The scanning line driving circuit executes an operation of sequentially applying the selection voltage to the plurality of scanning lines at a predetermined cycle,
A voltage that turns the third transistor on and off is supplied to the first power supply line by being inverted every time a selection voltage is applied to the scanning line.
The third power supply line is supplied with one voltage on the lower side or the higher side over a period of at least one frame,
A voltage for turning off the fifth transistor is supplied to the control line,
In the second mode,
The scanning line driving circuit includes a first operation for sequentially applying the selection voltage to the plurality of scanning lines, and a second operation for sequentially applying the selection voltage to the partial scanning lines. It repeats alternately with a period longer than a predetermined period,
One of a voltage for turning on the third transistor during the first operation or a voltage for turning off the third transistor during the first operation is applied to the first power supply line, and the third transistor is turned on during the second operation. The other of the voltage to be turned on or the voltage to be turned off is applied over a period of time when the selection voltage is applied to the part of the scanning lines,
The third power supply line is supplied with one voltage on the lower side or the higher side over a period of at least one frame,
The control line is supplied with a voltage for turning on the fifth transistor over a part or all of a period from the end of the first operation to the start of the second operation, and the fifth line is supplied over the other period. The drive circuit for the electro-optical device according to claim 3, wherein a voltage for turning off the transistor is supplied. Of the scanning lines and common electrodes,
The source electrode of the fifth transistor in the odd-numbered row is connected to the first signal line to which one of the low and high voltages is supplied,
The drive circuit of the electro-optical device according to claim 2, wherein the source electrode of the fifth transistor in the even-numbered row is connected to a second signal line to which the other voltage on the lower side or the higher side is supplied. . A first mode for performing effective display using all pixels;
A second mode for performing effective display using only pixels corresponding to some scanning lines,
In the first mode,
The scanning line driving circuit executes an operation of sequentially applying the selection voltage to the plurality of scanning lines at a predetermined cycle,
A voltage that turns the third transistor on and off is supplied to the first power supply line by being inverted every time a selection voltage is applied to the scanning line.
The third power supply line is supplied with one voltage on the lower side or the higher side over a period of at least one frame,
A voltage for turning off the fifth transistor is supplied to the control line,
In the second mode,
The scanning line driving circuit includes a first operation for sequentially applying the selection voltage to the plurality of scanning lines, and a second operation for sequentially applying the selection voltage to the partial scanning lines. It repeats alternately with a period longer than a predetermined period,
During the first and second operations, a voltage that turns the third transistor on and off is inverted and supplied to the first power supply line every time a selection voltage is applied to the scanning line. ,
The third power supply line is supplied with one voltage on the lower side or the higher side over a period of at least one frame,
The control line is supplied with a voltage that turns on the fifth transistor over part or all of the period from the end of the first operation to the start of the second operation, and the fifth line is supplied over the other period. The drive circuit for the electro-optical device according to claim 5, wherein a voltage for turning off the transistor is supplied. A plurality of scanning lines, a plurality of data lines, a plurality of common electrodes provided on each of the plurality of scanning lines,
Provided corresponding to the intersection of the scan line and the data line,
One end of the pixel switching element is connected to the data line and becomes conductive when a selection voltage is applied to the scanning line;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to the common electrode;
A pixel having a gradation according to the holding voltage of the pixel capacitor,
A scanning line driving circuit for applying the selection voltage to the plurality of scanning lines in a predetermined order;
A common electrode driving circuit for individually driving the plurality of common electrodes;
A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the selection voltage is applied via the data line;
Comprising
The common electrode driving circuit is provided for each common electrode.
A switch circuit that is set to an on or off state according to a voltage held in the gate electrode, and that applies either a low-side voltage or a high-side voltage to the common electrode when the on-state is set. ,
A first application circuit that applies an on-voltage that sets the switch circuit to an on state to the gate electrode of the switch circuit when the selection voltage is applied to a scanning line that is paired with the common electrode;
When there is an instruction through a predetermined control line after the application of the selection voltage to the scanning line is completed, a second voltage is applied to either the low-side or the high-side for each of the common electrodes. Two application circuits;
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 7.

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