JP2009162983A - Electro-optical device, driving circuit, driving method, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress display unevenness which occurs in a lateral direction in configuration of changing the voltage of a common electrode 108. <P>SOLUTION: A pixel 110 includes pixel capacity and storage capacity with one end connected to a pixel electrode and with the other end connected to the common electrode 108. The common electrode 108 is provided corresponding to each of 1-320 lines, and has TFT 171 in each of the 1-320 lines. The common electrode 108 in a certain i-th line applies either one of low voltage and high voltage in a second period out of a temporally forward first period and a temporally backward second period of a period of applying selection voltage to a scanning line in the i-th line. When a first voltage is applied in the second period, a third voltage further lower than the first voltage is applied beforehand in the first period, and when a second voltage is applied in the second period, a fourth voltage further higher than the second voltage is applied beforehand in the first period. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for suppressing display unevenness generated in a horizontal direction when a voltage of a common electrode is changed in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. In order to suppress the voltage amplitude of the data line when the pixel capacitor is AC driven. The common electrode is individualized for each scanning line (each row), and when the scanning line is selected, the common electrode corresponding to the selected scanning line is set to one of binary voltages corresponding to the writing polarity. A technique is known (see Patent Document 1).
See Japanese Patent Application Laid-Open No. 2005-3000948

However, in this technique, when the common electrode is set to one of the binary voltages, if the resistance to the common electrode is large, display unevenness is caused.
The present invention has been made in view of such circumstances, and one of its purposes is to provide a technique for suppressing the occurrence of display unevenness in a configuration in which common electrodes are individually driven.

  In order to achieve the above object, a drive circuit of an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of common electrodes provided corresponding to the plurality of scanning lines, Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each of which is connected to the data line and is in a conductive state when a selection voltage is applied to the scanning line. A pixel switching element, and a pixel including one end connected to the other end of the pixel switching element and the other end connected to a common electrode. A scanning line driving circuit that selects a plurality of scanning lines in a predetermined order and applies a selection voltage to the selected scanning line, and a common electrode provided corresponding to the scanning line to which the selection voltage is applied, Selection voltage is applied Between the first period closer to the front and the second period closer to the rear, either the first voltage or the second voltage higher than the first voltage is applied in the second period. In addition, when applying the first voltage in the second period, a third voltage lower than the first voltage is applied in advance in the first period, and the second voltage is applied in the second period. In the case of applying, a common electrode driving circuit that applies a fourth voltage higher than the second voltage in the first period in advance, and a pixel corresponding to the scanning line to which the selection voltage is applied, A data line driving circuit for supplying a data signal having a voltage corresponding to the gray level of the pixel through the data line. According to the present invention, the third (fourth) voltage that is excessively swung in the voltage change direction is applied to the one common electrode during the period in which the selection voltage is applied to the scanning line in order to write the voltage to the pixel capacitor. After that, since the first (second) voltage is applied, even when the resistance to the common electrode is large at the end of the application of the selection voltage, the first (second) voltage can be approached.

In the present invention, the common electrode driving circuit has a transistor corresponding to each of the common electrodes, and the transistor corresponding to one common electrode has a scanning line whose gate electrode corresponds to the one common electrode. The common electrode corresponding to the scanning line to which the selection voltage is applied is preferably supplied through the power supply line, with the source electrode connected to the power supply line that supplies the common signal.
In this configuration, the common electrode is provided corresponding to each of the common electrodes, and each of the common electrode and the detection line is applied when the selection voltage is applied to the scanning line corresponding to the one common electrode. A switching element for detection that is turned on in between, a voltage obtained by buffering the third or fourth voltage in the first period, and a control that controls the detection line to be the first or second voltage in the second period It is preferable to further include a common signal output circuit that outputs the obtained voltage as the common signal to the feeder line.
Among the selection voltage application periods, in the first period closer to the front in time, the voltage difference between the common electrode and the detection line may be large, so the voltage of the detection line suddenly becomes the first (second) voltage. Such a control may cause a problem that a large amount of current flows or oscillates. In this configuration, since such control is not performed in the first period, only the buffering is performed so that the voltage difference is reduced, and then the control is performed in the second period thereafter, the above-described problem. Occurrence is suppressed.
As a configuration of such a common signal output circuit, a target signal that becomes the third or fourth voltage in the first period and becomes the first or second voltage in the second period is input to a non-inverting input terminal. , An operational amplifier whose output terminal is connected to the power supply line, and an electrical terminal between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier, and is turned on in the first period, and in the second period. A first switch that is turned off, and a second switch that is electrically inserted between the detection line and the inverting input terminal of the operational amplifier, and is turned off in the first period and turned on in the second period. It is possible.
The common signal output circuit further includes an auxiliary switch that is turned on between the power supply line and the detection line in a temporally forward period in a period in which a selection voltage is applied to one scanning line. It is good also as a structure. According to such a configuration, when the auxiliary switch is turned on, the common signal output by the common signal output circuit is shared not only by the path via the feeder line and the transistor but also by the path via the detection line and the auxiliary switch. The electrode can be supplied.

  In the present invention, the common electrode driving circuit has a set of first to fourth transistors corresponding to each of the common electrodes, and the first transistor corresponding to one common electrode is a source electrode. Is connected to a first feed line that feeds a first common signal, the second transistor has a source electrode connected to a second feed line that feeds a second common signal, and drain electrodes of the first and second transistors Is connected to the one common electrode, the third transistor has a gate electrode connected to the scanning line corresponding to the one common electrode, and a source electrode connected to the first signal line to which the first gate signal is supplied. The drain electrode is connected to the gate electrode of the first transistor; the fourth transistor has a gate electrode connected to the scanning line corresponding to the one common electrode; The second electrode is connected to a second signal line to which a second gate signal is supplied, the drain electrode is connected to the gate electrode of the second transistor, and the first and second gate signals are the first and second The voltage is used to turn on and off the transistors exclusively, and power is supplied to the common electrode corresponding to the scanning line to which the selection voltage is applied via the first power supply line or via the second power supply line. It is good also as a structure which prescribes | regulates whether to do. According to this configuration, since the common electrode is connected to the first or second feeder line even in the non-selection period, the period in which the potential is indefinite can be eliminated or minimized.

The common electrode is provided corresponding to each of the common electrodes, and each of the common electrodes is provided between the common electrode and the detection line when the selection voltage is applied to the scanning line corresponding to the common electrode. In the case where the detection switching element that is turned on and the common electrode corresponding to the scanning line to which the selection voltage is applied are fed through the first feeding line, the third or fourth in the first period. A voltage obtained by buffering the voltage and controlling the voltage of the detection line to be the first or second voltage in the second period is output to the first power supply line as the first common signal, respectively. On the other hand, when power is supplied to the common electrode corresponding to the scanning line to which the selection voltage is applied via the second power supply line, the third or fourth voltage is buffered in the first period. A common signal output circuit that outputs a voltage that is controlled so that the voltage of the detection line becomes the first or second voltage in the second period, as the second common signal, respectively, It is good also as a structure which further has. According to this configuration, it is possible to suppress the occurrence of a problem that a large amount of current flows or oscillates.
Further, the first and second gate signals are determined so as to alternate between when power is supplied to one common electrode through the first power supply line and through the second power supply line. It is good also as composition to do. According to this configuration, the ON period of the first and second transistors is shortened, so that characteristic deterioration can be prevented.
The present invention can be conceptualized not only as a driving circuit for an electro-optical device, but also as a driving method, an electro-optical device, and an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, in the electro-optical device 10, a scanning line driving circuit 140, a common electrode driving circuit 170, and a data line driving circuit 190 are arranged around the display region 100, and the control circuit 20 includes these components. Each part is controlled individually.

The display area 100 is an area in which the pixels 110 are arranged. In this embodiment, 320 scanning lines 112 are provided so as to extend in the row (X) direction, and 240 data lines 114 are arranged in the column. It is provided so as to extend in the (Y) direction. The pixels 110 are arranged corresponding to the intersections of the scanning lines 112 in the 1st to 320th rows and the data lines 114 in the 1st to 240th columns. Therefore, in the present embodiment, the pixels 110 are arranged in a matrix of 320 vertical rows × 240 horizontal columns in the display area 100. However, the present invention is not intended to be limited to this arrangement.
Corresponding to the scanning lines 112 in the 1st to 320th rows, the common electrodes 108 are provided extending in the X direction.

A detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram showing the configuration of the pixel 110, corresponding to the intersection of the i row and the (i + 1) row adjacent thereto in the downward direction and the j column and the (j + 1) column adjacent thereto in the right direction. A 2 × 2 configuration for a total of four pixels is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 110 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 110 are arranged. It is a symbol in the case of showing generally, and is an integer of 1 or more and 240 or less.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, And a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in the i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to one end of the pixel capacitor 120 and the storage capacitor 130, respectively. The other end of the pixel capacitor 120 and the other end of the storage capacitor 130 are connected to the common electrode 108, respectively.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the scanning lines 112 of i and (i + 1) rows, respectively, and Ci and C (i + 1) indicate i and (i + 1) rows, respectively. The voltage of the common electrode 108 of the eye is shown. The optical characteristics and the like of these pixel capacitors 120 will be described later.

Returning again to FIG. 1, the control circuit 20 outputs various control signals to control each part in the electro-optical device 10, and the common signal Vc is supplied to the common electrode driving circuit 170 via the feeder line 161. To supply.

As described above, peripheral circuits such as the scanning line driving circuit 140, the common electrode driving circuit 170, and the data line driving circuit 190 are provided around the display region 100.
Among these, the scanning line driving circuit 140 scans the scanning signals Y1, Y2, Y3,..., Y320 in the first, second, third,. The line 112 is supplied. Specifically, the scanning line driving circuit 140 selects the scanning lines 112 in the order of the first, second, third,..., 320th rows from the top in FIG. The H level corresponding to the voltage Vdd is set, and the scanning signals to the other scanning lines are set to the L level corresponding to the non-selection voltage Vss.
As shown in FIG. 4, the scanning line driving circuit 140 sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly.
The scanning signals Y1, Y2, Y3, Y4,..., Y320 are set to the H level in this order.
In this embodiment, in the period of one frame, as shown in the figure, in addition to the vertical effective scanning period Fa from when the scanning signal Y1 becomes H level to when the scanning signal Y320 becomes L level, Other vertical blanking periods are included. A period during which one row of scanning lines 112 is selected is a horizontal scanning period H.

  In the present embodiment, the common electrode driving circuit 170 includes n-channel TFTs 171 (transistors) provided corresponding to the common electrodes 108 in the first to 320th rows. Here, the TFT 171 corresponding to the i-th common electrode 108 will be described. The gate electrode of the TFT 171 is connected to the i-th scanning line 112, its source electrode is connected to the power supply line 161, and its drain The electrode is connected to the i-th common electrode 108.

The data line driving circuit 190 is a voltage corresponding to the gradation for the pixel 110 located on the scanning line (selected scanning line) selected by the scanning line driving circuit 140 and is designated by the polarity instruction signal Pol. A data signal having a voltage corresponding to the polarity is supplied to the data line 114.
Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation value (brightness) of the corresponding pixel 110. Display data Da for designating the data is stored. The display data Da stored in each storage area is supplied with the changed display data Da by the control circuit 20 when the display contents are changed, and the contents of the storage area are rewritten.
The data line driving circuit 190 reads out the display data Da of the pixels 110 located on the selected scanning line for one row from the storage area, and at a voltage corresponding to the gradation specified by the read display data and the specified polarity. The operation of converting to a data signal and supplying it to the data line 114 is executed for each of the 1st to 240th columns positioned at the selected scanning line.

Further, the control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at the timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 outputs the scanning signals Y1, Y2, Y3, Y4,..., Y320 by sequentially shifting the start pulse Dy according to the clock signal Cly. The start timing of this period is the timing at which the logic level of the clock signal Cly transitions. Therefore, the data line driving circuit 190 knows which scanning line is selected by continuing to count the latch pulse Lp from the start of the period of one frame, for example.
Furthermore, the selection start timing can be known from the supply timing of the latch pulse Lp.

The write polarity is designated by a polarity designation signal Pol output by the control circuit 20. Specifically, in this embodiment, the polarity designation signal Pol is supplied to odd-numbered 1, 3, 5,..., 319 lines in a period of one frame (denoted as “n frame”) as shown in FIG. In the period when the scanning signal is at the H level, the positive writing is designated, and the scanning signal to even rows 2, 4, 6,. Specifies sex writing. Therefore, in this embodiment, a scanning line inversion (line inversion) method in which the writing polarity to the pixel is inverted for each scanning line is employed.
In addition, in the next (n + 1) frame, the polarity instruction signal Pol becomes L level during a period when the scanning signal to the odd-numbered row is H level, and becomes H level during the period when the scanning signal to the even-numbered row is H level. Thus, the writing polarity is inverted for each row as compared with the n frame. The reason for reversing the writing polarity in this way is to prevent deterioration of the liquid crystal due to application of a DC component.
As for the writing polarity in the present embodiment, when the voltage is held in the pixel capacitor 120, the case where the potential of the pixel electrode 118 is set higher than the voltage of the common electrode 108 is called positive polarity, and the lower level. The case of the side is called negative polarity. As for the voltage, unless otherwise specified, the ground potential of a power source (not shown) is used as a reference for zero voltage.

If the positive polarity writing is designated for a pixel in a certain row by the polarity instruction signal Pol, the common signal Vc is closer to the front in the period in which the scanning signal to the row is at the H level. In the period Ha, the voltage (Vsl−Va) is reached, and in the remaining period, the time Hb, which is closer to the rear, the voltage Vsl is reached. On the other hand, if negative polarity writing is designated, the scanning signal to the row is H In the period of level, the voltage (Vsh + Va) is obtained in the period Ha, and the voltage Vsh is obtained in the period Hb.
Here, the voltages Vsl and Vsh have a relationship of (Vss ≦) Vsl <Vsh (≦ Vdd), and the voltage Vsl (first voltage) is relatively lower than the voltage Vsh (second voltage). ing.

  In the present embodiment, the display region 100 has a configuration in which a pair of substrates of an element substrate and a counter substrate are bonded to each other while maintaining a certain gap, and the liquid crystal 105 is sealed in the gap. Here, the scanning line 112, the data line 114, the common electrode 108, the pixel electrode 118, and the TFTs 116 and 171 are formed on the element substrate, and are bonded so that the electrode formation surface faces the counter substrate. . FIG. 3 is a plan view showing the vicinity of the boundary between the display region 100 and the common electrode driving circuit 170 in this configuration.

As can be seen from FIG. 3, the display region 100 is an FFS (fringe field switching) mode, which is a modification of the IPS mode in which the electric field direction applied to the liquid crystal is the substrate surface direction. In this embodiment, the TFTs 116 and 171 are amorphous silicon types, and are bottom gate types in which the gate electrodes are located below the semiconductor layer (the back side of the drawing).
Specifically, the scanning line 112, the common electrode 108, and the connection wiring are formed by patterning the gate electrode layer serving as the first conductive layer, a gate insulating film (not shown) is formed thereon, and the TFT semiconductor is further formed. The layer is formed in an island shape. A comb-shaped pixel electrode 118 is formed on the semiconductor layer by patterning an ITO (indium tin oxide) layer serving as a second conductive layer via a protective layer, and further, aluminum serving as a third conductive layer. In addition to the TFT source electrode and drain electrode, various connection electrodes are formed in addition to the data line 114 and the power supply line 161 by patterning the metal layer.

In the present embodiment, the storage capacitor 130 is a capacitance component generated by a stacked structure in which the pixel electrode 118 and the common electrode 108 are interposed via an insulating layer. In addition, since liquid crystal is also sealed in the gap between the element substrate and the counter substrate, a capacitance component is generated between the pixel electrode 118 and the common electrode 108 due to the structure through the liquid crystal serving as a dielectric. In the present embodiment, the capacitive component resulting from the liquid crystal is a pixel capacitor 120.
In this configuration, an electric field corresponding to the holding voltage of the parallel capacitor of the pixel capacitor 120 and the storage capacitor 130 is generated in the X direction along the element substrate surface and orthogonal to the comb teeth of the pixel electrode 118, and the liquid crystal The orientation state of the is changed. Thereby, the amount of light passing through the polarizer (not shown) becomes a value corresponding to the effective value of the holding voltage.
In this embodiment, the FFS mode is used. However, the IPS mode may be used, and other modes may be used as long as the electrical equivalent circuit is a circuit as shown in FIG.

Since the holding voltage of the parallel capacitor is a difference voltage between the pixel electrode 118 and the common electrode 108, the scanning signal Yi is set to the H level and the TFT 116 is turned on in order to set the pixel in i row and j column to the target gradation. The data signal Xj having a voltage such that the difference voltage becomes a value corresponding to the gradation of the pixel is set via the data line 114 in the j-th column and the TFT 116 turned on in the i-th row and j-th column. Thus, it may be supplied to the pixel electrode 118.
In the present embodiment, for convenience of explanation, if the voltage effective value is close to zero, the light transmittance is maximized to display white, while the amount of transmitted light decreases as the voltage effective value increases. Finally, a normally white mode in which the black display with the minimum transmittance is set.

On the other hand, the scanning lines 112 in each row are provided so as to extend in the X direction in the display region 100 as described above. Here, the i-th scanning line 112 has a portion branched in the Y (down) direction in the common electrode driving circuit 170, and this branched portion is a gate electrode of the TFT 171.
Further, the drain electrode 108a of the TFT 171 is obtained by patterning the third conductive layer. However, since an insulating layer is interposed between the gate electrode layer and the common electrode 108, the two electrodes are insulated from each other. They are connected by contact holes 108b (denoted by x in the figure) penetrating the layers.
Since the common electrode 108 in each row intersects with the data line 114 in the first to 240th columns via an insulating layer, it is capacitively coupled to each other via a parasitic capacitance as shown by a broken line in FIG. Become.

The configuration shown in FIG. 3 is merely an example, and the TFT type may be another structure, for example, a top gate type in terms of arrangement of gate electrodes, or a polysilicon type in terms of process. Further, instead of building the elements of the common electrode driving circuit 170 on the substrate by the same process as the display region 100, an IC chip may be mounted on the element substrate. When the IC chip is mounted on the element substrate, the scanning line driving circuit 140 and the common electrode driving circuit 170 may be integrated as a semiconductor chip together with the data line driving circuit 190, or may be separate chips. On the other hand, the control circuit 20 may be configured to be built in the element substrate.
In addition, the present embodiment may be a transmissive type, a reflective type, or a so-called transflective type that combines both a transmissive type and a reflective type. For this reason, no particular reference is made to the reflective layer or the like.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
First, in the n frame, the scanning signal driving circuit 140 first sets the scanning signal Y1 to the H level, and the polarity designation signal Pol becomes the H level, and the positive writing is designated for the first row. .
When the latch pulse Lp is output at the timing when the scanning signal Y1 becomes H level,
The data line driving circuit 190 reads out the display data Da of the pixels in the first row and the first to 240th columns, and as the gradation specified by the display data Da becomes darker, the data line driving circuit 190 becomes higher with reference to the voltage Vsl. Are converted into data signals X1 to X240 having the voltages as described above, and supplied to the data lines 114 of 1 to 240 columns, respectively. Thereby, for example, a voltage that is higher than the voltage Vsl is applied to the j-th data line 114 as the data signal Xj as the gradation specified for the pixel 110 in the first row and j-th column becomes darker. .
When the scanning signal Y1 becomes H level, the TFTs 116 in the pixels in the 1st row and 1st column to the 1st row and 240th column are turned on, so that the data signals X1 to X240 are applied to these pixel electrodes 118.

  On the other hand, when the scanning signal Y1 becomes the H level, in the common electrode driving circuit 170, the TFT 171 in the first row is turned on, so that the common electrode 108 in the first row is connected to the power supply line 161. In the horizontal scanning period H in which the scanning signal Y1 is at the H level in the n frame, the positive writing is designated, so the common signal Vc becomes the voltage (Vsl−Va) in the period Ha and becomes the voltage Vsl in the period Hb. Accordingly, at the end of the horizontal scanning period, the common electrode 108 in the first row becomes the voltage Vsl. Therefore, the parallel capacitances of the pixel capacitors 120 and the storage capacitors 130 in the first row and first column to the first row and 240 columns are respectively connected to the respective levels. A positive voltage corresponding to the tone is written.

Next, the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level. When the scanning signal Y1 becomes the L level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned off, and in the common electrode driving circuit 170, the TFT 171 in the first row is also turned off.
Therefore, in each pixel 110 in the first row and the first column to the first row and the 240th column, the pixel electrode 118 is in a high impedance state that is not electrically connected to any portion. Similarly, since 108 is in a high impedance state, the voltage state written in the parallel capacitor of the pixel capacitor 120 and the storage capacitor 130 in the 1st row and 1st column to the 1st row and 240th column is maintained as it is.

Further, when the latch pulse Lp is output at the timing when the scanning signal Y2 becomes H level, the data line driving circuit 190 displays the display data of the pixels in the second row and in the first, second, third,. As Da is read out and the gradation specified by the display data Da becomes darker, it is converted into data signals X1 to X240 of voltages set to the lower side with reference to the voltage Vsh, and the data lines 114 of 1 to 240 columns are respectively applied. Supply. Thus, for example, a voltage that is lower than the voltage Vsh by the voltage specified by the display data Da of the pixel 110 in the 2nd row and jth column is applied to the jth data line 114 as the data signal Xj.
When the scanning signal Y2 becomes H level, the TFTs 116 in the pixels in the 2nd row and the 1st column to the 2nd row and the 240th column are turned on, so that the data signals X1 to X240 are applied to these pixel electrodes 118.
On the other hand, when the scanning signal Y2 becomes H level, in the common electrode driving circuit 170, the TFT 171 in the second row is turned on, so that the common electrode 108 in the second row is connected to the power supply line 161. Since the negative polarity writing is designated in the horizontal scanning period H in which the scanning signal Y2 is at the H level in the n frame, the common signal Vc becomes the voltage (Vsh + Va) in the period Ha and becomes the voltage Vsh in the period Hb. Therefore, since the common electrode 108 in the second row becomes the voltage Vsh at the end of the horizontal scanning period, the parallel capacitance of the pixel capacitor 120 and the storage capacitor 130 in the 2nd row and the 1st column to the 2nd row and 240th column has respective levels. A negative voltage corresponding to the tone is written.

Next, the scanning signal Y2 becomes L level and the scanning signal Y3 becomes H level. When the scanning signal Y2 becomes L level, the TFTs 116 in the pixels of the 2nd row and the 1st column to the 2nd row and the 240th column are turned off and the TFT 171 in the second row is also turned off. Therefore, in each pixel 110 in the 2nd row and the 1st column to the 2nd row and the 240th column, the pixel electrode 118 is in a high impedance state, but the common electrode 108 in the second row is also in a high impedance state. Therefore, the voltage state written in the parallel capacitor of the pixel capacitor 120 and the storage capacitor 130 of 2 rows and 1 column to 2 rows and 240 columns is maintained as it is.

When the scanning signal Y3 becomes H level, a positive voltage corresponding to the gradation is written in the parallel capacitance of the pixel capacitor 120 and the storage capacitor 130 in the third row. Next, the scanning signal When Y4 becomes H level, a negative voltage corresponding to the gradation is written in the parallel capacitor of the pixel capacitor 120 and the storage capacitor 130 in the fourth row.
In the n-th frame, the same operation is repeated up to the 320th row. As a result, a positive voltage corresponding to the gradation is written in the parallel capacitance of the pixel capacitor 120 and the storage capacitor 130 in the odd row, In the parallel capacitors of the pixel capacitors 120 and the storage capacitors 130 in even-numbered rows, negative voltages corresponding to the respective gradations are written. In this manner, voltages corresponding to gradations are written in the parallel capacitors in all the pixels, so that one (frame) image is displayed in the display region 100.

  The same operation is repeated in the next (n + 1) frame. However, since the writing polarity of each row is inverted, the pixel capacitor 120 and the storage capacitor 130 in the odd-numbered row each have a negative electrode corresponding to the gradation. The positive voltage corresponding to the gradation is written in the parallel capacitor of the pixel capacitor 120 and the storage capacitor 130 in the even-numbered row.

Such voltage writing will be described with reference to FIG. FIG. 5 shows scanning voltages of the voltage Pix (i, j) at the pixel electrode 118 in the odd-numbered i rows and j columns and the voltage Pix (i + 1, j) at the pixel electrode 118 in the even-numbered (i + 1) rows and j columns. It is a figure shown in relation to Yi and Y (i + 1).
The common signal Vc becomes a voltage (Vsl−Va) in the period Ha in the horizontal scanning period H in which the scanning signal to the odd-numbered row is H level in the n frame, and the voltage Vsl in the period Hb.
It becomes. Therefore, the voltage Ci of the odd-numbered i-th common electrode 108 also becomes a voltage (Vsl−Va) in the period Ha in the horizontal scanning period H in which the scanning signal Yi is at the H level, as shown in FIG. In the period Hb, the voltage Vsl should be obtained. On the other hand, a data signal Xj of a voltage (shown by ↑ in the drawing) higher than the voltage Vsl by a voltage corresponding to the gray level of the pixel in i row and j column is supplied to the data line 114 in the j column. Is done. When the scanning signal Yi is at the H level, the TFT 116 in the i-th row is turned on, so that the pixel electrode 118 in the i-th row and j-th column becomes the voltage of the data signal Xj. In the parallel capacitor 130, a voltage difference between the voltage Pix (i, j) of the pixel electrode 118 and the voltage Vsl of the common electrode 108, that is, a positive voltage corresponding to the gradation is written. In FIG. 5, the difference voltage corresponds to a hatched portion.

  When the scanning signal Yi becomes the L level, the TFTs 116 and 171 are turned off. Therefore, in the i-th row, the common electrode 108 in the i-th row is also in a high impedance state together with the pixel electrodes 118, and The voltage written in the column is held as it is. In the figure, the broken line portion of the voltage Ci indicates a high impedance state.

Since the negative polarity writing is designated when the scanning signal Yi becomes H level again after the lapse of one frame, the voltage Ci of the common electrode 108 in the odd-numbered i-th row is equal to the H level of the scanning signal Yi. In the horizontal scanning period H that becomes the level, the voltage becomes (Vsh + Va) in the period Ha, and the period Hb
At voltage Vsh. On the other hand, a data signal Xj having a voltage (indicated by ↓ in the drawing) lower than the voltage Vsh by a voltage corresponding to the gradation of the pixel in i row and j column is supplied to the data line 114 in the j column. Is done. As a result, the negative voltage corresponding to the gradation is written in the parallel capacitor of the pixel capacitor 120 and the storage capacitor 130 in the i row and j column.
In the n frame in which positive polarity writing is designated for the i-th row, negative polarity writing is designated for the (i + 1) th row, and negative polarity writing is designated for the i-th row ( In the (n + 1) th frame, positive writing is designated for the (i + 1) th row, and it is inverted every scanning line.

  According to the first embodiment, a data signal having a voltage higher than the voltage Vsl by a voltage corresponding to the gradation is supplied to the pixels in the row in which the positive writing is designated. Since the data signal having a voltage lower than the voltage Vsh by a voltage corresponding to the gradation is supplied to the pixels in the row in which negative polarity writing is designated, the voltage amplitude of the data signal is equal to the common electrode. Compared with the case where the voltage 108 is constant, the voltage becomes narrower. For this reason, the withstand voltage required for the constituent elements of the data line driving circuit 190 can be kept low, the configuration can be simplified correspondingly, and the power consumed unnecessarily by the voltage change can be suppressed. It becomes.

By the way, in the present embodiment, for example, if the positive electrode writing is designated for the i-th row, the common electrode 108 in the i-th row is temporal in the horizontal scanning period H in which the scanning signal Yi becomes H level. If the negative polarity writing is designated while the voltage Vsl becomes equal to the voltage Vsl-Va in the forward period Ha and the voltage Vsl in the backward period Hb, the period Ha is included in the horizontal scanning period. The common signal Vc, which becomes the voltage (Vsh + Va) in the period Hb and becomes the voltage Vsh in the period Hb, is applied through the TFT 171 which is turned on.
Thus, before describing the effect of applying the voltage to the common electrode in two stages in the horizontal scanning period H in which the scanning signal to the scanning line is at the H level, the voltage Vsl is not divided into two stages. Or the problem of the structure which applies only one side of the voltage Vsh is demonstrated.

  When the scanning signal Yi becomes H level and the TFT 116 corresponding to the i-th row is turned on, the pixel capacitor 120 and the storage capacitor 130 are charged with voltages corresponding to the data signals, respectively. The charging current at this time flows to the turned on TFT 171 via the i-th common electrode 108. Here, various capacitances are actually parasitic on the common electrode 108 in each row, and a kind of integration circuit is formed by the on-resistance of the TFT 171. Therefore, in the i-th common electrode 108, when positive writing is designated, the change from the voltage Vsh to the voltage Vsl when the scanning signal becomes H level is not ideally pulsed. As shown in FIG. 6A, the waveform becomes dull.

  Further, since the common electrodes 108 in the 1st to 320th rows intersect with the data lines 114 in the 1st to 240th columns, respectively, while maintaining electrical insulation, the data lines in each column are indicated by broken lines in FIG. It couple | bonds with 114 through a capacity | capacitance. Therefore, the common electrode 108 in each row is also affected by the voltage change of the data line 114.

Here, the voltage change direction of the data line is determined according to the display content in the display region 100. For example, in the common electrode 108 in the i-th row, the common in the i-th row when the scanning signal Yi becomes H level. When the voltage change direction at the electrode is opposite to the voltage change of the data line, the i-th common electrode 108 is greatly affected by the voltage change of the data line 114. Specifically, when the positive polarity writing is designated and the scanning signal Yi becomes H level, the common electrode 108 in the i-th row drops from the voltage Vsh toward the voltage Vsl, but the voltage of the data line If the change is in the upward direction, a differential pulse (positive noise) in the positive direction as shown in FIG. 6A is superimposed on the i-th common electrode 108.
Therefore, the voltage Ci of the i-th common electrode 108 actually deviates from the voltage Vsl by the voltage ΔV when viewed at the end timing of the horizontal scanning period, as shown in FIG. To do. Since the data signal supplied when the scanning signal Yi becomes H level is determined with reference to the voltage Vsl, the i-th common electrode 108 is shifted from the voltage Vsl by the voltage ΔV due to waveform dullness or noise. As a result, the pixel capacitor 120 and the storage capacitor 13
The parallel capacitor of 0 holds not the voltage corresponding to the gradation but the voltage shifted by ΔV from the voltage corresponding to the gradation, and the optical characteristics (transmittance or reflectance) corresponding to the held voltage. ) Will end up.

This phenomenon occurs not only in i row and j column but also in one row of pixels corresponding to the common electrode 108 in the i row, so that it is visually recognized as uneven display in the horizontal direction.
Here, the influence of waveform dullness and positive noise when positive polarity writing is designated for the i-th row has been described, but even when negative polarity writing is designated, only the direction is different but the same. Since waveform dullness and negative noise occur, the voltage Ci of the i-th common electrode 108 actually deviates from the voltage Vsh by the voltage ΔV, as shown in FIG. 6B. Furthermore, although the voltage Ci of the common electrode 108 in the i-th row has been described here, the same occurs in the adjacent (i + 1) -th row, that is, the same occurs in the 1st to 320th rows.

Note that the influence of the blunting due to the on-resistance of the TFT 171 and the voltage change of the data line is dominant because various conditions such as the configuration of the panel and the driving method are entangled. . If the influence of waveform dullness is large, the on-resistance of the TFT 171 may be reduced, but the TFT 171 requires a large transistor size. When the transistor size of the TFT 171 is increased, the outer area (so-called frame) of the display region 100 is enlarged when the TFT 171 is built in the element substrate.
In any case, a state in which each common electrode 108 does not correctly reach the voltage Vsl or the voltage Vsh occurs at the end of the horizontal scanning period, that is, by the timing when the TFT 171 is turned off.

On the other hand, in the present embodiment, if positive polarity writing is designated for the i-th row, the common signal Vc is the forward period Ha of the horizontal scanning period H in which the scanning signal Yi is at the H level. The voltage (Vsl−Va) is obtained at, and when the voltage Vsh changes to the voltage Vsl, the voltage Va is excessively shaken. For this reason, since positive noise attenuates rapidly, the voltage Ci of the i-th common electrode 108 is actually as shown in FIG. At this time, the positive noise may not be completely lost depending on the display content, or the voltage Ci of the common electrode 108 may be swung to the lower side exceeding the target voltage Vsl. Even in such a case, the difference from the voltage Vsl is negligible. Since the common signal Vc becomes the target voltage Vsl in the rearward period Hb, the influence of the positive noise becomes so small that it can be ignored, and the voltage Ci of the common electrode can be converged to almost the voltage Vsl.
If negative polarity writing is designated for the i-th row, the common signal Vc becomes a voltage (Vsh + Va) in the period Ha and is excessively swung by the voltage Va when changing from the voltage Vsl to the voltage Vsh. As shown in FIG. 6D, the influence of negative noise also becomes so small that it can be ignored, and the voltage Ci of the common electrode can be converged to the voltage Vsh.

  Therefore, according to the present embodiment, the common electrode 108 of the selected row can be converged to almost the voltage Vsl or the voltage Vsh by the end of the horizontal scanning period. It is possible to suppress the occurrence of display unevenness that occurs in the horizontal direction while reducing the amplitude, and it is not necessary to reduce the on-resistance of the TFT 171 and the like, so that the frame is narrowed and the area of the display region 100 is increased. Is also possible.

<Application and modification of the first embodiment>
In the first embodiment described above, the following applications and modifications are possible. That is, in the first embodiment described above, the writing polarity is inverted for each scanning line, but a plane inversion (frame inversion) method in which the writing polarity in the frame period is the same over each row may be used. In the case of the frame inversion method, for example, the polarity designation signal Pol and the common signal Vc are as shown in FIG.
That is, in the case of the surface inversion method, the polarity designation signal Pol is inverted every frame period, and the common signal Vc is included in the period during which the selection voltage is applied to the scanning line if positive polarity writing is designated. In the period Ha, the voltage (Vsl−Va) is obtained, and in the period Hb, the voltage Vsl is obtained.
If negative-polarity writing is designated, the voltage (Vsh + Va) is set in the period Ha and the voltage Vsh is set in the period Hb in the period in which the selection voltage is applied to the scanning line.

  In addition, since the characteristics of the TFT 171, particularly the on-resistance, tend to change depending on the ambient temperature, the degree of waveform dullness when the voltage of the common electrode changes changes according to the temperature. For this reason, the voltage ± Va that fluctuates the voltages Vsl and Vsh in the period Ha may be changed according to the temperature. In the horizontal scanning period H in which the selection voltage is applied to one scanning line, the period Ha, The ratio of Hb may be changed, or both the voltage ± Va and the ratios of the periods Ha and Hb may be changed.

Second Embodiment
Next, an electro-optical device according to a second embodiment of the invention will be described. FIG. 8 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment.
8 differs from the first embodiment shown in FIG. 1 mainly in that TFTs 175 are provided corresponding to each row, a detection line 185 and a common signal output circuit 31 are provided, and The control circuit 20 outputs the target signal Vcref and the period specifying signal Hs.
Therefore, the following will be described focusing on these differences.

  First, the common electrode driving circuit 170 is provided with TFTs 175 that function as switching elements for detection corresponding to the common electrodes 108 in each row. Here, the gate electrode of the i-th TFT 175 is connected to the i-th scanning line 112, the source electrode is connected to the i-th common electrode 108, and the drain electrode is connected to the detection line 185. The detection line 185 is commonly connected to the drain electrode of the TFT 175 in each row.

FIG. 9 is a plan view showing the configuration of the common electrode driving circuit 170 and the vicinity of the display area 100 in the element substrate according to the second embodiment.
The configuration shown in this figure is substantially the same as the example shown in FIG. 3 except for the TFT 175 and its periphery. The gate electrode of the i-th TFT 175 is a portion branched from the i-th scanning line 112 in a T-shape in the Y (downward) direction. Further, the drain electrode 108a of the TFT 171 corresponding to the i-th row also serves as the source electrode of the TFT 175 corresponding to the i-th row, and the contact of the i-th row through the contact hole 108b penetrating the gate insulating film and the protective layer. Connected to the common electrode 108. Further, the wide portion of the detection line 185 is the drain electrode of the TFT 175.

FIG. 10 is a diagram illustrating a configuration of the common signal output circuit 31.
As shown in this figure, the common signal output circuit 31 includes an operational amplifier 300, switches 311 and 312, a NOT circuit 315, and a resistance element 316.
The output terminal of the operational amplifier 300 is connected to one end of the power supply line 161 and the switch 311, and the detection line 185 is connected to one end of the switch 312. The other ends of the switches 311 and 312 are commonly connected to the inverting input terminal (−) of the operational amplifier 300. In other words, the switch 311 (first switch) is electrically inserted between the output terminal (feed line 161) and the inverting input terminal (−) of the operational amplifier 300, and the switch 312 (second switch) is It is electrically inserted between the detection line 185 and the inverting input terminal (−).

On the other hand, the target signal Vcref from the control circuit 20 is supplied to the non-inverting input terminal (+) of the operational amplifier 300. In addition to the switch 311, a resistance element 316 is inserted between the output terminal and the inverting input terminal (−) of the operational amplifier 300.
The switches 311 and 312 are exclusively turned on / off according to the logic level of the period specifying signal Hs supplied from the control circuit 20. Specifically, the switches 311 and 312 are turned on and off when the period designation signal Hs is at the H level, and are turned off and on when the period designation signal Hs is at the L level.

Here, as shown in FIG. 11, the period designation signal Hs becomes H level in the forward period Ha during the horizontal scanning period H in which the selection voltage is applied to a certain scanning line, and the rearward direction. It is a signal that becomes L level during the period Hb. On the other hand, the target signal Vcref supplied from the control circuit 20 has the same waveform as the common signal Vc in FIG. 4 as shown in FIG.

In such a configuration, when the scanning signal Yi is at the H level, the i-th TFT 175 is turned on, so that the i-th common electrode 108 is connected to the detection line 185. However, since the switch 312 is turned off in the period Ha, the voltage of the detection line 185 does not affect the output of the common signal output circuit 31.
Further, since the switch 311 is turned on in the period Ha, the operational amplifier 300 becomes a voltage follower circuit. For this reason, in the period Ha, the common signal output circuit 31 buffers the voltage of the target signal Vcref as it is and outputs it to the feeder line 161 as the common signal Vc.
Here, the target signal Vcref becomes the voltage (Vsl−Va) if the positive polarity writing is designated for the i-th row in the period Ha, and the voltage (Vsl−Va) if the negative polarity writing is designated. Vsh + Va), and in the second embodiment, this voltage is supplied to the power supply line 161 as it is, so that the influence of the waveform dullness and noise can be rapidly attenuated as in the first embodiment.

Next, in the period Hb, the switches 311 and 312 are turned off and on, respectively, and the detection line 1
The voltage 85 is fed back to the inverting input terminal (−) of the operational amplifier 300. Therefore, in the period Hb, the common signal output circuit 31 outputs the common signal Vc controlled so that the voltage of the detection line 185 becomes the voltage of the target signal Vcref.
Here, in the horizontal scanning period H in which the scanning signal Yi is at the H level, the (actual) voltage of the i-th common electrode 108 appears on the detection line 185 by the i-th TFT 175. On the other hand, the target signal Vcref is the voltage Vsl if positive polarity writing is designated for the i-th row in the period Hb, and is the voltage Vsh if negative polarity writing is designated. For this reason, in the period Hb, if the positive polarity writing is designated for the i-th common electrode 108 in the period Hb, the negative polarity writing is designated so as to be the voltage Vsl. If so, negative feedback control is performed so that the voltage Vsh is obtained.

Therefore, according to the second embodiment, as compared with the first embodiment, the common electrode 108 in the i-th row is connected to the waveform dullness or noise by the end of the horizontal scanning period H when the scanning signal Yi becomes H level. Regardless of the degree, the voltage Vsl or the voltage Vsh can be stabilized more accurately.
Therefore, according to the second embodiment, similarly to the first embodiment, the voltage amplitude of the data line can be reduced, the transistor size of the TFT 171 does not need to be increased as necessary, and the first embodiment is performed. Compared with the form, it is possible to more reliably suppress the occurrence of display unevenness that occurs in the horizontal direction.
Further, for example, the common electrode 108 in the i-th row is close to the voltage Vsh immediately after the scanning signal Yi becomes the H level when the positive polarity writing is designated, so that the difference from the voltage Vsl is large and the negative polarity writing is designated. Sometimes, immediately after the scanning signal Yi becomes H level, it is close to the voltage Vsl, so the difference from the voltage Vsh is large. Therefore, in a configuration in which negative feedback control is performed so that the common electrode 108 (detection line 185) in the i-th row becomes the voltage Vsl or the voltage Vsh over the horizontal scanning period H in which the scanning signal Yi is at the H level, the scanning signal Yi is H Immediately after reaching the level, the current consumed by the operational amplifier 300 may increase or the operational amplifier 300 may oscillate. However, in the second embodiment, in the period Ha immediately after the scanning signal Yi becomes the H level, it functions as a simple voltage follower circuit, not as a negative feedback control, so such a possibility is extremely small.
In addition, although operation | movement description is represented and represented here by the i-th line, about 1-320 lines, it is performed in order similarly.

<Application and Modification of Second Embodiment>
In the second embodiment, the following applications and modifications are possible.
Specifically, as shown in FIG. 12, in the common signal output circuit 31, between the power supply line 161 (the output terminal of the operational amplifier 300) and the detection line 185, for example, if the period specifying signal Hs is H level, the signal is turned on. A switch 318 (auxiliary switch) may be inserted.
As described above, in the period Ha, the operational amplifier 300 becomes a voltage follower circuit, so that the voltage of the target signal Vcref is directly output to the feeder line 161 as the common signal Vc.
It is supplied to the common electrode 108 via the TFT 171 in the on state. In this configuration, when the switch 318 is turned on, the power supply line 161 is connected to the detection line 185. Therefore, the common signal Vc is also supplied to the common electrode 108 through the path of the switch 318, the detection line 185, and the TFT 175 in the on state. To be supplied. That is, in the configuration shown in FIG. 12, there are two paths for supplying the common signal Vc to the common electrode 108 in the period Ha.
Therefore, according to the configuration, in the period Ha, the combined resistance value from the output terminal of the operational amplifier 300 to the common electrode 108 is the denominator of the sum of the resistance values in the two paths, and the product of the resistance values is the numerator. Since it can be reduced to a fraction, the influence of waveform dullness can be particularly suppressed.

In this configuration, the signal flow in the TFT 175 is in the direction from the common electrode 108 to the detection line 185 in the period Hb, but is in the direction from the detection line 185 to the common electrode 108 in the period Ha. The TFT 175 is preferably not a single channel, but a transmission gate (analog switch) combining both p-type and n-type.
Further, in this configuration, the ON period of the switch 318 and the ON period of the switch 311 (the OFF period of the switch 312) are matched with each other, but without being matched, either one is turned off first. And may be controlled. Note that. When the switch 318 is controlled independently of the switches 311 and 312, the control signal increases.

<Third Embodiment>
In the first and second embodiments described above, when the scanning signal Y (i + 1) is changed from the H level to the L level, the scanning electrode Yi is again set to the H level after a period of one frame has elapsed. Until it becomes, it will be in the high impedance state (floating state) which is not electrically connected to any part. Since the common electrode 108 in each row is coupled to other wirings that intersect (or are close to each other) via parasitic capacitance, the common electrodes 108 are easily affected by voltage fluctuations in these wirings.
Therefore, a third embodiment in which the voltage is determined without setting the common electrode 108 in each row to a high impedance state will be described.

FIG. 13 is a block diagram illustrating a configuration of an electro-optical device according to the third embodiment of the invention.
As shown in this figure, the common electrode driving circuit 170 in the third embodiment is composed of a set of TFTs 171a, 171b, 172a, 172, 175 with respect to the common electrodes 108 in the first to 320th rows.
Here, the i-th row will be described. The source electrode of the TFT 171a (first transistor) is connected to the first power supply line 161a, and the gate electrode is connected to the drain electrode of the TFT 172a. The source electrode of the TFT 171b (second transistor) is connected to the second power supply line 161b, and the gate electrode is connected to the drain electrode of the TFT 172b. On the other hand, the drain electrodes of the TFTs 171a and 171b are commonly connected to the i-th common electrode 108.
The source electrode of the TFT 172a (third transistor) is connected to the first signal line 163a, the source electrode of the TFT 172b (fourth transistor) is connected to the second signal line 163b, and the gate electrodes of the TFTs 172a and 172b are Both are commonly connected to the i-th scanning line 112.
The TFT 175 is the same as that in the second embodiment.

Gate signals Vg1 and Vg2 are supplied from the control circuit 20 to the first signal line 163a and the second signal line 163b, respectively. Among these, as shown in FIG. 16, the gate signal Vg1 has the same waveform as the polarity designation signal Pol, and the gate signal Vg2 is a signal obtained by inverting the logic level of the gate signal Vg1. That is, the logic levels of the gate signals Vg1 and Vg2 are mutually exclusive.
Here, among the logic levels of the gate signals Vg1 and Vg2, the L level is a voltage that turns the TFT off (the source and the drain are not conducting) even if it is applied to the gate electrodes of the TFTs 171a and 171b. Further, the H level is a voltage that turns on the TFT (the source and drain are conductive) when it is applied to the gate electrodes of the TFTs 171a and 171b.
The first power supply line 161a is supplied with the first common signal Vc1 from the first common signal output circuit 33, and the second power supply line 161b is supplied with the second common signal Vc2 from the second common signal output circuit 35. Is done.

On the other hand, the switch 40 distributes the detection line 185 to one of the signal lines 187 and 188 according to the logic level of the signal Sel-a supplied from the control circuit 20. Specifically, the switch 40 connects the detection line 185 to the signal line 187 when the signal Sel-a is at the H level, and connects to the signal line 188 when the signal Sel-a is at the L level. Here, the signal Sel-a has the same waveform as the polarity designation signal Pol, as shown in FIG. Therefore, the switch 40 connects the detection line 185 to the signal line 187 when positive polarity writing is designated, and to the signal line 188 when negative polarity writing is designated. .

FIG. 14 is a plan view showing a configuration of the common electrode driving circuit 170 and the vicinity of the display area 100 in the element substrate according to the third embodiment.
This figure will be described in the i-th row. The gate electrodes of the TFTs 172a and 172b share a portion branched in a T shape from the i-th scanning line 112 in the Y (downward) direction. Among these, the source electrode of the TFT 172a undercrosses the second signal line 163b by a connection wiring in which the gate electrode layer is patterned and is connected to the first signal line 163a, while the drain electrode of the TFT 172a is connected to the gate electrode of the TFT 171a. It is connected. The source electrode of the TFT 172b is a portion where the second signal line 163b is widened, and the drain electrode of the TFT 172b is connected to the gate electrode of the TFT 171b.
Further, the source electrode of the TFT 171a is a portion where the first power supply line 161a is wide, and similarly, the source electrode of the TFT 171b is a portion where the second power supply line 161b is wide. The common drain electrodes of the TFTs 171a and 171b are connected to the i-th common electrode 108.

The first common signal output circuit 33 has the same configuration as that shown in FIG. 10 as indicated by the solid line in FIG. 15A, but the signal line 187 is connected to one end of the switch 312 and the non-operational amplifier 300 is not connected. The first target signal Vc1ref from the control circuit 20 is supplied to the inverting input terminal (+),
The output terminal of the operational amplifier 300 is connected to the first feeder line 161a. The second common signal output circuit 35 has the same configuration as that shown in FIG. 10 as shown by the solid line in FIG. 15B, but the signal line 188 is connected to one end of the switch 312 and the operational amplifier 300 is not connected. The second target signal Vc2ref from the control circuit 20 is supplied to the inverting input terminal (+), and the output terminal of the operational amplifier 300 is connected to the second power supply line 161b.

Here, as shown in FIG. 16, the first target signal Vc1ref has a horizontal scanning period in which positive polarity writing is designated (the signal Sel-a and the gate signal Vg1 are at the H level, and the gate signal Vg2 is at the L level. Of the level), the voltage (Vsl−Va) is obtained in the period Ha, and the voltage Vsl is obtained in the period Hb. The second target signal Vc2ref is a period of a horizontal scanning period (period in which the signal Sel-a and the gate signal Vg1 are at L level and the gate signal Vg2 is at H level) in which negative polarity writing is specified. In Ha, the voltage is (Vsh + Va), and in period Hb, the voltage is Vsh.

The operation of the third embodiment will be described.
In the third embodiment, when the scanning signal Yi becomes H level, the TFTs 172a and 172b in the i-th row are turned on. When positive polarity writing is designated for the i-th row, the gate signal Vg1 becomes H level and the gate signal Vg2 becomes L level over the horizontal scanning period H in which the scanning signal Yi becomes H level, so that the TFTs 171a and 171b Turns on and off respectively. Therefore, when positive polarity writing is designated for the i-th row, the common electrode 108 of the i-th row is connected to the first power supply line 161a when the scanning signal Yi becomes the H level.
When the scanning signal Yi becomes H level, the i-th TFT 175 is also turned on, so that the i-th common electrode 108 is connected to the detection line 185. When positive polarity writing is designated for the i-th row, the switch 40 connects the detection line 185 to the signal line 187, so that the first target signal Vc1ref is a horizontal signal at which the scanning signal Yi is at the H level. In the scanning period H, the voltage (Vsl−Va) is obtained in the period Ha and the voltage Vsl is obtained in the period Hb. Therefore, the first common signal output circuit 33 operates in the same manner as the common signal output circuit 31 in the second embodiment. . That is, the first common signal output circuit 33 buffers the voltage (Vsl−Va) as it is by the voltage follower circuit in the period Ha, and the detection line 185 is set to the voltage Vsl in the period Hb.
The first common signal Vc1 controlled so as to be output to the first feeder line 161a.

  Next, when the scanning signal Y (i + 1) becomes H level, the scanning signal Yi becomes L level, so that the i-th TFTs 172a and 172b are turned off. For this reason, the gate electrodes of the TFTs 171a and 171b are both in a high impedance state, but are held at the H level and the L level, which are the immediately preceding states, by the parasitic capacitance, respectively. Therefore, since the TFT 171a is kept on and the TFT 171b is kept off, the i-th common electrode 108 is connected to the first power supply line 161a even when the scanning signal Yi changes from H to L level. The state is maintained and becomes the voltage of the first common signal Vc1.

The first common signal Vc1 is a signal as described above in the horizontal scanning period in which the positive polarity writing is designated. In the horizontal scanning period in which negative polarity writing is specified, the switch 40 connects the detection line 185 to the signal line 188, so that the signal line 187 is in a high impedance state, but the previous voltage Vsl (positive polarity writing). The controlled voltage Vsl) is held in the horizontal scanning period Hb in which the scanning is specified. Therefore, the first common signal Vc1 may be considered to be constant at the voltage Vsl during the horizontal scanning period in which negative polarity writing is designated.

On the other hand, when negative polarity writing is designated for the i-th row, the gate signal Vg1 becomes L level and the gate signal Vg2 becomes H level over the horizontal scanning period H in which the scanning signal Yi becomes H level. The TFTs 171a and 171b are turned off and on, respectively, contrary to the case where the sexual writing is designated. Therefore, when negative polarity writing is designated for the i-th row, the i-th common electrode 108 is connected to the second feeder 161b when the scanning signal Yi becomes the H level.
Further, when negative polarity writing is designated for the i-th row, the switch 40 connects the detection line 185 to the signal line 188, and therefore, the second target signal Vc2ref further indicates that the scanning signal Yi is at the H level. In the horizontal scanning period H, the voltage (Vsh + Va) is obtained in the period Ha, and the voltage Vsh is obtained in the period Hb. Therefore, the second common signal output circuit 35 has the voltage (Vsh in the period Ha.
+ Va) is buffered as it is by the voltage follower circuit, and in the period Hb, the second common signal Vc2 controlled so that the detection line 185 becomes the voltage Vsh is output to the second feeder line 161b.
Next, even if the scanning signal Yi becomes the L level, the gate electrodes of the TFTs 171a and 171b are held at the L level and the H level, respectively, which are in the immediately preceding state. The voltage of the second common signal Vc2 is maintained while maintaining the state connected to the electric wire 161b.

The second common signal Vc2 is a signal as described above in the horizontal scanning period in which negative polarity writing is designated. In the horizontal scanning period in which positive polarity writing is designated, the switch 40 connects the detection line 185 to the signal line 187, so that the signal line 188 is in a high impedance state, but the voltage Vsh (negative polarity The voltage Vsh controlled in the horizontal scanning period Hb in which the data is specified is held. Therefore, the second common signal Vc2 may be considered to be constant at the voltage Vsh during the horizontal scanning period in which positive polarity writing is specified.

In the third embodiment, when viewed in the i-th row, the voltage of the common electrode 108 in the i-th row also changes during the period in which the scanning signal Yi is at the L level. However, if the scanning signal Yi is at the L level, The TFT 116 in the i-th row is also in an off state, and the pixel electrode 118 is in a high impedance state. For this reason, as shown in FIG. 17, since the pixel electrode 118 changes following the voltage of the common electrode 108, the differential voltage of the pixel capacitor 120 does not fluctuate.
For this reason, according to the third embodiment, since the common electrode 108 in each row is not in a high impedance state and the potential is fixed, the display unevenness that occurs in the horizontal direction compared to the second embodiment is reduced. Occurrence can be suppressed even more reliably.

Here, in the TFT, particularly in the amorphous silicon type, the current characteristics of the transistor tend to change. Specifically, the threshold voltage for turning on the TFT tends to increase as the cumulative time during which the TFT is turned on becomes longer. For this reason, if a configuration in which the potential of the common electrode in one row is determined only by turning on one TFT, the threshold voltage of the TFT becomes high due to long-term use, and the above-described driving cannot be performed normally, or There is a possibility of malfunction.
On the other hand, in the third embodiment, in each row, the selection period when the positive voltage is written and the selection period when the TFT 171a is turned on in the subsequent non-selection period and the negative voltage is written. The TFT 171b is turned on in the subsequent non-selection period, that is, the two TFTs 171a and 171b are alternately turned on to determine the potential of the common electrode in one row. For this reason, according to the third embodiment, the period during which the TFTs 171a and 171b are turned on is halved compared to the configuration in which the potential of the common electrode in one row is determined only by turning on one TFT. It is possible to suppress the possibility of malfunction and the like.

Also in the third embodiment, the first common signal output circuit 33 and the second common signal output circuit 35 are configured not only in FIGS. 15A and 15B but also in the configuration shown in FIG. be able to.
Further, since the signal lines 187 and 188 are short in wiring, there is a possibility that the parasitic capacitance is small and the voltages Vsl and Vsh cannot be held. Therefore, the first common signal output circuit 33 is turned on when the signal Sel-a is not distributed because the signal Sel-a is at the L level as shown in FIG. When the switch 321 for determining the voltage Vsl is provided and the second common signal output circuit 35 is not distributed because the signal Sel-a is at the H level as shown in FIG. A switch 322 that turns on the signal line 188 to determine the voltage Vsh may be provided.
Alternatively, as shown in these figures, a configuration in which one end is connected to each of the signal lines 187 and 188 and a capacitive element having the other end at a constant potential may be positively provided.

<Fourth embodiment>
Next, an electro-optical device according to a fourth embodiment of the invention will be described. FIG. 18 is a diagram illustrating a configuration of an electro-optical device according to the fourth embodiment of the invention.
In the configuration shown in this figure, among the rows of the common electrode driving circuit 170, the source electrodes of the odd-numbered TFTs 171 are connected to the first feed line 165a, and the source electrodes of the odd-numbered TFTs 171 are connected to the second feed line 165b. Has been. In each row, a detection capacitor 176 is provided instead of the TFT 175. Specifically, the detection capacitor 176 corresponding to the odd-numbered row has one end connected to the common electrode 108 of the row and the other end connected to the first detection line 185a, while the detection capacitor 176 corresponding to the even-numbered row has , One end thereof is connected to the common electrode 108 of the row, and the other end is connected to the second detection line 185b.

The first common signal Vc1 from the first common signal output circuit 37 is supplied to the first power supply line 165a, and the second common signal Vc2 from the second common signal output circuit 39 is supplied to the second power supply line 165b. .
The first common signal output circuit 37 and the second common signal output circuit 39 have the same configuration as that shown in FIG. 10, but the non-inverting input terminal (+) of the operational amplifier 300 in the first common signal output circuit 37 has The first target signal Vc1ref is supplied and the second common signal output circuit 39 is supplied.
The second target signal Vc2ref is supplied to the non-inverting input terminal (+) of the operational amplifier 300 in FIG.

Here, as shown in FIG. 20, the first target signal Vc1ref in the fourth embodiment is an n frame in which positive writing is specified for odd rows and negative writing is specified for even rows. In the horizontal scanning period in which the scanning signal for the odd-numbered rows is at the H level, the voltage (Vsl-Va) is obtained in the period Ha and the voltage Vsl is designated in the other periods, while negative polarity writing is designated for the odd-numbered rows In the (n + 1) frame in which positive polarity writing is specified for even rows, the voltage (Vsh + Va) becomes the voltage (Vsh + Va) in the period Ha during the horizontal scanning period in which the scanning signal to the odd rows is at the H level. At voltage Vsh.
Further, as shown in the figure, the second target signal Vc2ref becomes a voltage (Vsh + Va) in the period Ha in the horizontal scanning period in which the scanning signal to the even-numbered row is at the H level in the n frame. During the period, the voltage Vsh becomes the voltage (Vsl−Va) in the period Ha of the horizontal scanning period in which the scanning signal to the even-numbered row becomes the H level in the (n + 1) frame, and the voltage Vsl in the other periods. Become.

FIG. 19 is a plan view showing configurations of the common electrode driving circuit 170 and the vicinity of the display area 100 in the element substrate according to the fourth embodiment.
As shown in this figure, the odd-numbered i-row detection capacitors 176 are formed by overlapping the widened portion of the first detection line 185a via the insulating layer with the widened portion of the i-th common electrode 108. It is configured. Similarly, the detection capacitors 176 in the even (i + 1) th row are configured by overlapping the widened portion of the common electrode 108 in the (i + 1) th row via the insulating layer with the widened portion of the second detection line 185b. Has been.

According to the fourth embodiment, when noise is generated in the selected common electrode 108 in the odd-numbered row when the scanning line 112 whose scanning signal is at the H level is an odd-numbered row, the noise is selected. The signal is propagated to the first detection line 185 a via the detection capacitor 176 in the first row and supplied to the first common signal output circuit 37. The first common signal output circuit 37 outputs a first common signal Vc1 having the following voltage to the first feed line 165a. That is, the first common signal output circuit 37 buffers and outputs a voltage that is excessively shifted by the voltage Va in the voltage change direction in the period Ha of the horizontal scanning period in which the scanning signal to the odd-numbered row is at the H level. In the period Hb, control is performed so that the voltage of the first detection line 185a becomes the voltage of the first target signal Vc1ref. For this reason, at the end of the horizontal scanning period, the selected common electrode 108 in the odd-numbered row is more accurately stabilized to one of the voltage Vsl and the voltage Vsh.
On the other hand, when the scanning line 112 where the scanning signal is at the H level is an even number row, when noise is generated in the common electrode 108 of the selected even thin row, the noise is detected capacitance of the selected row. The signal is propagated to the second detection line 185 b via 176 and supplied to the second common signal output circuit 39. The second common signal output circuit 39 outputs a second common signal Vc2 having the following voltage to the second feeder 165b. That is, the second common signal output circuit 39 buffers and outputs a voltage that is excessively shifted by the voltage Va with respect to the voltage change direction in the period Ha of the horizontal scanning period in which the scanning signal to the even-numbered row is at the H level. In the period Hb, the second detection line 185
The voltage b is controlled and output so as to be the voltage of the second target signal Vc2ref. Therefore, at the end of the horizontal scanning period, the selected even-numbered common electrode 108 is more accurately stabilized at one of the voltage Vsl and the voltage Vsh.
As a result, in the fourth embodiment, as in the second embodiment, the voltage amplitude of the data line can not be reduced, and the transistor size of the TFT 171 does not need to be increased as necessary, and is generated in the lateral direction. It is possible to more reliably suppress the occurrence of display unevenness.

In the fourth embodiment, the element connecting the common electrode 108 and the first detection line 185a or the second detection line 185b is the detection capacitor 176 that does not allow a direct current component to flow. For this reason, the configuration shown in FIG. 12 cannot be used as the first common signal output circuit 37 or the second common signal output circuit 39.
Also in the fourth embodiment, as in the third embodiment, a set of TFTs 171a, 171b, 172a, and 172b may be provided in each row, and the potential of the common electrode 108 may be determined in the non-selection period.

<Related matters of the first to fourth embodiments>
In each of the embodiments described above, in the scanning line driving circuit 140, the selection voltage is applied to the scanning line 112 in the order of the first, second, third,..., 320th rows, but the 320th, 319, 318,. You may select in order. In addition, since it is meaningless to specify the writing polarity in the vertical blanking period, a logic signal such as the period designation signal Ha may be fixed at a certain level. You can omit it.
Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed. Further, for example, G is changed to YG (yellowish green) and EG ( It is also possible to make a wide color band by forming one dot with these four color pixels.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 21 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to any of the embodiments.
As shown in this figure, a mobile phone 1200 includes the electro-optical device 10 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that the components of the electro-optical device 10 corresponding to the display region 100 do not appear as appearance.

  As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 21, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. And car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, photo storage viewers, devices equipped with touch panels, and the like. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. It is a figure which shows the influence of the waveform blunt of a common electrode, noise, etc. in the same electro-optical device. FIG. 6 is a diagram for explaining another operation of the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. It is a figure which shows the structure of the common signal output circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows another structure of a common signal output circuit. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. It is a figure which shows the structure of the common signal output circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. FIG. 10 is a diagram illustrating a configuration of an electro-optical device according to a fourth embodiment of the invention. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 31 ... Common signal output circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 120 ... Pixel capacity , 130: Storage capacitor, 140: Scanning line drive circuit, 161 ... Feed line, 170 ... Common electrode drive circuit, 171, 171a, 171b, 172a, 172b, 175 ... TFT, 176 ... Detection capacity, 185 ... Detection line, 300 ... operational amplifiers, 311, 312, 318 ... switches, 1200 ... mobile phones

Claims (12)

A plurality of scan lines;
Multiple data lines,
A plurality of common electrodes provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
Each has one end connected to the data line and a conductive state when a selection voltage is applied to the scanning line, and one end connected to the other end of the pixel switching element. A pixel capacitor connected to the common electrode;
A pixel containing
A drive circuit for an electro-optical device having:
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying a selection voltage to the selected scanning lines;
For a common electrode provided corresponding to the scanning line to which the selection voltage is applied, a first period closer to the front and a second period closer to the rear of the period in which the selection voltage is applied, While applying either the first voltage or the second voltage higher than the first voltage in the second period,
When applying the first voltage in the second period, a third voltage lower than the first voltage is applied in the first period in advance,
A common electrode driving circuit that applies a fourth voltage higher than the second voltage in the first period in advance when applying the second voltage in the second period;
A data line driving circuit for supplying a data signal having a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the selection voltage is applied, via the data line;
A drive circuit for an electro-optical device, comprising: The common electrode drive circuit is
A transistor is provided for each of the common electrodes,
In the transistor corresponding to one common electrode, a gate electrode is connected to a scanning line corresponding to the one common electrode, and a source electrode is connected to a power supply line that supplies a common signal.
The drive circuit of the electro-optical device according to claim 1, wherein the common electrode corresponding to the scanning line to which the selection voltage is applied is fed through the feeding line. Provided corresponding to each of the common electrodes, and each is turned on between the one common electrode and the detection line when the selection voltage is applied to the scanning line corresponding to the one common electrode. A switching element for detection;
A voltage obtained by buffering the third or fourth voltage in the first period;
A voltage controlled so that the detection line becomes the first or second voltage in the second period,
A common signal output circuit that outputs the common signal to the feeder line,
The drive circuit for the electro-optical device according to claim 2, further comprising: The common signal output circuit is:
An operational amplifier in which the target signal that becomes the third or fourth voltage in the first period and becomes the first or second voltage in the second period is input to the non-inverting input terminal, and the output terminal is connected to the feeder line When,
A first switch electrically inserted between an output terminal of the operational amplifier and an inverting input terminal of the operational amplifier, turned on in the first period, and turned off in the second period;
A second switch electrically interposed between the detection line and the inverting input terminal of the operational amplifier, and turned off in the first period and turned on in the second period;
The drive circuit of the electro-optical device according to claim 3, comprising: The common signal output circuit is:
5. The apparatus according to claim 4, further comprising an auxiliary switch that is turned on between the power supply line and the detection line in a period that is temporally forward in a period in which the selection voltage is applied to one scanning line. The electro-optical device described. The common electrode drive circuit is
Corresponding to each of the common electrodes, it has a set of first to fourth transistors,
A source electrode of the first transistor corresponding to one common electrode is connected to a first feeder line that feeds a first common signal;
The second transistor has a source electrode connected to a second feed line that feeds a second common signal,
The drain electrodes of the first and second transistors are connected to the one common electrode;
The third transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, a source electrode connected to a first signal line to which a first gate signal is supplied, and a drain electrode connected to the first transistor. Connected to the gate electrode of
The fourth transistor has a gate electrode connected to a scanning line corresponding to the one common electrode, a source electrode connected to a second signal line to which a second gate signal is supplied, and a drain electrode connected to the second transistor. Connected to the gate electrode of
The first and second gate signals are voltages for turning on and off the first and second transistors exclusively, and supply power to the common electrode corresponding to the scanning line to which the selection voltage is applied. The drive circuit of the electro-optical device according to claim 1, wherein the drive circuit is defined as being via a feeder line or via the second feeder line. Provided corresponding to each of the common electrodes, and each is turned on between the one common electrode and the detection line when the selection voltage is applied to the scanning line corresponding to the one common electrode. A switching element for detection;
When power is supplied to the common electrode corresponding to the scanning line to which the selection voltage is applied via the first power supply line, a voltage obtained by buffering the third or fourth voltage in the first period is While the voltage controlled so that the voltage of the detection line becomes the first or second voltage in the second period, respectively, the first common signal is output to the first feeder line,
When power is supplied to the common electrode corresponding to the scanning line to which the selection voltage is applied via the second power supply line, a voltage obtained by buffering the third or fourth voltage in the first period, A common signal output circuit that outputs a voltage controlled so that the voltage of the detection line becomes the first or second voltage in the second period as the second common signal to the second feeder line, respectively. The drive circuit for an electro-optical device according to claim 6. The first and second gate signals are:
The power supply to one common electrode is determined so as to alternate between a case where the power supply is performed via the first power supply line and a case where the power supply is performed via the second power supply line. Drive circuit for electro-optical device. Corresponding to each of the common electrodes, a detection capacitor electrically inserted between the one common electrode and the detection line,
A voltage obtained by buffering the third or fourth voltage in the first period;
The voltage controlled so that the voltage of the detection line becomes the first or second voltage in the second period,
A common signal output circuit that outputs the common signal to the feeder line,
The drive circuit for the electro-optical device according to claim 2, further comprising: A plurality of scan lines;
Multiple data lines,
A plurality of common electrodes provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
Each has one end connected to the data line and a conductive state when a selection voltage is applied to the scanning line, and one end connected to the other end of the pixel switching element. A pixel capacitor connected to the common electrode;
A pixel containing
A driving method of an electro-optical device having:
Selecting the plurality of scanning lines in a predetermined order, and applying a selection voltage to the selected scanning lines;
For a common electrode provided corresponding to the scanning line to which the selection voltage is applied, a first period closer to the front and a second period closer to the rear of the period in which the selection voltage is applied, While applying either the first voltage or the second voltage higher than the first voltage in the second period,
When applying the first voltage in the second period, a third voltage lower than the first voltage is applied in the first period in advance,
When applying the second voltage in the second period, a fourth voltage higher than the second voltage is applied in the first period in advance,
A driving method of an electro-optical device, characterized in that a data signal having a voltage corresponding to a gradation of the pixel is supplied to each pixel corresponding to the scanning line to which the selection voltage is applied via the data line. A plurality of scan lines;
Multiple data lines,
A plurality of common electrodes provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
Each has one end connected to the data line and a conductive state when a selection voltage is applied to the scanning line, and one end connected to the other end of the pixel switching element. A pixel capacitor connected to the common electrode;
A pixel containing
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying a selection voltage to the selected scanning lines;
For a common electrode provided corresponding to the scanning line to which the selection voltage is applied, a first period closer to the front and a second period closer to the rear of the period in which the selection voltage is applied, While applying either the first voltage or the second voltage higher than the first voltage in the second period,
When applying the first voltage in the second period, a third voltage lower than the first voltage is applied in the first period in advance,
A common electrode driving circuit that applies a fourth voltage higher than the second voltage in the first period in advance when applying the second voltage in the second period;
A data line driving circuit for supplying a data signal having a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the selection voltage is applied, via the data line;
An electro-optical device comprising: An electronic apparatus comprising the electro-optical device according to claim 11.

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