JP2009162982A - Electro-optical device, driving circuit, driving method, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress display unevenness which occurs in a lateral direction in a configuration of changing the voltage of a capacity line 132. <P>SOLUTION: A pixel 110 includes pixel capacity and storage capacity with one end connected to a pixel electrode and the other end connected to the capacity line 132. The capacity line 132 is provided corresponding to each of 1-320 lines, and a capacity line driving circuit 150 has a pair of TFTs 151, 152 in each of the 1-320 lines. When the capacity line 132 in a certain i-th line is changed in voltage from a second voltage to a predetermined value from application of selection voltage to an i-th scanning line 112 until the end of application of the selection voltage, the voltage of a first capacity signal Vc1 is set to a first voltage which is excessively changed in a voltage change direction from the second voltage in a first-half period where the selection voltage is applied to the i-th scanning line 1 112, and set to a second voltage in a second-half period. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for suppressing display unevenness that occurs in a horizontal direction when a voltage of a capacitor line is changed in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. When this pixel capacitor needs to be AC driven, the voltage amplitude of the data signal is positive or negative. The polarity is For this reason, in a data line driving circuit that supplies a data signal to the data line, a breakdown voltage corresponding to the voltage amplitude is required for the constituent elements. Therefore, a storage capacitor is provided in parallel with the pixel capacitor, and a capacitor line commonly connected to the storage capacitor in each row is driven with a binary voltage in synchronization with the selection of the scanning line, thereby narrowing the voltage amplitude of the data signal. A technique has been proposed (see Patent Document 1).
See JP 2001-83943 A

By the way, in this technique, when the voltage of the capacitor line deviates from a predetermined voltage due to superimposition of noise or the like at the time of voltage writing to the pixel capacitor, the pixel corresponding to the capacitor line has a target gradation. It will not become. Since one row of capacitor lines corresponds to a large number of pixels, and all of these pixels do not have the target gradation, display unevenness occurs along the horizontal direction, which is the extending direction of the capacitor lines / scanning lines. Will appear.
The present invention has been made in view of such circumstances, and one of its purposes is to provide a technique for suppressing display unevenness that occurs in the horizontal direction in a configuration in which the voltage of a capacitor line is changed.

In order to achieve the above object, a drive circuit for an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of capacitance lines provided corresponding to the plurality of scanning lines, Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each of which is connected to the data line and is in a conductive state when a selection voltage is applied to the scanning line. A pixel switching element, one end of which is connected to the other end of the pixel switching element and the other end of which is connected to a common electrode, and a capacitance line provided corresponding to one end of the pixel capacity and the scanning line And a pixel including a storage capacitor electrically interposed between the plurality of scanning lines, wherein the plurality of scanning lines are selected in a predetermined order, and the selected scanning lines are selected. A scanning line driving circuit for applying a selection voltage; A first voltage is applied to a capacitor line provided corresponding to a scan line in a first period closer to the front in a period in which a selection voltage is applied to the one scan line. A capacitor line driving circuit that applies a second voltage in a second period closer to the rear and changes the second voltage by a predetermined value after the application of the selection voltage to the one scanning line is completed, and the selection voltage A data line driving circuit that supplies a data signal having a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the pixel is applied via the data line, and the first voltage is The voltage is different from the second voltage, and is a voltage in a direction opposite to the direction of change to the predetermined value with respect to the second voltage. According to the present invention, the voltage of one capacitor line changes from the second voltage by a predetermined value from the period when the selection voltage is applied to the scanning line corresponding to itself to after the application of the selection voltage is completed. At this time, since the charge accumulated in the storage capacitor is redistributed to the pixel capacitor, the pixel capacitor can hold a voltage equal to or higher than the value corresponding to the data signal. Further, the first capacitor line is applied with the second voltage after the first voltage that is excessively swung in the voltage change direction is applied during the period in which the selection voltage is applied to the scanning line in order to write the voltage to the pixel capacitor. Therefore, it is possible to converge to the second voltage at the end of application of the selection voltage.

In the present invention, in one pixel capacitor, positive polarity writing in which the potential of the pixel electrode with respect to the common electrode is on the higher side and negative polarity writing on the lower side are alternately performed, and the capacitance line driving circuit A low voltage is applied as the second voltage to the capacitor line of the pixel capacitance for the positive polarity writing, and a high voltage is applied as the second voltage to the capacitance line of the pixel capacitance for the negative polarity writing. The structure which does is preferable.
In the present invention, the capacitor line driving circuit has a set of first and second transistors corresponding to each of the capacitor lines, and the first transistor corresponding to one capacitor line is a gate. The electrode is connected to the scanning line corresponding to the one capacitance line, the source electrode is connected to the first feeding line that feeds the first capacitance signal, and the gate electrode of the second transistor is connected to the one scanning line. Connected to a scanning line separated by a predetermined number of rows, a source electrode is connected to a second feeding line that feeds a second capacitance signal, and the drain electrodes of the first and second transistors are commonly connected to the one capacitance line The first transistor corresponding to each capacitor line may have a pair of first to fourth transistors, and the gate electrode of the first transistor corresponding to one capacitor line may be the one capacitor. Run corresponding to the line A source electrode connected to a first feed line feeding a first capacitance signal, the second transistor connected to a second feed line feeding a second capacitance signal, and the third transistor The transistor has a gate electrode connected to a scanning line corresponding to the one capacitor line, a source electrode connected to an off-voltage power supply line that supplies an off-voltage for turning off the second transistor, and the fourth transistor includes The gate electrode is connected to a scanning line separated by a predetermined number of rows from the one scanning line, and the source electrode is connected to an on-voltage power supply line that supplies an on-voltage for turning on the second transistor, The drain electrodes of the third and fourth transistors are commonly connected to the gate electrode of the second transistor, and the drain electrodes of the first and second transistors are connected to the one capacitor. It may be connected to each to. In particular, in the structure including the first to fourth transistor groups with respect to the capacitor line, a period in which the potential of the capacitor line is uncertain can be eliminated or minimized.

Further, in the configuration having the first and second transistor groups or the first to fourth transistor groups with respect to the capacitor line, the capacitor line is provided corresponding to each of the capacitor lines. A switching element for detection that is turned on between the one capacitance line and the detection line when the selection voltage is applied to the scanning line corresponding to the line, and the first voltage is buffered in the first period. A capacitance signal output circuit that outputs a voltage, the voltage of which is controlled so that the voltage of the detection line becomes the second voltage in the second period, to the first feeder line as the first capacitance signal, respectively. It is good also as a structure provided. Among the selection voltage application periods, in the first period closer to the front in time, there may be a large voltage difference between the capacitance line and the detection line. Therefore, if the voltage of the detection line is suddenly controlled to become the second voltage. There may be a problem that a large amount of current flows or oscillates. In this configuration, since such control is not performed in the first period, only the buffering is performed so that the voltage difference is reduced, and then the control is performed in the second period thereafter, the above-described problem. Occurrence is suppressed.
As such a configuration, the storage signal output circuit has the first voltage in the first period, the target signal that becomes the second voltage in the second period, is input to the non-inverting input terminal, and the output terminal is the output terminal. An operational amplifier connected to the first feeder, and electrically inserted between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier, and is turned on in the first period and turned off in the second period. And a second switch that is electrically inserted between the detection line and the inverting input terminal of the operational amplifier, and is turned off in the first period and turned on in the second period. good.
On the other hand, the capacitance signal output circuit includes an auxiliary switch that is turned on between the power supply line and the detection line in a period that is temporally forward in a period in which a selection voltage is applied to one scanning line. Also good. According to such a configuration, when the auxiliary switch is turned on, the first capacitance signal output by the capacitance signal output circuit is supplied to the detection line and the auxiliary switch together with the path through the first power supply line and the first transistor. The capacitor line can also be supplied through the route.
Further, a detection capacitor electrically inserted between the one capacitance line and the detection line, and a voltage obtained by buffering the first voltage in the first period, corresponding to each of the capacitance lines. A capacitance signal output circuit that outputs the voltage controlled so that the voltage of the detection line becomes the second voltage in the second period as the first capacitance signal to the first feeder line, respectively. It is good also as a structure. According to this configuration, simplification can be achieved as compared with the case of using a transistor or the like.
The present invention can be conceptualized not only as a driving circuit for an electro-optical device, but also as a driving method, an electro-optical device, and an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, in the electro-optical device 10, a scanning line driving circuit 140, a capacitor line driving circuit 150, and a data line driving circuit 190 are arranged around the display area 100, and the control circuit 20 includes these components. Each part is controlled individually.

  The display area 100 is an area where the pixels 110 are arranged. In the present embodiment, the display area 100 is provided so that a total of 321 scanning lines 112 from the first line to the 321st line extend in the row (X) direction. In addition, 240 data lines 114 are provided so as to extend in the column (Y) direction. Then, the pixels 110 are arranged corresponding to the intersections of the scanning lines 112 in the 1st to 320th lines excluding the lowermost 321st line in FIG. 1 and the data lines 114 in the 1st to 240th columns. Therefore, in the present embodiment, the pixels 110 are arranged in a matrix of 320 vertical rows × 240 horizontal columns in the display area 100. However, the present invention is not intended to be limited to this arrangement.

Since the scanning line 112 in the 321st row does not correspond to the pixel 110, it functions as a dummy scanning line. For this reason, even if the scanning line 112 in the 321st row is selected in the vertical scanning of the display region 100 (operation of sequentially applying the selection voltage to the scanning line), it does not contribute to voltage writing to the pixel 110 at all.
In addition, corresponding to the scanning lines 112 in the first to 320th rows, capacitance lines 132 are provided extending in the X direction, respectively. For this reason, in the present embodiment, the capacitor line 132 is provided corresponding to the 1st to 320th scanning lines 112 excluding the dummy 321st scanning line 112.

Here, a detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram showing the configuration of the pixel 110, corresponding to the intersection of the i row and the (i + 1) row adjacent thereto in the downward direction and the j column and the (j + 1) column adjacent thereto in the right direction. A 2 × 2 configuration for a total of four pixels is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 110 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 110 are arranged. It is a symbol in the case of showing generally, and is an integer of 1 or more and 240 or less. Here, i and (i + 1) are integers of 1 or more and 320 or less when generally indicating the row in which the pixels 110 are arranged, but are dummy when describing the row of the scanning line 112. Since there is a case where a certain 321st line is included, it is an integer of 1 to 321.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, And a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 that is one end of the pixel capacitor 120.
The other end of the pixel capacitor 120 is connected to the common electrode 108. As shown in FIG. 1, the common electrode 108 is common to all the pixels 110, and a common signal Vcom is supplied from the control circuit 20. In the present embodiment, the common signal Vcom is constant at the voltage LCcom in terms of time as will be described later.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the i and (i + 1) th scanning lines 112, respectively, and Ci and C (i + 1) indicate i and (i + 1), respectively. ) The voltage of the capacitor line 132 in the row is shown.

In the display region 100, a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, are bonded together with a certain gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in the gap. Therefore, the pixel capacitor 120 sandwiches the liquid crystal 105 that is a kind of dielectric between the pixel electrode 118 and the common electrode 108, and holds the differential voltage between the pixel electrode 118 and the common electrode 108. In this configuration, in the pixel capacitor 120, the amount of transmitted light changes according to the effective value of the holding voltage.
In the present embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value is increased. The normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

  The storage capacitor 130 in the pixel 110 in the i row and j column has one end connected to the pixel electrode 118 (the drain electrode of the TFT 116) and the other end connected to the i-th capacitor line 132. Here, the capacitance values in the pixel capacitor 120 and the storage capacitor 130 are Cpix and Cs, respectively.

Returning to FIG. 1 again, the control circuit 20 outputs various control signals to control each part in the electro-optical device 10, and supplies the first capacitance signal Vc1 to the first power supply line 165. The second capacitance signal Vc2 is supplied to the second power supply line 167, and the common signal Vcom is supplied to the common electrode. The control signal, the first capacitance signal Vc1, and the second capacitance signal Vc2 will be described later.

As described above, peripheral circuits such as the scanning line driving circuit 140, the capacitor line driving circuit 150, and the data line driving circuit 190 are provided around the display region 100.
Among these, the scanning line driving circuit 140 sends the scanning signals Y1, Y2, Y3,..., Y320, Y321 to 1, 2, 3,. This is supplied to the scanning line 112 in the 321st row. Specifically, the scanning line driving circuit 140 selects the scanning lines 112 in the order of the first, second, third,..., 320, and 321st rows from the top in FIG. Is set to the H level corresponding to the selection voltage Vdd, and the scanning signals to the other scanning lines are set to the L level corresponding to the non-selection voltage Vss.

As shown in FIG. 4, the scanning line driving circuit 140 sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly.
The scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 are output. In this embodiment, during the period of one frame, the scanning signal Y1 becomes H level until the scanning signal Y320 becomes L level. In addition to the effective scanning period Fa, other vertical blanking periods are included. The horizontal scanning period H is a period in which one row of scanning lines 112 is selected and a selection voltage is applied.

  In the present embodiment, the capacitor line driving circuit 150 includes a set of n-channel TFTs 151 and 152 provided corresponding to the capacitor lines 132 in the first to 320th rows. Here, the TFTs 151 and 152 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 151 (first transistor) is connected to the i-th scanning line 112, and the source electrode thereof is the first On the other hand, the gate electrode of the TFT 152 (second transistor) is connected to the scanning line 112 in the (i + 1) th row, and its source electrode is connected to the second power supply line 167 while being connected to the power supply line 165. The drain electrodes of the TFTs 151 and 152 are commonly connected to the i-th capacitor line 132.

In such a configuration, when the scanning signal Yi supplied to the i-th scanning line 112 becomes H level, since the scanning signal Y (i + 1) is at L level, the i-th TFT 151 is turned on and the TFT 152 is turned on. Since it is turned off, the i-th capacitor line 132 is connected to the first power supply line 165. For this reason, the voltage of the capacitor line 132 in the i-th row is determined by the first capacitor signal Vc1 supplied to the first feeder line 165.
Next, when the scanning signal Yi becomes L level and the scanning signal Y (i + 1) supplied to the next (i + 1) th scanning line 112 becomes H level, the i-th TFT 151 is turned off and the TFT 152 is turned on. Therefore, the i-th capacitor line 132 is connected to the second power feed line 167. For this reason, the voltage of the capacitance line 132 in the i-th row is determined by the second capacitance signal Vc2 supplied to the second feeder line 167.

The data line driving circuit 190 is a voltage corresponding to the gradation with respect to the pixel 110 located on the scanning line (selected scanning line) to which the H level scanning signal is supplied by the scanning line driving circuit 140, and A data signal having a voltage (details will be described later) corresponding to the polarity designated by the polarity instruction signal Pol is supplied to the data line 114.
Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation value (brightness) of the corresponding pixel 110. Display data Da for designating the data is stored. The display data Da stored in each storage area is supplied with the changed display data Da by the control circuit 20 when the display contents are changed, and the contents of the storage area are rewritten.
The data line driving circuit 190 reads out the display data Da of the pixels 110 located on the selected scanning line for one row from the storage area, and at a voltage corresponding to the gradation specified by the read display data and the specified polarity. The operation of converting to a data signal and supplying it to the data line 114 is executed for each of the 1st to 240th columns positioned at the selected scanning line.

The write polarity is designated by a polarity designation signal Pol output by the control circuit 20. Specifically, in this embodiment, the polarity designation signal Pol is supplied to odd-numbered 1, 3, 5,..., 319 lines in a period of one frame (denoted as “n frame”) as shown in FIG. In the period when the scanning signal is at the H level, the positive writing is designated, and the scanning signal to even rows 2, 4, 6,. Specifies sex writing. Therefore, in this embodiment, a scanning line inversion (line inversion) method in which the writing polarity to the pixel is inverted for each scanning line is employed.
In addition, in the next (n + 1) frame, the polarity instruction signal Pol becomes L level during a period when the scanning signal to the odd-numbered row is H level, and becomes H level during the period when the scanning signal to the even-numbered row is H level. Thus, the writing polarity is inverted for each row as compared with the n frame. The reason for reversing the writing polarity in this way is to prevent deterioration of the liquid crystal due to application of a DC component.
As for the writing polarity in the present embodiment, when the voltage is held in the pixel capacitor 120, the case where the potential of the pixel electrode 118 is higher than the voltage LCcom of the common electrode 108 is called positive polarity. The case of the lower side is called negative polarity.
As for the voltage, unless otherwise specified, the ground potential of a power source (not shown) is used as a reference for zero voltage.

If positive polarity writing is designated for a pixel in a certain row by the polarity instruction signal Pol, the first capacitance signal Vc1 is temporally forward in the period in which the scanning signal to the row is at the H level. The voltage becomes Vsl−Va in the close period Ha, and becomes the voltage Vsl in the time period Hb that is the rearward period, which is the remaining period. On the other hand, if negative polarity writing is designated for a pixel in a certain row, the first capacitance signal Vc1 becomes a voltage (Vsh + Va) in the period Ha during the period in which the scanning signal to that row is at the H level. In the period Hb, the voltage becomes Vsh.
Further, in the present embodiment, the second capacitance signal Vc2 is constant at the same voltage LCcom as that of the common electrode 108, regardless of the writing polarity specified by the polarity instruction signal Pol.
Here, the voltages Vsl and Vsh have a relationship of (Vss ≦) Vsl <Vsh (≦ Vdd), and the voltage Vsl is relatively lower than the voltage Vsh. In the present embodiment, the difference between the voltage Vsl and the voltage LCcom and the difference between the voltage Vsh and the voltage LCcom are respectively set to ΔV. Therefore, the voltage (Vsl−Va) and the voltage (Vsh + Va), and the voltage Vsl and the voltage Vsh are in a symmetrical positional relationship with respect to the voltage LCcom.

The control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at the timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 outputs the scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 by sequentially shifting the start pulse Dy according to the clock signal Cly. The start timing of the period during which becomes H level is the timing at which the logic level of the clock signal Cly transitions. Therefore, the data line driving circuit 190 becomes H level depending on, for example, which row scanning signal becomes H level by continuously counting the latch pulse Lp over a period of one frame and the supply timing of the latch pulse Lp. You can know the start timing of the period.

  In the present embodiment, the element substrate includes the scanning lines 112 in the display region 100, the data lines 114, the TFTs 116, the pixel electrodes 118, and the storage capacitors 130, as well as the TFTs 151 and 152 in the capacitor line driving circuit 150, and the first feeder lines. 165, the second feeder 167, and the like are also formed.

FIG. 3 is a plan view showing the configuration of the capacitive line driving circuit 150 and the vicinity of the display area 100 in such an element substrate.
As shown in this figure, in the present embodiment, the TFTs 116, 151, and 152 are of an amorphous silicon type, and are of a bottom gate type in which the gate electrode is located below the semiconductor layer. Specifically, the scanning line 112, the capacitor line 132, and the like are formed by patterning the gate electrode layer serving as the first conductive layer, a gate insulating film (not shown) is formed thereon, and the semiconductors of the TFTs 116, 151, and 152 are further formed. The layer is formed in an island shape. On the semiconductor layer, an ITO (indium tin oxide) layer serving as a second conductive layer is patterned through a protective layer to form a pixel electrode 118 having a rectangular shape and transparency. A metal layer such as aluminum to be the three conductive layers is patterned to form source / drain electrodes of the TFTs 116, 151, 152, wirings such as the data line 114, the first power supply line 165, and the second power supply line 167. Yes.

Here, in the capacitor line driving circuit 150, the gate electrode of the TFT 151 corresponding to the i-th row is a portion branched in a T shape in the Y (downward) direction from the i-th scanning line 112. The gate electrode of the TFT 152 corresponding to is a portion branched in a T shape in the Y (up) direction from the scanning line 112 in the (i + 1) th row.
The common drain electrode 132a of the TFTs 151 and 152 corresponding to the i-th row is obtained by patterning the third conductive layer, and has a contact hole (marked with x in the figure) 132b penetrating the gate insulating film and the protective layer. Through the i-th capacitor line 132.
On the other hand, in the display region 100, the storage capacitor 130 has a configuration in which the gate insulating film is sandwiched as a dielectric by the portion of the capacitor line 132 formed so as to be wide in the lower layer of the pixel electrode 118 and the pixel electrode 118. is there. For this reason, the other end of the storage capacitor 130 becomes the capacitor line 132 itself.
Note that the common electrode 108 facing the pixel electrode 118 is formed on the counter substrate, and thus does not appear in FIG. 3 showing a plan view of the element substrate.

The configuration shown in FIG. 3 is merely an example, and the TFT may have another structure, for example, a top gate type in terms of the arrangement of the gate electrode, or a polysilicon type in terms of the process. In addition, the constituent elements of the capacitor line driving circuit 150 are not formed by a common process with the TFT 116, but a separate IC chip may be mounted on the element substrate side.
When the IC chip is mounted on the element substrate side, the scanning line driving circuit 140 and the capacitor line driving circuit 150 may be integrated as a semiconductor chip together with the data line driving circuit 190, or may be separate chips. Further, the control circuit 20 may be configured to be built in the element substrate.
When the present embodiment is a reflective type instead of a transmissive type, the reflective conductive layer may be patterned for the pixel electrode 118, or a separate reflective metal layer may be provided. Furthermore, a so-called transflective type in which both a transmissive type and a reflective type are combined may be used.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
In the n frame, the scanning line driving circuit 140 sequentially sets the scanning signals Y1, Y2, Y3,. First, of these rows, the operations of the i-th row and the (i + 1) -th row will be described as a representative. Here, i is an odd number, (i + 1) is an even number, and a positive voltage is written to a pixel in the i-th row.
When the scanning signal Yi becomes H level, the TFTs 116 in the i-th row and j-th column are turned on, so that the positive data signal Xj is applied to one end of the pixel capacitor 120 (pixel electrode 118) and one end of the storage capacitor 130, respectively.
On the other hand, when the scanning signal Yi is at the H level, the scanning signal Y (i + 1) is at the L level. For this reason, in the capacitor line driving circuit 150, the TFT 151 corresponding to the i-th row is turned on and the TFT 152 is turned off, so that the i-th row capacitor line 132 is connected to the first power supply line 165. . Here, since the first capacity signal Vc1 supplied to the first power supply line 165 is designated as positive polarity writing for the i-th row, the first capacitance signal Vc1 is closer to the first half of the period in which the scanning signal Yi is at the H level. In the period Ha, the voltage is Vsl-Va, and in the period Hb closer to the second half, the voltage is Vsl.
Therefore, if the voltage of the data signal Xj at this time is Vj, the voltage is applied to the pixel capacitor 120 in the i row and j column as shown in FIG. 5A at the end of the period in which the scanning signal Yi is at the H level. (Vj−LCcom) is charged, and the storage capacitor 130 is charged with a voltage (Vj−Vsl).

Next, the scanning signal Yi becomes L level and the scanning signal Y (i + 1) becomes H level. When the scanning signal Yi becomes L level, the TFTs 116 in the pixels in the i row 1 column to the i row 240 column are turned off. If the scanning signal Yi is L level and the scanning signal Y (i + 1) is H level, the capacitor line driving circuit 150 turns off the TFT 151 corresponding to the i-th row, turns on the TFT 152, and turns on the i-th row. The capacitor line 132 is connected to the second power supply line 167 and rises to the voltage LCcom. For this reason, as shown in FIG. 5B, in the series connection of the pixel capacitor 120 and the storage capacitor 130, the other end (common electrode) of the pixel capacitor 120 is maintained at the voltage LCcom. Since the other end rises from the voltage Vsl to the voltage LCcom by the voltage ΔV, the voltage of the pixel electrode 118 also rises due to charge redistribution.

Specifically, the voltage of the pixel electrode 118 which is the series connection point is
Vj + {Cs / (Cs + Cpix)} · ΔV
Therefore, the capacitance ratio {Cs / (Cs + Cpix) of the pixel capacitor 120 and the storage capacitor 130 is more than the voltage change ΔV of the capacitor line 132 in the i-th row than the voltage Vj of the data signal when the scanning signal Yi is at the H level. )}.
In other words, when the voltage Ci of the capacitor line 132 in the i-th row is increased by ΔV, the voltage of the pixel electrode 118 is more than {Cs than the voltage Vj of the data signal when the scanning signal Yi is at the H level.
/ (Cs + Cpix)} · ΔV (= ΔVpix). Note that the parasitic capacitance of each part is ignored.

Thereafter, in the present embodiment, the capacitance line 132 in the i-th row is held at the voltage LCcom by the parasitic capacitance until the scanning signal Yi becomes the H level again. Therefore, the voltage held by the pixel capacitor 120 is only the voltage ΔVpix. This is a difference voltage between the increased voltage of the pixel electrode 118 and the voltage LCcom of the common electrode 108.
Therefore, the data line driving circuit 190 uses the data signal Xj when the scanning signal Yi is at the H level as a voltage in anticipation that the pixel electrode 118 rises by the voltage ΔVpix when positive polarity writing is designated. To do. That is, the data line driving circuit 190 determines that the data signal Xj has a voltage of the pixel electrode 118 after the rise is higher than the voltage LCcom of the common electrode 108, and the difference voltage between the two corresponds to the gray level of i row and j column. Set the voltage to a value.
Specifically, as shown in FIG. 6, when the voltage ΔVpix increases, the pixel electrode has a range c from a voltage Vw (+) corresponding to white w to a voltage Vb (+) corresponding to black b. Since the voltage becomes higher from the voltage Vw (+) as the gray level becomes lower (darker), the data signal to be applied to the pixel electrode before rising by the voltage ΔVpix lowers the range c by ΔVpix. Within the range d, the voltage becomes higher as the lower gradation is designated.

On the other hand, when the positive polarity writing is designated for the pixel in the i-th row, the negative polarity writing is designated for the pixel in the next (i + 1) -th row. When the scanning signal Y (i + 1) becomes H level, the TFT 116 in (i + 1) rows and j columns is turned on, and the negative data signal Xj is supplied to one end of the pixel capacitor 120 (pixel electrode 118) and one end of the storage capacitor 130. Each is applied.
If the scanning signal Y (i + 1) is at the H level, the scanning signal Y (i + 2) is at the L level, so the TFT 151 corresponding to the (i + 1) th row is turned on, the TFT 152 is turned off, and the (i + 1) th row. The capacitor line 132 is connected to the first power supply line 165. Here, since the first capacity signal Vc1 supplied to the first power supply line 165 designates negative polarity writing for the (i + 1) th row, the period during which the scanning signal Y (i + 1) is at the H level. Among them, the voltage (Vsh + Va) is in the period Ha near the first half, and the voltage Vsh is in the period Hb near the second half.
Therefore, at the end of the period in which the scanning signal Y (i + 1) is at the H level, as shown in FIG. 5C, the pixel capacitor 120 in (i + 1) rows and j columns is charged with a voltage (LCcom−Vj). The storage capacitor 130 is charged with a voltage (Vsh−Vj).

Next, the scanning signal Y (i + 1) becomes L level and the scanning signal Y (i + 2) becomes H level. When the scanning signal Y (i + 1) becomes L level, the TFTs 116 in the pixels in the (i + 1) row 1 column to the (i + 1) row 240 column are turned off. If the scanning signal Y (i + 1) is L level and the scanning signal Y (i + 2) is H level, the TFT 151 corresponding to the (i + 1) th row is turned off, the TFT 152 is turned on, and the (i + 1) th row is turned on. The capacitor line 132 is connected to the second power supply line 167 and drops to the voltage LCcom. For this reason, as shown in FIG. 5D, in the serial connection of the pixel capacitor 120 and the storage capacitor 130, the other end (common electrode) of the pixel capacitor 120 is maintained at the voltage LCcom and Since the end decreases from the voltage Vsh to the voltage LCcom by the voltage ΔV, the voltage of the pixel electrode 118 also decreases due to the charge redistribution.

Specifically, the voltage of the pixel electrode 118 is
Vj− {Cs / (Cs + Cpix)} · ΔV
Thus, the capacitance ratio {Cs / (Cs + Cpix)} is greater than the voltage change ΔV of the capacitor line 132 in the (i + 1) th row, rather than the voltage Vj of the data signal when the scanning signal Y (i + 1) is at the H level.
Decreases by the value multiplied by.

Therefore, when the negative polarity writing is designated, the data line driving circuit 190 uses the data signal Xj when the scanning signal Yi is at the H level as a voltage in anticipation that the pixel electrode 118 drops by the voltage ΔVpix. To do. That is, the data line driving circuit 190 determines that the data signal Xj is a voltage corresponding to the gray level of the i row and j column when the voltage of the pixel electrode 118 after the drop is higher than the voltage LCcom of the common electrode 108. Set the voltage to a value. Specifically, as shown in FIG. 6, when the voltage ΔVpix drops, the pixel electrode has a range e from a voltage Vw (−) corresponding to white w to a voltage Vb (−) corresponding to black b. Since the voltage becomes lower from the voltage Vw (−) as the gradation becomes lower (darker), the data signal to be applied to the pixel electrode before dropping by the voltage ΔVpix increases the range e by ΔVpix. Within the range f, the voltage becomes lower as the lower gradation is designated.

FIG. 7 is a diagram showing the voltage relationship among the scanning signal, the capacitor line, and the pixel electrode. The voltage change of the pixel electrode 118 in i row and j column is indicated by Pix (i, j), and i row (j + 1). The voltage change of the pixel electrode 118 in the column is indicated by Pix (i + 1, j).
As shown in this figure, when positive polarity writing is designated in the i-th row, the voltage Ci of the capacitance line 132 in the i-th row is just before the timing when the scanning signal Yi changes from the H level to the L level. When the next scanning signal Y (i + 1) becomes H level, the voltage becomes LCcom and increases by the voltage ΔV.
On the other hand, when positive polarity writing is designated in the i-th row, negative polarity writing is designated in the (i + 1) -th row, so that the voltage C (i + 1) of the capacitor line 132 in the (i + 1) -th row is The voltage Vsh immediately before the timing when the scanning signal Y (i + 1) changes from the H level to the L level, and when the next scanning signal Y (i + 2) becomes the H level, the voltage becomes LCcom and decreases by the voltage ΔV. To do.
Note that the voltages Ci and C (i + 1) of the capacitor line 132 shown in this figure show an ideal case, and the actual waveforms are as described later.

Next, in the n frame, the actual operation of each row will be described in order. The scanning signal driving circuit 140 first sets the scanning signal Y1 to the H level. On the other hand, when the latch pulse Lp is output at the timing when the scanning signal Y1 becomes the H level, the data line driving circuit 190 is output.
Reads out the display data Da of the pixels in the first row and the 1st to 240th columns, and at the same time, the voltage corresponding to the gradation and the positive polarity specified by the display data Da (range d The data signals are converted to data signals X1 to X240 having higher voltages as a low gradation is specified, and are supplied to the data lines 114 of 1 to 240 columns, respectively. When the scanning signal Y1 becomes H level, the TFTs 116 in the pixels in the 1st row and 1st column to the 1st row and 240th column are turned on, so that the data signals X1 to X240 are applied to these pixel electrodes 118. For this reason, during the period in which the scanning signal Y1 is at the H level, the voltage difference between the voltage of the data signals X1 to X240 and the voltage LCcom of the common electrode 108 is applied to the pixel capacitors 120 in the first row and first column to the first row and 240 columns, respectively. Will be written.

On the other hand, if the scanning signal Y1 is H level, the scanning signal Y2 is L level. For this reason, the capacitor line 132 in the first row is connected to the first power supply line 165 and becomes the voltage (Vsl−Va) in the period Ha near the first half of the period in which the scanning signal Y1 is at the H level. During the period Hb, the voltage is Vsl.
Therefore, when viewed at the timing immediately before the end of the period in which the scanning signal Y1 is at the H level, the voltage of the data signals X1 to X240 and the voltage Vsl are respectively stored in the storage capacitor 130 of the 1st row 1st column to the 1st row 240th column. The difference voltage is written.

Next, the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level.
When the scanning signal Y1 becomes L level, the TFTs 116 in the pixels in the first row and first column to the first row and 240th column are turned off. Further, when the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level, the capacitor line 132 in the first row is connected to the second power supply line 167 and is increased by the voltage ΔV. As a result, the pixel electrode 118 in the first row rises by the voltage ΔVpix and shifts to a higher voltage as the designated gradation becomes darker, and the voltage held in the pixel capacitor 120 differs depending on the gradation. Voltage.

On the other hand, when the latch pulse Lp is output at the timing when the scanning signal Y2 becomes H level, the data line driving circuit 190 reads the display data Da of the pixels in the second row and the first to 240th columns, and Converted to data signals X1 to X240 of a voltage corresponding to the gradation specified by the display data Da and the negative polarity (a voltage that becomes lower as the lower gradation is specified in the range f in anticipation of the fall of ΔVpix) Then, the data lines 114 are supplied to 1 to 240 columns of data lines 114, respectively. When the scanning signal Y2 becomes H level, the TFTs 116 in the pixels in the 2nd row and the 1st column to the 2nd row and the 240th column are turned on, so that the data signals X1 to X240 are applied to these pixel electrodes 118. For this reason, during the period in which the scanning signal Y2 is at the H level, the voltage difference between the voltage of the data signals X1 to X240 and the voltage LCcom of the common electrode 108 is respectively applied to the pixel capacitors 120 in the 2nd row and 1st column to the 2nd row and 240th column. Will be written.

On the other hand, if the scanning signal Y2 is at the H level, the scanning signal Y3 is at the L level. For this reason, the capacitor line 132 in the second row is connected to the first power supply line 165 and becomes the voltage (Vsh + Va) in the period Ha near the first half of the period in which the scanning signal Y2 is at the H level. The voltage Vsh at Hb.
For this reason, when viewed at the timing immediately before the end of the period in which the scanning signal Y2 is at the H level, the voltage of the data signals X1 to X240 and the voltage Vsh are respectively stored in the storage capacitor 130 of 2 rows 1 column to 2 rows 240 columns. The difference voltage is written.

Subsequently, the scanning signal Y2 becomes L level and the scanning signal Y3 becomes H level. When the scanning signal Y2 becomes L level, the TFTs 116 in the pixels of 2 rows and 1 column to 2 rows and 240 columns are turned off. When the scanning signal Y2 becomes L level and the scanning signal Y3 becomes H level, the capacitor line 132 in the second row is connected to the second power supply line 167 and drops from the voltage Vsh to the voltage LCcom by the voltage ΔV. As a result, the pixel electrode 118 in the second row drops by the voltage ΔVpix and shifts to a lower voltage as the designated gradation becomes darker, and the voltage held in the pixel capacitor 120 differs depending on the gradation. Voltage.

In the nth frame, the write operation and the capacitor line voltage shift operation are executed up to the 320th row in the same manner. As a result, in the n frames, the pixel capacitors 120 in the odd-numbered 1, 3, 5,..., 319 rows hold the positive voltage corresponding to the gradation after the voltage ΔV of the capacitor line 132 rises, while the even number. In the pixel capacitors 120 in the second, fourth, sixth,..., 320th rows, a negative voltage corresponding to the gradation is held after the voltage ΔV of the capacitor line 132 is lowered.
The same operation is repeated in the next (n + 1) frame. However, since the writing polarity of each row is inverted, the pixel capacitance 120 in the odd-numbered row corresponds to the gradation after the voltage ΔV of the capacitance line 132 is lowered. While the negative voltage is held, the pixel capacitors 120 in the even-numbered rows hold the positive voltage corresponding to the gradation after the voltage ΔV of the capacitor line 132 rises.

In the AC driving of the pixel capacitor 120, positive and negative voltages are alternately applied to the pixel electrode 118 with respect to the common electrode 108 kept constant at the voltage LCcom, so that the voltage of the pixel electrode 118 is normally set. In the white mode, as shown in FIG. 6, the voltage ranges from a voltage Vb (−) corresponding to negative black to a voltage Vb (+) corresponding to positive black.
However, in the present embodiment, when the pixel electrode is in the positive voltage range c, the voltage of the data signal applied via the data line is increased by the voltage ΔVpix by the voltage shift of the capacitance line, while the pixel electrode is In the case of the voltage range e, the voltage of the data signal is lowered by the voltage ΔVpix due to the voltage shift of the capacitance line, so that the voltage range of the data signal may be narrow.
For this reason, according to the present embodiment, not only the breakdown voltage of the elements constituting the data line driving circuit 190 can be kept low, but also the power consumed wastefully due to the parasitic capacitance of the data line can be reduced.

By the way, in the present embodiment, for the capacitor lines 132 of 1 to 320 rows, for example, if positive polarity writing is designated for the i-th capacitor line 132 for the i-th row, the i-th row scanning signal is generated. In the horizontal scanning period H that becomes the H level, the voltage (Vsl−Va) is obtained in the time period Ha closer to the front, and the voltage Vsl is obtained in the time period Hb closer to the rear, while the negative polarity writing is designated. In the horizontal scanning period, the first capacitance signal Vc1 that becomes the voltage (Vsh + Va) in the period Ha and becomes the voltage Vsh in the period Hb is applied via the TFT 151 that is turned on.
In this way, in the horizontal scanning period H in which the scanning signal to the scanning line is at the H level, the voltage Vsl or the voltage Vsl is not divided into two stages before describing the effect when the voltage of the capacitor line is applied in two stages. The problem of the configuration in which only one of the voltages Vsh is applied will be described.

When the i-th row scanning signal Yi becomes H level, the i-th row capacitance line 132 is connected to the first power supply line 165 by turning on the i-th row TFT 151, and the scanning signal Yi becomes L level. At the same time, when the scanning signal Y (i + 1) becomes the H level, it is connected to the second feeder 167 in order to change the voltage ΔV.
However, various capacitances are actually parasitic on the capacitance line 132 of each row, and a kind of integration circuit is formed by the on-resistance of the TFT 151. Therefore, the voltage Vsl when the scanning signal becomes H level. Alternatively, the change to the voltage Vsh is not ideally pulse-like, and as shown in FIG. 8A or FIG.
Further, since the capacitor lines 132 in the 1st to 320th rows intersect with the data lines 114 in the 1st to 240th columns respectively while maintaining electrical insulation, the data lines in the respective columns as shown by broken lines in FIG. It couple | bonds with 114 through a capacity | capacitance. For this reason, the capacitor line 132 of each row is also affected by the voltage change of the data line 114.

Here, the voltage change direction of the data line is determined according to the display content in the display region 100. For example, in the capacitor line 132 in the i-th row, the capacitance in the i-th row when the scanning signal Yi becomes H level. When the voltage change direction in the line is opposite to the voltage change in the data line, the i-th capacitor line 132 is greatly affected by the voltage change in the data line 114. Specifically, when the positive polarity writing is designated and the scanning signal Yi becomes H level, the voltage of the data line when the capacitance line 132 of the i-th row drops from the voltage LCcom toward the voltage Vsl. If the change is in the upward direction, a differential pulse (positive noise) in the positive direction as shown in FIG. 8A is superimposed on the capacitance line 132 in the i-th row.
For this reason, the voltage Ci of the capacitance line 132 in the i-th row actually converges with a deviation of the voltage ΔVp from the voltage Vsl when viewed at the end timing of the horizontal scanning period, as shown in FIG. A state occurs in which the voltage ΔV does not change.
When the scanning signal Yi changes from the H level to the L level and the scanning signal Y (i + 1) changes to the H level in a state where the i-th capacitance line has not converged to the voltage Vsl, the i-th capacitance line 132 Therefore, the voltage change of ΔVp changes only by ΔVp (ΔV−ΔVp).

Here, considering the pixel in the i-th row and j-th column, when the data signal Xj is the voltage Vj during the period in which the scanning signal Yi is at the H level, the i-th row is obtained when the scanning signal Y (i + 1) is at the H level. When the capacitance line 132 of the pixel changes only by the voltage (ΔV−ΔVp), the voltage of the pixel electrode 118 is
Vj + {Cs / (Cs + Cpix)}. (ΔV−ΔVp)
Than the original voltage,
{Cs / (Cs + Cpix)} · ΔVp
The gradation changes according to this voltage.
This phenomenon occurs not only for i rows and j columns but also for one row of pixels corresponding to the capacitance line 132 of the i row, so that it is visually recognized as uneven display in the horizontal direction.

Note that the influence of the blunting due to the on-resistance of the TFT 151 and the voltage change of the data line is dominant because various conditions such as the configuration of the panel and the driving method are entangled. . If the influence of waveform dullness is large, the on-resistance of the TFT 151 may be reduced, but the TFT 151 is required to have a large transistor size. When the transistor size of the TFT 151 is increased, the outer area (so-called frame) of the display region 100 is enlarged when the TFT 151 is built in the element substrate.
In any case, when the voltage of each capacitor line 132 changes from the H level to the L level to the corresponding scanning line, a state in which the voltage ΔV does not change accurately occurs.

In addition, here, an example has been described in which positive noise is superimposed on the i-th capacitor line 132 when positive-polarity writing is designated for the i-th row, but negative-polarity writing is designated. In the case where negative noise is superimposed on the capacitance line 132, the capacitance line 132 does not change from the voltage ΔVsh to the voltage LCcom, as shown in FIG. appear.

In contrast, in the present embodiment, if positive polarity writing is designated for the i-th row, the first capacitance signal Vc1 is closer to the front in the horizontal scanning period H in which the scanning signal Yi is at the H level. During this period Ha, the voltage becomes (Vsl-Va), and when the voltage LCcom changes to the voltage Vsl, the voltage Va is excessively shaken. For this reason, since the positive noise is rapidly attenuated, the voltage Ci of the capacitance line 132 in the i-th row is actually as shown in FIG. At this time, the positive noise may not completely disappear depending on the display content, or the voltage Ci of the capacitance line may pass the target voltage Vsl and be further swung to the lower side. However, even in such a case, the difference from the voltage Vsl is small. And in the period Hb closer to the rear, the first
Since the capacitance signal Vc1 becomes the voltage Vsl, the influence of the positive noise becomes so small that it can be ignored, and the voltage Ci of the capacitance line can be converged to the voltage Vsl.
If negative polarity writing is specified for the i-th row, the first capacitance signal Vc1 becomes a voltage (Vsh + Va) in the period Ha, and excessively swings by the voltage Va when changing from the voltage LCcom to the voltage Vsh. Therefore, as shown in FIG. 8D, the influence of negative noise is reduced to a negligible level, and the voltage Ci of the capacitance line can be converged to the voltage Vsh.

Therefore, according to the present embodiment, since the capacitor line 132 can be accurately changed to the voltage ΔV, the occurrence of display unevenness that occurs in the horizontal direction can be suppressed while the voltage amplitude of the data line is reduced as described above. In addition, since it is not necessary to reduce the on-resistance of the TFT 151, the frame can be narrowed and the area of the display region 100 can be increased.

<Application and modification of the first embodiment>
In the first embodiment described above, the following applications and modifications are possible.

<Part 1>
As shown in FIG. 3, the first power supply line 165 and the second power supply line 167 intersect with the scanning line 112 while maintaining insulation, and thus parasitic capacitance is generated. Therefore, when the voltage between the first power supply line 165 and the second power supply line 167 changes, wasteful power is consumed by this parasitic capacitance. In general, if the parasitic capacitance is C, the change voltage is V, and the change frequency (frequency) is f, the power consumption can be expressed by CV ² f.

Therefore, a configuration in which not only the first capacitance signal Vc1 but also the second capacitance signal Vc2 is changed with time is conceivable. The purpose of the second capacitance signal Vc2 is to change the voltage of the second capacitance signal Vc2 by the voltage ΔV after the voltage of the first capacitance signal Vc1 is applied to the capacitance line. The voltage ΔV is changed by using the relative change between Vc1 and the second capacitance signal Vc2. Specifically, as shown in FIG. 9, the second capacitance signal Vc2 is set to the voltage Vfl when the positive polarity writing is designated, and is set to the voltage Vfh when the negative polarity writing is designated. . On the other hand, if positive polarity writing is designated, the first capacitance signal Vc1 is supplied with the voltage (Vfl−
Va), the voltage Vfl in the period Hb, and if negative polarity writing is specified, the voltage (Vfh + Va) in the period Ha and the voltage Vfh in the period Hb. Then, the absolute value of the difference between the voltage Vfh and the voltage Vfl is set to be the voltage ΔV.
With this configuration, the voltage amplitude of the first capacitance signal Vc1 and the second capacitance signal Vc2 can be made almost half the voltage amplitude of the first capacitance signal Vc1 in FIG. However, since both the first feed line 165 and the second feed line 167 change in voltage,
2C (V / 2) ² f = (1/2) CV ² f
Thus, compared with the case of FIG. 4, the power consumed by the first feeder 165 and the second feeder 167 can be halved.

<Part 2>
Although not particularly shown in the figure, the gate electrode of the TFT 151 in the i-th row is connected to the scanning line 112 in the (i + 2) -th row, not the (i + 1) -th scanning line 112, in the structure. As shown in FIG. 10, the second capacitance signal Vc2 may be configured by inverting the waveform shown in FIG. If the first capacitance signal Vc1 and the second capacitance signal Vc2 have waveforms as shown in FIG. 10, the voltage change directions at the start (or end) timing of the horizontal scanning period are opposite to each other. The influence of the voltage change of 165 can be offset by the influence of the voltage change of the second feeder 167, or can be suppressed to a small level.

<Part 3>
Further, the present invention is not limited to the scanning line inversion method, and may be a surface inversion (frame inversion) method in which the writing polarity in the frame period is the same for each row. When the frame inversion method is used, the polarity designation signal Pol, the first capacitance signal Vc1, and the second capacitance signal Vc2 are as shown in FIG. 11, for example.
That is, in the case of the surface inversion method, the polarity designation signal Pol is inverted every frame period, and the first capacitance signal Vc1 is a period during which the selection voltage is applied to the scanning line if the positive polarity writing is designated. Of these, the voltage (Vsl−Va) is obtained in the period Ha, and the voltage Vsl is obtained in the period Hb. On the other hand, if negative polarity writing is designated, the period Ha is selected among the periods in which the selection voltage is applied to the scanning lines.
The voltage becomes (Vsh + Va) at, and becomes the voltage Vsh during the period Hb. The second capacitance signal V
c2 may be constant at the voltage LCcom.

<Part 4>
In addition, since the characteristics of the TFT 151, particularly the on-resistance, tend to change depending on the ambient temperature, the degree of waveform dullness when the voltage of the capacitor line changes changes according to the temperature. For this reason, the voltage ± Va that fluctuates the voltages Vsl and Vsh in the period Ha may be changed according to the temperature. In the horizontal scanning period H in which the selection voltage is applied to one scanning line, the period Ha, The ratio of Hb may be changed, or both the voltage ± Va and the ratios of the periods Ha and Hb may be changed.

Second Embodiment
Next, an electro-optical device according to a second embodiment of the invention will be described. FIG. 12 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment.
12 differs from the first embodiment shown in FIG. 1 mainly in that TFTs 176 are provided corresponding to each row, a detection line 185 and a capacitance signal output circuit 31 are provided, and The control circuit 20 outputs the target signal Vc1ref and the period specifying signal Hs. Therefore, the following will be described focusing on these differences.

  First, the capacitor line driving circuit 150 is provided with a TFT 176 that functions as a switching element for detection corresponding to the capacitor line 132 of each row. Here, the gate electrode of the i-th TFT 176 is connected to the i-th scanning line 112, the source electrode is connected to the i-th capacitance line 132, and the drain electrode is connected to the detection line 185. The detection line 185 is commonly connected to the drain electrode of the TFT 176 in each row.

FIG. 13 is a plan view showing a configuration of the capacitive line driving circuit 150 and the vicinity of the periphery of the display region 100 in the element substrate according to the second embodiment.
The configuration shown in this figure is substantially the same as the example shown in FIG. 3 except for the TFT 176 and its periphery. The gate electrode of the i-th TFT 176 is a portion branched from the i-th scanning line 112 in a T-shape in the Y (downward) direction. The source electrode 132c and the detection line 185 of the TFT 176 corresponding to the i-th row are obtained by patterning the third conductive layer. Among these, the source electrode 132c of the TFT 176 is connected to the i-th capacitor line 132 through a contact hole 132d that penetrates the gate insulating film and the protective layer. Further, the wide portion of the detection line 185 is the drain electrode of the TFT 176.

FIG. 14 is a diagram illustrating a configuration of the capacitance signal output circuit 31.
As shown in this figure, the capacitive signal output circuit 31 includes an operational amplifier 300, switches 311 and 312, a NOT circuit 315, and a resistance element 316.
The output terminal of the operational amplifier 300 is connected to one end of the first power supply line 165 and the switch 311, and the detection line 185 is connected to one end of the switch 312. The other ends of the switches 311 and 312 are connected to the inverting input terminal (−) of the operational amplifier 300, respectively. In other words, the switch 311 (first switch) is electrically inserted between the output terminal (first feed line 165) and the inverting input terminal (−) of the operational amplifier 300, and the switch 312 (second switch). Is electrically interposed between the detection line 185 and the inverting input terminal (−).

On the other hand, the target signal Vc1ref from the control circuit 20 is supplied to the non-inverting input terminal (+) of the operational amplifier 300. A switch 3 is provided between the output terminal and the inverting input terminal (−) of the operational amplifier 300.
11, a resistance element 316 is inserted.
The switches 311 and 312 are exclusively turned on / off according to the logic level of the period specifying signal Hs supplied from the control circuit 20. Specifically, the switches 311 and 312 are turned on and off when the period designation signal Hs is at the H level, and are turned off and on when the period designation signal Hs is at the L level.

Here, as shown in FIG. 15, the period specifying signal Hs becomes H level in the front period Ha in the horizontal scanning period H in which the selection voltage is applied to a certain scanning line, and is a period closer to the rear. It is a signal that becomes L level at Hb. On the other hand, the target signal Vc1ref supplied from the control circuit 20 has the same waveform as the first capacitance signal Vc1 in FIG. 4, as shown in FIG.

In such a configuration, when the scanning signal Yi is at the H level, the i-th TFT 176 is turned on, so that the i-th capacitor line 132 is connected to the detection line 185. However, since the switch 312 is turned off in the period Ha, the voltage of the detection line 185 does not affect the output of the capacitance signal output circuit 31.
Further, since the switch 311 is turned on in the period Ha, the operational amplifier 300 becomes a voltage follower circuit. For this reason, during the period Ha, the capacitance signal output circuit 31 buffers the voltage of the target signal Vc1ref as it is to obtain the first capacitance signal Vc1, and the first feeder 16
5 is output.
Here, the target signal Vc1ref becomes the voltage (Vsl−Va) if the positive polarity writing is designated for the i-th row in the period Ha, and the voltage (Vsl−Va) if the negative polarity writing is designated. Vsh + Va), and in the second embodiment, this voltage is supplied to the first feeder 165 as it is, so that the effects of waveform dullness and noise can be rapidly attenuated as in the first embodiment.

Next, in the period Hb, the switches 311 and 312 are turned off and on, respectively, and the detection line 1
The voltage 85 is fed back to the inverting input terminal (−) of the operational amplifier 300. Therefore, in the period Hb, the capacitance signal output circuit 31 outputs the first capacitance signal Vc1 that is controlled so that the voltage of the detection line 185 becomes the voltage of the target signal Vc1ref.
Here, in the horizontal scanning period H in which the scanning signal Yi is at the H level, the (actual) voltage of the i-th capacitor line 132 appears on the detection line 185 by the i-th TFT 176. On the other hand, the target signal Vc1ref is the voltage Vsl if positive polarity writing is designated for the i-th row in the period Hb, and is the voltage Vsh if negative polarity writing is designated. For this reason, if the positive polarity writing is designated for the i-th capacitance line 132 in the period Hb, the capacitance signal output circuit 31 designates the negative polarity writing so as to be the voltage Vsl. If so, negative feedback control is performed so that the voltage Vsh is obtained.

Therefore, according to the second embodiment, as compared with the first embodiment, at the end of the horizontal scanning period H in which the scanning signal Yi is at the H level, the capacitor line 132 in the i-th row is set to a level of waveform dullness or noise. Regardless, the voltage Vsl or the voltage Vsh can be stabilized more accurately.
For this reason, according to the second embodiment, as in the first embodiment, the voltage amplitude of the data line can be reduced, the transistor size of the TFT 151 does not need to be increased as necessary, and the first embodiment is performed. Compared with the form, it is possible to more reliably suppress the occurrence of display unevenness that occurs in the horizontal direction.
For example, the capacitance line 132 in the i-th row is close to the voltage LCcom immediately after the scanning signal Yi becomes the H level, so that the difference from the voltage Vsl or the voltage Vsh is large. For this reason, the scanning signal Yi
In the configuration in which negative feedback control is performed so that the capacitance line 132 (detection line 185) in the i-th row becomes the voltage Vsl or the voltage Vsh over the horizontal scanning period H during which the H level becomes H level, immediately after the scanning signal Yi becomes H level. The current consumed by the operational amplifier 300 may increase or the operational amplifier 300 may oscillate. However, in the second embodiment, in the period Ha immediately after the scanning signal Yi becomes the H level, it functions as a simple voltage follower circuit, not as a negative feedback control, so such a possibility is extremely small.
In addition, although operation | movement description is represented and represented here by the i-th line, about 1-320 lines, it is performed in order similarly.

<Application and Modification of Second Embodiment>
In the second embodiment, the following applications and modifications are possible.
Specifically, as shown in FIG. 16, in the capacitance signal output circuit 31, for example, a period designation signal Hs is H between the first feeder 165 (the output terminal of the operational amplifier 300) and the detection line 185.
If it is level, a switch 318 (auxiliary switch) that turns on may be inserted.
As described above, since the operational amplifier 300 becomes a voltage follower circuit during the period Ha, the voltage of the target signal Vc1ref is output as it is to the first power supply line 165 as the first capacitance signal Vc1, and the capacitance line is connected via the TFT 151 in the on state. 132. In this configuration, when the switch 318 is turned on, the first power supply line 165 is connected to the detection line 185. Therefore, the first capacitance signal Vc1 is also transmitted through the path of the switch 318, the detection line 185, and the TFT 176 in the on state. The same capacity line 132 is supplied. That is, in the configuration shown in FIG. 16, there are two paths for supplying the first capacitance signal Vc1 to the capacitance line 132 in the period Ha.
Therefore, according to the configuration, in the period Ha, the combined resistance value from the output terminal of the operational amplifier 300 to the capacitance line is a fraction with the sum of the resistance values in the two paths as the denominator and the product of the resistance values as the numerator. In particular, the influence of waveform dullness can be kept small.

In this configuration, the signal flow in the TFT 176 is in the direction from the capacitance line 132 to the detection line 185 in the period Hb, but is in the direction from the detection line 185 to the capacitance line 132 in the period Ha. The TFT 176 is preferably not a single channel but a transmission gate (analog switch) combining both p-type and n-type.
Further, in this configuration, the ON period of the switch 318 and the ON period of the switch 311 (the OFF period of the switch 312) are matched with each other, but without being matched, either one is turned off first. And may be controlled. Note that. When the switch 318 is controlled independently of the switches 311 and 312, the control signal increases.

<Third Embodiment>
In the first and second embodiments described above, when the scanning signal Y (i + 1) is changed from the H level to the L level, the scanning signal Yi is again set to the H level after the passage of one frame. Until it becomes, it will be in the high impedance state (floating state) which is not electrically connected to any part. Since the capacitor lines 132 in each row are coupled to other wirings that intersect (or are close to each other) via parasitic capacitance, they are easily affected by voltage fluctuations in these wirings.
Therefore, a third embodiment will be described in which the voltage is fixed without setting the capacitance line 132 of each row to the high impedance state.

FIG. 17 is a block diagram illustrating a configuration of an electro-optical device according to the third embodiment of the invention.
As shown in this figure, in the third embodiment, the configuration of the capacitive line driving circuit 150 is mainly different from that of the second embodiment. Specifically, the capacitor line driving circuit 150 according to the third embodiment includes a set of n-channel TFTs 153 and 154 in addition to the TFTs 151, 152, and 176 with respect to the capacitor lines 132 in the first to 320th rows. .
Here, the TFTs 151 to 154 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 151 is connected to the i-th scanning line 112, and its source electrode is connected to the first power supply line 165. However, the gate electrode of the TFT 152 is commonly connected to the drain electrodes of the TFTs 153 and 154. Note that the source electrode of the TFT 152 is connected to the second power supply line 167, and the drain electrodes of the TFTs 151 and 152 are commonly connected to the i-th capacitor line 132.

The gate electrode of the i-th TFT 153 (third transistor) is connected to the i-th scanning line 112, the source electrode is connected to the off-voltage power supply line 161, and the TFT 154 (fourth transistor) gate. The electrode is connected to the scanning line 112 in the (i + 1) th row, and the source electrode is connected to the on-voltage power supply line 163.
Here, the signal Voff is supplied to the off-voltage power supply line 161, and the voltage of the signal Voff is in a state where the TFT 152 is turned off (the source and the drain are not conductive) even when the signal Voff is applied to the gate electrode of the TFT 152. The voltage to be Further, a signal Von is supplied to the on-voltage power supply line 163, and the voltage of the signal Von turns on the TFT 152 (conduction between the source and drain) when it is applied to the gate electrode of the TFT 152. Voltage.
In the configuration shown in FIG. 17, the arrangement of the TFTs 151 and 152 is reversed left and right as compared with the configuration shown in FIG. 12, but this is a convenient measure, and the first feed line 165, There is no change in the connection relationship between the two power supply lines 167 and the capacity line 132. Further, the same waveform as that of the second embodiment (see FIG. 15) can be used for signals in the third embodiment.

FIG. 18 is a plan view showing the configuration of the capacitive line drive circuit 150 and the vicinity of the periphery of the display region 100 in the element substrate according to the third embodiment.
As shown in this figure, the gate electrode of the TFT 153 in the i-th row is a portion branched in a T-shape in the Y (downward) direction from the scanning line 112 in the i-th row, and the TFT 154 corresponding to the i-th row in the same manner. The gate electrode is a portion branched from the scanning line 112 in the (i + 1) th row in the Y (up) direction in a T shape. The common drain electrode 51a of the TFTs 153 and 154 is connected to the gate electrode 51c of the TFT 152 through the contact hole 51b.
Further, in the third embodiment, the gate electrodes of the i-th TFTs 151 and 176 share a portion branched in a T-shape from the i-th scanning line 112 in the Y (downward) direction. Further, the drain electrode 176a of the TFT 176 in the i-th row is once connected to a wiring 176c having a patterned gate electrode layer through a contact hole 176b. The wiring 176c is further connected to a detection line through a contact hole 176d. 185.

According to the third embodiment, when the scanning signal Yi becomes H level, the 153 in the i-th row is turned on over the horizontal scanning period H. For this reason, the TFT 152 in the i-th row is turned off because the signal Voff of the off-voltage power supply line 161 is applied to the gate electrode. In addition, the 151st line 151
176 is turned on, and the capacitor line 132 in the i-th row is connected to the detection line 185 together with the first power supply line 165, so that the capacitor signal output circuit 31 has the voltage of the target signal Vc1ref.
Controlled by.

  Next, when the scanning signal Yi becomes L level and the scanning signal Y (i + 1) becomes H level, the i-th row 153 is turned off and the TFT 154 is turned on over the horizontal scanning period (H). For this reason, the TFT 152 in the i-th row is turned on because the signal Von of the on-voltage power supply line 163 is applied to the gate electrode. For this reason, the capacitor line 132 in the i-th row is connected to the second feeder line 167 and becomes the voltage LCcom.

Subsequently, when the scanning signal Y (i + 1) becomes L level and the scanning signal Y (i + 2) becomes H level, the i-th row 154 is turned off, so that the gate electrode of the TFT 152 is in a high impedance state. The voltage of the signal Von that is in the immediately preceding state is held by the parasitic capacitance. For this reason, since the TFT 152 is kept on, the i-th capacitor line 132 maintains the voltage LCcom of the second power feed line 167. That is, the i-th capacitance line 1
No. 32 determines the voltage LCcom even if the scanning signals Yi and Y (i + 1) are both at the L level.

Therefore, according to the third embodiment, since the capacitor line 132 in each row does not enter a high impedance state, the voltage amplitude of the data line can be reduced, and the transistor size of the TFT 151 is not increased as necessary. In addition, as compared with the second embodiment, it is possible to further reliably suppress the occurrence of display unevenness that occurs in the horizontal direction.
Also in the third embodiment, the configuration shown in FIG. 16 as well as FIG. 14 can be adopted for the capacitance signal output circuit 31.

<Fourth embodiment>
Next, an electro-optical device according to a fourth embodiment of the invention will be described. FIG. 19 is a diagram illustrating a configuration of an electro-optical device according to the fourth embodiment of the invention.
The main difference between the configuration shown in this figure and the second embodiment (see FIG. 12) is that a detection capacitor 179 is provided instead of the TFT 176 in each row of the capacitor line driving circuit 150. .
Specifically, one end of the detection capacitor 179 corresponding to the odd row is connected to the capacitor line 132 of the row, and the other end is connected to the first detection line 187, while the detection capacitor 179 corresponding to the even row is , One end thereof is connected to the capacitor line 132 of the row, and the other end is connected to the second detection line 188.

The switch 35 selects one of the detection lines according to a signal Oe supplied from the control circuit 20. Specifically, the switch 35 selects the first detection line 187 when the scanning signal to the odd-numbered row is at the H level by the scanning line driving circuit 140, and the scanning signal to the even-numbered row is at the H level. If so, the second detection line 188 is selected.

FIG. 20 is a plan view showing the configuration of the capacitive line driving circuit 150 and the vicinity of the display area 100 in the element substrate according to the fourth embodiment.
As shown in this figure, the odd-numbered i-th row detection capacitors 179 are formed by overlapping the i-th row capacitance line 132 with the wider first detection line 187 via the insulating layer. It is configured. Similarly, the detection capacitors 179 in the even (i + 1) th row are configured by overlapping the widened portion of the capacitor line 132 in the (i + 1) th row with the widened portion of the second detection line 188 through an insulating layer. Has been.

According to the fourth embodiment, when the scanning line 112 to which the selection voltage is applied is an odd number row, when noise occurs in the selected odd number row capacitance line 132, the noise is selected. The signal propagates to the first detection line 187 via the row detection capacitor 179 and is supplied to the capacitance signal output circuit 31 via the switch 35. The capacitance signal output circuit 31 buffers and outputs to the first feeder 165 the voltage that is excessively shifted by the voltage Va with respect to the voltage change direction in the period Ha of the horizontal scanning period as described above, and outputs the voltage in the period Hb. Outputs a voltage controlled so that the voltage of the first detection line 187 becomes the voltage of the target signal Vc1ref. Therefore, at the end of the horizontal scanning period, the selected odd-numbered capacitor line 132 has the voltage Vsl or voltage Stabilizes more precisely to one of the Vsh.
On the other hand, in the case where the scanning line 112 to which the selection voltage is applied is an even row, when noise occurs in the selected capacitance line 132 in the even row, the noise is detected capacitance 179 in the selected even row. Is transmitted to the second detection line 188 and supplied to the capacitance signal output circuit 31 via the switch 35, and thus the same operation is performed.
As a result, in the fourth embodiment, as in the second embodiment, the voltage amplitude of the data line can not be reduced, the transistor size of the TFT 151 does not have to be increased as necessary, and the voltage is generated in the lateral direction. It is possible to more reliably suppress the occurrence of display unevenness.

In the fourth embodiment, the element connecting the capacitance line 132 and the detection line is the detection capacitance 179 that does not flow a direct current component. For this reason, the configuration shown in FIG. 16 cannot be used as the capacitance signal output circuit 31.
Also in the fourth embodiment, as in the third embodiment, a set of TFTs 153 and 154 may be provided in each row so that the potential of the capacitor line 132 is determined in the non-selection period.

<Related matters of the first to fourth embodiments>
In the embodiment described above, the gate electrode of the TFT 152 (TFT 154 in the third embodiment) corresponding to the i-th capacitor line 132 is connected to the next (i + 1) -th scanning line 112 in the capacitor line driving circuit 150. However, the configuration may be such that the scanning lines 112 are separated by a certain number of rows m (m is an integer of 2 or more). However, when the number m of separated rows increases, it is necessary to connect the gate electrode of the TFT 152 corresponding to the i-th capacitor line 132 to the (i + m) -th scanning line 112, and the wiring becomes complicated.
In addition, in order to drive up to the TFT 152 (154) corresponding to the capacitor line 132 of the final 320th row, m dummy scanning lines 112 are required. However, if m is “1” as in each embodiment, the vertical blanking period is eliminated, and the gate electrode of the TFT 152 (154) corresponding to the capacitor line 132 in the 320th row is used as the scanning line in the first row. 112, and for example, if m is “2”, the vertical blanking period is eliminated, and the gate electrode of the TFT 152 (154) corresponding to the capacitor line 132 in the 319th and 320th rows is replaced by If each is connected to the first and second rows of scanning lines 112, there is no need to provide dummy scanning lines.
In addition, since it is meaningless to specify the writing polarity in the vertical blanking period, a logic signal such as the period specifying signal Ha may be fixed at a certain level. Furthermore, the voltage Vcom of the common electrode 108 may be switched to a low level when the positive polarity writing is designated and switched to a high level when the negative polarity writing is designated.

Further, in each embodiment, the liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108 as the pixel capacitor 120, and the electric field direction applied to the liquid crystal is set to be the direction perpendicular to the substrate surface. A common electrode may be stacked so that the direction of the electric field applied to the liquid crystal is the horizontal direction of the substrate surface.
On the other hand, in each embodiment, since the vertical scanning direction is a direction from the top to the bottom in FIG. 1, the gate electrode of the TFT 152 corresponding to the i-th capacitor line 132 is used as the (i + 1) -th scanning line. In the case where the vertical scanning direction is the direction from the bottom to the top, it is only necessary to connect to the scanning line 112 in the (i-1) th row. That is, the gate electrode of the TFT 152 corresponding to the i-th capacitance line 132 is a scanning line other than the i-th scanning line, and the selection voltage is applied after the application of the selection voltage to the i-th scanning line is completed. Any structure connected to the scanning line 112 to be applied may be used.

  Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed. Further, for example, G is changed to YG (yellowish green) and EG ( It is also possible to make a wide color band by forming one dot with these four color pixels.

In the above description, the reference of the writing polarity is the voltage LCcom applied to the common electrode 108. This is a case where the TFT 116 in the pixel 110 functions as an ideal switch. -Due to the parasitic capacitance between the drains, a phenomenon in which the potential of the drain electrode (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, penetration, field-through, etc.) occurs. In order to prevent the deterioration of the liquid crystal, the pixel capacitor 120 must be AC driven. However, when AC driving is performed with the applied voltage LCcom applied to the common electrode 108 as a reference for the writing polarity, negative writing is performed for pushdown. The effective voltage value of the pixel capacitor 120 is slightly larger than the effective value of the positive polarity writing (when the TFT 116 is n-channel). Therefore, in actuality, the reference voltage of the write polarity and the voltage LCcom of the common electrode 108 are separated from each other, and the reference voltage of the write polarity is set higher than the voltage LCcom so that the influence of pushdown is offset. You may make it set by offsetting.
Further, since the storage capacitor 130 is insulated in terms of direct current, it is sufficient that only the potential difference applied to the first feeder 165 and the second feeder 167 has the above-described relationship. The potential difference between and may be any number of volts.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 21 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to any of the embodiments.
As shown in this figure, a mobile phone 1200 includes the electro-optical device 10 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that the components of the electro-optical device 10 corresponding to the display region 100 do not appear as appearance.

  As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 21, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. And car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, photo storage viewers, devices equipped with touch panels, and the like. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the voltage shift of a capacitive line in the same electro-optical apparatus. It is a figure which shows the relationship between the voltage of the data signal of the same electro-optical apparatus, and the voltage of a pixel electrode. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. It is a figure which shows the influence of the waveform dullness of a capacitance line, noise, etc. in the same electro-optical device. FIG. 6 is a diagram for explaining another operation (part 1) of the electro-optical device. FIG. 10 is a diagram for explaining another operation (part 2) of the same electro-optical device. FIG. 11 is a diagram for explaining another operation (part 3) of the same electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. It is a figure which shows the structure of the capacitive signal output circuit in the same electro-optical apparatus. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows another structure of a capacitive signal output circuit. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. FIG. 3 is a diagram illustrating a peripheral configuration of a display area of the electro-optical device. It is a figure which shows the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 31 ... Capacitance signal output circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 120 ... Pixel capacity , 130: Storage capacitor, 132: Capacitor line, 140: Scanning line drive circuit, 150 ... Capacitance line drive circuit, 151-154 ... TFT, 165 ... First feed line, 167 ... Second feed line, 176 ... TFT, 179 ... Detection capacity, 185 ... detection line, 300 ... op amp, 311, 312, 318 ... switch, 1200 ... cell phone

Claims (11)

A plurality of scan lines;
Multiple data lines,
A plurality of capacitance lines provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
Each has one end connected to the data line and a conductive state when a selection voltage is applied to the scanning line, and one end connected to the other end of the pixel switching element. A pixel capacitor connected to a common electrode, a storage capacitor electrically interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line,
A pixel containing
A drive circuit for an electro-optical device having:
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying a selection voltage to the selected scanning lines;
For the capacitance line provided corresponding to one scanning line,
The first voltage is applied in the first period closer to the front in the period in which the selection voltage is applied to the one scanning line,
Applying a second voltage in a second period closer to the rear in time;
A capacitance line driving circuit that changes the second voltage by a predetermined value after the application of the selection voltage to the one scanning line is completed;
A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the selection voltage is applied via the data line;
Comprising
The first voltage is a voltage different from the second voltage, and is a voltage in a direction opposite to the direction of change to the predetermined value with respect to the second voltage. circuit. In one pixel capacitance, positive polarity writing in which the potential of the pixel electrode with respect to the common electrode is on the higher side and negative polarity writing on the lower side are alternately performed,
The capacitor line driving circuit includes:
Applying a low voltage as the second voltage to the capacitor line of the pixel capacitance that is the positive polarity writing,
The drive circuit of the electro-optical device according to claim 1, wherein a high potential voltage is applied as the second voltage to a capacitor line of a pixel capacitor that becomes the negative polarity writing. The capacitor line driving circuit includes:
Corresponding to each of the capacitance lines, it has a set of first and second transistors,
In the first transistor corresponding to one capacitance line, a gate electrode is connected to a scanning line corresponding to the one capacitance line, and a source electrode is connected to a first supply line that supplies a first capacitance signal.
The second transistor has a gate electrode connected to a scanning line separated by a predetermined number of rows from the one scanning line, a source electrode connected to a second feeding line that feeds a second capacitance signal,
The drive circuit of the electro-optical device according to claim 1, wherein drain electrodes of the first and second transistors are commonly connected to the one capacitor line. The capacitor line driving circuit includes:
Corresponding to each of the capacitance lines, it has a set of first to fourth transistors,
In the first transistor corresponding to one capacitance line, a gate electrode is connected to a scanning line corresponding to the one capacitance line, and a source electrode is connected to a first supply line that supplies a first capacitance signal.
The second transistor has a source electrode connected to a second feed line that feeds the second capacitance signal,
The third transistor has a gate electrode connected to a scanning line corresponding to the one capacitor line, and a source electrode connected to an off-voltage power supply line that supplies an off-voltage for turning off the second transistor,
In the fourth transistor, a gate electrode is connected to a scanning line separated by a predetermined number of rows from the one scanning line, and a source electrode supplies an on-voltage power supply line for supplying an on-voltage for turning on the second transistor. Connected to
The drain electrodes of the third and fourth transistors are commonly connected to the gate electrode of the second transistor;
The drive circuit of the electro-optical device according to claim 1, wherein drain electrodes of the first and second transistors are connected to the one capacitance line. Provided corresponding to each of the capacitance lines, and each is turned on between the one capacitance line and the detection line when the selection voltage is applied to the scanning line corresponding to the one capacitance line. A switching element for detection;
A voltage obtained by buffering the first voltage in the first period;
The voltage controlled so that the voltage of the detection line becomes the second voltage in the second period,
A capacitance signal output circuit that outputs the first capacitance signal to the first feeder line, respectively.
The drive circuit of the electro-optical device according to claim 3, further comprising: The capacitance signal output circuit includes:
An operational amplifier having the first voltage in the first period and the second voltage in the second period being input to a non-inverting input terminal and an output terminal connected to the first power supply line;
A first switch electrically inserted between an output terminal of the operational amplifier and an inverting input terminal of the operational amplifier, turned on in the first period, and turned off in the second period;
A second switch electrically interposed between the detection line and the inverting input terminal of the operational amplifier, and turned off in the first period and turned on in the second period;
The drive circuit for the electro-optical device according to claim 5, comprising: The capacitance signal output circuit includes:
6. The auxiliary switch according to claim 5, further comprising an auxiliary switch that is turned on between the power supply line and the detection line in a period that is temporally forward in a period in which the selection voltage is applied to one scanning line. Electro-optic device. A detection capacitor electrically inserted between the one capacitance line and the detection line, corresponding to each of the capacitance lines,
A voltage obtained by buffering the first voltage in the first period;
The voltage controlled so that the voltage of the detection line becomes the second voltage in the second period,
A capacitance signal output circuit that outputs the first capacitance signal to the first feeder line, respectively.
The drive circuit of the electro-optical device according to claim 3, further comprising: A plurality of scan lines;
Multiple data lines,
A plurality of capacitance lines provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
Each has one end connected to the data line and a conductive state when a selection voltage is applied to the scanning line, and one end connected to the other end of the pixel switching element. A pixel capacitor connected to a common electrode, a storage capacitor electrically interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line,
A pixel containing
A driving method of an electro-optical device having:
Selecting the plurality of scanning lines in a predetermined order, and applying a selection voltage to the selected scanning lines;
A first voltage is applied in a first period closer to the front in the time period in which a selection voltage is applied to the one scanning line with respect to a capacitor line provided corresponding to one scanning line,
Applying a second voltage in a second period closer to the rear in time;
After the application of the selection voltage to the one scanning line is completed, the second voltage is changed by the predetermined value,
A data signal having a voltage corresponding to the gradation of the pixel is supplied to the pixel corresponding to the scanning line to which the selection voltage is applied via the data line,
The first voltage is a voltage different from the second voltage, and is a voltage in a direction opposite to the direction of change to the predetermined value with respect to the second voltage. . A plurality of scan lines;
Multiple data lines,
A plurality of capacitance lines provided corresponding to the plurality of scanning lines;
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
Each has one end connected to the data line and a conductive state when a selection voltage is applied to the scanning line, and one end connected to the other end of the pixel switching element. A pixel capacitor connected to a common electrode, a storage capacitor electrically interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line,
A pixel containing
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying a selection voltage to the selected scanning lines;
For the capacitance line provided corresponding to one scanning line,
The first voltage is applied in the first period closer to the front in the period in which the selection voltage is applied to the one scanning line,
Applying a second voltage in a second period closer to the rear in time;
A capacitance line driving circuit for changing the predetermined voltage from the second voltage after the application of the selection voltage to the one scanning line is completed;
A data line driving circuit for supplying a data signal of a voltage corresponding to the gradation of the pixel to the pixel corresponding to the scanning line to which the selection voltage is applied via the data line;
Comprising
The electro-optical device, wherein the first voltage is a voltage different from the second voltage, and is a voltage in a direction opposite to a change direction to the predetermined value with respect to the second voltage. An electronic apparatus comprising the electro-optical device according to claim 10.

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