JP2008040202A - Electrooptical device, driving circuit, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a voltage amplitude of a data line small while deterring the constitution of a capacity line driving circuit from becoming complicated. <P>SOLUTION: In the electrooptical device, a pixel 110 includes a pixel capacitor and a storage capacitor which has one end connected to a pixel electrode and the other end connected to a capacity line 1332. Capacity lines 132 are provided corresponding to respective 1 to 130 lines, and a capacity line driving circuit 150 has a pair of TFTs 155 and 157 for each of the 1 to 320 lines. Here, when a scanning line in a line (i) of interest is selected, a TFT 155 turns on, and when a scanning line which is one line below the line of interest is selected, a TFT 157 turns on. Source electrodes of the TFTs 155 and 157 are connected to a feeder 166 switched between voltages Vsl and Vsh each time the scanning line 112 is selected. Consequently, a capacity line 132 of the line of interest can be varied by a voltage ΔV after the scanning line of the line of interest is selected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for suppressing a voltage amplitude of a data line with a simple configuration in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. When this pixel capacitor needs to be AC driven, the voltage amplitude of the data signal is positive or negative. Therefore, in the data line driving circuit for supplying a data signal to the data line, a breakdown voltage corresponding to the voltage amplitude is required for the constituent elements. For this reason, a storage capacitor is provided in parallel with the pixel capacitor, and a capacitor line commonly connected to the storage capacitor in each row is driven in binary in synchronization with the selection of the scanning line, thereby suppressing the voltage amplitude of the data signal. A technique has been proposed (see Patent Document 1).
JP 2001-83943 A

By the way, in this technique, the circuit for driving the capacitance line is equivalent to the scanning line driving circuit (substantially shift register) for driving the scanning line, so that the circuit configuration for driving the capacitance line is complicated. End up.
SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device, a driving circuit, and an electronic apparatus that can suppress the voltage amplitude of a data line with a simple configuration. There is to do.

  In order to achieve the above object, a drive circuit for an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of capacitors provided corresponding to the plurality of scanning lines. Each of the scanning lines of the plurality of rows and the data lines of the plurality of columns is provided corresponding to an intersection, and each of the scanning lines is connected to a data line corresponding to itself and a scanning line corresponding to itself is provided. A pixel switching element that becomes conductive when selected, a pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to a common electrode, one end of the pixel capacitor, and the scanning line A drive circuit for an electro-optical device having a pixel including a storage capacitor interposed between correspondingly provided capacitor lines, wherein the scan line drive selects the scan lines in a predetermined order. Each time a circuit and scan line are selected, the lower side Select the power supply line when the one scanning line is selected for the power supply line that is switched by alternately switching the voltage and the higher voltage and the capacitance line that corresponds to the one scanning line. A capacitive line driving circuit that selects the power supply line and applies the voltage of the power supply line even when a scan line separated by a predetermined odd number of rows from the one scan line is selected, A data line driving circuit that supplies a data signal corresponding to a gray level of the pixel to the pixel corresponding to the scanning line through the data line; According to the present invention, from the time when the scanning line corresponding to the capacitor line is selected to the time when the scanning line separated by a predetermined odd number of rows is selected, the one capacitance line changes from the lower voltage to the higher voltage, or Conversely, the voltage changes. At this time, since the charge accumulated in the storage capacitor is redistributed, the holding voltage of the pixel capacitor becomes equal to or higher than the data signal voltage. For this reason, it is possible to suppress the voltage amplitude of the data line while suppressing the complexity of the configuration of the capacitor line driving circuit.

In the present invention, the capacitor line driving circuit may select the one capacitor line after the selection of the scan line separated from the one scan line by the predetermined odd number of rows in the downward or upward direction. A configuration may be adopted in which a high impedance state is maintained until the scanning line is selected again. The capacitance line driving circuit includes first and second transistors corresponding to the capacitance lines, and the gate electrode of the first transistor corresponding to one capacitance line is the one capacitance line. The second transistor has a gate electrode spaced downward or upward from the one scanning line by the predetermined odd number of rows. The source electrode may be connected to the power supply line, and the drain electrodes of the first and second transistors may be commonly connected to the one capacitor line.
In the present invention, the capacitance line driving circuit can switch the selection direction of the scanning line downward or upward, and the capacitance line driving circuit selects the one capacitance line in the selection direction of the scanning line. Is downward, the scanning line separated by the predetermined odd number of rows in the downward direction with respect to the one scanning line is completed, and then the predetermined odd number of rows is spaced upward with respect to the one scanning line. If the selected scanning line is in the high impedance state until the selected scanning line is selected again and the scanning line is selected in the upward direction, selection of the scanning line spaced apart by the predetermined odd number of rows upward with respect to the one scanning line is selected. After completion of the above, a high impedance state may be adopted until a scanning line separated by the predetermined odd number of rows in the downward direction with respect to the one scanning line is selected again. The capacitor line driving circuit includes first, second and third transistors corresponding to each of the capacitor lines, and the gate electrode of the first transistor corresponding to one capacitor line is the one. Connected to the scanning line corresponding to the capacitor line, the source electrode is connected to the power supply line, and the second transistor scans with the gate electrode spaced upward by the predetermined odd number of rows with respect to the one scanning line. The third transistor has a gate electrode connected to a scan line spaced downward from the one scan line by the predetermined odd number of rows, and the source electrode May be connected to the feeder line, and the drain electrodes of the first, second, and third transistors may be commonly connected to the one capacitor line.
In the present invention, the terms “below” and “above” are merely conveniences indicating directions orthogonal to the scanning line rows.
Further, the present invention can be conceptualized not only as a drive circuit for an electro-optical device, but also as an electro-optical device, and further as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, the electro-optical device 10 has a display area 100, and a control circuit 20, a scanning line driving circuit 140, a capacitor line driving circuit 150, and a data line driving circuit 190 are arranged around the display area 100. The arrangement is arranged. Among these, the display area 100 is an area where the pixels 110 are arranged. In the present embodiment, a total of 321 scanning lines 112 from the first line to the 321st line extend in the row (X) direction, The 240 data lines 114 are provided so as to extend in the column (Y) direction.
Then, the pixels 110 are arranged corresponding to the intersections of the scanning lines 112 in the 1st to 320th lines excluding the lowermost 321st line in FIG. 1 and the data lines 114 in the 1st to 240th columns. Therefore, in this embodiment, the pixels 110 are arranged in a matrix of 320 rows × 240 columns in the display region 100, but the present invention is not limited to this arrangement.
Here, since the scanning line 112 in the 321st row does not correspond to the pixel 110, it functions as a dummy scanning line. That is, the scanning line 112 in the 321st row does not contribute to voltage writing to the pixel 110 even if it is selected in the vertical scanning of the display area 100 (operation for selecting the scanning lines in order).
In addition, corresponding to the scanning lines 112 in the first to 320th rows, capacitance lines 132 are provided extending in the X direction, respectively. For this reason, in the present embodiment, the capacitor line 132 is provided corresponding to the 1st to 320th scanning lines 112 excluding the dummy 321st scanning line 112.

Here, a detailed configuration of the pixel 110 will be described. FIG. 2 is a diagram illustrating the configuration of the pixel 110, and corresponds to the intersection of the i row and the (i + 1) row adjacent thereto in the downward direction and the j column and the (j + 1) column adjacent thereto in the right direction. A configuration of a total of 4 pixels of 2 × 2 is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 110 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 110 are arranged. It is a symbol in the general case, and is an integer from 1 to 240. Here, i and (i + 1) are integers of 1 or more and 320 or less when generally indicating the row in which the pixels 110 are arranged, but are dummy when describing the row of the scanning line 112. Since it is necessary to include a certain 321st line, it is an integer between 1 and 321 inclusive.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, And a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in the i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 that is one end of the pixel capacitor 120.
The other end of the pixel capacitor 120 is a common electrode 108. The common electrode 108 is common to all the pixels 110 as shown in FIG. 1 and is supplied with a common signal Vcom. In the present embodiment, the common signal Vcom is constant at the voltage LCcom in terms of time as will be described later.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the i and (i + 1) th scanning lines 112, respectively, and Ci and C (i + 1) indicate i and (i + 1), respectively. ) The voltage of the capacitor line 132 in the row is shown.

  In the display region 100, a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, are bonded to each other with a certain gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in the gap. Therefore, the pixel capacitor 120 has a structure in which the liquid crystal 105 which is a kind of dielectric is sandwiched between the pixel electrode 118 and the common electrode 108, and holds a differential voltage between the pixel electrode 118 and the common electrode 108. In this configuration, in the pixel capacitor 120, the amount of transmitted light changes according to the effective value of the holding voltage. In the present embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value increases. It is assumed that the normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

  The storage capacitor 130 in the pixel 110 in the i row and j column has one end connected to the pixel electrode 118 (the drain electrode of the TFT 116) and the other end connected to the i-th capacitor line 132. Here, the capacitance values in the pixel capacitor 120 and the storage capacitor 130 are Cpix and Cs, respectively.

Returning to FIG. 1 again, the control circuit 20 outputs various control signals to control each part in the electro-optical device 10 and supplies the capacitance signal Vc to the power supply line 166.
A common signal Vcom is supplied to the common electrode 108.
As described above, peripheral circuits such as the scanning line driving circuit 140, the capacitor line driving circuit 150, and the data line driving circuit 190 are provided around the display region 100.

Among these, the scanning line driving circuit 140 sends the scanning signals Y1, Y2, Y3,..., Y320, Y321 to 1, 2, 3,. This is supplied to the scanning line 112 in the row. Specifically, the scanning line driving circuit 140 selects the scanning lines 112 in the order of the first, second, third,..., 320, and 321st rows from the top in FIG. Is set to the H level corresponding to the selection voltage Vdd, and the scanning signals to the other scanning lines are set to the L level corresponding to the non-selection voltage (ground potential Gnd).
As shown in FIG. 4, the scanning line driving circuit 140 sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly.
The scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 are output in this order. Also, in this embodiment, during the period of one frame, as shown in FIG. In addition to the effective scanning period Fa from when the scanning signal Y320 becomes L level, other blanking periods are included. A period during which one row of scanning lines 112 is selected is a horizontal scanning period (H).

  In the present embodiment, the capacitor line driving circuit 150 includes a set of n-channel TFTs 155 and 157 provided corresponding to the capacitor lines 132 in the first to 320th rows. Here, the TFTs 155 and 157 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 155 (first transistor) is connected to the i-th scanning line 112, and the source electrode thereof is a power supply line. On the other hand, the gate electrode of the TFT 157 (second transistor) is connected to the scanning line 112 in the (i + 1) th row, and its source electrode is connected to the power supply line 166. The drain electrodes of the TFTs 155 and 157 are commonly connected to the i-th capacitor line 132.

The data line driving circuit 190 is a voltage corresponding to the gradation of the pixel 110 located on the scanning line 112 selected by the scanning line driving circuit 140 and having a voltage corresponding to the polarity specified by the polarity instruction signal Pol. The operation of converting into a signal and supplying it to the data line 114 is performed for each of the 1 to 240 columns positioned on the selected scanning line 112.
Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation value (brightness) of the corresponding pixel 110. Display data Da for designating the data is stored. The display data Da stored in each storage area is rewritten by the display circuit Da after the change together with the address by the control circuit 20 when the display contents are changed.
The data line driving circuit 190 reads out the display data Da of the pixel 110 located on the selected scanning line 112 from the storage area, and is designated by a voltage corresponding to the gradation designated by the read display data. It is converted into a data signal having a voltage corresponding to the polarity and supplied to the data line 114.

Here, the polarity instruction signal Pol is a signal for designating the positive polarity writing when it is at the H level, and the negative polarity writing is designated when it is at the L level. As shown in FIG. Inverted every H). For this reason, in the present embodiment, a scanning line (line) inversion method is employed in which the writing polarity to the pixel is inverted for each scanning line. Further, the polarity instruction signal Pol has an inverted relationship when viewed in a period in which the same scanning signal is at the H level (the same scanning line is selected) in adjacent frames. The reason for polarity inversion is to prevent deterioration of the liquid crystal due to application of a DC component.
The capacitance signal Vc becomes the voltage Vsh when the polarity instruction signal Pol is at the L level, and becomes the voltage Vsl when the polarity instruction signal Pol is at the H level.
As for the writing polarity in this embodiment, when the voltage corresponding to the gradation is held in the pixel capacitor 120, the potential of the pixel electrode 118 is higher than the voltage LCcom of the common electrode 108. It is called positive polarity, and the case of the lower side is called negative polarity. On the other hand, with respect to the voltage, unless otherwise specified, the ground potential Gnd of the power supply is used as a reference of zero voltage.

The control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at the timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 outputs the scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 in this order by sequentially shifting the start pulse Dy according to the clock signal Cly. Therefore, the start timing of the period during which the scanning line is selected is the timing at which the logic level of the clock signal Cly transitions. Therefore, the data line driving circuit 190 selects each row according to, for example, which row scanning line is selected by continuously counting the latch pulse Lp over a period of one frame and the supply timing of the latch pulse Lp. You can know the start timing.

  In this embodiment, in addition to the scanning lines 112, the data lines 114, the TFTs 116, the pixel electrodes 118, and the storage capacitors 130 in the display region 100, the element substrates include TFTs 155 and 157 in the capacitor line driving circuit 150, and power supply lines. 166 and the like are also formed.

FIG. 3 is a plan view showing a configuration in the vicinity of the boundary between the capacitive line driving circuit 150 and the display region 100 in such an element substrate.
As shown in this figure, in this embodiment, the TFTs 155 and 157 are of an amorphous silicon type, and are of a bottom gate type in which the gate electrode is located below the semiconductor layer. Specifically, the scanning line 112 and the capacitor line 132 are formed by patterning the gate electrode layer serving as the first conductive layer, a gate insulating film (not shown) is formed thereon, and the semiconductor layers of the TFTs 116, 155, and 157 are further formed. Is formed in an island shape. On the semiconductor layer, a pixel electrode 118 having a rectangular shape and transparency is formed by patterning an ITO (indium tin oxide) layer serving as a second conductive layer via a protective layer. The source / drain electrodes of the TFTs 116, 155, 157, the data line 114, the power supply line 166, and the like are formed by patterning a metal layer such as aluminum as a conductive layer.

Here, in the capacitor line driving circuit 150, the gate electrode of the TFT 155 corresponding to the i-th row is a portion branched in a T shape in the Y (down) direction from the i-th scanning line 112. The gate electrode of the TFT 157 corresponding to is a portion branched in a T shape in the Y (up) direction from the scanning line 112 in the (i + 1) th row. Further, the drain electrodes of the TFTs 155 and 157 corresponding to the i-th row are obtained by patterning the third conductive layer, and the i-th row is connected via a contact hole (marked with x in the drawing) penetrating the gate insulating film. The capacitor line 132 is electrically connected.
On the other hand, in the display region 100, the storage capacitor 130 has a configuration in which the gate insulating film is sandwiched as a dielectric by the portion of the capacitor line 132 formed so as to be wide in the lower layer of the pixel electrode 118 and the pixel electrode 118. is there. For this reason, the other end of the storage capacitor 130 becomes the capacitor line 132 itself.
Note that the common electrode 108 facing the pixel electrode 118 is formed on the counter substrate, and thus does not appear in FIG. 3 showing a plan view of the element substrate.

The configuration shown in FIG. 3 is merely an example, and the TFT type may be another structure, for example, a top gate type in terms of arrangement of gate electrodes, or a polysilicon type in terms of process. Further, instead of building the element of the capacitor line driving circuit 150 in the display region 100, an IC chip may be mounted on the element substrate side.
When the IC chip is mounted on the element substrate side, the scanning line driving circuit 140 and the capacitor line driving circuit 150 may be integrated as a semiconductor chip together with the data line driving circuit 190, or may be separate chips. The control circuit 20 is FPC (flexible printed
circuit) may be connected via a substrate or the like, or may be configured to be mounted on an element substrate as a semiconductor chip.
When the present embodiment is a reflective type instead of a transmissive type, the reflective conductive layer may be patterned for the pixel electrode 118, or a separate reflective metal layer may be provided. Furthermore, a so-called transflective type that combines both a transmissive type and a reflective type may be used.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
As described above, in this embodiment, the line inversion method is used for the pixel writing polarity. For this reason, as shown in FIG. 4, the control circuit 20 performs a horizontal scanning period in which the scanning signal Y1 is at the H level in a period of a certain frame (denoted as “n frame”). In the horizontal scanning period in which the scanning signals Y2, Y3,..., Y320, Y321 are at the H level, the polarity is inverted every horizontal scanning period as the L, H,. Further, in the horizontal scanning period in which the scanning signal Y1 is at the H level in the next (n + 1) frame period, the scanning signal Y1, the horizontal scanning period in which the scanning signals Y2, Y3,..., Y320, Y321 are at the H level. AC driving is performed at H, L,..., H, L levels.
Further, the control circuit 20 defines the capacitance signal Vc in accordance with the logic level of the polarity instruction signal Pol. That is, the lower voltage Vsl is set in the horizontal scanning period in which the polarity instruction signal Pol is at the H level, and the higher voltage Vsh is set in the horizontal scanning period in which the polarity instruction signal Pol is in the L level. Here, the lower voltage Vsl and the higher voltage Vsh are the voltage LCcom applied to the common electrode 108.
The voltage difference is ΔV.
Therefore, the capacitance signal Vc rises by a voltage ΔV from the horizontal scanning period in which the polarity instruction signal Pol becomes H level and the positive writing is designated to the next horizontal scanning period, while the polarity instruction signal Pol is L The voltage decreases by a voltage ΔV from the horizontal scanning period in which negative writing is designated at the level to the next horizontal scanning period.

In the n frame, the scanning signal drive circuit 140 first sets the scanning signal Y1 to the H level, and the polarity instruction signal Pol becomes the H level to specify the positive writing. Here, when the latch pulse Lp is output at the timing when the scanning signal Y1 becomes the H level, the data line driving circuit 190 displays the pixels in the first row and the columns 1, 2, 3,. The data Da is read and converted into data signals X1, X2, X3,..., X240 corresponding to the read display data Da and voltages corresponding to positive polarity (the meaning of which will be described later). , 240 are supplied to the data lines 114 in 240 columns.
Accordingly, for example, a voltage corresponding to the display data Da of the pixel 110 in the first row and j column is applied as the data signal Xj to the data line 114 in the jth column.
Now, when the scanning signal Y1 becomes the H level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned on, so that the data signals X1, X2, X3,. Is done. For this reason, in the pixel capacitor 120 in the 1st row and 1st column to the 1st row and 240th column, the voltage corresponding to the gradation is written to the pixel electrode 118 which is one end, so that the difference voltage between the voltage and the voltage LCcom is held. It will be.

On the other hand, when the scanning signal Y1 is at the H level, in the capacitor line driving circuit 150, the TFT 155 corresponding to the capacitor line 132 in the first row is turned on. (TFT 157 is off). For this reason, since the capacitor line 132 in the first row is connected to the power supply line 166, the capacitor signal Vc
Voltage Vsl. For this reason, in the storage capacitor 130 in the 1st row and the 1st column to the 1st row and the 240th column, a voltage corresponding to the gradation is written to one end, so that the differential voltage between the positive voltage and the voltage Vsl is held. .

Next, the scanning signal Y1 becomes L level, the scanning signal Y2 becomes H level, the polarity instruction signal Pol is inverted to L level, and negative polarity writing is designated.
When the scanning signal Y1 becomes L level, the TFTs 116 in the pixels in the first row and first column to the first row and 240th column are turned off. When the latch pulse Lp is output at the timing when the scanning signal Y2 becomes H level, the data line driving circuit 190 is in the second row and is 1, 2, 3,.
The display data Da of the pixels in the column is read out and converted into data signals X1, X2, X3,..., X240 corresponding to the read display data Da and corresponding to the negative polarity. , 240 are supplied to the data lines 114 of 240 columns.
Thus, for example, a voltage corresponding to the display data Da of the pixel 110 in the second row and j column is applied to the jth data line 114 as the data signal Xj. When the scanning signal Y2 becomes H level, the TFTs 116 in the pixels in the 2nd row and the 1st column to the 2nd row and the 240th column are turned on. Therefore, in each of these pixel capacitors 120, a difference voltage between the voltage corresponding to the gradation and the voltage LCcom is held. Will be.

On the other hand, when the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level, in the capacitor line driving circuit 150, the TFT 155 corresponding to the capacitor line 132 in the first row is turned off and the TFT 157 is turned on. For this reason, the capacitance line 132 in the second row becomes the voltage Vsh of the capacitance signal Vc, and increases by the voltage ΔV. As a result, the charge is redistributed as described later. The pixel capacitance 120 varies from the hold voltage when the scanning signal Y1 is at the H level.
Further, since the TFT 155 corresponding to the capacitor line 132 in the second row is turned on (TFT 157 is turned off), the capacitor line 132 in the second row becomes the voltage Vsh. For this reason, in the storage capacitor 130 in the 2nd row and the 1st column to the 2nd row and the 240th column, a voltage corresponding to the gradation is written to one end, so that a difference voltage between the voltage and the voltage Vsh is held.

Subsequently, the scanning signal Y2 becomes L level, the scanning signal Y3 becomes H level, the polarity instruction signal Pol is inverted to H level, and the positive writing is designated. Therefore, similarly to the horizontal scanning period in which the scanning signal Y1 is at the H level, in the pixel capacitor 120 of 3 rows 1 column to 3 rows 240 columns, the pixel electrode 118 which is one end corresponds to each gradation and has positive polarity. Therefore, the difference voltage between the voltage and the voltage LCcom is held.
On the other hand, when the scanning signal Y2 becomes L level, the capacitor line driving circuit 150 also turns off the TFT 157 corresponding to the capacitor line 132 in the first row, so that the capacitor line 132 in the first row is electrically connected to any portion. It becomes a high impedance state that is not connected. Here, a capacitance is parasitic on the capacitance line 132. For this reason, the capacitor line 132 in the first row is held at the voltage Vsh that is in the state immediately before the TFT 157 in the first row is turned off, so that the voltage that has fluctuated due to charge redistribution is maintained.
In addition, since the TFT 155 corresponding to the capacitor line 132 in the second row is turned off and the TFT 157 is turned on, the capacitor line 132 in the second row becomes the voltage Vsl and decreases by the voltage ΔV. As a result of the reallocation, the pixel capacity 120 in the 2nd row and the 1st column to the 2nd row and the 240th column varies.
Since the TFT 155 corresponding to the capacitor line 132 in the third row is turned on (TFT 157 is turned off), the capacitor line 132 in the third row becomes the voltage Vsl. For this reason, in the storage capacitor 130 of 3 rows and 1 column to 3 rows and 240 columns, a voltage corresponding to the gradation is written to one end, so that a difference voltage between the voltage and the voltage Vsl is held.

Thereafter, in the period of n frames, the same operation is repeated until the scanning signal Y321 becomes H level.
That is, in the odd-numbered (1, 3, 5,..., 319) rows, the pixel capacitance 120 varies from the voltage written by the data signal as the voltage ΔV of the capacitance line 132 increases, while the even-numbered (2, 4). , 6,..., 320), the pixel capacitance 120 varies due to a decrease in the voltage ΔV of the capacitance line 132, rather than the voltage written by the data signal.
Therefore, voltage variation of the pixel capacitance due to increase (decrease) in the voltage ΔV of the capacitance line 132 will be described next.

FIG. 5 is a diagram for explaining the voltage variation of the pixel capacitor 120 in the i row and j column when the capacitance line 132 in the i row rises by the voltage ΔV. FIG. 6 is a diagram showing the relationship between the scanning signals Yi and Y (i + 1) and the voltage Pix (i, j) of the pixel electrode 118 in i row and j column.
First, when the polarity instruction signal Pol is at the H level and the positive polarity writing is designated, when the scanning signal Yi becomes the H level, as shown in FIG. Since it is turned on, the voltage of the data signal Xj is applied to one end of the pixel capacitor 120 (pixel electrode 118) and one end of the storage capacitor 130, respectively. On the other hand, if the polarity instruction signal Pol is at the H level, the capacitance signal Vc is the voltage Vsl. In the period when the scanning signal Yi is at the H level, the i-th TFT
Since 155 is turned on, the voltage Ci of the capacitor line 132 in the i-th row becomes the voltage Vsl. The common electrode 108 is constant at the voltage LCcom.
Therefore, if the voltage of the data signal Xj at this time is Vj, the pixel capacitor 120 in the i row and j column is charged with the voltage (Vj−LCcom), and the storage capacitor 130 is charged with the voltage (Vj−Vsl). The

Next, when the scanning signal Yi becomes the L level and the scanning signal Y (i + 1) becomes the H level ((i + 1) rows are not shown in FIG. 5B), the TFTs 116 in the i rows and j columns are turned on. In addition to turning off, the voltage Ci of the capacitance line 132 in the i-th row increases from the voltage Vsl to the voltage Vsh by the voltage ΔV.
For this reason, in the serial connection of the pixel capacitor 120 and the storage capacitor 130, the other end (common electrode 108) of the pixel capacitor 120 is kept constant at the voltage LCcom, and the other end of the storage capacitor 130 is increased by the voltage ΔV. Therefore, the voltage of the pixel electrode 118 also increases.
Here, the voltage of the pixel electrode 118 which is the series connection point is
Vj + {Cs / (Cs + Cpix)} · ΔV
Therefore, the capacitance ratio {Cs / (Cs + Cpix) of the pixel capacitor 120 and the storage capacitor 130 is more than the voltage change ΔV of the capacitor line 132 in the i-th row than the voltage Vj of the data signal when the scanning signal Yi is at the H level. )}. That is, the i-th capacitance line 1
When the voltage Ci of 32 is increased by ΔV, the voltage of the pixel electrode 118 is {Cs / (Cs + Cpix)} · ΔV (= Δ) rather than the voltage Vj of the data signal when the scanning signal Yi is at the H level.
Vpix). Note that the parasitic capacitance of each part is ignored.

When the polarity instruction signal Pol is at the H level and the positive polarity writing is designated, the voltage Vj of the data signal Xj is applied to the pixel electrode 118 and then the pixel electrode is set to the voltage ΔVpix.
Is set so that the voltage when the voltage increases only higher than the voltage LCcom of the common electrode 108, and the difference voltage between them becomes a voltage value V (+) corresponding to the gradation of i rows and j columns (FIG. 6).
Specifically, in the present embodiment, since the normally white mode is set, as shown in FIG. 7A, the pixel in i row and j column should have any gradation from white w to black b. In the case of positive polarity writing, the voltage of the pixel electrode 118 when the voltage ΔVpix is increased is in the range A from the voltage Vw (+) corresponding to white w to the voltage Vb (+) corresponding to black b. As the gray level becomes lower (darker), the voltage may be higher than the voltage LCcom. Therefore, the data signal Xj is set to a voltage lower by ΔVpix than the voltage V (+) corresponding to this gray level. Voltage Vj is set.

Here, the increase in the voltage ΔV in the i-th capacitance line 132 when the positive polarity writing is designated has been described, but in the (i + 1) th row, the negative polarity writing is designated and the (i + 1) The capacity line 132 in the row drops from the voltage Vsh to the voltage Vsl by the voltage ΔV. The operation at this time is only the reverse direction of the voltage change, and the other operations are the same as when the voltage ΔV is increased.
Therefore, in the (i + 1) th row where negative polarity writing is designated, the scanning signal Y (i + 1) is H
The data signal Vj at the level may be set as follows. That is, as shown in FIG. 7B, the voltage of the pixel electrode 118 when the voltage ΔVpix is lowered is from the voltage Vw (−) corresponding to white w to the voltage Vb (−) corresponding to black b. In the range C, as the gradation becomes lower (darker), the voltage V (−) should be lower than the voltage LCcom (see also FIG. 6). The voltage Vj of the data signal Xj is set so that the voltage becomes higher by ΔVpix.

At this time, if the voltage range is set to match between the positive polarity writing and the negative polarity writing, the amplitude range of the data signal can be minimized.
That is, the center of the amplitude B of the data signal corresponding to the positive polarity writing in FIG. 6A and the center of the amplitude D of the data signal corresponding to the negative polarity writing in FIG. When the voltage ΔVpix increases, the voltage shifts to a range A from the voltage Vw (+) to the voltage Vb (+), and when the voltage ΔVpix decreases, the voltage Vw (−) changes to the voltage. The voltage ΔV (= Vsh−LCcom = LCcom−Vsl) may be set so as to shift to the range C up to Vb (−).
However, in the amplitude B of the data signal corresponding to the positive writing in FIG. 6A, the white w side is low and the black b side is high, but the data signal corresponding to the negative writing in FIG. 6B. In the amplitude D, the white w side is high and the black b side is low, and the gradation relationship is reversed.

In the present embodiment, the voltage range B of the data signal when the positive polarity writing is designated matches the voltage range D of the data signal when the negative polarity writing is designated. For this reason, according to the present embodiment, the voltage range J is about half that of the voltage range J in the case of directly applying a voltage corresponding to the gradation, so that the breakdown voltage of the elements constituting the data line driving circuit 190 is narrow. In addition, since the voltage amplitude in the data line 114 having parasitic capacitance is reduced, power is not wasted due to the parasitic capacitance.
That is, assuming that the common electrode 108 is maintained at the voltage LCcom and the voltage of the capacitor line 132 is constant, when the pixel capacitor 120 is AC driven, if positive writing is specified, If writing to the pixel electrode 118 is performed with a voltage in the range A from the positive voltage Vw (+) to the voltage Vb (+) according to the gradation, and negative writing is specified, the pixel electrode 118 is The voltage must be written in the range C from the positive voltage Vw (−) to the voltage Vb (−) according to the key. Therefore, when the voltage of the common electrode 108 is constant and the voltage of the capacitor line 132 is constant, the voltage of the data signal extends in the range J in the figure, so that the breakdown voltage of the elements constituting the data line driving circuit 190 is also in the range J. In addition, if the voltage changes in the range J on the data line 114 having parasitic capacitance, power is wasted due to the parasitic capacitance. The inconvenience is solved.
Note that even if the voltage range of the data signal when the positive polarity writing is designated and the voltage range of the data signal when the negative polarity writing is designated do not coincide with each other, the data changes due to the voltage change of the capacitor line 132. The voltage amplitude of the signal can be suppressed.

  In this embodiment, since the pixel writing polarity is the line inversion method, display with a high contrast ratio is possible as compared with the surface inversion method. At this time, the power supply line 166 that defines the voltage of the capacitor line 132 requires two values of the voltages Vsl and Vsh as the voltage of the capacitor line 132 in accordance with the polarity instruction signal Pol for each horizontal scanning period. Since it is configured to switch, only one is required. Therefore, in the present embodiment, the wiring can be reduced correspondingly, so that the configuration can be simplified.

<Second Embodiment>
In the first embodiment described above, the scanning lines 112 are selected in the order of the first, second, third, fourth,..., 320, and 321st rows from the top in FIG. In this case, the voltage of each capacitor line 132 in the first to 320th rows is switched in accordance with this.
By the way, in recent years, a type in which a display panel can be rotated 180 degrees, such as a viewfinder such as a video camera or a digital still camera, has appeared. Here, when the rotation angle of the display panel is 0 degree and when it is 180 degrees, the vertical scanning direction is reversed when viewed from the fixed point of the panel. The voltage cannot be switched correctly.
Therefore, a second embodiment will be described in which the voltage of the capacitor line 132 can be switched correctly even when the vertical scanning direction is switched between forward and reverse.

FIG. 8 is a diagram illustrating a configuration of the electro-optical device according to the second embodiment.
The difference between the second embodiment shown in FIG. 1 and the first embodiment shown in FIG. 1 is that the first scanning line 112 is mainly on the first scanning line. Second, in the capacitor line driving circuit 150, the TFT 159 is provided corresponding to the first to 320th rows, and thirdly, the scanning line driving circuit 140 moves in the vertical scanning direction. The point corresponds to either the case of the downward direction or the case of the upward direction.

First, the first point will be described. Since the pixel 110 is not provided in correspondence with the scanning line 112 of the 0th row, it functions as a dummy scanning line, like the scanning line 112 of the 321st row. It will be.
Next, the second point will be described by taking the i-th TFT 159 (third transistor) as an example. The gate electrode of the TFT 159 is one row above the i-th row (i−1) row. Connected to the scanning line 112 of the eye, its source electrode is connected to the power supply line 166, and its drain electrode is connected to the i-th capacitor line 132 together with the drain electrodes of the TFTs 155 and 157.
Next, the third point will be described. When the vertical scanning direction is designated as the downward direction by the transfer direction instruction signal (not shown) from the control circuit 20, the scanning line driving circuit 140 determines the scanning line 112 as follows. When selecting from the 0th, 1st, 2nd, 3rd, 4th,..., 320, 321st rows from the top and the direct scanning direction is designated as the upward direction, the scanning lines 112 are counted 321 from the top. , 320,..., 4, 3, 2, and 1st line.
In order to avoid confusion, the rows specifying the scanning lines 112 are counted from the top regardless of the vertical scanning direction.
Here, if the vertical scanning direction is the downward direction, the scanning signal becomes H level in the order of Y0, Y1, Y2, Y3, Y4,..., Y320, Y321 as shown in FIG. If the direction is upward, as shown in parentheses in the figure, it becomes H level in the order of Y321, Y320,..., Y4, Y3, Y2, Y1, Y0.

Since the scanning line 112 in the 0th row is a dummy, the period during which the scanning signal Y0 is at the H level is included in the horizontal blanking period regardless of the vertical scanning direction.
The polarity instruction signal Pol is the same as that of the first embodiment in that the polarity is inverted every horizontal scanning period (H). If the vertical scanning direction is downward, the polarity instruction signal Pol is H level in the period when the scanning signal Y1 is H level in the n frame, and is the period in which the scanning signal Y1 is H level in the (n + 1) frame. On the other hand, if the vertical scanning direction is upward, the L level becomes the H level in the period in which the scanning signal Y320 becomes the H level in the n frame, and the L level in the period in which the scanning signal Y320 becomes the H level in the (n + 1) frame. It becomes.

In the second embodiment, when the vertical scanning direction is the downward direction and the positive polarity writing is designated for the i-th row, the scanning signals Y (i−1), Yi, Y (i + 1) are sequentially supplied. In the period of H level, the polarity instruction signal Pol becomes L, H, L level.
When the scanning signal Y (i−1) becomes the H level, the TFT 159 corresponding to the i-th row is turned on, so that the voltage Ci of the capacitance line 132 in the i-th row becomes the voltage Vsh as shown in FIG. . Next, when the scanning signal Yi becomes H level, the TFT 159 corresponding to the i-th row is turned off and the TFT 155 is turned on, so that the voltage Ci becomes the voltage Vsl. When the scanning signal Y (i + 1) becomes the H level, the TFT 155 corresponding to the i-th row is turned off and the TFT 157 is turned on, so that the voltage Ci becomes the voltage Vsh. When the scanning signal Y (i + 1) becomes L level, the i-th capacitor line 132 is in a high impedance state until the scanning signal Y (i-1) becomes H level again in the next frame. As indicated by a broken line in the figure, the voltage Vsh is maintained by the parasitic capacitance.
When positive polarity writing is designated for the i-th row when the vertical scanning direction is the downward direction, as in the first embodiment, the i-th capacitance line 132 scans the next (i + 1) -th row. When line 112 is selected, it rises by a voltage ΔV.
On the other hand, when the negative polarity writing is designated for the i-th row when the vertical scanning direction is the downward direction, the scanning signals Y (i−1), Yi, and Y (i + 1) are sequentially at the H level. Since the polarity instruction signal Pol becomes H, L, and H levels, the capacitance line 132 in the i-th row is lowered by the voltage ΔV when the next (i + 1) -th scanning line 112 is selected.

Further, when the vertical scanning direction is the upward direction and the positive polarity writing is designated for the i-th row, the scanning signals Y (i + 1), Yi, and Y (i-1) are sequentially in the H level. , The polarity instruction signal Pol becomes L, H, L level.
When the scanning signal Y (i + 1) becomes H level, the TFT 157 corresponding to the i-th row is turned on, so that the voltage Ci of the capacitance line 132 in the i-th row becomes the voltage Vsh as shown in FIG. Next, when the scanning signal Yi becomes H level, the TFT 157 corresponding to the i-th row is turned off and the TFT 155 is turned on, so that the voltage Ci becomes the voltage Vsl. When the scanning signal Y (i-1) becomes H level, the TFT 155 corresponding to the i-th row is turned off and the TFT 159 is turned on, so that the voltage Ci becomes the voltage Vsh.
Therefore, when positive polarity writing is designated for the i-th row when the vertical scanning direction is the upward direction, the i-th capacitance line 132 is the next (i−1) -th scanning line 112. Is increased by a voltage ΔV. On the other hand, when the negative scanning is designated for the i-th row when the vertical scanning direction is the upward direction, the scanning signals Y (i + 1), Yi, Y (i-1) are sequentially in the H level. Since the polarity instruction signal Pol becomes H, L, and H levels, the capacitance line 132 in the i-th row is only the voltage ΔV when the next (i−1) -th scanning line 112 is selected. descend.
Therefore, in the second embodiment, the voltage amplitude of the data signal can be suppressed by the voltage change of the capacitor line 132 as in the first embodiment.

In the second embodiment, if the vertical scanning direction is the downward direction, the capacitance line 132 in the i-th row has the vertical scanning direction upward when the scanning signal Y (i−1) becomes H level. If there is, when the scanning signal Y (i + 1) becomes the H level, the voltage Vsl or Vsh in the high impedance state respectively changes from the voltage Vsl or Vsh by the voltage ΔV. Due to the change in the voltage ΔV, the pixel capacitor 120 in the i-th row is shifted from the voltage corresponding to the gradation.
However, since this voltage shift cancels out every frame period, no DC component is applied to the pixel capacitor 120. Further, the voltage is shifted from the voltage corresponding to the gradation, but this shift period is only the horizontal scanning period (H). Since this period (H) is 1/321 or less of the period of one frame which is a unit period of the voltage effective value (less than the reciprocal of the total number of scanning lines), the influence on the voltage effective value of the pixel capacitor 120 can be almost ignored. It can be said that it is small.

As described above, according to the second embodiment, in the capacitor line driving circuit 150, only the TFT 159 is provided corresponding to each row, so that the scanning line driving circuit 140 sets the vertical scanning direction to the downward direction or the upward direction. It is possible to obtain the same effect as in the first embodiment.
10 and 11, the voltage state when the i-th capacitance line 132 is in the high impedance state is indicated by a broken line.

In the capacitor line driving circuit 150 described above, in the first embodiment (FIG. 1), the gate electrode of the TFT 157 corresponding to the i-th row is spaced downward by one row with respect to the i-th row (i + 1). In the second embodiment (FIG. 8), the gate electrode of the TFT 159 corresponding to the i-th row is spaced upward by one row in the second embodiment (FIG. 8). Connected to line 112. That is, when the (i−1) -th and (i + 1) -th scanning lines one row above the i-th row are selected, the i-th capacitance line 132 is connected to the feeder line. It was set as the structure connected to 166.
However, in the first and second embodiments, the capacitance signal Vc is switched to the voltages Vsl and Vsh every horizontal scanning period (H), so that the gate electrode of the TFT 157 in the i-th row is an odd-numbered row in the downward direction. For example, it is configured to connect to the (i + 3) -th scanning line 112 separated by three rows, and the gate electrode of the i-th TFT 159 is an odd number upward, for example, (i-3) rows separated by three rows. By connecting to the scanning line 112 of the eye, the capacitance line 132 of the i-th row can be raised or lowered by the voltage ΔV in accordance with the writing polarity after writing the data signal in its own i-th row. it can.
However, when the number of spaced rows increases, not only the wiring of the gate electrode becomes complicated, but, for example, if the number of spaced rows is “3”, the capacity of the 318th to 320th rows when the vertical scanning direction is downward. In order to drive the TFT 157 corresponding to the line 132, the dummy scanning lines in the 321st to 323rd rows, and the TFT 159 corresponding to the capacitor line 132 in the first, second and third rows when the vertical scanning direction is the upward direction. To drive the dummy scanning lines 112 in the “−2”, “−1”, and “0” rows, respectively.
On the other hand, if the number of spaced rows is “1” as in the first and second embodiments, the blanking period is eliminated, and in the first embodiment, the gate electrode of the TFT 157 corresponding to the 320th row is 1 If it is connected to the scanning line 112 of the row, and in the second embodiment, the gate electrode of the TFT 159 corresponding to the first row is connected to the scanning line 112 of the 320th row and circulated, it is a dummy. It is not necessary to provide the scanning line.
Furthermore, the voltage Vcom of the common electrode 108 is set to a low level when the positive polarity writing is designated,
A configuration may be adopted in which high-order switching is performed when negative polarity writing is designated.

Further, in the embodiment, the liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108 as the pixel capacitor 120 and the electric field direction applied to the liquid crystal is set to the direction perpendicular to the substrate surface. However, the pixel electrode, the insulating layer, and the common It is good also as a structure which laminated | stacked an electrode and made the electric field direction concerning a liquid crystal into the substrate surface horizontal direction.
In the embodiment, the pixel capacitor 120 is set to the normally white mode. However, the pixel capacitor 120 may be set to a normally black mode that is dark when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed, and another color (for example, cyan (C)) may be used. In addition, one dot may be configured with these four color pixels to improve the color reproducibility.

In the above description, the reference of the writing polarity is the voltage LCcom applied to the common electrode 108. This is a case where the TFT 116 in the pixel 110 functions as an ideal switch. -Due to the parasitic capacitance between the drain electrodes, a phenomenon in which the potential of the drain (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, penetration, field through, etc.) occurs. In order to prevent the deterioration of the liquid crystal, the pixel capacitor 120 must be AC driven. However, if the AC driving is performed with the applied voltage LCcom applied to the common electrode 108 as a reference for the writing polarity, the negative polarity writing is performed for pushdown. The effective voltage value of the pixel capacitor 120 due to is slightly larger than the effective value due to positive polarity writing (when the TFT 116 is n-channel). For this reason, in actuality, the reference voltage of the write polarity and the voltage LCcom of the common electrode 108 are separated, and more specifically, the reference voltage of the write polarity is set to the voltage LCcom so that the influence of pushdown is offset. Alternatively, the offset may be set to a higher position.
Furthermore, since the storage capacitor 130 is insulated in terms of direct current, it is sufficient that the capacitance signal Vc fed to the feeder line 166 has the above relationship. For example, what is the potential difference from the voltage LCcom? It doesn't matter.
In FIG. 4, after the scanning signal Y321 becomes H level (the scanning line of the 321st row is selected) and before the scanning signal Y1 becomes H level (the scanning line of the first row is selected). The voltage of the capacitor line is changed during the period up to this time, but this is not always necessary and may be a constant voltage.

<Electronic equipment>
Next, two examples of an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described.
FIG. 12 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to the first embodiment. As shown in this figure, a cellular phone 1200 includes the electro-optical device 10 described above together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206.

FIG. 13 is a perspective view showing a configuration of a video camera in which the electro-optical device 10 according to the second embodiment is applied to a viewfinder.
As shown in this figure, the main body 2210 of the video camera 2200 is provided with an optical system 2212, a hand grip 2214, and the like in addition to the electro-optical device 10 used as a viewfinder. Here, the display area 100 of the electro-optical device 10 is attached to a hinge 2216 so as to be rotatable about a shaft 2224, and the hinge 2216 opens and closes with respect to the main body 2210 about the shaft 2222. It has a structure to do.

  For this reason, the electro-optical device 10 needs to be in a relationship in which the display image is inverted in the vertical and horizontal directions between the mode illustrated in the figure and the mode used by the photographer as the viewfinder. Here, in the present embodiment, as described above, if the vertical scanning direction by the scanning line driving circuit 140 is reversed and the horizontal scanning direction by the data line driving circuit 190 is reversed, the display image can be vertically and horizontally shifted. Can be reversed.

  In addition to the mobile phone shown in FIG. 12 and the video camera shown in FIG. 13, the electronic apparatus to which the electro-optical device 10 is applied includes a digital still camera, a laptop computer, a liquid crystal television, a video recorder, a car recorder, and the like. Examples of such devices include navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, touch panels, and the like. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a plan view illustrating a configuration of a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the positive polarity writing of the same electro-optical apparatus. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. It is a figure which shows the relationship between the data signal and holding voltage of the same electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 6 is a diagram for explaining an operation of the electro-optical device. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. It is a figure which shows the mobile telephone using the electro-optical apparatus which concerns on 1st Embodiment. It is a figure which shows the video camera using the electro-optical apparatus which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 120 ... Pixel capacity, 130 ... Storage capacity, 132 ... Capacitance line, 140 ... Scanning line drive circuit, 150 ... Capacitance line drive circuit, 155, 157, 159 ... TFT, 166 ... Power supply line, 1200 ... Mobile phone, 2200 ... Video camera

Claims (7)

Multiple rows of scanning lines;
Multiple columns of data lines;
A plurality of capacitance lines provided corresponding to the plurality of rows of scanning lines;
Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines,
Each is
A pixel switching element having one end connected to a data line corresponding to the pixel and a conductive state when a scanning line corresponding to the data line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to a common electrode;
A storage capacitor interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line;
A pixel containing
A drive circuit for an electro-optical device having:
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
Each time a scanning line is selected, a low-side voltage and a high-side voltage are alternately switched between and fed to the power supply line,
For the capacitance line provided corresponding to one scanning line, a feeding line is selected when the one scanning line is selected, and scanning lines separated by a predetermined odd number of rows from the one scanning line are selected. Capacitance line driving circuit that selects the power supply line when selected and applies the voltage of the power supply line; and
A data line driving circuit for supplying a data signal corresponding to the gradation of the pixel to the pixel corresponding to the selected scanning line via the data line;
An electro-optical device driving circuit comprising: The capacitor line driving circuit includes:
The one capacitance line
After the selection of the scanning lines separated by the predetermined odd number of rows downward or upward with respect to the one scanning line is completed, until the one scanning line is selected again.
The drive circuit of the electro-optical device according to claim 1, wherein the driving circuit is in a high impedance state. The capacitor line driving circuit includes:
Corresponding to each of the capacitance lines, there are first and second transistors,
The first transistor corresponding to one capacitor line has a gate electrode connected to a scanning line corresponding to the one capacitor line, a source electrode connected to the power supply line,
The second transistor has a gate electrode connected to the scan line spaced apart by the predetermined odd number of lines in the lower or upper direction with respect to the one scan line, a source electrode connected to the power supply line,
The drive circuit of the electro-optical device according to claim 1, wherein drain electrodes of the first and second transistors are commonly connected to the one capacitance line. The scanning line driving circuit is capable of switching the selection direction of the scanning line downward or upward,
The capacitor line driving circuit is configured to connect the one capacitor line to
If the selection direction of the scanning line is downward, the selection of the scanning line separated by the predetermined odd number of rows in the downward direction with respect to the one scanning line is completed, and then the upward direction with respect to the one scanning line. Until a scanning line separated by the predetermined odd number of rows is selected again, it is in a high impedance state,
If the selection direction of the scanning line is upward, the selection of the scanning line separated by the predetermined odd number of rows in the upward direction with respect to the one scanning line is completed, and then downward with respect to the one scanning line. The drive circuit for an electro-optical device according to claim 1, wherein the high-impedance state is maintained until the scanning lines separated by the predetermined odd number of rows are selected again. The capacitor line driving circuit includes:
Corresponding to each of the capacitance lines, there are first, second and third transistors,
The first transistor corresponding to one capacitor line has a gate electrode connected to a scanning line corresponding to the one capacitor line, a source electrode connected to the power supply line,
The second transistor has a gate electrode connected to the scan line spaced upward by the predetermined odd number of rows with respect to the one scan line, a source electrode connected to the power supply line,
The third transistor has a gate electrode connected to the scan line spaced apart by the predetermined odd number of rows downward with respect to the one scan line, a source electrode connected to the power supply line,
The drive circuit of the electro-optical device according to claim 1, wherein drain electrodes of the first, second, and third transistors are commonly connected to the one capacitor line. Multiple rows of scanning lines;
Multiple columns of data lines;
A plurality of capacitance lines provided corresponding to the plurality of rows of scanning lines;
A plurality of pixels provided corresponding to intersections of the plurality of rows of scanning lines and the plurality of columns of data lines,
A pixel switching element having one end connected to a data line corresponding to the pixel and a conductive state when a scanning line corresponding to the data line is selected;
A pixel capacitor having one end connected to the other end of the pixel switching element and the other end connected to a common electrode;
A pixel including a storage capacitor interposed between one end of the pixel capacitor and a capacitor line provided corresponding to the scanning line;
A scanning line driving circuit for selecting the scanning lines in a predetermined order;
Each time a scanning line is selected, a low-side voltage and a high-side voltage are alternately switched between and fed to the power supply line,
For the capacitance line provided corresponding to one scanning line, a feeding line is selected when the one scanning line is selected, and scanning lines separated by a predetermined odd number of rows from the one scanning line are selected. Capacitance line driving circuit that selects the power supply line when selected and applies the voltage of the power supply line; and
A data line driving circuit for supplying a data signal corresponding to the gradation of the pixel to the pixel corresponding to the selected scanning line via the data line;
An electro-optical device comprising: An electronic apparatus comprising the electro-optical device according to claim 6.

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